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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_dma.h
blob1a8cae9f741a7adb386129cd8fbefc94d9fd3a5c
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_DMA_H
38 #define __STM32F3xx_LL_DMA_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx.h"
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 #if defined (DMA1) || defined (DMA2)
52
53 /** @defgroup DMA_LL DMA
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
60 * @{
61 */
62 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
63 static const uint8_t CHANNEL_OFFSET_TAB[] =
64 {
65 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
66 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
67 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
72 };
73 /**
74 * @}
75 */
76
77 /* Private constants ---------------------------------------------------------*/
78 /* Private macros ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
81 * @{
82 */
83 /**
84 * @}
85 */
86 #endif /*USE_FULL_LL_DRIVER*/
87
88 /* Exported types ------------------------------------------------------------*/
89 #if defined(USE_FULL_LL_DRIVER)
90 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
91 * @{
92 */
93 typedef struct
94 {
95 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
96 or as Source base address in case of memory to memory transfer direction.
97
98 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
99
100 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
101 or as Destination base address in case of memory to memory transfer direction.
102
103 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
104
105 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
106 from memory to memory or from peripheral to memory.
107 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
108
109 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
110
111 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
112 This parameter can be a value of @ref DMA_LL_EC_MODE
113 @note: The circular buffer mode cannot be used if the memory to memory
114 data transfer direction is configured on the selected Channel
115
116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
117
118 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
119 is incremented or not.
120 This parameter can be a value of @ref DMA_LL_EC_PERIPH
121
122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
123
124 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
125 is incremented or not.
126 This parameter can be a value of @ref DMA_LL_EC_MEMORY
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
129
130 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
131 in case of memory to memory transfer direction.
132 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
135
136 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
137 in case of memory to memory transfer direction.
138 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
141
142 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
143 The data unit is equal to the source buffer configuration set in PeripheralSize
144 or MemorySize parameters depending in the transfer direction.
145 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
146
147 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
148
149 uint32_t Priority; /*!< Specifies the channel priority level.
150 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
151
152 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
153
154 } LL_DMA_InitTypeDef;
155 /**
156 * @}
157 */
158 #endif /*USE_FULL_LL_DRIVER*/
159
160 /* Exported constants --------------------------------------------------------*/
161 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
162 * @{
163 */
164 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
165 * @brief Flags defines which can be used with LL_DMA_WriteReg function
166 * @{
167 */
168 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
169 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
170 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
171 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
172 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
173 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
174 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
175 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
176 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
177 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
178 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
179 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
180 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
181 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
182 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
183 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
184 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
185 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
186 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
187 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
188 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
189 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
190 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
191 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
192 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
193 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
194 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
195 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
196 /**
197 * @}
198 */
199
200 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
201 * @brief Flags defines which can be used with LL_DMA_ReadReg function
202 * @{
203 */
204 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
205 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
206 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
207 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
208 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
209 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
210 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
211 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
212 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
213 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
214 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
215 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
216 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
217 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
218 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
219 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
220 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
221 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
222 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
223 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
224 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
225 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
226 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
227 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
228 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
229 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
230 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
231 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
232 /**
233 * @}
234 */
235
236 /** @defgroup DMA_LL_EC_IT IT Defines
237 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
238 * @{
239 */
240 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
241 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
242 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
243 /**
244 * @}
245 */
246
247 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
248 * @{
249 */
250 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
251 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
252 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
253 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
254 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
255 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
256 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
257 #if defined(USE_FULL_LL_DRIVER)
258 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
259 #endif /*USE_FULL_LL_DRIVER*/
260 /**
261 * @}
262 */
263
264 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
265 * @{
266 */
267 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
268 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
269 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
270 /**
271 * @}
272 */
273
274 /** @defgroup DMA_LL_EC_MODE Transfer mode
275 * @{
276 */
277 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
278 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
279 /**
280 * @}
281 */
282
283 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
284 * @{
285 */
286 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
287 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
288 /**
289 * @}
290 */
291
292 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
293 * @{
294 */
295 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
296 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
297 /**
298 * @}
299 */
300
301 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
302 * @{
303 */
304 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
305 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
306 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
307 /**
308 * @}
309 */
310
311 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
312 * @{
313 */
314 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
315 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
316 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
317 /**
318 * @}
319 */
320
321 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
322 * @{
323 */
324 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
325 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
326 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
327 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
328 /**
329 * @}
330 */
331
332
333 /**
334 * @}
335 */
336
337 /* Exported macro ------------------------------------------------------------*/
338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
339 * @{
340 */
341
342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
343 * @{
344 */
345 /**
346 * @brief Write a value in DMA register
347 * @param __INSTANCE__ DMA Instance
348 * @param __REG__ Register to be written
349 * @param __VALUE__ Value to be written in the register
350 * @retval None
351 */
352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
353
354 /**
355 * @brief Read a value in DMA register
356 * @param __INSTANCE__ DMA Instance
357 * @param __REG__ Register to be read
358 * @retval Register value
359 */
360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
361 /**
362 * @}
363 */
364
365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
366 * @{
367 */
368 /**
369 * @brief Convert DMAx_Channely into DMAx
370 * @param __CHANNEL_INSTANCE__ DMAx_Channely
371 * @retval DMAx
372 */
373 #if defined(DMA2)
374 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
375 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
376 #else
377 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
378 #endif
379
380 /**
381 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
382 * @param __CHANNEL_INSTANCE__ DMAx_Channely
383 * @retval LL_DMA_CHANNEL_y
384 */
385 #if defined (DMA2)
386 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
400 LL_DMA_CHANNEL_7)
401 #else
402 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
403 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
408 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
414 LL_DMA_CHANNEL_7)
415 #endif
416 #else
417 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
418 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
424 LL_DMA_CHANNEL_7)
425 #endif
426
427 /**
428 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
429 * @param __DMA_INSTANCE__ DMAx
430 * @param __CHANNEL__ LL_DMA_CHANNEL_y
431 * @retval DMAx_Channely
432 */
433 #if defined (DMA2)
434 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
435 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
436 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
442 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
443 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
444 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
445 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
446 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
447 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
448 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
449 DMA2_Channel7)
450 #else
451 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
463 DMA1_Channel7)
464 #endif
465 #else
466 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
467 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
473 DMA1_Channel7)
474 #endif
475
476 /**
477 * @}
478 */
479
480 /**
481 * @}
482 */
483
484 /* Exported functions --------------------------------------------------------*/
485 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
486 * @{
487 */
488
489 /** @defgroup DMA_LL_EF_Configuration Configuration
490 * @{
491 */
492 /**
493 * @brief Enable DMA channel.
494 * @rmtoll CCR EN LL_DMA_EnableChannel
495 * @param DMAx DMAx Instance
496 * @param Channel This parameter can be one of the following values:
497 * @arg @ref LL_DMA_CHANNEL_1
498 * @arg @ref LL_DMA_CHANNEL_2
499 * @arg @ref LL_DMA_CHANNEL_3
500 * @arg @ref LL_DMA_CHANNEL_4
501 * @arg @ref LL_DMA_CHANNEL_5
502 * @arg @ref LL_DMA_CHANNEL_6
503 * @arg @ref LL_DMA_CHANNEL_7
504 * @retval None
505 */
506 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
507 {
508 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
509 }
510
511 /**
512 * @brief Disable DMA channel.
513 * @rmtoll CCR EN LL_DMA_DisableChannel
514 * @param DMAx DMAx Instance
515 * @param Channel This parameter can be one of the following values:
516 * @arg @ref LL_DMA_CHANNEL_1
517 * @arg @ref LL_DMA_CHANNEL_2
518 * @arg @ref LL_DMA_CHANNEL_3
519 * @arg @ref LL_DMA_CHANNEL_4
520 * @arg @ref LL_DMA_CHANNEL_5
521 * @arg @ref LL_DMA_CHANNEL_6
522 * @arg @ref LL_DMA_CHANNEL_7
523 * @retval None
524 */
525 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
526 {
527 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
528 }
529
530 /**
531 * @brief Check if DMA channel is enabled or disabled.
532 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
533 * @param DMAx DMAx Instance
534 * @param Channel This parameter can be one of the following values:
535 * @arg @ref LL_DMA_CHANNEL_1
536 * @arg @ref LL_DMA_CHANNEL_2
537 * @arg @ref LL_DMA_CHANNEL_3
538 * @arg @ref LL_DMA_CHANNEL_4
539 * @arg @ref LL_DMA_CHANNEL_5
540 * @arg @ref LL_DMA_CHANNEL_6
541 * @arg @ref LL_DMA_CHANNEL_7
542 * @retval State of bit (1 or 0).
543 */
544 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
545 {
546 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
547 DMA_CCR_EN) == (DMA_CCR_EN));
548 }
549
550 /**
551 * @brief Configure all parameters link to DMA transfer.
552 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
553 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
554 * CCR CIRC LL_DMA_ConfigTransfer\n
555 * CCR PINC LL_DMA_ConfigTransfer\n
556 * CCR MINC LL_DMA_ConfigTransfer\n
557 * CCR PSIZE LL_DMA_ConfigTransfer\n
558 * CCR MSIZE LL_DMA_ConfigTransfer\n
559 * CCR PL LL_DMA_ConfigTransfer
560 * @param DMAx DMAx Instance
561 * @param Channel This parameter can be one of the following values:
562 * @arg @ref LL_DMA_CHANNEL_1
563 * @arg @ref LL_DMA_CHANNEL_2
564 * @arg @ref LL_DMA_CHANNEL_3
565 * @arg @ref LL_DMA_CHANNEL_4
566 * @arg @ref LL_DMA_CHANNEL_5
567 * @arg @ref LL_DMA_CHANNEL_6
568 * @arg @ref LL_DMA_CHANNEL_7
569 * @param Configuration This parameter must be a combination of all the following values:
570 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
571 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
572 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
573 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
574 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
575 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
576 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
577 * @retval None
578 */
579 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
580 {
581 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
582 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
583 Configuration);
584 }
585
586 /**
587 * @brief Set Data transfer direction (read from peripheral or from memory).
588 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
589 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
590 * @param DMAx DMAx Instance
591 * @param Channel This parameter can be one of the following values:
592 * @arg @ref LL_DMA_CHANNEL_1
593 * @arg @ref LL_DMA_CHANNEL_2
594 * @arg @ref LL_DMA_CHANNEL_3
595 * @arg @ref LL_DMA_CHANNEL_4
596 * @arg @ref LL_DMA_CHANNEL_5
597 * @arg @ref LL_DMA_CHANNEL_6
598 * @arg @ref LL_DMA_CHANNEL_7
599 * @param Direction This parameter can be one of the following values:
600 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
601 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
602 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
603 * @retval None
604 */
605 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
606 {
607 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
608 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
609 }
610
611 /**
612 * @brief Get Data transfer direction (read from peripheral or from memory).
613 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
614 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
615 * @param DMAx DMAx Instance
616 * @param Channel This parameter can be one of the following values:
617 * @arg @ref LL_DMA_CHANNEL_1
618 * @arg @ref LL_DMA_CHANNEL_2
619 * @arg @ref LL_DMA_CHANNEL_3
620 * @arg @ref LL_DMA_CHANNEL_4
621 * @arg @ref LL_DMA_CHANNEL_5
622 * @arg @ref LL_DMA_CHANNEL_6
623 * @arg @ref LL_DMA_CHANNEL_7
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
626 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
627 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
628 */
629 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
630 {
631 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
632 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
633 }
634
635 /**
636 * @brief Set DMA mode circular or normal.
637 * @note The circular buffer mode cannot be used if the memory-to-memory
638 * data transfer is configured on the selected Channel.
639 * @rmtoll CCR CIRC LL_DMA_SetMode
640 * @param DMAx DMAx Instance
641 * @param Channel This parameter can be one of the following values:
642 * @arg @ref LL_DMA_CHANNEL_1
643 * @arg @ref LL_DMA_CHANNEL_2
644 * @arg @ref LL_DMA_CHANNEL_3
645 * @arg @ref LL_DMA_CHANNEL_4
646 * @arg @ref LL_DMA_CHANNEL_5
647 * @arg @ref LL_DMA_CHANNEL_6
648 * @arg @ref LL_DMA_CHANNEL_7
649 * @param Mode This parameter can be one of the following values:
650 * @arg @ref LL_DMA_MODE_NORMAL
651 * @arg @ref LL_DMA_MODE_CIRCULAR
652 * @retval None
653 */
654 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
655 {
656 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
657 Mode);
658 }
659
660 /**
661 * @brief Get DMA mode circular or normal.
662 * @rmtoll CCR CIRC LL_DMA_GetMode
663 * @param DMAx DMAx Instance
664 * @param Channel This parameter can be one of the following values:
665 * @arg @ref LL_DMA_CHANNEL_1
666 * @arg @ref LL_DMA_CHANNEL_2
667 * @arg @ref LL_DMA_CHANNEL_3
668 * @arg @ref LL_DMA_CHANNEL_4
669 * @arg @ref LL_DMA_CHANNEL_5
670 * @arg @ref LL_DMA_CHANNEL_6
671 * @arg @ref LL_DMA_CHANNEL_7
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_DMA_MODE_NORMAL
674 * @arg @ref LL_DMA_MODE_CIRCULAR
675 */
676 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
677 {
678 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
679 DMA_CCR_CIRC));
680 }
681
682 /**
683 * @brief Set Peripheral increment mode.
684 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
685 * @param DMAx DMAx Instance
686 * @param Channel This parameter can be one of the following values:
687 * @arg @ref LL_DMA_CHANNEL_1
688 * @arg @ref LL_DMA_CHANNEL_2
689 * @arg @ref LL_DMA_CHANNEL_3
690 * @arg @ref LL_DMA_CHANNEL_4
691 * @arg @ref LL_DMA_CHANNEL_5
692 * @arg @ref LL_DMA_CHANNEL_6
693 * @arg @ref LL_DMA_CHANNEL_7
694 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
695 * @arg @ref LL_DMA_PERIPH_INCREMENT
696 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
697 * @retval None
698 */
699 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
700 {
701 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
702 PeriphOrM2MSrcIncMode);
703 }
704
705 /**
706 * @brief Get Peripheral increment mode.
707 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
708 * @param DMAx DMAx Instance
709 * @param Channel This parameter can be one of the following values:
710 * @arg @ref LL_DMA_CHANNEL_1
711 * @arg @ref LL_DMA_CHANNEL_2
712 * @arg @ref LL_DMA_CHANNEL_3
713 * @arg @ref LL_DMA_CHANNEL_4
714 * @arg @ref LL_DMA_CHANNEL_5
715 * @arg @ref LL_DMA_CHANNEL_6
716 * @arg @ref LL_DMA_CHANNEL_7
717 * @retval Returned value can be one of the following values:
718 * @arg @ref LL_DMA_PERIPH_INCREMENT
719 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
720 */
721 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
722 {
723 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
724 DMA_CCR_PINC));
725 }
726
727 /**
728 * @brief Set Memory increment mode.
729 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
730 * @param DMAx DMAx Instance
731 * @param Channel This parameter can be one of the following values:
732 * @arg @ref LL_DMA_CHANNEL_1
733 * @arg @ref LL_DMA_CHANNEL_2
734 * @arg @ref LL_DMA_CHANNEL_3
735 * @arg @ref LL_DMA_CHANNEL_4
736 * @arg @ref LL_DMA_CHANNEL_5
737 * @arg @ref LL_DMA_CHANNEL_6
738 * @arg @ref LL_DMA_CHANNEL_7
739 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
740 * @arg @ref LL_DMA_MEMORY_INCREMENT
741 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
742 * @retval None
743 */
744 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
745 {
746 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
747 MemoryOrM2MDstIncMode);
748 }
749
750 /**
751 * @brief Get Memory increment mode.
752 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
753 * @param DMAx DMAx Instance
754 * @param Channel This parameter can be one of the following values:
755 * @arg @ref LL_DMA_CHANNEL_1
756 * @arg @ref LL_DMA_CHANNEL_2
757 * @arg @ref LL_DMA_CHANNEL_3
758 * @arg @ref LL_DMA_CHANNEL_4
759 * @arg @ref LL_DMA_CHANNEL_5
760 * @arg @ref LL_DMA_CHANNEL_6
761 * @arg @ref LL_DMA_CHANNEL_7
762 * @retval Returned value can be one of the following values:
763 * @arg @ref LL_DMA_MEMORY_INCREMENT
764 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
765 */
766 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
767 {
768 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
769 DMA_CCR_MINC));
770 }
771
772 /**
773 * @brief Set Peripheral size.
774 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
775 * @param DMAx DMAx Instance
776 * @param Channel This parameter can be one of the following values:
777 * @arg @ref LL_DMA_CHANNEL_1
778 * @arg @ref LL_DMA_CHANNEL_2
779 * @arg @ref LL_DMA_CHANNEL_3
780 * @arg @ref LL_DMA_CHANNEL_4
781 * @arg @ref LL_DMA_CHANNEL_5
782 * @arg @ref LL_DMA_CHANNEL_6
783 * @arg @ref LL_DMA_CHANNEL_7
784 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
785 * @arg @ref LL_DMA_PDATAALIGN_BYTE
786 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
787 * @arg @ref LL_DMA_PDATAALIGN_WORD
788 * @retval None
789 */
790 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
791 {
792 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
793 PeriphOrM2MSrcDataSize);
794 }
795
796 /**
797 * @brief Get Peripheral size.
798 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
799 * @param DMAx DMAx Instance
800 * @param Channel This parameter can be one of the following values:
801 * @arg @ref LL_DMA_CHANNEL_1
802 * @arg @ref LL_DMA_CHANNEL_2
803 * @arg @ref LL_DMA_CHANNEL_3
804 * @arg @ref LL_DMA_CHANNEL_4
805 * @arg @ref LL_DMA_CHANNEL_5
806 * @arg @ref LL_DMA_CHANNEL_6
807 * @arg @ref LL_DMA_CHANNEL_7
808 * @retval Returned value can be one of the following values:
809 * @arg @ref LL_DMA_PDATAALIGN_BYTE
810 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
811 * @arg @ref LL_DMA_PDATAALIGN_WORD
812 */
813 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
814 {
815 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
816 DMA_CCR_PSIZE));
817 }
818
819 /**
820 * @brief Set Memory size.
821 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
822 * @param DMAx DMAx Instance
823 * @param Channel This parameter can be one of the following values:
824 * @arg @ref LL_DMA_CHANNEL_1
825 * @arg @ref LL_DMA_CHANNEL_2
826 * @arg @ref LL_DMA_CHANNEL_3
827 * @arg @ref LL_DMA_CHANNEL_4
828 * @arg @ref LL_DMA_CHANNEL_5
829 * @arg @ref LL_DMA_CHANNEL_6
830 * @arg @ref LL_DMA_CHANNEL_7
831 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
832 * @arg @ref LL_DMA_MDATAALIGN_BYTE
833 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
834 * @arg @ref LL_DMA_MDATAALIGN_WORD
835 * @retval None
836 */
837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
838 {
839 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
840 MemoryOrM2MDstDataSize);
841 }
842
843 /**
844 * @brief Get Memory size.
845 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
846 * @param DMAx DMAx Instance
847 * @param Channel This parameter can be one of the following values:
848 * @arg @ref LL_DMA_CHANNEL_1
849 * @arg @ref LL_DMA_CHANNEL_2
850 * @arg @ref LL_DMA_CHANNEL_3
851 * @arg @ref LL_DMA_CHANNEL_4
852 * @arg @ref LL_DMA_CHANNEL_5
853 * @arg @ref LL_DMA_CHANNEL_6
854 * @arg @ref LL_DMA_CHANNEL_7
855 * @retval Returned value can be one of the following values:
856 * @arg @ref LL_DMA_MDATAALIGN_BYTE
857 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
858 * @arg @ref LL_DMA_MDATAALIGN_WORD
859 */
860 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
861 {
862 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
863 DMA_CCR_MSIZE));
864 }
865
866 /**
867 * @brief Set Channel priority level.
868 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
869 * @param DMAx DMAx Instance
870 * @param Channel This parameter can be one of the following values:
871 * @arg @ref LL_DMA_CHANNEL_1
872 * @arg @ref LL_DMA_CHANNEL_2
873 * @arg @ref LL_DMA_CHANNEL_3
874 * @arg @ref LL_DMA_CHANNEL_4
875 * @arg @ref LL_DMA_CHANNEL_5
876 * @arg @ref LL_DMA_CHANNEL_6
877 * @arg @ref LL_DMA_CHANNEL_7
878 * @param Priority This parameter can be one of the following values:
879 * @arg @ref LL_DMA_PRIORITY_LOW
880 * @arg @ref LL_DMA_PRIORITY_MEDIUM
881 * @arg @ref LL_DMA_PRIORITY_HIGH
882 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
883 * @retval None
884 */
885 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
886 {
887 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
888 Priority);
889 }
890
891 /**
892 * @brief Get Channel priority level.
893 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
894 * @param DMAx DMAx Instance
895 * @param Channel This parameter can be one of the following values:
896 * @arg @ref LL_DMA_CHANNEL_1
897 * @arg @ref LL_DMA_CHANNEL_2
898 * @arg @ref LL_DMA_CHANNEL_3
899 * @arg @ref LL_DMA_CHANNEL_4
900 * @arg @ref LL_DMA_CHANNEL_5
901 * @arg @ref LL_DMA_CHANNEL_6
902 * @arg @ref LL_DMA_CHANNEL_7
903 * @retval Returned value can be one of the following values:
904 * @arg @ref LL_DMA_PRIORITY_LOW
905 * @arg @ref LL_DMA_PRIORITY_MEDIUM
906 * @arg @ref LL_DMA_PRIORITY_HIGH
907 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
908 */
909 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
910 {
911 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
912 DMA_CCR_PL));
913 }
914
915 /**
916 * @brief Set Number of data to transfer.
917 * @note This action has no effect if
918 * channel is enabled.
919 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
920 * @param DMAx DMAx Instance
921 * @param Channel This parameter can be one of the following values:
922 * @arg @ref LL_DMA_CHANNEL_1
923 * @arg @ref LL_DMA_CHANNEL_2
924 * @arg @ref LL_DMA_CHANNEL_3
925 * @arg @ref LL_DMA_CHANNEL_4
926 * @arg @ref LL_DMA_CHANNEL_5
927 * @arg @ref LL_DMA_CHANNEL_6
928 * @arg @ref LL_DMA_CHANNEL_7
929 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
930 * @retval None
931 */
932 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
933 {
934 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
935 DMA_CNDTR_NDT, NbData);
936 }
937
938 /**
939 * @brief Get Number of data to transfer.
940 * @note Once the channel is enabled, the return value indicate the
941 * remaining bytes to be transmitted.
942 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
943 * @param DMAx DMAx Instance
944 * @param Channel This parameter can be one of the following values:
945 * @arg @ref LL_DMA_CHANNEL_1
946 * @arg @ref LL_DMA_CHANNEL_2
947 * @arg @ref LL_DMA_CHANNEL_3
948 * @arg @ref LL_DMA_CHANNEL_4
949 * @arg @ref LL_DMA_CHANNEL_5
950 * @arg @ref LL_DMA_CHANNEL_6
951 * @arg @ref LL_DMA_CHANNEL_7
952 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
953 */
954 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
955 {
956 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
957 DMA_CNDTR_NDT));
958 }
959
960 /**
961 * @brief Configure the Source and Destination addresses.
962 * @note This API must not be called when the DMA channel is enabled.
963 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
964 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
965 * CMAR MA LL_DMA_ConfigAddresses
966 * @param DMAx DMAx Instance
967 * @param Channel This parameter can be one of the following values:
968 * @arg @ref LL_DMA_CHANNEL_1
969 * @arg @ref LL_DMA_CHANNEL_2
970 * @arg @ref LL_DMA_CHANNEL_3
971 * @arg @ref LL_DMA_CHANNEL_4
972 * @arg @ref LL_DMA_CHANNEL_5
973 * @arg @ref LL_DMA_CHANNEL_6
974 * @arg @ref LL_DMA_CHANNEL_7
975 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
976 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
977 * @param Direction This parameter can be one of the following values:
978 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
979 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
980 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
981 * @retval None
982 */
983 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
984 uint32_t DstAddress, uint32_t Direction)
985 {
986 /* Direction Memory to Periph */
987 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
988 {
989 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
990 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
991 }
992 /* Direction Periph to Memory and Memory to Memory */
993 else
994 {
995 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
996 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
997 }
998 }
999
1000 /**
1001 * @brief Set the Memory address.
1002 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1003 * @note This API must not be called when the DMA channel is enabled.
1004 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1005 * @param DMAx DMAx Instance
1006 * @param Channel This parameter can be one of the following values:
1007 * @arg @ref LL_DMA_CHANNEL_1
1008 * @arg @ref LL_DMA_CHANNEL_2
1009 * @arg @ref LL_DMA_CHANNEL_3
1010 * @arg @ref LL_DMA_CHANNEL_4
1011 * @arg @ref LL_DMA_CHANNEL_5
1012 * @arg @ref LL_DMA_CHANNEL_6
1013 * @arg @ref LL_DMA_CHANNEL_7
1014 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1015 * @retval None
1016 */
1017 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1018 {
1019 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1020 }
1021
1022 /**
1023 * @brief Set the Peripheral address.
1024 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1025 * @note This API must not be called when the DMA channel is enabled.
1026 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1027 * @param DMAx DMAx Instance
1028 * @param Channel This parameter can be one of the following values:
1029 * @arg @ref LL_DMA_CHANNEL_1
1030 * @arg @ref LL_DMA_CHANNEL_2
1031 * @arg @ref LL_DMA_CHANNEL_3
1032 * @arg @ref LL_DMA_CHANNEL_4
1033 * @arg @ref LL_DMA_CHANNEL_5
1034 * @arg @ref LL_DMA_CHANNEL_6
1035 * @arg @ref LL_DMA_CHANNEL_7
1036 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1037 * @retval None
1038 */
1039 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1040 {
1041 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1042 }
1043
1044 /**
1045 * @brief Get Memory address.
1046 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1047 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1048 * @param DMAx DMAx Instance
1049 * @param Channel This parameter can be one of the following values:
1050 * @arg @ref LL_DMA_CHANNEL_1
1051 * @arg @ref LL_DMA_CHANNEL_2
1052 * @arg @ref LL_DMA_CHANNEL_3
1053 * @arg @ref LL_DMA_CHANNEL_4
1054 * @arg @ref LL_DMA_CHANNEL_5
1055 * @arg @ref LL_DMA_CHANNEL_6
1056 * @arg @ref LL_DMA_CHANNEL_7
1057 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1058 */
1059 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1060 {
1061 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1062 }
1063
1064 /**
1065 * @brief Get Peripheral address.
1066 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1067 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1068 * @param DMAx DMAx Instance
1069 * @param Channel This parameter can be one of the following values:
1070 * @arg @ref LL_DMA_CHANNEL_1
1071 * @arg @ref LL_DMA_CHANNEL_2
1072 * @arg @ref LL_DMA_CHANNEL_3
1073 * @arg @ref LL_DMA_CHANNEL_4
1074 * @arg @ref LL_DMA_CHANNEL_5
1075 * @arg @ref LL_DMA_CHANNEL_6
1076 * @arg @ref LL_DMA_CHANNEL_7
1077 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1078 */
1079 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1080 {
1081 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1082 }
1083
1084 /**
1085 * @brief Set the Memory to Memory Source address.
1086 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1087 * @note This API must not be called when the DMA channel is enabled.
1088 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1089 * @param DMAx DMAx Instance
1090 * @param Channel This parameter can be one of the following values:
1091 * @arg @ref LL_DMA_CHANNEL_1
1092 * @arg @ref LL_DMA_CHANNEL_2
1093 * @arg @ref LL_DMA_CHANNEL_3
1094 * @arg @ref LL_DMA_CHANNEL_4
1095 * @arg @ref LL_DMA_CHANNEL_5
1096 * @arg @ref LL_DMA_CHANNEL_6
1097 * @arg @ref LL_DMA_CHANNEL_7
1098 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1099 * @retval None
1100 */
1101 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1102 {
1103 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1104 }
1105
1106 /**
1107 * @brief Set the Memory to Memory Destination address.
1108 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1109 * @note This API must not be called when the DMA channel is enabled.
1110 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1111 * @param DMAx DMAx Instance
1112 * @param Channel This parameter can be one of the following values:
1113 * @arg @ref LL_DMA_CHANNEL_1
1114 * @arg @ref LL_DMA_CHANNEL_2
1115 * @arg @ref LL_DMA_CHANNEL_3
1116 * @arg @ref LL_DMA_CHANNEL_4
1117 * @arg @ref LL_DMA_CHANNEL_5
1118 * @arg @ref LL_DMA_CHANNEL_6
1119 * @arg @ref LL_DMA_CHANNEL_7
1120 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1121 * @retval None
1122 */
1123 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1124 {
1125 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1126 }
1127
1128 /**
1129 * @brief Get the Memory to Memory Source address.
1130 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1131 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1132 * @param DMAx DMAx Instance
1133 * @param Channel This parameter can be one of the following values:
1134 * @arg @ref LL_DMA_CHANNEL_1
1135 * @arg @ref LL_DMA_CHANNEL_2
1136 * @arg @ref LL_DMA_CHANNEL_3
1137 * @arg @ref LL_DMA_CHANNEL_4
1138 * @arg @ref LL_DMA_CHANNEL_5
1139 * @arg @ref LL_DMA_CHANNEL_6
1140 * @arg @ref LL_DMA_CHANNEL_7
1141 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1142 */
1143 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1144 {
1145 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1146 }
1147
1148 /**
1149 * @brief Get the Memory to Memory Destination address.
1150 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1151 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1152 * @param DMAx DMAx Instance
1153 * @param Channel This parameter can be one of the following values:
1154 * @arg @ref LL_DMA_CHANNEL_1
1155 * @arg @ref LL_DMA_CHANNEL_2
1156 * @arg @ref LL_DMA_CHANNEL_3
1157 * @arg @ref LL_DMA_CHANNEL_4
1158 * @arg @ref LL_DMA_CHANNEL_5
1159 * @arg @ref LL_DMA_CHANNEL_6
1160 * @arg @ref LL_DMA_CHANNEL_7
1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1162 */
1163 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1164 {
1165 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1166 }
1167
1168
1169 /**
1170 * @}
1171 */
1172
1173 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1174 * @{
1175 */
1176
1177 /**
1178 * @brief Get Channel 1 global interrupt flag.
1179 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1180 * @param DMAx DMAx Instance
1181 * @retval State of bit (1 or 0).
1182 */
1183 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1184 {
1185 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1186 }
1187
1188 /**
1189 * @brief Get Channel 2 global interrupt flag.
1190 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1191 * @param DMAx DMAx Instance
1192 * @retval State of bit (1 or 0).
1193 */
1194 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1195 {
1196 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1197 }
1198
1199 /**
1200 * @brief Get Channel 3 global interrupt flag.
1201 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1202 * @param DMAx DMAx Instance
1203 * @retval State of bit (1 or 0).
1204 */
1205 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1206 {
1207 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1208 }
1209
1210 /**
1211 * @brief Get Channel 4 global interrupt flag.
1212 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1213 * @param DMAx DMAx Instance
1214 * @retval State of bit (1 or 0).
1215 */
1216 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1217 {
1218 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1219 }
1220
1221 /**
1222 * @brief Get Channel 5 global interrupt flag.
1223 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1224 * @param DMAx DMAx Instance
1225 * @retval State of bit (1 or 0).
1226 */
1227 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1228 {
1229 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1230 }
1231
1232 /**
1233 * @brief Get Channel 6 global interrupt flag.
1234 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1235 * @param DMAx DMAx Instance
1236 * @retval State of bit (1 or 0).
1237 */
1238 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1239 {
1240 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1241 }
1242
1243 /**
1244 * @brief Get Channel 7 global interrupt flag.
1245 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1246 * @param DMAx DMAx Instance
1247 * @retval State of bit (1 or 0).
1248 */
1249 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1250 {
1251 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1252 }
1253
1254 /**
1255 * @brief Get Channel 1 transfer complete flag.
1256 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1257 * @param DMAx DMAx Instance
1258 * @retval State of bit (1 or 0).
1259 */
1260 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1261 {
1262 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1263 }
1264
1265 /**
1266 * @brief Get Channel 2 transfer complete flag.
1267 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1268 * @param DMAx DMAx Instance
1269 * @retval State of bit (1 or 0).
1270 */
1271 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1272 {
1273 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1274 }
1275
1276 /**
1277 * @brief Get Channel 3 transfer complete flag.
1278 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1279 * @param DMAx DMAx Instance
1280 * @retval State of bit (1 or 0).
1281 */
1282 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1283 {
1284 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1285 }
1286
1287 /**
1288 * @brief Get Channel 4 transfer complete flag.
1289 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1290 * @param DMAx DMAx Instance
1291 * @retval State of bit (1 or 0).
1292 */
1293 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1294 {
1295 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1296 }
1297
1298 /**
1299 * @brief Get Channel 5 transfer complete flag.
1300 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1301 * @param DMAx DMAx Instance
1302 * @retval State of bit (1 or 0).
1303 */
1304 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1305 {
1306 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1307 }
1308
1309 /**
1310 * @brief Get Channel 6 transfer complete flag.
1311 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1312 * @param DMAx DMAx Instance
1313 * @retval State of bit (1 or 0).
1314 */
1315 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1316 {
1317 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1318 }
1319
1320 /**
1321 * @brief Get Channel 7 transfer complete flag.
1322 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1323 * @param DMAx DMAx Instance
1324 * @retval State of bit (1 or 0).
1325 */
1326 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1327 {
1328 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1329 }
1330
1331 /**
1332 * @brief Get Channel 1 half transfer flag.
1333 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1334 * @param DMAx DMAx Instance
1335 * @retval State of bit (1 or 0).
1336 */
1337 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1338 {
1339 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1340 }
1341
1342 /**
1343 * @brief Get Channel 2 half transfer flag.
1344 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1345 * @param DMAx DMAx Instance
1346 * @retval State of bit (1 or 0).
1347 */
1348 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1349 {
1350 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1351 }
1352
1353 /**
1354 * @brief Get Channel 3 half transfer flag.
1355 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1356 * @param DMAx DMAx Instance
1357 * @retval State of bit (1 or 0).
1358 */
1359 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1360 {
1361 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1362 }
1363
1364 /**
1365 * @brief Get Channel 4 half transfer flag.
1366 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1367 * @param DMAx DMAx Instance
1368 * @retval State of bit (1 or 0).
1369 */
1370 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1371 {
1372 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1373 }
1374
1375 /**
1376 * @brief Get Channel 5 half transfer flag.
1377 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1378 * @param DMAx DMAx Instance
1379 * @retval State of bit (1 or 0).
1380 */
1381 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1382 {
1383 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1384 }
1385
1386 /**
1387 * @brief Get Channel 6 half transfer flag.
1388 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1389 * @param DMAx DMAx Instance
1390 * @retval State of bit (1 or 0).
1391 */
1392 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1393 {
1394 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1395 }
1396
1397 /**
1398 * @brief Get Channel 7 half transfer flag.
1399 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1400 * @param DMAx DMAx Instance
1401 * @retval State of bit (1 or 0).
1402 */
1403 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1404 {
1405 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1406 }
1407
1408 /**
1409 * @brief Get Channel 1 transfer error flag.
1410 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1411 * @param DMAx DMAx Instance
1412 * @retval State of bit (1 or 0).
1413 */
1414 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1415 {
1416 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1417 }
1418
1419 /**
1420 * @brief Get Channel 2 transfer error flag.
1421 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1422 * @param DMAx DMAx Instance
1423 * @retval State of bit (1 or 0).
1424 */
1425 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1426 {
1427 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1428 }
1429
1430 /**
1431 * @brief Get Channel 3 transfer error flag.
1432 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1433 * @param DMAx DMAx Instance
1434 * @retval State of bit (1 or 0).
1435 */
1436 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1437 {
1438 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1439 }
1440
1441 /**
1442 * @brief Get Channel 4 transfer error flag.
1443 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1444 * @param DMAx DMAx Instance
1445 * @retval State of bit (1 or 0).
1446 */
1447 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1448 {
1449 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1450 }
1451
1452 /**
1453 * @brief Get Channel 5 transfer error flag.
1454 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1455 * @param DMAx DMAx Instance
1456 * @retval State of bit (1 or 0).
1457 */
1458 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1459 {
1460 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1461 }
1462
1463 /**
1464 * @brief Get Channel 6 transfer error flag.
1465 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1466 * @param DMAx DMAx Instance
1467 * @retval State of bit (1 or 0).
1468 */
1469 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1470 {
1471 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1472 }
1473
1474 /**
1475 * @brief Get Channel 7 transfer error flag.
1476 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1477 * @param DMAx DMAx Instance
1478 * @retval State of bit (1 or 0).
1479 */
1480 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1481 {
1482 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1483 }
1484
1485 /**
1486 * @brief Clear Channel 1 global interrupt flag.
1487 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1488 * @param DMAx DMAx Instance
1489 * @retval None
1490 */
1491 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1492 {
1493 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1494 }
1495
1496 /**
1497 * @brief Clear Channel 2 global interrupt flag.
1498 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1499 * @param DMAx DMAx Instance
1500 * @retval None
1501 */
1502 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1503 {
1504 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1505 }
1506
1507 /**
1508 * @brief Clear Channel 3 global interrupt flag.
1509 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1510 * @param DMAx DMAx Instance
1511 * @retval None
1512 */
1513 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1514 {
1515 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1516 }
1517
1518 /**
1519 * @brief Clear Channel 4 global interrupt flag.
1520 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1521 * @param DMAx DMAx Instance
1522 * @retval None
1523 */
1524 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1525 {
1526 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1527 }
1528
1529 /**
1530 * @brief Clear Channel 5 global interrupt flag.
1531 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1532 * @param DMAx DMAx Instance
1533 * @retval None
1534 */
1535 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1536 {
1537 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1538 }
1539
1540 /**
1541 * @brief Clear Channel 6 global interrupt flag.
1542 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1543 * @param DMAx DMAx Instance
1544 * @retval None
1545 */
1546 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1547 {
1548 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1549 }
1550
1551 /**
1552 * @brief Clear Channel 7 global interrupt flag.
1553 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1554 * @param DMAx DMAx Instance
1555 * @retval None
1556 */
1557 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1558 {
1559 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1560 }
1561
1562 /**
1563 * @brief Clear Channel 1 transfer complete flag.
1564 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1565 * @param DMAx DMAx Instance
1566 * @retval None
1567 */
1568 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1569 {
1570 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1571 }
1572
1573 /**
1574 * @brief Clear Channel 2 transfer complete flag.
1575 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1576 * @param DMAx DMAx Instance
1577 * @retval None
1578 */
1579 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1580 {
1581 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1582 }
1583
1584 /**
1585 * @brief Clear Channel 3 transfer complete flag.
1586 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1587 * @param DMAx DMAx Instance
1588 * @retval None
1589 */
1590 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1591 {
1592 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1593 }
1594
1595 /**
1596 * @brief Clear Channel 4 transfer complete flag.
1597 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1598 * @param DMAx DMAx Instance
1599 * @retval None
1600 */
1601 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1602 {
1603 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1604 }
1605
1606 /**
1607 * @brief Clear Channel 5 transfer complete flag.
1608 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1609 * @param DMAx DMAx Instance
1610 * @retval None
1611 */
1612 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1613 {
1614 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1615 }
1616
1617 /**
1618 * @brief Clear Channel 6 transfer complete flag.
1619 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1620 * @param DMAx DMAx Instance
1621 * @retval None
1622 */
1623 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1624 {
1625 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1626 }
1627
1628 /**
1629 * @brief Clear Channel 7 transfer complete flag.
1630 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1631 * @param DMAx DMAx Instance
1632 * @retval None
1633 */
1634 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1635 {
1636 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1637 }
1638
1639 /**
1640 * @brief Clear Channel 1 half transfer flag.
1641 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1642 * @param DMAx DMAx Instance
1643 * @retval None
1644 */
1645 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1646 {
1647 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1648 }
1649
1650 /**
1651 * @brief Clear Channel 2 half transfer flag.
1652 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1653 * @param DMAx DMAx Instance
1654 * @retval None
1655 */
1656 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1657 {
1658 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1659 }
1660
1661 /**
1662 * @brief Clear Channel 3 half transfer flag.
1663 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1664 * @param DMAx DMAx Instance
1665 * @retval None
1666 */
1667 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1668 {
1669 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1670 }
1671
1672 /**
1673 * @brief Clear Channel 4 half transfer flag.
1674 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1675 * @param DMAx DMAx Instance
1676 * @retval None
1677 */
1678 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1679 {
1680 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1681 }
1682
1683 /**
1684 * @brief Clear Channel 5 half transfer flag.
1685 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1686 * @param DMAx DMAx Instance
1687 * @retval None
1688 */
1689 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1690 {
1691 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1692 }
1693
1694 /**
1695 * @brief Clear Channel 6 half transfer flag.
1696 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1697 * @param DMAx DMAx Instance
1698 * @retval None
1699 */
1700 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1701 {
1702 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1703 }
1704
1705 /**
1706 * @brief Clear Channel 7 half transfer flag.
1707 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1708 * @param DMAx DMAx Instance
1709 * @retval None
1710 */
1711 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1712 {
1713 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1714 }
1715
1716 /**
1717 * @brief Clear Channel 1 transfer error flag.
1718 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1719 * @param DMAx DMAx Instance
1720 * @retval None
1721 */
1722 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1723 {
1724 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1725 }
1726
1727 /**
1728 * @brief Clear Channel 2 transfer error flag.
1729 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1730 * @param DMAx DMAx Instance
1731 * @retval None
1732 */
1733 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1734 {
1735 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1736 }
1737
1738 /**
1739 * @brief Clear Channel 3 transfer error flag.
1740 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1741 * @param DMAx DMAx Instance
1742 * @retval None
1743 */
1744 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1745 {
1746 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1747 }
1748
1749 /**
1750 * @brief Clear Channel 4 transfer error flag.
1751 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1752 * @param DMAx DMAx Instance
1753 * @retval None
1754 */
1755 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1756 {
1757 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1758 }
1759
1760 /**
1761 * @brief Clear Channel 5 transfer error flag.
1762 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1763 * @param DMAx DMAx Instance
1764 * @retval None
1765 */
1766 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1767 {
1768 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1769 }
1770
1771 /**
1772 * @brief Clear Channel 6 transfer error flag.
1773 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1774 * @param DMAx DMAx Instance
1775 * @retval None
1776 */
1777 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1778 {
1779 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1780 }
1781
1782 /**
1783 * @brief Clear Channel 7 transfer error flag.
1784 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1785 * @param DMAx DMAx Instance
1786 * @retval None
1787 */
1788 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1789 {
1790 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1791 }
1792
1793 /**
1794 * @}
1795 */
1796
1797 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1798 * @{
1799 */
1800 /**
1801 * @brief Enable Transfer complete interrupt.
1802 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1803 * @param DMAx DMAx Instance
1804 * @param Channel This parameter can be one of the following values:
1805 * @arg @ref LL_DMA_CHANNEL_1
1806 * @arg @ref LL_DMA_CHANNEL_2
1807 * @arg @ref LL_DMA_CHANNEL_3
1808 * @arg @ref LL_DMA_CHANNEL_4
1809 * @arg @ref LL_DMA_CHANNEL_5
1810 * @arg @ref LL_DMA_CHANNEL_6
1811 * @arg @ref LL_DMA_CHANNEL_7
1812 * @retval None
1813 */
1814 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1815 {
1816 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1817 }
1818
1819 /**
1820 * @brief Enable Half transfer interrupt.
1821 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1822 * @param DMAx DMAx Instance
1823 * @param Channel This parameter can be one of the following values:
1824 * @arg @ref LL_DMA_CHANNEL_1
1825 * @arg @ref LL_DMA_CHANNEL_2
1826 * @arg @ref LL_DMA_CHANNEL_3
1827 * @arg @ref LL_DMA_CHANNEL_4
1828 * @arg @ref LL_DMA_CHANNEL_5
1829 * @arg @ref LL_DMA_CHANNEL_6
1830 * @arg @ref LL_DMA_CHANNEL_7
1831 * @retval None
1832 */
1833 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1834 {
1835 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1836 }
1837
1838 /**
1839 * @brief Enable Transfer error interrupt.
1840 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1841 * @param DMAx DMAx Instance
1842 * @param Channel This parameter can be one of the following values:
1843 * @arg @ref LL_DMA_CHANNEL_1
1844 * @arg @ref LL_DMA_CHANNEL_2
1845 * @arg @ref LL_DMA_CHANNEL_3
1846 * @arg @ref LL_DMA_CHANNEL_4
1847 * @arg @ref LL_DMA_CHANNEL_5
1848 * @arg @ref LL_DMA_CHANNEL_6
1849 * @arg @ref LL_DMA_CHANNEL_7
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1853 {
1854 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1855 }
1856
1857 /**
1858 * @brief Disable Transfer complete interrupt.
1859 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1860 * @param DMAx DMAx Instance
1861 * @param Channel This parameter can be one of the following values:
1862 * @arg @ref LL_DMA_CHANNEL_1
1863 * @arg @ref LL_DMA_CHANNEL_2
1864 * @arg @ref LL_DMA_CHANNEL_3
1865 * @arg @ref LL_DMA_CHANNEL_4
1866 * @arg @ref LL_DMA_CHANNEL_5
1867 * @arg @ref LL_DMA_CHANNEL_6
1868 * @arg @ref LL_DMA_CHANNEL_7
1869 * @retval None
1870 */
1871 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1872 {
1873 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1874 }
1875
1876 /**
1877 * @brief Disable Half transfer interrupt.
1878 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1879 * @param DMAx DMAx Instance
1880 * @param Channel This parameter can be one of the following values:
1881 * @arg @ref LL_DMA_CHANNEL_1
1882 * @arg @ref LL_DMA_CHANNEL_2
1883 * @arg @ref LL_DMA_CHANNEL_3
1884 * @arg @ref LL_DMA_CHANNEL_4
1885 * @arg @ref LL_DMA_CHANNEL_5
1886 * @arg @ref LL_DMA_CHANNEL_6
1887 * @arg @ref LL_DMA_CHANNEL_7
1888 * @retval None
1889 */
1890 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1891 {
1892 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1893 }
1894
1895 /**
1896 * @brief Disable Transfer error interrupt.
1897 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1898 * @param DMAx DMAx Instance
1899 * @param Channel This parameter can be one of the following values:
1900 * @arg @ref LL_DMA_CHANNEL_1
1901 * @arg @ref LL_DMA_CHANNEL_2
1902 * @arg @ref LL_DMA_CHANNEL_3
1903 * @arg @ref LL_DMA_CHANNEL_4
1904 * @arg @ref LL_DMA_CHANNEL_5
1905 * @arg @ref LL_DMA_CHANNEL_6
1906 * @arg @ref LL_DMA_CHANNEL_7
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1910 {
1911 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1912 }
1913
1914 /**
1915 * @brief Check if Transfer complete Interrupt is enabled.
1916 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1917 * @param DMAx DMAx Instance
1918 * @param Channel This parameter can be one of the following values:
1919 * @arg @ref LL_DMA_CHANNEL_1
1920 * @arg @ref LL_DMA_CHANNEL_2
1921 * @arg @ref LL_DMA_CHANNEL_3
1922 * @arg @ref LL_DMA_CHANNEL_4
1923 * @arg @ref LL_DMA_CHANNEL_5
1924 * @arg @ref LL_DMA_CHANNEL_6
1925 * @arg @ref LL_DMA_CHANNEL_7
1926 * @retval State of bit (1 or 0).
1927 */
1928 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1929 {
1930 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1931 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1932 }
1933
1934 /**
1935 * @brief Check if Half transfer Interrupt is enabled.
1936 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1937 * @param DMAx DMAx Instance
1938 * @param Channel This parameter can be one of the following values:
1939 * @arg @ref LL_DMA_CHANNEL_1
1940 * @arg @ref LL_DMA_CHANNEL_2
1941 * @arg @ref LL_DMA_CHANNEL_3
1942 * @arg @ref LL_DMA_CHANNEL_4
1943 * @arg @ref LL_DMA_CHANNEL_5
1944 * @arg @ref LL_DMA_CHANNEL_6
1945 * @arg @ref LL_DMA_CHANNEL_7
1946 * @retval State of bit (1 or 0).
1947 */
1948 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1949 {
1950 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1951 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1952 }
1953
1954 /**
1955 * @brief Check if Transfer error Interrupt is enabled.
1956 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1957 * @param DMAx DMAx Instance
1958 * @param Channel This parameter can be one of the following values:
1959 * @arg @ref LL_DMA_CHANNEL_1
1960 * @arg @ref LL_DMA_CHANNEL_2
1961 * @arg @ref LL_DMA_CHANNEL_3
1962 * @arg @ref LL_DMA_CHANNEL_4
1963 * @arg @ref LL_DMA_CHANNEL_5
1964 * @arg @ref LL_DMA_CHANNEL_6
1965 * @arg @ref LL_DMA_CHANNEL_7
1966 * @retval State of bit (1 or 0).
1967 */
1968 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1969 {
1970 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1971 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1972 }
1973
1974 /**
1975 * @}
1976 */
1977
1978 #if defined(USE_FULL_LL_DRIVER)
1979 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1980 * @{
1981 */
1982
1983 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1984 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1985 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1986
1987 /**
1988 * @}
1989 */
1990 #endif /* USE_FULL_LL_DRIVER */
1991
1992 /**
1993 * @}
1994 */
1995
1996 /**
1997 * @}
1998 */
1999
2000 #endif /* DMA1 || DMA2 */
2001
2002 /**
2003 * @}
2004 */
2005
2006 #ifdef __cplusplus
2007 }
2008 #endif
2009
2010 #endif /* __STM32F3xx_LL_DMA_H */
2011
2012 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/