lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_fmc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_fmc.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of FMC HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_LL_FMC_H
  38 #define __STM32F3xx_LL_FMC_H
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f3xx_hal_def.h"
  46
  47 /** @addtogroup STM32F3xx_HAL_Driver
  48   * @{
  49   */
  50
  51 #if defined(FMC_BANK1)
  52
  53 /** @addtogroup FMC_LL
  54   * @{
  55   */
  56
  57 /** @addtogroup FMC_LL_Private_Macros
  58   * @{
  59   */
  60
  61 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
  62                                         ((__BANK__) == FMC_NORSRAM_BANK2) || \
  63                                         ((__BANK__) == FMC_NORSRAM_BANK3) || \
  64                                         ((__BANK__) == FMC_NORSRAM_BANK4))
  65
  66 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
  67                               ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
  68
  69 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
  70                                     ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
  71                                     ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
  72
  73 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
  74                                                  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
  75                                                  ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
  76
  77 #define IS_FMC_WRITE_BURST(__BURST__)          (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
  78                                                 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
  79
  80 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__)     (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
  81                                                 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
  82
  83 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
  84                                        ((__MODE__) == FMC_ACCESS_MODE_B) || \
  85                                        ((__MODE__) == FMC_ACCESS_MODE_C) || \
  86                                        ((__MODE__) == FMC_ACCESS_MODE_D))
  87
  88 #define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
  89                                 ((__BANK__) == FMC_NAND_BANK3))
  90
  91 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
  92                                       ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
  93
  94 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
  95                                          ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
  96
  97 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
  98                                  ((__STATE__) == FMC_NAND_ECC_ENABLE))
  99
 100 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \
 101                                    ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \
 102                                    ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
 103                                    ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
 104                                    ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
 105                                    ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
 106
 107 /** @defgroup FMC_TCLR_Setup_Time FMC_TCLR_Setup_Time
 108   * @{
 109   */
 110 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
 111 /**
 112   * @}
 113   */
 114
 115 /** @defgroup FMC_TAR_Setup_Time FMC_TAR_Setup_Time
 116   * @{
 117   */
 118 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255)
 119 /**
 120   * @}
 121   */
 122
 123 /** @defgroup FMC_Setup_Time FMC_Setup_Time
 124   * @{
 125   */
 126 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 255)
 127 /**
 128   * @}
 129   */
 130
 131 /** @defgroup FMC_Wait_Setup_Time FMC_Wait_Setup_Time
 132   * @{
 133   */
 134 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 255)
 135 /**
 136   * @}
 137   */
 138
 139 /** @defgroup FMC_Hold_Setup_Time FMC_Hold_Setup_Time
 140   * @{
 141   */
 142 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 255)
 143 /**
 144   * @}
 145   */
 146
 147 /** @defgroup FMC_HiZ_Setup_Time FMC_HiZ_Setup_Time
 148   * @{
 149   */
 150 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 255)
 151 /**
 152   * @}
 153   */
 154
 155 /** @defgroup FMC_NORSRAM_Device_Instance FMC NOR/SRAM Device Instance
 156   * @{
 157   */
 158
 159 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
 160
 161 /**
 162   * @}
 163   */
 164
 165 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NOR/SRAM EXTENDED Device Instance
 166   * @{
 167   */
 168
 169 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
 170
 171 /**
 172   * @}
 173   */
 174
 175 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
 176   * @{
 177   */
 178 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
 179 /**
 180   * @}
 181   */
 182
 183 /** @defgroup FMC_PCCARD_Device_Instance FMC PCCARD Device Instance
 184   * @{
 185   */
 186 #define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
 187
 188 /**
 189   * @}
 190   */
 191 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
 192                                       ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
 193
 194 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
 195                                              ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
 196
 197 #define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
 198                                      ((__MODE__) == FMC_WRAP_MODE_ENABLE))
 199
 200 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
 201                                                 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
 202
 203 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
 204                                                 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
 205
 206 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
 207                                           ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
 208
 209 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
 210                                          ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
 211
 212 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
 213                                      ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
 214
 215 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
 216
 217 /** @defgroup FMC_Data_Latency FMC Data Latency
 218   * @{
 219   */
 220 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
 221 /**
 222   * @}
 223   */
 224
 225 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
 226   * @{
 227   */
 228 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
 229 /**
 230   * @}
 231   */
 232
 233 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
 234   * @{
 235   */
 236 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
 237 /**
 238   * @}
 239   */
 240
 241 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
 242   * @{
 243   */
 244 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
 245 /**
 246   * @}
 247   */
 248
 249 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
 250   * @{
 251   */
 252 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
 253 /**
 254   * @}
 255   */
 256
 257 /**
 258   * @}
 259   */
 260
 261 /* Exported typedef ----------------------------------------------------------*/
 262
 263 /** @defgroup FMC_NORSRAM_Exported_typedef FMC Low Layer Exported Types
 264   * @{
 265   */
 266
 267 #define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef
 268 #define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef
 269 #define FMC_NAND_TypeDef               FMC_Bank2_3_TypeDef
 270 #define FMC_PCCARD_TypeDef             FMC_Bank4_TypeDef
 271
 272 #define FMC_NORSRAM_DEVICE             FMC_Bank1
 273 #define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E
 274 #define FMC_NAND_DEVICE                FMC_Bank2_3
 275 #define FMC_PCCARD_DEVICE              FMC_Bank4
 276
 277 /**
 278   * @brief  FMC_NORSRAM Configuration Structure definition
 279   */
 280 typedef struct
 281 {
 282   uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
 283                                               This parameter can be a value of @ref FMC_NORSRAM_Bank                     */
 284
 285   uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
 286                                               multiplexed on the data bus or not.
 287                                               This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */
 288
 289   uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
 290                                               the corresponding memory device.
 291                                               This parameter can be a value of @ref FMC_Memory_Type                      */
 292
 293   uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
 294                                               This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */
 295
 296   uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
 297                                               valid only with synchronous burst Flash memories.
 298                                               This parameter can be a value of @ref FMC_Burst_Access_Mode                */
 299
 300   uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
 301                                               the Flash memory in burst mode.
 302                                               This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */
 303
 304   uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
 305                                               memory, valid only when accessing Flash memories in burst mode.
 306                                               This parameter can be a value of @ref FMC_Wrap_Mode                        */
 307
 308   uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
 309                                               clock cycle before the wait state or during the wait state,
 310                                               valid only when accessing memories in burst mode.
 311                                               This parameter can be a value of @ref FMC_Wait_Timing                      */
 312
 313   uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.
 314                                               This parameter can be a value of @ref FMC_Write_Operation                  */
 315
 316   uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
 317                                               signal, valid for Flash memory access in burst mode.
 318                                               This parameter can be a value of @ref FMC_Wait_Signal                      */
 319
 320   uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
 321                                               This parameter can be a value of @ref FMC_Extended_Mode                    */
 322
 323   uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
 324                                               valid only with asynchronous Flash memories.
 325                                               This parameter can be a value of @ref FMC_AsynchronousWait                 */
 326
 327   uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
 328                                               This parameter can be a value of @ref FMC_Write_Burst                      */
 329
 330   uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.
 331                                               This parameter is only enabled through the FMC_BCR1 register, and don't care
 332                                               through FMC_BCR2..4 registers.
 333                                               This parameter can be a value of @ref FMC_Continous_Clock                  */
 334
 335 }FMC_NORSRAM_InitTypeDef;
 336
 337 /**
 338   * @brief  FMC_NORSRAM Timing parameters structure definition
 339   */
 340 typedef struct
 341 {
 342   uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
 343                                               the duration of the address setup time.
 344                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 345                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 346
 347   uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
 348                                               the duration of the address hold time.
 349                                               This parameter can be a value between Min_Data = 1 and Max_Data = 15.
 350                                               @note This parameter is not used with synchronous NOR Flash memories.      */
 351
 352   uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
 353                                               the duration of the data setup time.
 354                                               This parameter can be a value between Min_Data = 1 and Max_Data = 255.
 355                                               @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
 356                                               NOR Flash memories.                                                        */
 357
 358   uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
 359                                               the duration of the bus turnaround.
 360                                               This parameter can be a value between Min_Data = 0 and Max_Data = 15.
 361                                               @note This parameter is only used for multiplexed NOR Flash memories.      */
 362
 363   uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of
 364                                               HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
 365                                               @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
 366                                               accesses.                                                                  */
 367
 368   uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
 369                                               to the memory before getting the first data.
 370                                               The parameter value depends on the memory type as shown below:
 371                                               - It must be set to 0 in case of a CRAM
 372                                               - It is don't care in asynchronous NOR, SRAM or ROM accesses
 373                                               - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
 374                                                 with synchronous burst mode enable                                       */
 375
 376   uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.
 377                                               This parameter can be a value of @ref FMC_Access_Mode                      */
 378
 379 }FMC_NORSRAM_TimingTypeDef;
 380
 381 /**
 382   * @brief  FMC_NAND Configuration Structure definition
 383   */
 384 typedef struct
 385 {
 386   uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.
 387                                         This parameter can be a value of @ref FMC_NAND_Bank                    */
 388
 389   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.
 390                                         This parameter can be any value of @ref FMC_Wait_feature               */
 391
 392   uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.
 393                                         This parameter can be any value of @ref FMC_NAND_Data_Width            */
 394
 395   uint32_t EccComputation;         /*!< Enables or disables the ECC computation.
 396                                         This parameter can be any value of @ref FMC_ECC                        */
 397
 398   uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.
 399                                         This parameter can be any value of @ref FMC_ECC_Page_Size              */
 400
 401   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 402                                         delay between CLE low and RE low.
 403                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 404
 405   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 406                                         delay between ALE low and RE low.
 407                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 408
 409 }FMC_NAND_InitTypeDef;
 410
 411 /**
 412   * @brief  FMC_NAND_PCC Timing parameters structure definition
 413   */
 414 typedef struct
 415 {
 416   uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before
 417                                       the command assertion for NAND-Flash read or write access
 418                                       to common/Attribute or I/O memory space (depending on
 419                                       the memory space timing to be configured).
 420                                       This parameter can be a value between Min_Data = 0 and Max_Data = 255    */
 421
 422   uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the
 423                                       command for NAND-Flash read or write access to
 424                                       common/Attribute or I/O memory space (depending on the
 425                                       memory space timing to be configured).
 426                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 427
 428   uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address
 429                                       (and data for write access) after the command de-assertion
 430                                       for NAND-Flash read or write access to common/Attribute
 431                                       or I/O memory space (depending on the memory space timing
 432                                       to be configured).
 433                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 434
 435   uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the
 436                                       data bus is kept in HiZ after the start of a NAND-Flash
 437                                       write access to common/Attribute or I/O memory space (depending
 438                                       on the memory space timing to be configured).
 439                                       This parameter can be a number between Min_Data = 0 and Max_Data = 255   */
 440
 441 }FMC_NAND_PCC_TimingTypeDef;
 442
 443 /**
 444   * @brief  FMC_NAND Configuration Structure definition
 445   */
 446 typedef struct
 447 {
 448   uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the PCCARD Memory device.
 449                                         This parameter can be any value of @ref FMC_Wait_feature               */
 450
 451   uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the
 452                                         delay between CLE low and RE low.
 453                                         This parameter can be a value between Min_Data = 0 and Max_Data = 255  */
 454
 455   uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the
 456                                         delay between ALE low and RE low.
 457                                         This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
 458
 459 }FMC_PCCARD_InitTypeDef;
 460
 461 /**
 462   * @}
 463   */
 464
 465 /* Exported constants --------------------------------------------------------*/
 466
 467 /** @defgroup FMC_Exported_Constants FMC Low Layer Exported Constants
 468   * @{
 469   */
 470
 471 /** @defgroup FMC_NORSRAM_Exported_constants FMC NOR/SRAM Exported constants
 472   * @{
 473   */
 474
 475 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
 476   * @{
 477   */
 478 #define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
 479 #define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
 480 #define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
 481 #define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
 482
 483 /**
 484   * @}
 485   */
 486
 487 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
 488   * @{
 489   */
 490
 491 #define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
 492 #define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FMC_BCRx_MUXEN)
 493
 494 /**
 495   * @}
 496   */
 497
 498 /** @defgroup FMC_Memory_Type FMC Memory Type
 499   * @{
 500   */
 501
 502 #define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
 503 #define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FMC_BCRx_MTYP_0)
 504 #define FMC_MEMORY_TYPE_NOR                     ((uint32_t)FMC_BCRx_MTYP_1)
 505
 506 /**
 507   * @}
 508   */
 509
 510 /** @defgroup FMC_NORSRAM_Data_Width FMC NOR/SRAM Data Width
 511   * @{
 512   */
 513
 514 #define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
 515 #define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FMC_BCRx_MWID_0)
 516 #define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FMC_BCRx_MWID_1)
 517
 518 /**
 519   * @}
 520   */
 521
 522 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
 523   * @{
 524   */
 525
 526 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FMC_BCRx_FACCEN)
 527 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
 528 /**
 529   * @}
 530   */
 531
 532 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
 533   * @{
 534   */
 535
 536 #define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
 537 #define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FMC_BCRx_BURSTEN)
 538
 539 /**
 540   * @}
 541   */
 542
 543
 544 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
 545   * @{
 546   */
 547
 548 #define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
 549 #define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FMC_BCRx_WAITPOL)
 550
 551 /**
 552   * @}
 553   */
 554
 555 /** @defgroup FMC_Wrap_Mode FMC Wrap Mode
 556   * @{
 557   */
 558
 559 #define FMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
 560 #define FMC_WRAP_MODE_ENABLE                    ((uint32_t)FMC_BCRx_WRAPMOD)
 561
 562 /**
 563   * @}
 564   */
 565
 566 /** @defgroup FMC_Wait_Timing FMC Wait Timing
 567   * @{
 568   */
 569
 570 #define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
 571 #define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)FMC_BCRx_WAITCFG)
 572
 573 /**
 574   * @}
 575   */
 576
 577 /** @defgroup FMC_Write_Operation FMC Write Operation
 578   * @{
 579   */
 580
 581 #define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
 582 #define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)FMC_BCRx_WREN)
 583
 584 /**
 585   * @}
 586   */
 587
 588 /** @defgroup FMC_Wait_Signal FMC Wait Signal
 589   * @{
 590   */
 591
 592 #define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
 593 #define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FMC_BCRx_WAITEN)
 594
 595 /**
 596   * @}
 597   */
 598
 599 /** @defgroup FMC_Extended_Mode FMC Extended Mode
 600   * @{
 601   */
 602
 603 #define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
 604 #define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)FMC_BCRx_EXTMOD)
 605
 606 /**
 607   * @}
 608   */
 609
 610 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
 611   * @{
 612   */
 613
 614 #define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
 615 #define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FMC_BCRx_ASYNCWAIT)
 616
 617 /**
 618   * @}
 619   */
 620
 621 /** @defgroup FMC_Write_Burst FMC Write Burst
 622   * @{
 623   */
 624
 625 #define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
 626 #define FMC_WRITE_BURST_ENABLE                  ((uint32_t)FMC_BCRx_CBURSTRW)
 627
 628 /**
 629   * @}
 630   */
 631
 632 /** @defgroup FMC_Continous_Clock FMC Continous Clock
 633   * @{
 634   */
 635 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)
 636 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)FMC_BCR1_CCLKEN)
 637 /**
 638   * @}
 639   */
 640
 641 /** @defgroup FMC_Access_Mode FMC Access Mode
 642   * @{
 643   */
 644
 645 #define FMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
 646 #define FMC_ACCESS_MODE_B                        ((uint32_t)FMC_BTRx_ACCMOD_0)
 647 #define FMC_ACCESS_MODE_C                        ((uint32_t)FMC_BTRx_ACCMOD_1)
 648 #define FMC_ACCESS_MODE_D                        ((uint32_t)(FMC_BTRx_ACCMOD_0 | FMC_BTRx_ACCMOD_1))
 649
 650 /**
 651   * @}
 652   */
 653
 654 /**
 655   * @}
 656   */
 657
 658 /** @defgroup FMC_NAND_Controller FMC NAND and PCCARD Controller
 659   * @{
 660   */
 661
 662 /** @defgroup FMC_NAND_Bank FMC NAND Bank
 663   * @{
 664   */
 665 #define FMC_NAND_BANK2                          ((uint32_t)0x00000010)
 666 #define FMC_NAND_BANK3                          ((uint32_t)0x00000100)
 667
 668 /**
 669   * @}
 670   */
 671
 672 /** @defgroup FMC_Wait_feature FMC Wait feature
 673   * @{
 674   */
 675 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)
 676 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE            ((uint32_t)FMC_PCRx_PWAITEN)
 677
 678 /**
 679   * @}
 680   */
 681
 682 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
 683   * @{
 684   */
 685 #define FMC_PCR_MEMORY_TYPE_PCCARD        ((uint32_t)0x00000000)
 686 #define FMC_PCR_MEMORY_TYPE_NAND          ((uint32_t)FMC_PCRx_PTYP)
 687 /**
 688   * @}
 689   */
 690
 691 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
 692   * @{
 693   */
 694 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)
 695 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16               ((uint32_t)FMC_PCRx_PWID_0)
 696
 697 /**
 698   * @}
 699   */
 700
 701 /** @defgroup FMC_ECC FMC NAND ECC
 702   * @{
 703   */
 704 #define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)
 705 #define FMC_NAND_ECC_ENABLE                     ((uint32_t)FMC_PCRx_ECCEN)
 706
 707 /**
 708   * @}
 709   */
 710
 711 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
 712   * @{
 713   */
 714 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)
 715 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)FMC_PCRx_ECCPS_0)
 716 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)FMC_PCRx_ECCPS_1)
 717 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_1)
 718 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)FMC_PCRx_ECCPS_2)
 719 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)FMC_PCRx_ECCPS_0|FMC_PCRx_ECCPS_2)
 720
 721 /**
 722   * @}
 723   */
 724
 725 /** @defgroup FMC_Interrupt_definition FMC Interrupt definition
 726   * @brief FMC Interrupt definition
 727   * @{
 728   */
 729 #define FMC_IT_RISING_EDGE                ((uint32_t)FMC_SRx_IREN)
 730 #define FMC_IT_LEVEL                      ((uint32_t)FMC_SRx_ILEN)
 731 #define FMC_IT_FALLING_EDGE               ((uint32_t)FMC_SRx_IFEN)
 732
 733 /**
 734   * @}
 735   */
 736
 737 /** @defgroup FMC_Flag_definition FMC Flag definition
 738   * @brief FMC Flag definition
 739   * @{
 740   */
 741 #define FMC_FLAG_RISING_EDGE                    ((uint32_t)FMC_SRx_IRS)
 742 #define FMC_FLAG_LEVEL                          ((uint32_t)FMC_SRx_ILS)
 743 #define FMC_FLAG_FALLING_EDGE                   ((uint32_t)FMC_SRx_IFS)
 744 #define FMC_FLAG_FEMPT                          ((uint32_t)FMC_SRx_FEMPT)
 745
 746 /**
 747   * @}
 748   */
 749
 750 /**
 751   * @}
 752   */
 753
 754 /**
 755   * @}
 756   */
 757
 758 /* Exported macro ------------------------------------------------------------*/
 759
 760 /** @defgroup FMC_Exported_Macros FMC Low Layer Exported Macros
 761   * @{
 762   */
 763
 764 /** @defgroup FMC_NOR_Macros FMC NOR/SRAM Exported Macros
 765  *  @brief macros to handle NOR device enable/disable and read/write operations
 766  *  @{
 767  */
 768
 769 /**
 770   * @brief  Enable the NORSRAM device access.
 771   * @param  __INSTANCE__ FMC_NORSRAM Instance
 772   * @param  __BANK__ FMC_NORSRAM Bank
 773   * @retval none
 774   */
 775 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  SET_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
 776
 777 /**
 778   * @brief  Disable the NORSRAM device access.
 779   * @param  __INSTANCE__ FMC_NORSRAM Instance
 780   * @param  __BANK__ FMC_NORSRAM Bank
 781   * @retval none
 782   */
 783 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->BTCR[(__BANK__)], FMC_BCRx_MBKEN)
 784
 785 /**
 786   * @}
 787   */
 788
 789 /** @defgroup FMC_NAND_Macros FMC NAND Macros
 790  *  @brief macros to handle NAND device enable/disable
 791  *  @{
 792  */
 793
 794 /**
 795   * @brief  Enable the NAND device access.
 796   * @param  __INSTANCE__ FMC_NAND Instance
 797   * @param  __BANK__ FMC_NAND Bank
 798   * @retval None
 799   */
 800 #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__)  (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
 801                                                     SET_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
 802
 803 /**
 804   * @brief  Disable the NAND device access.
 805   * @param  __INSTANCE__ FMC_NAND Instance
 806   * @param  __BANK__ FMC_NAND Bank
 807   * @retval None
 808   */
 809 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
 810                                                    CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
 811
 812 /**
 813   * @}
 814   */
 815
 816 /** @defgroup FMC_PCCARD_Macros FMC PCCARD Macros
 817  *  @brief macros to handle PCCARD read/write operations
 818  *  @{
 819  */
 820
 821 /**
 822   * @brief  Enable the PCCARD device access.
 823   * @param  __INSTANCE__ FMC_PCCARD Instance
 824   * @retval None
 825   */
 826 #define __FMC_PCCARD_ENABLE(__INSTANCE__)  SET_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
 827
 828 /**
 829   * @brief  Disable the PCCARD device access.
 830   * @param  __INSTANCE__ FMC_PCCARD Instance
 831   * @retval None
 832   */
 833 #define __FMC_PCCARD_DISABLE(__INSTANCE__) CLEAR_BIT((__INSTANCE__)->PCR4, FMC_PCRx_PBKEN)
 834 /**
 835   * @}
 836   */
 837
 838 /** @defgroup FMC_Interrupt FMC Interrupt
 839  *  @brief macros to handle FMC interrupts
 840  * @{
 841  */
 842
 843 /**
 844   * @brief  Enable the NAND device interrupt.
 845   * @param  __INSTANCE__  FMC_NAND Instance
 846   * @param  __BANK__      FMC_NAND Bank
 847   * @param  __INTERRUPT__ FMC_NAND interrupt
 848   *         This parameter can be any combination of the following values:
 849   *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
 850   *            @arg FMC_IT_LEVEL Interrupt level.
 851   *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
 852   * @retval None
 853   */
 854 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? SET_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
 855                                                                                                         SET_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
 856
 857 /**
 858   * @brief  Disable the NAND device interrupt.
 859   * @param  __INSTANCE__  FMC_NAND Instance
 860   * @param  __BANK__      FMC_NAND Bank
 861   * @param  __INTERRUPT__ FMC_NAND interrupt
 862   *         This parameter can be any combination of the following values:
 863   *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
 864   *            @arg FMC_IT_LEVEL Interrupt level.
 865   *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
 866   * @retval None
 867   */
 868 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__)  (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__INTERRUPT__)): \
 869                                                                                                          CLEAR_BIT((__INSTANCE__)->SR3, (__INTERRUPT__)))
 870
 871 /**
 872   * @brief  Get flag status of the NAND device.
 873   * @param  __INSTANCE__ FMC_NAND Instance
 874   * @param  __BANK__     FMC_NAND Bank
 875   * @param  __FLAG__ FMC_NAND flag
 876   *         This parameter can be any combination of the following values:
 877   *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
 878   *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
 879   *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
 880   *            @arg FMC_FLAG_FEMPT FIFO empty flag.
 881   * @retval The state of FLAG (SET or RESET).
 882   */
 883 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
 884                                                                                                    (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
 885
 886 /**
 887   * @brief  Clear flag status of the NAND device.
 888   * @param  __INSTANCE__ FMC_NAND Instance
 889   * @param  __BANK__     FMC_NAND Bank
 890   * @param  __FLAG__ FMC_NAND flag
 891   *         This parameter can be any combination of the following values:
 892   *            @arg FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
 893   *            @arg FMC_FLAG_LEVEL Interrupt level edge flag.
 894   *            @arg FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
 895   *            @arg FMC_FLAG_FEMPT FIFO empty flag.
 896   * @retval None
 897   */
 898 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->SR2, (__FLAG__)): \
 899                                                                                                     CLEAR_BIT((__INSTANCE__)->SR3, (__FLAG__)))
 900
 901 /**
 902   * @brief  Enable the PCCARD device interrupt.
 903   * @param  __INSTANCE__ FMC_PCCARD Instance
 904   * @param  __INTERRUPT__ FMC_PCCARD interrupt
 905   *         This parameter can be any combination of the following values:
 906   *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
 907   *            @arg FMC_IT_LEVEL Interrupt level.
 908   *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
 909   * @retval None
 910   */
 911 #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  SET_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
 912
 913 /**
 914   * @brief  Disable the PCCARD device interrupt.
 915   * @param  __INSTANCE__ FMC_PCCARD Instance
 916   * @param  __INTERRUPT__ FMC_PCCARD interrupt
 917   *         This parameter can be any combination of the following values:
 918   *            @arg FMC_IT_RISING_EDGE Interrupt rising edge.
 919   *            @arg FMC_IT_LEVEL Interrupt level.
 920   *            @arg FMC_IT_FALLING_EDGE Interrupt falling edge.
 921   * @retval None
 922   */
 923 #define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  CLEAR_BIT((__INSTANCE__)->SR4, (__INTERRUPT__))
 924
 925 /**
 926   * @brief  Get flag status of the PCCARD device.
 927   * @param  __INSTANCE__ FMC_PCCARD Instance
 928   * @param  __FLAG__ FMC_PCCARD flag
 929   *         This parameter can be any combination of the following values:
 930   *            @arg  FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
 931   *            @arg  FMC_FLAG_LEVEL Interrupt level edge flag.
 932   *            @arg  FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
 933   *            @arg  FMC_FLAG_FEMPT FIFO empty flag.
 934   * @retval The state of FLAG (SET or RESET).
 935   */
 936 #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
 937
 938 /**
 939   * @brief  Clear flag status of the PCCARD device.
 940   * @param  __INSTANCE__ FMC_PCCARD Instance
 941   * @param  __FLAG__ FMC_PCCARD flag
 942   *         This parameter can be any combination of the following values:
 943   *            @arg  FMC_FLAG_RISING_EDGE Interrupt rising edge flag.
 944   *            @arg  FMC_FLAG_LEVEL Interrupt level edge flag.
 945   *            @arg  FMC_FLAG_FALLING_EDGE Interrupt falling edge flag.
 946   *            @arg  FMC_FLAG_FEMPT FIFO empty flag.
 947   * @retval None
 948   */
 949 #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__)  CLEAR_BIT((__INSTANCE__)->SR4, (__FLAG__))
 950
 951 /**
 952   * @}
 953   */
 954
 955
 956 /**
 957   * @}
 958   */
 959
 960 /* Exported functions --------------------------------------------------------*/
 961
 962 /** @addtogroup FMC_LL_Exported_Functions
 963  *  @{
 964  */
 965
 966 /** @addtogroup FMC_NORSRAM
 967  *  @{
 968  */
 969
 970 /** @addtogroup FMC_NORSRAM_Group1
 971  *  @{
 972  */
 973
 974 /* FMC_NORSRAM Controller functions ******************************************/
 975 /* Initialization/de-initialization functions */
 976 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
 977 HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
 978 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
 979 HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
 980
 981 /**
 982   * @}
 983   */
 984
 985 /** @addtogroup FMC_NORSRAM_Group2
 986  *  @{
 987  */
 988
 989 /* FMC_NORSRAM Control functions */
 990 HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 991 HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
 992
 993 /**
 994   * @}
 995   */
 996
 997 /**
 998   * @}
 999   */
1000
1001 /** @addtogroup FMC_NAND
1002  *  @{
1003  */
1004
1005 /* FMC_NAND Controller functions **********************************************/
1006 /* Initialization/de-initialization functions */
1007 /** @addtogroup FMC_NAND_Exported_Functions_Group1
1008  *  @{
1009  */
1010
1011 HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1012 HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1013 HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1014 HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1015
1016 /**
1017   * @}
1018   */
1019
1020 /* FMC_NAND Control functions */
1021 /** @addtogroup FMC_NAND_Exported_Functions_Group2
1022  *  @{
1023  */
1024
1025 HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1026 HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1027 HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1028
1029 /**
1030   * @}
1031   */
1032
1033 /**
1034   * @}
1035   */
1036
1037 /** @addtogroup FMC_PCCARD
1038  *  @{
1039  */
1040
1041 /* FMC_PCCARD Controller functions ********************************************/
1042 /* Initialization/de-initialization functions */
1043 /** @addtogroup FMC_PCCARD_Exported_Functions_Group1
1044  *  @{
1045  */
1046
1047 HAL_StatusTypeDef  FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
1048 HAL_StatusTypeDef  FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1049 HAL_StatusTypeDef  FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1050 HAL_StatusTypeDef  FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing);
1051 HAL_StatusTypeDef  FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1052
1053 /**
1054   * @}
1055   */
1056
1057 /**
1058   * @}
1059   */
1060
1061 /**
1062   * @}
1063   */
1064
1065 /**
1066   * @}
1067   */
1068
1069 #endif /* FMC_BANK1 */
1070
1071 /**
1072   * @}
1073   */
1074
1075 #ifdef __cplusplus
1076 }
1077 #endif
1078
1079 #endif /* __STM32F3xx_LL_FMC_H */
1080
1081 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1082