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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_i2c.h
blob8e4a5b769f0ce0163dd98e2a213fae4513a127ff
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_i2c.h
4 * @author MCD Application Team
5 * @brief Header file of I2C LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_I2C_H
38 #define __STM32F3xx_LL_I2C_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx.h"
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 #if defined (I2C1) || defined (I2C2) || defined (I2C3)
52
53 /** @defgroup I2C_LL I2C
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59
60 /* Private constants ---------------------------------------------------------*/
61 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
62 * @{
63 */
64 /**
65 * @}
66 */
67
68 /* Private macros ------------------------------------------------------------*/
69 #if defined(USE_FULL_LL_DRIVER)
70 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
71 * @{
72 */
73 /**
74 * @}
75 */
76 #endif /*USE_FULL_LL_DRIVER*/
77
78 /* Exported types ------------------------------------------------------------*/
79 #if defined(USE_FULL_LL_DRIVER)
80 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
81 * @{
82 */
83 typedef struct
84 {
85 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
86 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
87
88 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
89
90 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
91 This parameter must be set by referring to the STM32CubeMX Tool and
92 the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
93
94 This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
95
96 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
97 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
98
99 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
100
101 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
102 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
103
104 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
105
106 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
107 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
108
109 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
110
111 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
112 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
113
114 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
115
116 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
117 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
118
119 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
120 } LL_I2C_InitTypeDef;
121 /**
122 * @}
123 */
124 #endif /*USE_FULL_LL_DRIVER*/
125
126 /* Exported constants --------------------------------------------------------*/
127 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
128 * @{
129 */
130
131 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
132 * @brief Flags defines which can be used with LL_I2C_WriteReg function
133 * @{
134 */
135 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
136 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
137 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
138 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
139 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
140 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
141 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
142 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
143 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
144 /**
145 * @}
146 */
147
148 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
149 * @brief Flags defines which can be used with LL_I2C_ReadReg function
150 * @{
151 */
152 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
153 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
154 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
155 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
156 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
157 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
158 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
159 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
160 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
161 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
162 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
163 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
164 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
165 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
166 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
167 /**
168 * @}
169 */
170
171 /** @defgroup I2C_LL_EC_IT IT Defines
172 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
173 * @{
174 */
175 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
176 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
177 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
178 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
179 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
180 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
181 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
182 /**
183 * @}
184 */
185
186 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
187 * @{
188 */
189 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
190 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
191 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
192 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
193 /**
194 * @}
195 */
196
197 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
198 * @{
199 */
200 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
201 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
202 /**
203 * @}
204 */
205
206 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
207 * @{
208 */
209 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
210 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
211 /**
212 * @}
213 */
214
215 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
216 * @{
217 */
218 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
219 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
220 /**
221 * @}
222 */
223
224 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
225 * @{
226 */
227 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
228 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
229 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
230 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
231 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
232 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
233 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
234 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
235 /**
236 * @}
237 */
238
239 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
240 * @{
241 */
242 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
243 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
244 /**
245 * @}
246 */
247
248 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
249 * @{
250 */
251 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
252 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
253 /**
254 * @}
255 */
256
257 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
258 * @{
259 */
260 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
261 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
262 /**
263 * @}
264 */
265
266 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
267 * @{
268 */
269 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
270 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
271 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
272 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
273 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
274 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
275 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
276 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
277 /**
278 * @}
279 */
280
281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
282 * @{
283 */
284 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
285 #define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
286 #define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
287 #define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
288 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
289 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
290 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
291 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
292 /**
293 * @}
294 */
295
296 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
297 * @{
298 */
299 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
300 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
301 /**
302 * @}
303 */
304
305 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
306 * @{
307 */
308 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
309 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
310 /**
311 * @}
312 */
313
314 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
315 * @{
316 */
317 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
318 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
319 /**
320 * @}
321 */
322
323 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
324 * @{
325 */
326 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
327 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
328 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /* Exported macro ------------------------------------------------------------*/
338 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
339 * @{
340 */
341
342 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
343 * @{
344 */
345
346 /**
347 * @brief Write a value in I2C register
348 * @param __INSTANCE__ I2C Instance
349 * @param __REG__ Register to be written
350 * @param __VALUE__ Value to be written in the register
351 * @retval None
352 */
353 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
354
355 /**
356 * @brief Read a value in I2C register
357 * @param __INSTANCE__ I2C Instance
358 * @param __REG__ Register to be read
359 * @retval Register value
360 */
361 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
362 /**
363 * @}
364 */
365
366 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
367 * @{
368 */
369 /**
370 * @brief Configure the SDA setup, hold time and the SCL high, low period.
371 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
372 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
373 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
374 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
375 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
376 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
377 */
378 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
379 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
380 (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
381 (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
382 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
383 (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
384 /**
385 * @}
386 */
387
388 /**
389 * @}
390 */
391
392 /* Exported functions --------------------------------------------------------*/
393 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
394 * @{
395 */
396
397 /** @defgroup I2C_LL_EF_Configuration Configuration
398 * @{
399 */
400
401 /**
402 * @brief Enable I2C peripheral (PE = 1).
403 * @rmtoll CR1 PE LL_I2C_Enable
404 * @param I2Cx I2C Instance.
405 * @retval None
406 */
407 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
408 {
409 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
410 }
411
412 /**
413 * @brief Disable I2C peripheral (PE = 0).
414 * @note When PE = 0, the I2C SCL and SDA lines are released.
415 * Internal state machines and status bits are put back to their reset value.
416 * When cleared, PE must be kept low for at least 3 APB clock cycles.
417 * @rmtoll CR1 PE LL_I2C_Disable
418 * @param I2Cx I2C Instance.
419 * @retval None
420 */
421 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
422 {
423 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
424 }
425
426 /**
427 * @brief Check if the I2C peripheral is enabled or disabled.
428 * @rmtoll CR1 PE LL_I2C_IsEnabled
429 * @param I2Cx I2C Instance.
430 * @retval State of bit (1 or 0).
431 */
432 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
433 {
434 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
435 }
436
437 /**
438 * @brief Configure Noise Filters (Analog and Digital).
439 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
440 * The filters can only be programmed when the I2C is disabled (PE = 0).
441 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
442 * CR1 DNF LL_I2C_ConfigFilters
443 * @param I2Cx I2C Instance.
444 * @param AnalogFilter This parameter can be one of the following values:
445 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
446 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
447 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
448 * This parameter is used to configure the digital noise filter on SDA and SCL input.
449 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
450 * @retval None
451 */
452 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
453 {
454 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
455 }
456
457 /**
458 * @brief Configure Digital Noise Filter.
459 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
460 * This filter can only be programmed when the I2C is disabled (PE = 0).
461 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
462 * @param I2Cx I2C Instance.
463 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
464 * This parameter is used to configure the digital noise filter on SDA and SCL input.
465 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
466 * @retval None
467 */
468 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
469 {
470 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
471 }
472
473 /**
474 * @brief Get the current Digital Noise Filter configuration.
475 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
476 * @param I2Cx I2C Instance.
477 * @retval Value between Min_Data=0x0 and Max_Data=0xF
478 */
479 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
480 {
481 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
482 }
483
484 /**
485 * @brief Enable Analog Noise Filter.
486 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
487 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
488 * @param I2Cx I2C Instance.
489 * @retval None
490 */
491 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
492 {
493 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
494 }
495
496 /**
497 * @brief Disable Analog Noise Filter.
498 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
499 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
500 * @param I2Cx I2C Instance.
501 * @retval None
502 */
503 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
504 {
505 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
506 }
507
508 /**
509 * @brief Check if Analog Noise Filter is enabled or disabled.
510 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
511 * @param I2Cx I2C Instance.
512 * @retval State of bit (1 or 0).
513 */
514 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
515 {
516 return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
517 }
518
519 /**
520 * @brief Enable DMA transmission requests.
521 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
522 * @param I2Cx I2C Instance.
523 * @retval None
524 */
525 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
526 {
527 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
528 }
529
530 /**
531 * @brief Disable DMA transmission requests.
532 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
533 * @param I2Cx I2C Instance.
534 * @retval None
535 */
536 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
537 {
538 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
539 }
540
541 /**
542 * @brief Check if DMA transmission requests are enabled or disabled.
543 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
544 * @param I2Cx I2C Instance.
545 * @retval State of bit (1 or 0).
546 */
547 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
548 {
549 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
550 }
551
552 /**
553 * @brief Enable DMA reception requests.
554 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
555 * @param I2Cx I2C Instance.
556 * @retval None
557 */
558 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
559 {
560 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
561 }
562
563 /**
564 * @brief Disable DMA reception requests.
565 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
566 * @param I2Cx I2C Instance.
567 * @retval None
568 */
569 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
570 {
571 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
572 }
573
574 /**
575 * @brief Check if DMA reception requests are enabled or disabled.
576 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
577 * @param I2Cx I2C Instance.
578 * @retval State of bit (1 or 0).
579 */
580 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
581 {
582 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
583 }
584
585 /**
586 * @brief Get the data register address used for DMA transfer
587 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
588 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
589 * @param I2Cx I2C Instance
590 * @param Direction This parameter can be one of the following values:
591 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
592 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
593 * @retval Address of data register
594 */
595 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
596 {
597 register uint32_t data_reg_addr = 0U;
598
599 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
600 {
601 /* return address of TXDR register */
602 data_reg_addr = (uint32_t) & (I2Cx->TXDR);
603 }
604 else
605 {
606 /* return address of RXDR register */
607 data_reg_addr = (uint32_t) & (I2Cx->RXDR);
608 }
609
610 return data_reg_addr;
611 }
612
613 /**
614 * @brief Enable Clock stretching.
615 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
616 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
617 * @param I2Cx I2C Instance.
618 * @retval None
619 */
620 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
621 {
622 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
623 }
624
625 /**
626 * @brief Disable Clock stretching.
627 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
628 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
629 * @param I2Cx I2C Instance.
630 * @retval None
631 */
632 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
633 {
634 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
635 }
636
637 /**
638 * @brief Check if Clock stretching is enabled or disabled.
639 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
640 * @param I2Cx I2C Instance.
641 * @retval State of bit (1 or 0).
642 */
643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
644 {
645 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
646 }
647
648 /**
649 * @brief Enable hardware byte control in slave mode.
650 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
651 * @param I2Cx I2C Instance.
652 * @retval None
653 */
654 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
655 {
656 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
657 }
658
659 /**
660 * @brief Disable hardware byte control in slave mode.
661 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
662 * @param I2Cx I2C Instance.
663 * @retval None
664 */
665 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
666 {
667 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
668 }
669
670 /**
671 * @brief Check if hardware byte control in slave mode is enabled or disabled.
672 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
673 * @param I2Cx I2C Instance.
674 * @retval State of bit (1 or 0).
675 */
676 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
677 {
678 return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
679 }
680
681 /**
682 * @brief Enable Wakeup from STOP.
683 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
684 * WakeUpFromStop feature is supported by the I2Cx Instance.
685 * @note This bit can only be programmed when Digital Filter is disabled.
686 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
687 * @param I2Cx I2C Instance.
688 * @retval None
689 */
690 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
691 {
692 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
693 }
694
695 /**
696 * @brief Disable Wakeup from STOP.
697 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
698 * WakeUpFromStop feature is supported by the I2Cx Instance.
699 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
700 * @param I2Cx I2C Instance.
701 * @retval None
702 */
703 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
704 {
705 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
706 }
707
708 /**
709 * @brief Check if Wakeup from STOP is enabled or disabled.
710 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
711 * WakeUpFromStop feature is supported by the I2Cx Instance.
712 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
713 * @param I2Cx I2C Instance.
714 * @retval State of bit (1 or 0).
715 */
716 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
717 {
718 return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
719 }
720
721 /**
722 * @brief Enable General Call.
723 * @note When enabled the Address 0x00 is ACKed.
724 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
725 * @param I2Cx I2C Instance.
726 * @retval None
727 */
728 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
729 {
730 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
731 }
732
733 /**
734 * @brief Disable General Call.
735 * @note When disabled the Address 0x00 is NACKed.
736 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
737 * @param I2Cx I2C Instance.
738 * @retval None
739 */
740 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
741 {
742 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
743 }
744
745 /**
746 * @brief Check if General Call is enabled or disabled.
747 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
748 * @param I2Cx I2C Instance.
749 * @retval State of bit (1 or 0).
750 */
751 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
752 {
753 return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
754 }
755
756 /**
757 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
758 * @note Changing this bit is not allowed, when the START bit is set.
759 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
760 * @param I2Cx I2C Instance.
761 * @param AddressingMode This parameter can be one of the following values:
762 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
763 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
764 * @retval None
765 */
766 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
767 {
768 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
769 }
770
771 /**
772 * @brief Get the Master addressing mode.
773 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
774 * @param I2Cx I2C Instance.
775 * @retval Returned value can be one of the following values:
776 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
777 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
778 */
779 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
780 {
781 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
782 }
783
784 /**
785 * @brief Set the Own Address1.
786 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
787 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
788 * @param I2Cx I2C Instance.
789 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
790 * @param OwnAddrSize This parameter can be one of the following values:
791 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
792 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
793 * @retval None
794 */
795 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
796 {
797 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
798 }
799
800 /**
801 * @brief Enable acknowledge on Own Address1 match address.
802 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
803 * @param I2Cx I2C Instance.
804 * @retval None
805 */
806 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
807 {
808 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
809 }
810
811 /**
812 * @brief Disable acknowledge on Own Address1 match address.
813 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
814 * @param I2Cx I2C Instance.
815 * @retval None
816 */
817 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
818 {
819 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
820 }
821
822 /**
823 * @brief Check if Own Address1 acknowledge is enabled or disabled.
824 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
825 * @param I2Cx I2C Instance.
826 * @retval State of bit (1 or 0).
827 */
828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
829 {
830 return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
831 }
832
833 /**
834 * @brief Set the 7bits Own Address2.
835 * @note This action has no effect if own address2 is enabled.
836 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
837 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
838 * @param I2Cx I2C Instance.
839 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
840 * @param OwnAddrMask This parameter can be one of the following values:
841 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
842 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
843 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
844 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
845 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
846 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
847 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
848 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
849 * @retval None
850 */
851 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
852 {
853 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
854 }
855
856 /**
857 * @brief Enable acknowledge on Own Address2 match address.
858 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
859 * @param I2Cx I2C Instance.
860 * @retval None
861 */
862 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
863 {
864 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
865 }
866
867 /**
868 * @brief Disable acknowledge on Own Address2 match address.
869 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
870 * @param I2Cx I2C Instance.
871 * @retval None
872 */
873 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
874 {
875 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
876 }
877
878 /**
879 * @brief Check if Own Address1 acknowledge is enabled or disabled.
880 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
881 * @param I2Cx I2C Instance.
882 * @retval State of bit (1 or 0).
883 */
884 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
885 {
886 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
887 }
888
889 /**
890 * @brief Configure the SDA setup, hold time and the SCL high, low period.
891 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
892 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
893 * @param I2Cx I2C Instance.
894 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
895 * @note This parameter is computed with the STM32CubeMX Tool.
896 * @retval None
897 */
898 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
899 {
900 WRITE_REG(I2Cx->TIMINGR, Timing);
901 }
902
903 /**
904 * @brief Get the Timing Prescaler setting.
905 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
906 * @param I2Cx I2C Instance.
907 * @retval Value between Min_Data=0x0 and Max_Data=0xF
908 */
909 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
910 {
911 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
912 }
913
914 /**
915 * @brief Get the SCL low period setting.
916 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
917 * @param I2Cx I2C Instance.
918 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
919 */
920 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
921 {
922 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
923 }
924
925 /**
926 * @brief Get the SCL high period setting.
927 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
928 * @param I2Cx I2C Instance.
929 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
930 */
931 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
932 {
933 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
934 }
935
936 /**
937 * @brief Get the SDA hold time.
938 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
939 * @param I2Cx I2C Instance.
940 * @retval Value between Min_Data=0x0 and Max_Data=0xF
941 */
942 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
943 {
944 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
945 }
946
947 /**
948 * @brief Get the SDA setup time.
949 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
950 * @param I2Cx I2C Instance.
951 * @retval Value between Min_Data=0x0 and Max_Data=0xF
952 */
953 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
954 {
955 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
956 }
957
958 /**
959 * @brief Configure peripheral mode.
960 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
961 * SMBus feature is supported by the I2Cx Instance.
962 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
963 * CR1 SMBDEN LL_I2C_SetMode
964 * @param I2Cx I2C Instance.
965 * @param PeripheralMode This parameter can be one of the following values:
966 * @arg @ref LL_I2C_MODE_I2C
967 * @arg @ref LL_I2C_MODE_SMBUS_HOST
968 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
969 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
970 * @retval None
971 */
972 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
973 {
974 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
975 }
976
977 /**
978 * @brief Get peripheral mode.
979 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
980 * SMBus feature is supported by the I2Cx Instance.
981 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
982 * CR1 SMBDEN LL_I2C_GetMode
983 * @param I2Cx I2C Instance.
984 * @retval Returned value can be one of the following values:
985 * @arg @ref LL_I2C_MODE_I2C
986 * @arg @ref LL_I2C_MODE_SMBUS_HOST
987 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
988 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
989 */
990 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
991 {
992 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
993 }
994
995 /**
996 * @brief Enable SMBus alert (Host or Device mode)
997 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
998 * SMBus feature is supported by the I2Cx Instance.
999 * @note SMBus Device mode:
1000 * - SMBus Alert pin is drived low and
1001 * Alert Response Address Header acknowledge is enabled.
1002 * SMBus Host mode:
1003 * - SMBus Alert pin management is supported.
1004 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
1005 * @param I2Cx I2C Instance.
1006 * @retval None
1007 */
1008 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
1009 {
1010 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1011 }
1012
1013 /**
1014 * @brief Disable SMBus alert (Host or Device mode)
1015 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1016 * SMBus feature is supported by the I2Cx Instance.
1017 * @note SMBus Device mode:
1018 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
1019 * Alert Response Address Header acknowledge is disabled.
1020 * SMBus Host mode:
1021 * - SMBus Alert pin management is not supported.
1022 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
1023 * @param I2Cx I2C Instance.
1024 * @retval None
1025 */
1026 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
1027 {
1028 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
1029 }
1030
1031 /**
1032 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
1033 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1034 * SMBus feature is supported by the I2Cx Instance.
1035 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
1036 * @param I2Cx I2C Instance.
1037 * @retval State of bit (1 or 0).
1038 */
1039 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1040 {
1041 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
1042 }
1043
1044 /**
1045 * @brief Enable SMBus Packet Error Calculation (PEC).
1046 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1047 * SMBus feature is supported by the I2Cx Instance.
1048 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1049 * @param I2Cx I2C Instance.
1050 * @retval None
1051 */
1052 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1053 {
1054 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1055 }
1056
1057 /**
1058 * @brief Disable SMBus Packet Error Calculation (PEC).
1059 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1060 * SMBus feature is supported by the I2Cx Instance.
1061 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1062 * @param I2Cx I2C Instance.
1063 * @retval None
1064 */
1065 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1066 {
1067 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1068 }
1069
1070 /**
1071 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1072 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1073 * SMBus feature is supported by the I2Cx Instance.
1074 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1075 * @param I2Cx I2C Instance.
1076 * @retval State of bit (1 or 0).
1077 */
1078 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1079 {
1080 return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
1081 }
1082
1083 /**
1084 * @brief Configure the SMBus Clock Timeout.
1085 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1086 * SMBus feature is supported by the I2Cx Instance.
1087 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1088 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1089 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1090 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1091 * @param I2Cx I2C Instance.
1092 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1093 * @param TimeoutAMode This parameter can be one of the following values:
1094 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1095 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1096 * @param TimeoutB
1097 * @retval None
1098 */
1099 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1100 uint32_t TimeoutB)
1101 {
1102 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1103 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1104 }
1105
1106 /**
1107 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1108 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1109 * SMBus feature is supported by the I2Cx Instance.
1110 * @note These bits can only be programmed when TimeoutA is disabled.
1111 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1112 * @param I2Cx I2C Instance.
1113 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1114 * @retval None
1115 */
1116 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1117 {
1118 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1119 }
1120
1121 /**
1122 * @brief Get the SMBus Clock TimeoutA setting.
1123 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1124 * SMBus feature is supported by the I2Cx Instance.
1125 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1126 * @param I2Cx I2C Instance.
1127 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1128 */
1129 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1130 {
1131 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1132 }
1133
1134 /**
1135 * @brief Set the SMBus Clock TimeoutA mode.
1136 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1137 * SMBus feature is supported by the I2Cx Instance.
1138 * @note This bit can only be programmed when TimeoutA is disabled.
1139 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1140 * @param I2Cx I2C Instance.
1141 * @param TimeoutAMode This parameter can be one of the following values:
1142 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1143 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1144 * @retval None
1145 */
1146 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1147 {
1148 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1149 }
1150
1151 /**
1152 * @brief Get the SMBus Clock TimeoutA mode.
1153 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1154 * SMBus feature is supported by the I2Cx Instance.
1155 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1156 * @param I2Cx I2C Instance.
1157 * @retval Returned value can be one of the following values:
1158 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1159 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1160 */
1161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1162 {
1163 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1164 }
1165
1166 /**
1167 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1168 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1169 * SMBus feature is supported by the I2Cx Instance.
1170 * @note These bits can only be programmed when TimeoutB is disabled.
1171 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1172 * @param I2Cx I2C Instance.
1173 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1174 * @retval None
1175 */
1176 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1177 {
1178 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1179 }
1180
1181 /**
1182 * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
1183 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1184 * SMBus feature is supported by the I2Cx Instance.
1185 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1186 * @param I2Cx I2C Instance.
1187 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1188 */
1189 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1190 {
1191 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1192 }
1193
1194 /**
1195 * @brief Enable the SMBus Clock Timeout.
1196 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1197 * SMBus feature is supported by the I2Cx Instance.
1198 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1199 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1200 * @param I2Cx I2C Instance.
1201 * @param ClockTimeout This parameter can be one of the following values:
1202 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1203 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1204 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1205 * @retval None
1206 */
1207 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1208 {
1209 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1210 }
1211
1212 /**
1213 * @brief Disable the SMBus Clock Timeout.
1214 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1215 * SMBus feature is supported by the I2Cx Instance.
1216 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1217 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1218 * @param I2Cx I2C Instance.
1219 * @param ClockTimeout This parameter can be one of the following values:
1220 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1221 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1222 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1223 * @retval None
1224 */
1225 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1226 {
1227 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1228 }
1229
1230 /**
1231 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1232 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1233 * SMBus feature is supported by the I2Cx Instance.
1234 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1235 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1236 * @param I2Cx I2C Instance.
1237 * @param ClockTimeout This parameter can be one of the following values:
1238 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1239 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1240 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1241 * @retval State of bit (1 or 0).
1242 */
1243 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1244 {
1245 return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
1246 }
1247
1248 /**
1249 * @}
1250 */
1251
1252 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1253 * @{
1254 */
1255
1256 /**
1257 * @brief Enable TXIS interrupt.
1258 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1259 * @param I2Cx I2C Instance.
1260 * @retval None
1261 */
1262 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1263 {
1264 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1265 }
1266
1267 /**
1268 * @brief Disable TXIS interrupt.
1269 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1270 * @param I2Cx I2C Instance.
1271 * @retval None
1272 */
1273 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1274 {
1275 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1276 }
1277
1278 /**
1279 * @brief Check if the TXIS Interrupt is enabled or disabled.
1280 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1281 * @param I2Cx I2C Instance.
1282 * @retval State of bit (1 or 0).
1283 */
1284 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1285 {
1286 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
1287 }
1288
1289 /**
1290 * @brief Enable RXNE interrupt.
1291 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1292 * @param I2Cx I2C Instance.
1293 * @retval None
1294 */
1295 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1296 {
1297 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1298 }
1299
1300 /**
1301 * @brief Disable RXNE interrupt.
1302 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1303 * @param I2Cx I2C Instance.
1304 * @retval None
1305 */
1306 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1307 {
1308 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1309 }
1310
1311 /**
1312 * @brief Check if the RXNE Interrupt is enabled or disabled.
1313 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1314 * @param I2Cx I2C Instance.
1315 * @retval State of bit (1 or 0).
1316 */
1317 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1318 {
1319 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
1320 }
1321
1322 /**
1323 * @brief Enable Address match interrupt (slave mode only).
1324 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1325 * @param I2Cx I2C Instance.
1326 * @retval None
1327 */
1328 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1329 {
1330 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1331 }
1332
1333 /**
1334 * @brief Disable Address match interrupt (slave mode only).
1335 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1336 * @param I2Cx I2C Instance.
1337 * @retval None
1338 */
1339 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1340 {
1341 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1342 }
1343
1344 /**
1345 * @brief Check if Address match interrupt is enabled or disabled.
1346 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1347 * @param I2Cx I2C Instance.
1348 * @retval State of bit (1 or 0).
1349 */
1350 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1351 {
1352 return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
1353 }
1354
1355 /**
1356 * @brief Enable Not acknowledge received interrupt.
1357 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1358 * @param I2Cx I2C Instance.
1359 * @retval None
1360 */
1361 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1362 {
1363 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1364 }
1365
1366 /**
1367 * @brief Disable Not acknowledge received interrupt.
1368 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1369 * @param I2Cx I2C Instance.
1370 * @retval None
1371 */
1372 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1373 {
1374 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1375 }
1376
1377 /**
1378 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1379 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1380 * @param I2Cx I2C Instance.
1381 * @retval State of bit (1 or 0).
1382 */
1383 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1384 {
1385 return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
1386 }
1387
1388 /**
1389 * @brief Enable STOP detection interrupt.
1390 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1391 * @param I2Cx I2C Instance.
1392 * @retval None
1393 */
1394 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1395 {
1396 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1397 }
1398
1399 /**
1400 * @brief Disable STOP detection interrupt.
1401 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1402 * @param I2Cx I2C Instance.
1403 * @retval None
1404 */
1405 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1406 {
1407 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1408 }
1409
1410 /**
1411 * @brief Check if STOP detection interrupt is enabled or disabled.
1412 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1413 * @param I2Cx I2C Instance.
1414 * @retval State of bit (1 or 0).
1415 */
1416 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1417 {
1418 return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
1419 }
1420
1421 /**
1422 * @brief Enable Transfer Complete interrupt.
1423 * @note Any of these events will generate interrupt :
1424 * Transfer Complete (TC)
1425 * Transfer Complete Reload (TCR)
1426 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1427 * @param I2Cx I2C Instance.
1428 * @retval None
1429 */
1430 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1431 {
1432 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1433 }
1434
1435 /**
1436 * @brief Disable Transfer Complete interrupt.
1437 * @note Any of these events will generate interrupt :
1438 * Transfer Complete (TC)
1439 * Transfer Complete Reload (TCR)
1440 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1441 * @param I2Cx I2C Instance.
1442 * @retval None
1443 */
1444 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1445 {
1446 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1447 }
1448
1449 /**
1450 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1451 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1452 * @param I2Cx I2C Instance.
1453 * @retval State of bit (1 or 0).
1454 */
1455 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1456 {
1457 return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
1458 }
1459
1460 /**
1461 * @brief Enable Error interrupts.
1462 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1463 * SMBus feature is supported by the I2Cx Instance.
1464 * @note Any of these errors will generate interrupt :
1465 * Arbitration Loss (ARLO)
1466 * Bus Error detection (BERR)
1467 * Overrun/Underrun (OVR)
1468 * SMBus Timeout detection (TIMEOUT)
1469 * SMBus PEC error detection (PECERR)
1470 * SMBus Alert pin event detection (ALERT)
1471 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1472 * @param I2Cx I2C Instance.
1473 * @retval None
1474 */
1475 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1476 {
1477 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1478 }
1479
1480 /**
1481 * @brief Disable Error interrupts.
1482 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1483 * SMBus feature is supported by the I2Cx Instance.
1484 * @note Any of these errors will generate interrupt :
1485 * Arbitration Loss (ARLO)
1486 * Bus Error detection (BERR)
1487 * Overrun/Underrun (OVR)
1488 * SMBus Timeout detection (TIMEOUT)
1489 * SMBus PEC error detection (PECERR)
1490 * SMBus Alert pin event detection (ALERT)
1491 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1492 * @param I2Cx I2C Instance.
1493 * @retval None
1494 */
1495 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1496 {
1497 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1498 }
1499
1500 /**
1501 * @brief Check if Error interrupts are enabled or disabled.
1502 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1503 * @param I2Cx I2C Instance.
1504 * @retval State of bit (1 or 0).
1505 */
1506 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1507 {
1508 return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
1509 }
1510
1511 /**
1512 * @}
1513 */
1514
1515 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1516 * @{
1517 */
1518
1519 /**
1520 * @brief Indicate the status of Transmit data register empty flag.
1521 * @note RESET: When next data is written in Transmit data register.
1522 * SET: When Transmit data register is empty.
1523 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1524 * @param I2Cx I2C Instance.
1525 * @retval State of bit (1 or 0).
1526 */
1527 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1528 {
1529 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
1530 }
1531
1532 /**
1533 * @brief Indicate the status of Transmit interrupt flag.
1534 * @note RESET: When next data is written in Transmit data register.
1535 * SET: When Transmit data register is empty.
1536 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1537 * @param I2Cx I2C Instance.
1538 * @retval State of bit (1 or 0).
1539 */
1540 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1541 {
1542 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
1543 }
1544
1545 /**
1546 * @brief Indicate the status of Receive data register not empty flag.
1547 * @note RESET: When Receive data register is read.
1548 * SET: When the received data is copied in Receive data register.
1549 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1550 * @param I2Cx I2C Instance.
1551 * @retval State of bit (1 or 0).
1552 */
1553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1554 {
1555 return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
1556 }
1557
1558 /**
1559 * @brief Indicate the status of Address matched flag (slave mode).
1560 * @note RESET: Clear default value.
1561 * SET: When the received slave address matched with one of the enabled slave address.
1562 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1563 * @param I2Cx I2C Instance.
1564 * @retval State of bit (1 or 0).
1565 */
1566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1567 {
1568 return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
1569 }
1570
1571 /**
1572 * @brief Indicate the status of Not Acknowledge received flag.
1573 * @note RESET: Clear default value.
1574 * SET: When a NACK is received after a byte transmission.
1575 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1576 * @param I2Cx I2C Instance.
1577 * @retval State of bit (1 or 0).
1578 */
1579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1580 {
1581 return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
1582 }
1583
1584 /**
1585 * @brief Indicate the status of Stop detection flag.
1586 * @note RESET: Clear default value.
1587 * SET: When a Stop condition is detected.
1588 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1589 * @param I2Cx I2C Instance.
1590 * @retval State of bit (1 or 0).
1591 */
1592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1593 {
1594 return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
1595 }
1596
1597 /**
1598 * @brief Indicate the status of Transfer complete flag (master mode).
1599 * @note RESET: Clear default value.
1600 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1601 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1602 * @param I2Cx I2C Instance.
1603 * @retval State of bit (1 or 0).
1604 */
1605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1606 {
1607 return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
1608 }
1609
1610 /**
1611 * @brief Indicate the status of Transfer complete flag (master mode).
1612 * @note RESET: Clear default value.
1613 * SET: When RELOAD=1 and NBYTES date have been transferred.
1614 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1615 * @param I2Cx I2C Instance.
1616 * @retval State of bit (1 or 0).
1617 */
1618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1619 {
1620 return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
1621 }
1622
1623 /**
1624 * @brief Indicate the status of Bus error flag.
1625 * @note RESET: Clear default value.
1626 * SET: When a misplaced Start or Stop condition is detected.
1627 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1628 * @param I2Cx I2C Instance.
1629 * @retval State of bit (1 or 0).
1630 */
1631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1632 {
1633 return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
1634 }
1635
1636 /**
1637 * @brief Indicate the status of Arbitration lost flag.
1638 * @note RESET: Clear default value.
1639 * SET: When arbitration lost.
1640 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1641 * @param I2Cx I2C Instance.
1642 * @retval State of bit (1 or 0).
1643 */
1644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1645 {
1646 return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
1647 }
1648
1649 /**
1650 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1651 * @note RESET: Clear default value.
1652 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1653 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1654 * @param I2Cx I2C Instance.
1655 * @retval State of bit (1 or 0).
1656 */
1657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1658 {
1659 return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
1660 }
1661
1662 /**
1663 * @brief Indicate the status of SMBus PEC error flag in reception.
1664 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1665 * SMBus feature is supported by the I2Cx Instance.
1666 * @note RESET: Clear default value.
1667 * SET: When the received PEC does not match with the PEC register content.
1668 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1669 * @param I2Cx I2C Instance.
1670 * @retval State of bit (1 or 0).
1671 */
1672 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1673 {
1674 return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
1675 }
1676
1677 /**
1678 * @brief Indicate the status of SMBus Timeout detection flag.
1679 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1680 * SMBus feature is supported by the I2Cx Instance.
1681 * @note RESET: Clear default value.
1682 * SET: When a timeout or extended clock timeout occurs.
1683 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1684 * @param I2Cx I2C Instance.
1685 * @retval State of bit (1 or 0).
1686 */
1687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1688 {
1689 return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
1690 }
1691
1692 /**
1693 * @brief Indicate the status of SMBus alert flag.
1694 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1695 * SMBus feature is supported by the I2Cx Instance.
1696 * @note RESET: Clear default value.
1697 * SET: When SMBus host configuration, SMBus alert enabled and
1698 * a falling edge event occurs on SMBA pin.
1699 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1700 * @param I2Cx I2C Instance.
1701 * @retval State of bit (1 or 0).
1702 */
1703 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1704 {
1705 return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
1706 }
1707
1708 /**
1709 * @brief Indicate the status of Bus Busy flag.
1710 * @note RESET: Clear default value.
1711 * SET: When a Start condition is detected.
1712 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1713 * @param I2Cx I2C Instance.
1714 * @retval State of bit (1 or 0).
1715 */
1716 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1717 {
1718 return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
1719 }
1720
1721 /**
1722 * @brief Clear Address Matched flag.
1723 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1724 * @param I2Cx I2C Instance.
1725 * @retval None
1726 */
1727 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1728 {
1729 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1730 }
1731
1732 /**
1733 * @brief Clear Not Acknowledge flag.
1734 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1735 * @param I2Cx I2C Instance.
1736 * @retval None
1737 */
1738 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1739 {
1740 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1741 }
1742
1743 /**
1744 * @brief Clear Stop detection flag.
1745 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1746 * @param I2Cx I2C Instance.
1747 * @retval None
1748 */
1749 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1750 {
1751 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1752 }
1753
1754 /**
1755 * @brief Clear Transmit data register empty flag (TXE).
1756 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1757 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1758 * @param I2Cx I2C Instance.
1759 * @retval None
1760 */
1761 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1762 {
1763 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1764 }
1765
1766 /**
1767 * @brief Clear Bus error flag.
1768 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1769 * @param I2Cx I2C Instance.
1770 * @retval None
1771 */
1772 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1773 {
1774 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1775 }
1776
1777 /**
1778 * @brief Clear Arbitration lost flag.
1779 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1780 * @param I2Cx I2C Instance.
1781 * @retval None
1782 */
1783 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1784 {
1785 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1786 }
1787
1788 /**
1789 * @brief Clear Overrun/Underrun flag.
1790 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1791 * @param I2Cx I2C Instance.
1792 * @retval None
1793 */
1794 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1795 {
1796 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1797 }
1798
1799 /**
1800 * @brief Clear SMBus PEC error flag.
1801 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1802 * SMBus feature is supported by the I2Cx Instance.
1803 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1804 * @param I2Cx I2C Instance.
1805 * @retval None
1806 */
1807 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1808 {
1809 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1810 }
1811
1812 /**
1813 * @brief Clear SMBus Timeout detection flag.
1814 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1815 * SMBus feature is supported by the I2Cx Instance.
1816 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1817 * @param I2Cx I2C Instance.
1818 * @retval None
1819 */
1820 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1821 {
1822 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1823 }
1824
1825 /**
1826 * @brief Clear SMBus Alert flag.
1827 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1828 * SMBus feature is supported by the I2Cx Instance.
1829 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1830 * @param I2Cx I2C Instance.
1831 * @retval None
1832 */
1833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1834 {
1835 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1836 }
1837
1838 /**
1839 * @}
1840 */
1841
1842 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1843 * @{
1844 */
1845
1846 /**
1847 * @brief Enable automatic STOP condition generation (master mode).
1848 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1849 * This bit has no effect in slave mode or when RELOAD bit is set.
1850 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1851 * @param I2Cx I2C Instance.
1852 * @retval None
1853 */
1854 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1855 {
1856 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1857 }
1858
1859 /**
1860 * @brief Disable automatic STOP condition generation (master mode).
1861 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1862 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1863 * @param I2Cx I2C Instance.
1864 * @retval None
1865 */
1866 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1867 {
1868 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1869 }
1870
1871 /**
1872 * @brief Check if automatic STOP condition is enabled or disabled.
1873 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1874 * @param I2Cx I2C Instance.
1875 * @retval State of bit (1 or 0).
1876 */
1877 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1878 {
1879 return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
1880 }
1881
1882 /**
1883 * @brief Enable reload mode (master mode).
1884 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1885 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1886 * @param I2Cx I2C Instance.
1887 * @retval None
1888 */
1889 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1890 {
1891 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1892 }
1893
1894 /**
1895 * @brief Disable reload mode (master mode).
1896 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1897 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1898 * @param I2Cx I2C Instance.
1899 * @retval None
1900 */
1901 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1902 {
1903 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1904 }
1905
1906 /**
1907 * @brief Check if reload mode is enabled or disabled.
1908 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1909 * @param I2Cx I2C Instance.
1910 * @retval State of bit (1 or 0).
1911 */
1912 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1913 {
1914 return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
1915 }
1916
1917 /**
1918 * @brief Configure the number of bytes for transfer.
1919 * @note Changing these bits when START bit is set is not allowed.
1920 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1921 * @param I2Cx I2C Instance.
1922 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1923 * @retval None
1924 */
1925 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1926 {
1927 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1928 }
1929
1930 /**
1931 * @brief Get the number of bytes configured for transfer.
1932 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1933 * @param I2Cx I2C Instance.
1934 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1935 */
1936 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1937 {
1938 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1939 }
1940
1941 /**
1942 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1943 * @note Usage in Slave mode only.
1944 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1945 * @param I2Cx I2C Instance.
1946 * @param TypeAcknowledge This parameter can be one of the following values:
1947 * @arg @ref LL_I2C_ACK
1948 * @arg @ref LL_I2C_NACK
1949 * @retval None
1950 */
1951 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1952 {
1953 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1954 }
1955
1956 /**
1957 * @brief Generate a START or RESTART condition
1958 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1959 * This action has no effect when RELOAD is set.
1960 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1961 * @param I2Cx I2C Instance.
1962 * @retval None
1963 */
1964 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1965 {
1966 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1967 }
1968
1969 /**
1970 * @brief Generate a STOP condition after the current byte transfer (master mode).
1971 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1972 * @param I2Cx I2C Instance.
1973 * @retval None
1974 */
1975 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1976 {
1977 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1978 }
1979
1980 /**
1981 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1982 * @note The master sends the complete 10bit slave address read sequence :
1983 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
1984 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1985 * @param I2Cx I2C Instance.
1986 * @retval None
1987 */
1988 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1989 {
1990 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1991 }
1992
1993 /**
1994 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1995 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1996 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1997 * @param I2Cx I2C Instance.
1998 * @retval None
1999 */
2000 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
2001 {
2002 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
2003 }
2004
2005 /**
2006 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
2007 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
2008 * @param I2Cx I2C Instance.
2009 * @retval State of bit (1 or 0).
2010 */
2011 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
2012 {
2013 return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
2014 }
2015
2016 /**
2017 * @brief Configure the transfer direction (master mode).
2018 * @note Changing these bits when START bit is set is not allowed.
2019 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
2020 * @param I2Cx I2C Instance.
2021 * @param TransferRequest This parameter can be one of the following values:
2022 * @arg @ref LL_I2C_REQUEST_WRITE
2023 * @arg @ref LL_I2C_REQUEST_READ
2024 * @retval None
2025 */
2026 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
2027 {
2028 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
2029 }
2030
2031 /**
2032 * @brief Get the transfer direction requested (master mode).
2033 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
2034 * @param I2Cx I2C Instance.
2035 * @retval Returned value can be one of the following values:
2036 * @arg @ref LL_I2C_REQUEST_WRITE
2037 * @arg @ref LL_I2C_REQUEST_READ
2038 */
2039 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2040 {
2041 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2042 }
2043
2044 /**
2045 * @brief Configure the slave address for transfer (master mode).
2046 * @note Changing these bits when START bit is set is not allowed.
2047 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2048 * @param I2Cx I2C Instance.
2049 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2050 * @retval None
2051 */
2052 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2053 {
2054 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2055 }
2056
2057 /**
2058 * @brief Get the slave address programmed for transfer.
2059 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2060 * @param I2Cx I2C Instance.
2061 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2062 */
2063 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2064 {
2065 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2066 }
2067
2068 /**
2069 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2070 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2071 * CR2 ADD10 LL_I2C_HandleTransfer\n
2072 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2073 * CR2 START LL_I2C_HandleTransfer\n
2074 * CR2 STOP LL_I2C_HandleTransfer\n
2075 * CR2 RELOAD LL_I2C_HandleTransfer\n
2076 * CR2 NBYTES LL_I2C_HandleTransfer\n
2077 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2078 * CR2 HEAD10R LL_I2C_HandleTransfer
2079 * @param I2Cx I2C Instance.
2080 * @param SlaveAddr Specifies the slave address to be programmed.
2081 * @param SlaveAddrSize This parameter can be one of the following values:
2082 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2083 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2084 * @param TransferSize Specifies the number of bytes to be programmed.
2085 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2086 * @param EndMode This parameter can be one of the following values:
2087 * @arg @ref LL_I2C_MODE_RELOAD
2088 * @arg @ref LL_I2C_MODE_AUTOEND
2089 * @arg @ref LL_I2C_MODE_SOFTEND
2090 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2091 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2092 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2093 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2094 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2095 * @param Request This parameter can be one of the following values:
2096 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2097 * @arg @ref LL_I2C_GENERATE_STOP
2098 * @arg @ref LL_I2C_GENERATE_START_READ
2099 * @arg @ref LL_I2C_GENERATE_START_WRITE
2100 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2101 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2102 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2103 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2104 * @retval None
2105 */
2106 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2107 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2108 {
2109 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2110 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2111 SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
2112 }
2113
2114 /**
2115 * @brief Indicate the value of transfer direction (slave mode).
2116 * @note RESET: Write transfer, Slave enters in receiver mode.
2117 * SET: Read transfer, Slave enters in transmitter mode.
2118 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2119 * @param I2Cx I2C Instance.
2120 * @retval Returned value can be one of the following values:
2121 * @arg @ref LL_I2C_DIRECTION_WRITE
2122 * @arg @ref LL_I2C_DIRECTION_READ
2123 */
2124 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2125 {
2126 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2127 }
2128
2129 /**
2130 * @brief Return the slave matched address.
2131 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2132 * @param I2Cx I2C Instance.
2133 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2134 */
2135 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2136 {
2137 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2138 }
2139
2140 /**
2141 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2142 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2143 * SMBus feature is supported by the I2Cx Instance.
2144 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
2145 * This bit has no effect when RELOAD bit is set.
2146 * This bit has no effect in device mode when SBC bit is not set.
2147 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2148 * @param I2Cx I2C Instance.
2149 * @retval None
2150 */
2151 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2152 {
2153 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2154 }
2155
2156 /**
2157 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2158 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2159 * SMBus feature is supported by the I2Cx Instance.
2160 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2161 * @param I2Cx I2C Instance.
2162 * @retval State of bit (1 or 0).
2163 */
2164 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2165 {
2166 return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
2167 }
2168
2169 /**
2170 * @brief Get the SMBus Packet Error byte calculated.
2171 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2172 * SMBus feature is supported by the I2Cx Instance.
2173 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2174 * @param I2Cx I2C Instance.
2175 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2176 */
2177 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2178 {
2179 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2180 }
2181
2182 /**
2183 * @brief Read Receive Data register.
2184 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2185 * @param I2Cx I2C Instance.
2186 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2187 */
2188 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2189 {
2190 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2191 }
2192
2193 /**
2194 * @brief Write in Transmit Data Register .
2195 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2196 * @param I2Cx I2C Instance.
2197 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2198 * @retval None
2199 */
2200 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2201 {
2202 WRITE_REG(I2Cx->TXDR, Data);
2203 }
2204
2205 /**
2206 * @}
2207 */
2208
2209 #if defined(USE_FULL_LL_DRIVER)
2210 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2211 * @{
2212 */
2213
2214 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2215 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2216 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2217
2218
2219 /**
2220 * @}
2221 */
2222 #endif /* USE_FULL_LL_DRIVER */
2223
2224 /**
2225 * @}
2226 */
2227
2228 /**
2229 * @}
2230 */
2231
2232 #endif /* I2C1 || I2C2 || I2C3 */
2233
2234 /**
2235 * @}
2236 */
2237
2238 #ifdef __cplusplus
2239 }
2240 #endif
2241
2242 #endif /* __STM32F3xx_LL_I2C_H */
2243
2244 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/