?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_rcc.h
blob20089b752f152f8734a6720262a2fca263dd0cfd
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_LL_RCC_H
38 #define __STM32F3xx_LL_RCC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f3xx.h"
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup RCC_LL RCC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
61 * @{
62 */
63 /* Defines used for the bit position in the register and perform offsets*/
64 #define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /*!< field position in register RCC_CFGR */
65 #define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /*!< field position in register RCC_CFGR */
66 #define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /*!< field position in register RCC_CFGR */
67 #define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /*!< field position in register RCC_CR */
68 #define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /*!< field position in register RCC_CR */
69 #define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL) /*!< field position in register RCC_CFGR */
70 #define RCC_POSITION_USART1SW (uint32_t)0U /*!< field position in register RCC_CFGR3 */
71 #define RCC_POSITION_USART2SW (uint32_t)16U /*!< field position in register RCC_CFGR3 */
72 #define RCC_POSITION_USART3SW (uint32_t)18U /*!< field position in register RCC_CFGR3 */
73 #define RCC_POSITION_TIM1SW (uint32_t)8U /*!< field position in register RCC_CFGR3 */
74 #define RCC_POSITION_TIM8SW (uint32_t)9U /*!< field position in register RCC_CFGR3 */
75 #define RCC_POSITION_TIM15SW (uint32_t)10U /*!< field position in register RCC_CFGR3 */
76 #define RCC_POSITION_TIM16SW (uint32_t)11U /*!< field position in register RCC_CFGR3 */
77 #define RCC_POSITION_TIM17SW (uint32_t)13U /*!< field position in register RCC_CFGR3 */
78 #define RCC_POSITION_TIM20SW (uint32_t)15U /*!< field position in register RCC_CFGR3 */
79 #define RCC_POSITION_TIM2SW (uint32_t)24U /*!< field position in register RCC_CFGR3 */
80 #define RCC_POSITION_TIM34SW (uint32_t)25U /*!< field position in register RCC_CFGR3 */
81
82 /**
83 * @}
84 */
85
86 /* Private macros ------------------------------------------------------------*/
87 #if defined(USE_FULL_LL_DRIVER)
88 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
89 * @{
90 */
91 /**
92 * @}
93 */
94 #endif /*USE_FULL_LL_DRIVER*/
95 /* Exported types ------------------------------------------------------------*/
96 #if defined(USE_FULL_LL_DRIVER)
97 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
98 * @{
99 */
100
101 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
102 * @{
103 */
104
105 /**
106 * @brief RCC Clocks Frequency Structure
107 */
108 typedef struct
109 {
110 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
111 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
112 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
113 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
114 } LL_RCC_ClocksTypeDef;
115
116 /**
117 * @}
118 */
119
120 /**
121 * @}
122 */
123 #endif /* USE_FULL_LL_DRIVER */
124
125 /* Exported constants --------------------------------------------------------*/
126 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
127 * @{
128 */
129
130 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
131 * @brief Defines used to adapt values of different oscillators
132 * @note These values could be modified in the user environment according to
133 * HW set-up.
134 * @{
135 */
136 #if !defined (HSE_VALUE)
137 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
138 #endif /* HSE_VALUE */
139
140 #if !defined (HSI_VALUE)
141 #define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */
142 #endif /* HSI_VALUE */
143
144 #if !defined (LSE_VALUE)
145 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
146 #endif /* LSE_VALUE */
147
148 #if !defined (LSI_VALUE)
149 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
150 #endif /* LSI_VALUE */
151 /**
152 * @}
153 */
154
155 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
156 * @brief Flags defines which can be used with LL_RCC_WriteReg function
157 * @{
158 */
159 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
160 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
161 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
162 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
163 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
164 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
165 /**
166 * @}
167 */
168
169 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
170 * @brief Flags defines which can be used with LL_RCC_ReadReg function
171 * @{
172 */
173 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
174 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
175 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
176 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
177 #define LL_RCC_CFGR_MCOF RCC_CFGR_MCOF /*!< MCO flag */
178 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
179 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
180 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
181 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
182 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
183 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
184 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
185 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
186 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
187 #if defined(RCC_CSR_V18PWRRSTF)
188 #define LL_RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF /*!< Reset flag of the 1.8 V domain. */
189 #endif /* RCC_CSR_V18PWRRSTF */
190 /**
191 * @}
192 */
193
194 /** @defgroup RCC_LL_EC_IT IT Defines
195 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
196 * @{
197 */
198 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
199 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
200 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
201 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
202 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
203 /**
204 * @}
205 */
206
207 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
208 * @{
209 */
210 #define LL_RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) /*!< Xtal mode lower driving capability */
211 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
212 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
213 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
214 /**
215 * @}
216 */
217
218 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
219 * @{
220 */
221 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
222 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
223 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
224 /**
225 * @}
226 */
227
228 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
229 * @{
230 */
231 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
232 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
233 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
234 /**
235 * @}
236 */
237
238 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
239 * @{
240 */
241 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
242 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
243 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
244 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
245 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
246 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
247 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
248 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
249 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
250 /**
251 * @}
252 */
253
254 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
255 * @{
256 */
257 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
258 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
259 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
260 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
261 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
262 /**
263 * @}
264 */
265
266 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
267 * @{
268 */
269 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
270 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
271 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
272 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
273 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
274 /**
275 * @}
276 */
277
278 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
279 * @{
280 */
281 #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */
282 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */
283 #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */
284 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */
285 #define LL_RCC_MCO1SOURCE_LSI RCC_CFGR_MCOSEL_LSI /*!< LSI selection as MCO source */
286 #define LL_RCC_MCO1SOURCE_LSE RCC_CFGR_MCOSEL_LSE /*!< LSE selection as MCO source */
287 #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/
288 #if defined(RCC_CFGR_PLLNODIV)
289 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_PLL_DIV2 | RCC_CFGR_PLLNODIV) /*!< PLL clock selected*/
290 #endif /* RCC_CFGR_PLLNODIV */
291 /**
292 * @}
293 */
294
295 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
296 * @{
297 */
298 #define LL_RCC_MCO1_DIV_1 ((uint32_t)0x00000000U)/*!< MCO Clock divided by 1 */
299 #if defined(RCC_CFGR_MCOPRE)
300 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO Clock divided by 2 */
301 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO Clock divided by 4 */
302 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO Clock divided by 8 */
303 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO Clock divided by 16 */
304 #define LL_RCC_MCO1_DIV_32 RCC_CFGR_MCOPRE_DIV32 /*!< MCO Clock divided by 32 */
305 #define LL_RCC_MCO1_DIV_64 RCC_CFGR_MCOPRE_DIV64 /*!< MCO Clock divided by 64 */
306 #define LL_RCC_MCO1_DIV_128 RCC_CFGR_MCOPRE_DIV128 /*!< MCO Clock divided by 128 */
307 #endif /* RCC_CFGR_MCOPRE */
308 /**
309 * @}
310 */
311
312 #if defined(USE_FULL_LL_DRIVER)
313 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
314 * @{
315 */
316 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
317 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
318 /**
319 * @}
320 */
321 #endif /* USE_FULL_LL_DRIVER */
322
323 /** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
324 * @{
325 */
326 #if defined(RCC_CFGR3_USART1SW_PCLK1)
327 #define LL_RCC_USART1_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK1) /*!< PCLK1 clock used as USART1 clock source */
328 #else
329 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_PCLK2) /*!< PCLK2 clock used as USART1 clock source */
330 #endif /*RCC_CFGR3_USART1SW_PCLK1*/
331 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_SYSCLK) /*!< System clock selected as USART1 clock source */
332 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_LSE) /*!< LSE oscillator clock used as USART1 clock source */
333 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART1SW << 24U) | RCC_CFGR3_USART1SW_HSI) /*!< HSI oscillator clock used as USART1 clock source */
334 #if defined(RCC_CFGR3_USART2SW)
335 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_PCLK) /*!< PCLK1 clock used as USART2 clock source */
336 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_SYSCLK) /*!< System clock selected as USART2 clock source */
337 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_LSE) /*!< LSE oscillator clock used as USART2 clock source */
338 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART2SW << 24U) | RCC_CFGR3_USART2SW_HSI) /*!< HSI oscillator clock used as USART2 clock source */
339 #endif /* RCC_CFGR3_USART2SW */
340 #if defined(RCC_CFGR3_USART3SW)
341 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_PCLK) /*!< PCLK1 clock used as USART3 clock source */
342 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_SYSCLK) /*!< System clock selected as USART3 clock source */
343 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_LSE) /*!< LSE oscillator clock used as USART3 clock source */
344 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_POSITION_USART3SW << 24U) | RCC_CFGR3_USART3SW_HSI) /*!< HSI oscillator clock used as USART3 clock source */
345 #endif /* RCC_CFGR3_USART3SW */
346 /**
347 * @}
348 */
349
350 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
351 /** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
352 * @{
353 */
354 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_PCLK) /*!< PCLK1 clock used as UART4 clock source */
355 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_SYSCLK) /*!< System clock selected as UART4 clock source */
356 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_LSE) /*!< LSE oscillator clock used as UART4 clock source */
357 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART4SW >> 8U) | RCC_CFGR3_UART4SW_HSI) /*!< HSI oscillator clock used as UART4 clock source */
358 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_PCLK) /*!< PCLK1 clock used as UART5 clock source */
359 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_SYSCLK) /*!< System clock selected as UART5 clock source */
360 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_LSE) /*!< LSE oscillator clock used as UART5 clock source */
361 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_UART5SW >> 8U) | RCC_CFGR3_UART5SW_HSI) /*!< HSI oscillator clock used as UART5 clock source */
362 /**
363 * @}
364 */
365
366 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
367
368 /** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
369 * @{
370 */
371 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_HSI) /*!< HSI oscillator clock used as I2C1 clock source */
372 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C1SW << 24U) | RCC_CFGR3_I2C1SW_SYSCLK) /*!< System clock selected as I2C1 clock source */
373 #if defined(RCC_CFGR3_I2C2SW)
374 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_HSI) /*!< HSI oscillator clock used as I2C2 clock source */
375 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C2SW << 24U) | RCC_CFGR3_I2C2SW_SYSCLK) /*!< System clock selected as I2C2 clock source */
376 #endif /*RCC_CFGR3_I2C2SW*/
377 #if defined(RCC_CFGR3_I2C3SW)
378 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_HSI) /*!< HSI oscillator clock used as I2C3 clock source */
379 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)((RCC_CFGR3_I2C3SW << 24U) | RCC_CFGR3_I2C3SW_SYSCLK) /*!< System clock selected as I2C3 clock source */
380 #endif /*RCC_CFGR3_I2C3SW*/
381 /**
382 * @}
383 */
384
385 #if defined(RCC_CFGR_I2SSRC)
386 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
387 * @{
388 */
389 #define LL_RCC_I2S_CLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK /*!< System clock selected as I2S clock source */
390 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CFGR_I2SSRC_EXT /*!< External clock selected as I2S clock source */
391 /**
392 * @}
393 */
394
395 #endif /* RCC_CFGR_I2SSRC */
396
397 #if defined(RCC_CFGR3_TIMSW)
398 /** @defgroup RCC_LL_EC_TIM1_CLKSOURCE Peripheral TIM clock source selection
399 * @{
400 */
401 #define LL_RCC_TIM1_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PCLK2) /*!< PCLK2 used as TIM1 clock source */
402 #define LL_RCC_TIM1_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM1SW_PLL) /*!< PLL clock used as TIM1 clock source */
403 #if defined(RCC_CFGR3_TIM8SW)
404 #define LL_RCC_TIM8_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PCLK2) /*!< PCLK2 used as TIM8 clock source */
405 #define LL_RCC_TIM8_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM8SW_PLL) /*!< PLL clock used as TIM8 clock source */
406 #endif /*RCC_CFGR3_TIM8SW*/
407 #if defined(RCC_CFGR3_TIM15SW)
408 #define LL_RCC_TIM15_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PCLK2) /*!< PCLK2 used as TIM15 clock source */
409 #define LL_RCC_TIM15_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM15SW_PLL) /*!< PLL clock used as TIM15 clock source */
410 #endif /*RCC_CFGR3_TIM15SW*/
411 #if defined(RCC_CFGR3_TIM16SW)
412 #define LL_RCC_TIM16_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PCLK2) /*!< PCLK2 used as TIM16 clock source */
413 #define LL_RCC_TIM16_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM16SW_PLL) /*!< PLL clock used as TIM16 clock source */
414 #endif /*RCC_CFGR3_TIM16SW*/
415 #if defined(RCC_CFGR3_TIM17SW)
416 #define LL_RCC_TIM17_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PCLK2) /*!< PCLK2 used as TIM17 clock source */
417 #define LL_RCC_TIM17_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM17SW_PLL) /*!< PLL clock used as TIM17 clock source */
418 #endif /*RCC_CFGR3_TIM17SW*/
419 #if defined(RCC_CFGR3_TIM20SW)
420 #define LL_RCC_TIM20_CLKSOURCE_PCLK2 (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PCLK2) /*!< PCLK2 used as TIM20 clock source */
421 #define LL_RCC_TIM20_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM20SW_PLL) /*!< PLL clock used as TIM20 clock source */
422 #endif /*RCC_CFGR3_TIM20SW*/
423 #if defined(RCC_CFGR3_TIM2SW)
424 #define LL_RCC_TIM2_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PCLK1) /*!< PCLK1 used as TIM2 clock source */
425 #define LL_RCC_TIM2_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM2SW_PLL) /*!< PLL clock used as TIM2 clock source */
426 #endif /*RCC_CFGR3_TIM2SW*/
427 #if defined(RCC_CFGR3_TIM34SW)
428 #define LL_RCC_TIM34_CLKSOURCE_PCLK1 (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PCLK1) /*!< PCLK1 used as TIM3/4 clock source */
429 #define LL_RCC_TIM34_CLKSOURCE_PLL (uint32_t)(((RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) << 27U) | RCC_CFGR3_TIM34SW_PLL) /*!< PLL clock used as TIM3/4 clock source */
430 #endif /*RCC_CFGR3_TIM34SW*/
431 /**
432 * @}
433 */
434
435 #endif /* RCC_CFGR3_TIMSW */
436
437 #if defined(HRTIM1)
438 /** @defgroup RCC_LL_EC_HRTIM1_CLKSOURCE Peripheral HRTIM1 clock source selection
439 * @{
440 */
441 #define LL_RCC_HRTIM1_CLKSOURCE_PCLK2 RCC_CFGR3_HRTIM1SW_PCLK2 /*!< PCLK2 used as HRTIM1 clock source */
442 #define LL_RCC_HRTIM1_CLKSOURCE_PLL RCC_CFGR3_HRTIM1SW_PLL /*!< PLL clock used as HRTIM1 clock source */
443 /**
444 * @}
445 */
446
447 #endif /* HRTIM1 */
448
449 #if defined(CEC)
450 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
451 * @{
452 */
453 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV244 RCC_CFGR3_CECSW_HSI_DIV244 /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
454 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_CFGR3_CECSW_LSE /*!< LSE clock selected as HDMI CEC entry clock source */
455 /**
456 * @}
457 */
458
459 #endif /* CEC */
460
461 #if defined(USB)
462 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
463 * @{
464 */
465 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE_DIV1 /*!< USB prescaler is PLL clock divided by 1 */
466 #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 RCC_CFGR_USBPRE_DIV1_5 /*!< USB prescaler is PLL clock divided by 1.5 */
467 /**
468 * @}
469 */
470
471 #endif /* USB */
472
473 #if defined(RCC_CFGR_ADCPRE)
474 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
475 * @{
476 */
477 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /*!< ADC prescaler PCLK divided by 2 */
478 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /*!< ADC prescaler PCLK divided by 4 */
479 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /*!< ADC prescaler PCLK divided by 6 */
480 #define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /*!< ADC prescaler PCLK divided by 8 */
481 /**
482 * @}
483 */
484
485 #elif defined(RCC_CFGR2_ADC1PRES)
486 /** @defgroup RCC_LL_EC_ADC1_CLKSOURCE Peripheral ADC clock source selection
487 * @{
488 */
489 #define LL_RCC_ADC1_CLKSRC_HCLK RCC_CFGR2_ADC1PRES_NO /*!< ADC1 clock disabled, ADC1 can use AHB clock */
490 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADC1PRES_DIV1 /*!< ADC1 PLL clock divided by 1 */
491 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADC1PRES_DIV2 /*!< ADC1 PLL clock divided by 2 */
492 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADC1PRES_DIV4 /*!< ADC1 PLL clock divided by 4 */
493 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADC1PRES_DIV6 /*!< ADC1 PLL clock divided by 6 */
494 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADC1PRES_DIV8 /*!< ADC1 PLL clock divided by 8 */
495 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADC1PRES_DIV10 /*!< ADC1 PLL clock divided by 10 */
496 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADC1PRES_DIV12 /*!< ADC1 PLL clock divided by 12 */
497 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADC1PRES_DIV16 /*!< ADC1 PLL clock divided by 16 */
498 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADC1PRES_DIV32 /*!< ADC1 PLL clock divided by 32 */
499 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADC1PRES_DIV64 /*!< ADC1 PLL clock divided by 64 */
500 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADC1PRES_DIV128 /*!< ADC1 PLL clock divided by 128 */
501 #define LL_RCC_ADC1_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADC1PRES_DIV256 /*!< ADC1 PLL clock divided by 256 */
502 /**
503 * @}
504 */
505
506 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
507 #if defined(RCC_CFGR2_ADCPRE12) && defined(RCC_CFGR2_ADCPRE34)
508 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC12 clock source selection
509 * @{
510 */
511 #define LL_RCC_ADC12_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_NO) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
512 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV1) /*!< ADC12 PLL clock divided by 1 */
513 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV2) /*!< ADC12 PLL clock divided by 2 */
514 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV4) /*!< ADC12 PLL clock divided by 4 */
515 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV6) /*!< ADC12 PLL clock divided by 6 */
516 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV8) /*!< ADC12 PLL clock divided by 8 */
517 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV10) /*!< ADC12 PLL clock divided by 10 */
518 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV12) /*!< ADC12 PLL clock divided by 12 */
519 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV16) /*!< ADC12 PLL clock divided by 16 */
520 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV32) /*!< ADC12 PLL clock divided by 32 */
521 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV64) /*!< ADC12 PLL clock divided by 64 */
522 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV128) /*!< ADC12 PLL clock divided by 128 */
523 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE12 << 16U) | RCC_CFGR2_ADCPRE12_DIV256) /*!< ADC12 PLL clock divided by 256 */
524 /**
525 * @}
526 */
527
528 /** @defgroup RCC_LL_EC_ADC34_CLKSOURCE Peripheral ADC34 clock source selection
529 * @{
530 */
531 #define LL_RCC_ADC34_CLKSRC_HCLK (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_NO) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
532 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV1) /*!< ADC34 PLL clock divided by 1 */
533 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV2) /*!< ADC34 PLL clock divided by 2 */
534 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV4) /*!< ADC34 PLL clock divided by 4 */
535 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV6) /*!< ADC34 PLL clock divided by 6 */
536 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV8) /*!< ADC34 PLL clock divided by 8 */
537 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV10) /*!< ADC34 PLL clock divided by 10 */
538 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV12) /*!< ADC34 PLL clock divided by 12 */
539 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV16) /*!< ADC34 PLL clock divided by 16 */
540 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV32) /*!< ADC34 PLL clock divided by 32 */
541 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV64) /*!< ADC34 PLL clock divided by 64 */
542 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV128) /*!< ADC34 PLL clock divided by 128 */
543 #define LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (uint32_t)((RCC_CFGR2_ADCPRE34 << 16U) | RCC_CFGR2_ADCPRE34_DIV256) /*!< ADC34 PLL clock divided by 256 */
544 /**
545 * @}
546 */
547
548 #else
549 /** @defgroup RCC_LL_EC_ADC12_CLKSOURCE Peripheral ADC clock source selection
550 * @{
551 */
552 #define LL_RCC_ADC12_CLKSRC_HCLK RCC_CFGR2_ADCPRE12_NO /*!< ADC12 clock disabled, ADC12 can use AHB clock */
553 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_1 RCC_CFGR2_ADCPRE12_DIV1 /*!< ADC12 PLL clock divided by 1 */
554 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_2 RCC_CFGR2_ADCPRE12_DIV2 /*!< ADC12 PLL clock divided by 2 */
555 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_4 RCC_CFGR2_ADCPRE12_DIV4 /*!< ADC12 PLL clock divided by 4 */
556 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_6 RCC_CFGR2_ADCPRE12_DIV6 /*!< ADC12 PLL clock divided by 6 */
557 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_8 RCC_CFGR2_ADCPRE12_DIV8 /*!< ADC12 PLL clock divided by 8 */
558 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_10 RCC_CFGR2_ADCPRE12_DIV10 /*!< ADC12 PLL clock divided by 10 */
559 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_12 RCC_CFGR2_ADCPRE12_DIV12 /*!< ADC12 PLL clock divided by 12 */
560 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_16 RCC_CFGR2_ADCPRE12_DIV16 /*!< ADC12 PLL clock divided by 16 */
561 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_32 RCC_CFGR2_ADCPRE12_DIV32 /*!< ADC12 PLL clock divided by 32 */
562 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_64 RCC_CFGR2_ADCPRE12_DIV64 /*!< ADC12 PLL clock divided by 64 */
563 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_128 RCC_CFGR2_ADCPRE12_DIV128 /*!< ADC12 PLL clock divided by 128 */
564 #define LL_RCC_ADC12_CLKSRC_PLL_DIV_256 RCC_CFGR2_ADCPRE12_DIV256 /*!< ADC12 PLL clock divided by 256 */
565 /**
566 * @}
567 */
568
569 #endif /* RCC_CFGR2_ADCPRE12 && RCC_CFGR2_ADCPRE34 */
570
571 #endif /* RCC_CFGR_ADCPRE */
572
573 #if defined(RCC_CFGR_SDPRE)
574 /** @defgroup RCC_LL_EC_SDADC_CLKSOURCE_SYSCLK Peripheral SDADC clock source selection
575 * @{
576 */
577 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_1 RCC_CFGR_SDPRE_DIV1 /*!< SDADC CLK not divided */
578 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_2 RCC_CFGR_SDPRE_DIV2 /*!< SDADC CLK divided by 2 */
579 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_4 RCC_CFGR_SDPRE_DIV4 /*!< SDADC CLK divided by 4 */
580 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_6 RCC_CFGR_SDPRE_DIV6 /*!< SDADC CLK divided by 6 */
581 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_8 RCC_CFGR_SDPRE_DIV8 /*!< SDADC CLK divided by 8 */
582 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_10 RCC_CFGR_SDPRE_DIV10 /*!< SDADC CLK divided by 10 */
583 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_12 RCC_CFGR_SDPRE_DIV12 /*!< SDADC CLK divided by 12 */
584 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_14 RCC_CFGR_SDPRE_DIV14 /*!< SDADC CLK divided by 14 */
585 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_16 RCC_CFGR_SDPRE_DIV16 /*!< SDADC CLK divided by 16 */
586 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_20 RCC_CFGR_SDPRE_DIV20 /*!< SDADC CLK divided by 20 */
587 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_24 RCC_CFGR_SDPRE_DIV24 /*!< SDADC CLK divided by 24 */
588 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_28 RCC_CFGR_SDPRE_DIV28 /*!< SDADC CLK divided by 28 */
589 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_32 RCC_CFGR_SDPRE_DIV32 /*!< SDADC CLK divided by 32 */
590 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_36 RCC_CFGR_SDPRE_DIV36 /*!< SDADC CLK divided by 36 */
591 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_40 RCC_CFGR_SDPRE_DIV40 /*!< SDADC CLK divided by 40 */
592 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_44 RCC_CFGR_SDPRE_DIV44 /*!< SDADC CLK divided by 44 */
593 #define LL_RCC_SDADC_CLKSRC_SYS_DIV_48 RCC_CFGR_SDPRE_DIV48 /*!< SDADC CLK divided by 48 */
594 /**
595 * @}
596 */
597
598 #endif /* RCC_CFGR_SDPRE */
599
600 /** @defgroup RCC_LL_EC_USART Peripheral USART get clock source
601 * @{
602 */
603 #define LL_RCC_USART1_CLKSOURCE RCC_POSITION_USART1SW /*!< USART1 Clock source selection */
604 #if defined(RCC_CFGR3_USART2SW)
605 #define LL_RCC_USART2_CLKSOURCE RCC_POSITION_USART2SW /*!< USART2 Clock source selection */
606 #endif /* RCC_CFGR3_USART2SW */
607 #if defined(RCC_CFGR3_USART3SW)
608 #define LL_RCC_USART3_CLKSOURCE RCC_POSITION_USART3SW /*!< USART3 Clock source selection */
609 #endif /* RCC_CFGR3_USART3SW */
610 /**
611 * @}
612 */
613
614 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
615 /** @defgroup RCC_LL_EC_UART Peripheral UART get clock source
616 * @{
617 */
618 #define LL_RCC_UART4_CLKSOURCE RCC_CFGR3_UART4SW /*!< UART4 Clock source selection */
619 #define LL_RCC_UART5_CLKSOURCE RCC_CFGR3_UART5SW /*!< UART5 Clock source selection */
620 /**
621 * @}
622 */
623
624 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
625
626 /** @defgroup RCC_LL_EC_I2C Peripheral I2C get clock source
627 * @{
628 */
629 #define LL_RCC_I2C1_CLKSOURCE RCC_CFGR3_I2C1SW /*!< I2C1 Clock source selection */
630 #if defined(RCC_CFGR3_I2C2SW)
631 #define LL_RCC_I2C2_CLKSOURCE RCC_CFGR3_I2C2SW /*!< I2C2 Clock source selection */
632 #endif /*RCC_CFGR3_I2C2SW*/
633 #if defined(RCC_CFGR3_I2C3SW)
634 #define LL_RCC_I2C3_CLKSOURCE RCC_CFGR3_I2C3SW /*!< I2C3 Clock source selection */
635 #endif /*RCC_CFGR3_I2C3SW*/
636 /**
637 * @}
638 */
639
640 #if defined(RCC_CFGR_I2SSRC)
641 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
642 * @{
643 */
644 #define LL_RCC_I2S_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
645 /**
646 * @}
647 */
648
649 #endif /* RCC_CFGR_I2SSRC */
650
651 #if defined(RCC_CFGR3_TIMSW)
652 /** @defgroup RCC_LL_EC_TIM TIMx Peripheral TIM get clock source
653 * @{
654 */
655 #define LL_RCC_TIM1_CLKSOURCE (RCC_POSITION_TIM1SW - RCC_POSITION_TIM1SW) /*!< TIM1 Clock source selection */
656 #if defined(RCC_CFGR3_TIM2SW)
657 #define LL_RCC_TIM2_CLKSOURCE (RCC_POSITION_TIM2SW - RCC_POSITION_TIM1SW) /*!< TIM2 Clock source selection */
658 #endif /*RCC_CFGR3_TIM2SW*/
659 #if defined(RCC_CFGR3_TIM8SW)
660 #define LL_RCC_TIM8_CLKSOURCE (RCC_POSITION_TIM8SW - RCC_POSITION_TIM1SW) /*!< TIM8 Clock source selection */
661 #endif /*RCC_CFGR3_TIM8SW*/
662 #if defined(RCC_CFGR3_TIM15SW)
663 #define LL_RCC_TIM15_CLKSOURCE (RCC_POSITION_TIM15SW - RCC_POSITION_TIM1SW) /*!< TIM15 Clock source selection */
664 #endif /*RCC_CFGR3_TIM15SW*/
665 #if defined(RCC_CFGR3_TIM16SW)
666 #define LL_RCC_TIM16_CLKSOURCE (RCC_POSITION_TIM16SW - RCC_POSITION_TIM1SW) /*!< TIM16 Clock source selection */
667 #endif /*RCC_CFGR3_TIM16SW*/
668 #if defined(RCC_CFGR3_TIM17SW)
669 #define LL_RCC_TIM17_CLKSOURCE (RCC_POSITION_TIM17SW - RCC_POSITION_TIM1SW) /*!< TIM17 Clock source selection */
670 #endif /*RCC_CFGR3_TIM17SW*/
671 #if defined(RCC_CFGR3_TIM20SW)
672 #define LL_RCC_TIM20_CLKSOURCE (RCC_POSITION_TIM20SW - RCC_POSITION_TIM1SW) /*!< TIM20 Clock source selection */
673 #endif /*RCC_CFGR3_TIM20SW*/
674 #if defined(RCC_CFGR3_TIM34SW)
675 #define LL_RCC_TIM34_CLKSOURCE (RCC_POSITION_TIM34SW - RCC_POSITION_TIM1SW) /*!< TIM3/4 Clock source selection */
676 #endif /*RCC_CFGR3_TIM34SW*/
677 /**
678 * @}
679 */
680
681 #endif /* RCC_CFGR3_TIMSW */
682
683 #if defined(HRTIM1)
684 /** @defgroup RCC_LL_EC_HRTIM1 Peripheral HRTIM1 get clock source
685 * @{
686 */
687 #define LL_RCC_HRTIM1_CLKSOURCE RCC_CFGR3_HRTIM1SW /*!< HRTIM1 Clock source selection */
688 /**
689 * @}
690 */
691
692 #endif /* HRTIM1 */
693
694 #if defined(CEC)
695 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
696 * @{
697 */
698 #define LL_RCC_CEC_CLKSOURCE RCC_CFGR3_CECSW /*!< CEC Clock source selection */
699 /**
700 * @}
701 */
702
703 #endif /* CEC */
704
705 #if defined(USB)
706 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
707 * @{
708 */
709 #define LL_RCC_USB_CLKSOURCE RCC_CFGR_USBPRE /*!< USB Clock source selection */
710 /**
711 * @}
712 */
713
714 #endif /* USB */
715
716 #if defined(RCC_CFGR_ADCPRE)
717 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
718 * @{
719 */
720 #define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /*!< ADC Clock source selection */
721 /**
722 * @}
723 */
724
725 #endif /* RCC_CFGR_ADCPRE */
726
727 #if defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
728 /** @defgroup RCC_LL_EC_ADCXX Peripheral ADC get clock source
729 * @{
730 */
731 #if defined(RCC_CFGR2_ADC1PRES)
732 #define LL_RCC_ADC1_CLKSOURCE RCC_CFGR2_ADC1PRES /*!< ADC1 Clock source selection */
733 #else
734 #define LL_RCC_ADC12_CLKSOURCE RCC_CFGR2_ADCPRE12 /*!< ADC12 Clock source selection */
735 #if defined(RCC_CFGR2_ADCPRE34)
736 #define LL_RCC_ADC34_CLKSOURCE RCC_CFGR2_ADCPRE34 /*!< ADC34 Clock source selection */
737 #endif /*RCC_CFGR2_ADCPRE34*/
738 #endif /*RCC_CFGR2_ADC1PRES*/
739 /**
740 * @}
741 */
742
743 #endif /* RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
744
745 #if defined(RCC_CFGR_SDPRE)
746 /** @defgroup RCC_LL_EC_SDADC Peripheral SDADC get clock source
747 * @{
748 */
749 #define LL_RCC_SDADC_CLKSOURCE RCC_CFGR_SDPRE /*!< SDADC Clock source selection */
750 /**
751 * @}
752 */
753
754 #endif /* RCC_CFGR_SDPRE */
755
756
757 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
758 * @{
759 */
760 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
761 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
762 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
763 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
764 /**
765 * @}
766 */
767
768 /** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
769 * @{
770 */
771 #define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
772 #define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
773 #define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
774 #define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
775 #define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
776 #define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
777 #define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
778 #define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
779 #define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMUL10 /*!< PLL input clock*10 */
780 #define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
781 #define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
782 #define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
783 #define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
784 #define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
785 #define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
786 /**
787 * @}
788 */
789
790 /** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
791 * @{
792 */
793 #define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< HSE/PREDIV clock selected as PLL entry clock source */
794 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
795 #define LL_RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< HSI/PREDIV clock selected as PLL entry clock source */
796 #else
797 #define LL_RCC_PLLSOURCE_HSI_DIV_2 RCC_CFGR_PLLSRC_HSI_DIV2 /*!< HSI clock divided by 2 selected as PLL entry clock source */
798 #define LL_RCC_PLLSOURCE_HSE_DIV_1 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV1) /*!< HSE clock selected as PLL entry clock source */
799 #define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV2) /*!< HSE/2 clock selected as PLL entry clock source */
800 #define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV3) /*!< HSE/3 clock selected as PLL entry clock source */
801 #define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV4) /*!< HSE/4 clock selected as PLL entry clock source */
802 #define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV5) /*!< HSE/5 clock selected as PLL entry clock source */
803 #define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV6) /*!< HSE/6 clock selected as PLL entry clock source */
804 #define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV7) /*!< HSE/7 clock selected as PLL entry clock source */
805 #define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV8) /*!< HSE/8 clock selected as PLL entry clock source */
806 #define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV9) /*!< HSE/9 clock selected as PLL entry clock source */
807 #define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV10) /*!< HSE/10 clock selected as PLL entry clock source */
808 #define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV11) /*!< HSE/11 clock selected as PLL entry clock source */
809 #define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV12) /*!< HSE/12 clock selected as PLL entry clock source */
810 #define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV13) /*!< HSE/13 clock selected as PLL entry clock source */
811 #define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV14) /*!< HSE/14 clock selected as PLL entry clock source */
812 #define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV15) /*!< HSE/15 clock selected as PLL entry clock source */
813 #define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR2_PREDIV_DIV16) /*!< HSE/16 clock selected as PLL entry clock source */
814 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
815 /**
816 * @}
817 */
818
819 /** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
820 * @{
821 */
822 #define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV_DIV1 /*!< PREDIV input clock not divided */
823 #define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV_DIV2 /*!< PREDIV input clock divided by 2 */
824 #define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV_DIV3 /*!< PREDIV input clock divided by 3 */
825 #define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV_DIV4 /*!< PREDIV input clock divided by 4 */
826 #define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV_DIV5 /*!< PREDIV input clock divided by 5 */
827 #define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV_DIV6 /*!< PREDIV input clock divided by 6 */
828 #define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV_DIV7 /*!< PREDIV input clock divided by 7 */
829 #define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV_DIV8 /*!< PREDIV input clock divided by 8 */
830 #define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV_DIV9 /*!< PREDIV input clock divided by 9 */
831 #define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV_DIV10 /*!< PREDIV input clock divided by 10 */
832 #define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV_DIV11 /*!< PREDIV input clock divided by 11 */
833 #define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV_DIV12 /*!< PREDIV input clock divided by 12 */
834 #define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV_DIV13 /*!< PREDIV input clock divided by 13 */
835 #define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV_DIV14 /*!< PREDIV input clock divided by 14 */
836 #define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV_DIV15 /*!< PREDIV input clock divided by 15 */
837 #define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV_DIV16 /*!< PREDIV input clock divided by 16 */
838 /**
839 * @}
840 */
841
842 /**
843 * @}
844 */
845
846 /* Exported macro ------------------------------------------------------------*/
847 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
848 * @{
849 */
850
851 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
852 * @{
853 */
854
855 /**
856 * @brief Write a value in RCC register
857 * @param __REG__ Register to be written
858 * @param __VALUE__ Value to be written in the register
859 * @retval None
860 */
861 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
862
863 /**
864 * @brief Read a value in RCC register
865 * @param __REG__ Register to be read
866 * @retval Register value
867 */
868 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
869 /**
870 * @}
871 */
872
873 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
874 * @{
875 */
876
877 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
878 /**
879 * @brief Helper macro to calculate the PLLCLK frequency
880 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetMultiplicator()
881 * , @ref LL_RCC_PLL_GetPrediv());
882 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
883 * @param __PLLMUL__ This parameter can be one of the following values:
884 * @arg @ref LL_RCC_PLL_MUL_2
885 * @arg @ref LL_RCC_PLL_MUL_3
886 * @arg @ref LL_RCC_PLL_MUL_4
887 * @arg @ref LL_RCC_PLL_MUL_5
888 * @arg @ref LL_RCC_PLL_MUL_6
889 * @arg @ref LL_RCC_PLL_MUL_7
890 * @arg @ref LL_RCC_PLL_MUL_8
891 * @arg @ref LL_RCC_PLL_MUL_9
892 * @arg @ref LL_RCC_PLL_MUL_10
893 * @arg @ref LL_RCC_PLL_MUL_11
894 * @arg @ref LL_RCC_PLL_MUL_12
895 * @arg @ref LL_RCC_PLL_MUL_13
896 * @arg @ref LL_RCC_PLL_MUL_14
897 * @arg @ref LL_RCC_PLL_MUL_15
898 * @arg @ref LL_RCC_PLL_MUL_16
899 * @param __PLLPREDIV__ This parameter can be one of the following values:
900 * @arg @ref LL_RCC_PREDIV_DIV_1
901 * @arg @ref LL_RCC_PREDIV_DIV_2
902 * @arg @ref LL_RCC_PREDIV_DIV_3
903 * @arg @ref LL_RCC_PREDIV_DIV_4
904 * @arg @ref LL_RCC_PREDIV_DIV_5
905 * @arg @ref LL_RCC_PREDIV_DIV_6
906 * @arg @ref LL_RCC_PREDIV_DIV_7
907 * @arg @ref LL_RCC_PREDIV_DIV_8
908 * @arg @ref LL_RCC_PREDIV_DIV_9
909 * @arg @ref LL_RCC_PREDIV_DIV_10
910 * @arg @ref LL_RCC_PREDIV_DIV_11
911 * @arg @ref LL_RCC_PREDIV_DIV_12
912 * @arg @ref LL_RCC_PREDIV_DIV_13
913 * @arg @ref LL_RCC_PREDIV_DIV_14
914 * @arg @ref LL_RCC_PREDIV_DIV_15
915 * @arg @ref LL_RCC_PREDIV_DIV_16
916 * @retval PLL clock frequency (in Hz)
917 */
918 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__, __PLLPREDIV__) \
919 (((__INPUTFREQ__) / ((((__PLLPREDIV__) & RCC_CFGR2_PREDIV) + 1U))) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
920
921 #else
922 /**
923 * @brief Helper macro to calculate the PLLCLK frequency
924 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
925 * @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv / HSI div 2)
926 * @param __PLLMUL__ This parameter can be one of the following values:
927 * @arg @ref LL_RCC_PLL_MUL_2
928 * @arg @ref LL_RCC_PLL_MUL_3
929 * @arg @ref LL_RCC_PLL_MUL_4
930 * @arg @ref LL_RCC_PLL_MUL_5
931 * @arg @ref LL_RCC_PLL_MUL_6
932 * @arg @ref LL_RCC_PLL_MUL_7
933 * @arg @ref LL_RCC_PLL_MUL_8
934 * @arg @ref LL_RCC_PLL_MUL_9
935 * @arg @ref LL_RCC_PLL_MUL_10
936 * @arg @ref LL_RCC_PLL_MUL_11
937 * @arg @ref LL_RCC_PLL_MUL_12
938 * @arg @ref LL_RCC_PLL_MUL_13
939 * @arg @ref LL_RCC_PLL_MUL_14
940 * @arg @ref LL_RCC_PLL_MUL_15
941 * @arg @ref LL_RCC_PLL_MUL_16
942 * @retval PLL clock frequency (in Hz)
943 */
944 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
945 ((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMUL) >> RCC_POSITION_PLLMUL) + 2U))
946 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
947 /**
948 * @brief Helper macro to calculate the HCLK frequency
949 * @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
950 * ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
951 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
952 * @param __AHBPRESCALER__ This parameter can be one of the following values:
953 * @arg @ref LL_RCC_SYSCLK_DIV_1
954 * @arg @ref LL_RCC_SYSCLK_DIV_2
955 * @arg @ref LL_RCC_SYSCLK_DIV_4
956 * @arg @ref LL_RCC_SYSCLK_DIV_8
957 * @arg @ref LL_RCC_SYSCLK_DIV_16
958 * @arg @ref LL_RCC_SYSCLK_DIV_64
959 * @arg @ref LL_RCC_SYSCLK_DIV_128
960 * @arg @ref LL_RCC_SYSCLK_DIV_256
961 * @arg @ref LL_RCC_SYSCLK_DIV_512
962 * @retval HCLK clock frequency (in Hz)
963 */
964 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
965
966 /**
967 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
968 * @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
969 * ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
970 * @param __HCLKFREQ__ HCLK frequency
971 * @param __APB1PRESCALER__: This parameter can be one of the following values:
972 * @arg @ref LL_RCC_APB1_DIV_1
973 * @arg @ref LL_RCC_APB1_DIV_2
974 * @arg @ref LL_RCC_APB1_DIV_4
975 * @arg @ref LL_RCC_APB1_DIV_8
976 * @arg @ref LL_RCC_APB1_DIV_16
977 * @retval PCLK1 clock frequency (in Hz)
978 */
979 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
980
981 /**
982 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
983 * @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
984 * ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
985 * @param __HCLKFREQ__ HCLK frequency
986 * @param __APB2PRESCALER__: This parameter can be one of the following values:
987 * @arg @ref LL_RCC_APB2_DIV_1
988 * @arg @ref LL_RCC_APB2_DIV_2
989 * @arg @ref LL_RCC_APB2_DIV_4
990 * @arg @ref LL_RCC_APB2_DIV_8
991 * @arg @ref LL_RCC_APB2_DIV_16
992 * @retval PCLK2 clock frequency (in Hz)
993 */
994 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
995
996 /**
997 * @}
998 */
999
1000 /**
1001 * @}
1002 */
1003
1004 /* Exported functions --------------------------------------------------------*/
1005 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1006 * @{
1007 */
1008
1009 /** @defgroup RCC_LL_EF_HSE HSE
1010 * @{
1011 */
1012
1013 /**
1014 * @brief Enable the Clock Security System.
1015 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1016 * @retval None
1017 */
1018 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1019 {
1020 SET_BIT(RCC->CR, RCC_CR_CSSON);
1021 }
1022
1023 /**
1024 * @brief Disable the Clock Security System.
1025 * @note Cannot be disabled in HSE is ready (only by hardware)
1026 * @rmtoll CR CSSON LL_RCC_HSE_DisableCSS
1027 * @retval None
1028 */
1029 __STATIC_INLINE void LL_RCC_HSE_DisableCSS(void)
1030 {
1031 CLEAR_BIT(RCC->CR, RCC_CR_CSSON);
1032 }
1033
1034 /**
1035 * @brief Enable HSE external oscillator (HSE Bypass)
1036 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1037 * @retval None
1038 */
1039 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1040 {
1041 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1042 }
1043
1044 /**
1045 * @brief Disable HSE external oscillator (HSE Bypass)
1046 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1047 * @retval None
1048 */
1049 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1050 {
1051 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1052 }
1053
1054 /**
1055 * @brief Enable HSE crystal oscillator (HSE ON)
1056 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1057 * @retval None
1058 */
1059 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1060 {
1061 SET_BIT(RCC->CR, RCC_CR_HSEON);
1062 }
1063
1064 /**
1065 * @brief Disable HSE crystal oscillator (HSE ON)
1066 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1067 * @retval None
1068 */
1069 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1070 {
1071 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1072 }
1073
1074 /**
1075 * @brief Check if HSE oscillator Ready
1076 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1077 * @retval State of bit (1 or 0).
1078 */
1079 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1080 {
1081 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
1082 }
1083
1084 /**
1085 * @}
1086 */
1087
1088 /** @defgroup RCC_LL_EF_HSI HSI
1089 * @{
1090 */
1091
1092 /**
1093 * @brief Enable HSI oscillator
1094 * @rmtoll CR HSION LL_RCC_HSI_Enable
1095 * @retval None
1096 */
1097 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1098 {
1099 SET_BIT(RCC->CR, RCC_CR_HSION);
1100 }
1101
1102 /**
1103 * @brief Disable HSI oscillator
1104 * @rmtoll CR HSION LL_RCC_HSI_Disable
1105 * @retval None
1106 */
1107 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1108 {
1109 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1110 }
1111
1112 /**
1113 * @brief Check if HSI clock is ready
1114 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1115 * @retval State of bit (1 or 0).
1116 */
1117 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1118 {
1119 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
1120 }
1121
1122 /**
1123 * @brief Get HSI Calibration value
1124 * @note When HSITRIM is written, HSICAL is updated with the sum of
1125 * HSITRIM and the factory trim value
1126 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
1127 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1128 */
1129 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1130 {
1131 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
1132 }
1133
1134 /**
1135 * @brief Set HSI Calibration trimming
1136 * @note user-programmable trimming value that is added to the HSICAL
1137 * @note Default value is 16, which, when added to the HSICAL value,
1138 * should trim the HSI to 16 MHz +/- 1 %
1139 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
1140 * @param Value between Min_Data = 0x00 and Max_Data = 0x1F
1141 * @retval None
1142 */
1143 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1144 {
1145 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
1146 }
1147
1148 /**
1149 * @brief Get HSI Calibration trimming
1150 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
1151 * @retval Between Min_Data = 0x00 and Max_Data = 0x1F
1152 */
1153 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1154 {
1155 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
1156 }
1157
1158 /**
1159 * @}
1160 */
1161
1162 /** @defgroup RCC_LL_EF_LSE LSE
1163 * @{
1164 */
1165
1166 /**
1167 * @brief Enable Low Speed External (LSE) crystal.
1168 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1169 * @retval None
1170 */
1171 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1172 {
1173 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1174 }
1175
1176 /**
1177 * @brief Disable Low Speed External (LSE) crystal.
1178 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1179 * @retval None
1180 */
1181 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1182 {
1183 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1184 }
1185
1186 /**
1187 * @brief Enable external clock source (LSE bypass).
1188 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1189 * @retval None
1190 */
1191 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1192 {
1193 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1194 }
1195
1196 /**
1197 * @brief Disable external clock source (LSE bypass).
1198 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1199 * @retval None
1200 */
1201 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1202 {
1203 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1204 }
1205
1206 /**
1207 * @brief Set LSE oscillator drive capability
1208 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1209 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1210 * @param LSEDrive This parameter can be one of the following values:
1211 * @arg @ref LL_RCC_LSEDRIVE_LOW
1212 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1213 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1214 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1215 * @retval None
1216 */
1217 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1218 {
1219 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1220 }
1221
1222 /**
1223 * @brief Get LSE oscillator drive capability
1224 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1225 * @retval Returned value can be one of the following values:
1226 * @arg @ref LL_RCC_LSEDRIVE_LOW
1227 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1228 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1229 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1230 */
1231 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1232 {
1233 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1234 }
1235
1236 /**
1237 * @brief Check if LSE oscillator Ready
1238 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1239 * @retval State of bit (1 or 0).
1240 */
1241 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1242 {
1243 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
1244 }
1245
1246 /**
1247 * @}
1248 */
1249
1250 /** @defgroup RCC_LL_EF_LSI LSI
1251 * @{
1252 */
1253
1254 /**
1255 * @brief Enable LSI Oscillator
1256 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1257 * @retval None
1258 */
1259 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1260 {
1261 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1262 }
1263
1264 /**
1265 * @brief Disable LSI Oscillator
1266 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1267 * @retval None
1268 */
1269 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1270 {
1271 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1272 }
1273
1274 /**
1275 * @brief Check if LSI is Ready
1276 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1277 * @retval State of bit (1 or 0).
1278 */
1279 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1280 {
1281 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
1282 }
1283
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup RCC_LL_EF_System System
1289 * @{
1290 */
1291
1292 /**
1293 * @brief Configure the system clock source
1294 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1295 * @param Source This parameter can be one of the following values:
1296 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1297 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1298 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1299 * @retval None
1300 */
1301 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1302 {
1303 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1304 }
1305
1306 /**
1307 * @brief Get the system clock source
1308 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1309 * @retval Returned value can be one of the following values:
1310 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1311 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1312 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1313 */
1314 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1315 {
1316 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1317 }
1318
1319 /**
1320 * @brief Set AHB prescaler
1321 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1322 * @param Prescaler This parameter can be one of the following values:
1323 * @arg @ref LL_RCC_SYSCLK_DIV_1
1324 * @arg @ref LL_RCC_SYSCLK_DIV_2
1325 * @arg @ref LL_RCC_SYSCLK_DIV_4
1326 * @arg @ref LL_RCC_SYSCLK_DIV_8
1327 * @arg @ref LL_RCC_SYSCLK_DIV_16
1328 * @arg @ref LL_RCC_SYSCLK_DIV_64
1329 * @arg @ref LL_RCC_SYSCLK_DIV_128
1330 * @arg @ref LL_RCC_SYSCLK_DIV_256
1331 * @arg @ref LL_RCC_SYSCLK_DIV_512
1332 * @retval None
1333 */
1334 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1335 {
1336 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1337 }
1338
1339 /**
1340 * @brief Set APB1 prescaler
1341 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1342 * @param Prescaler This parameter can be one of the following values:
1343 * @arg @ref LL_RCC_APB1_DIV_1
1344 * @arg @ref LL_RCC_APB1_DIV_2
1345 * @arg @ref LL_RCC_APB1_DIV_4
1346 * @arg @ref LL_RCC_APB1_DIV_8
1347 * @arg @ref LL_RCC_APB1_DIV_16
1348 * @retval None
1349 */
1350 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1351 {
1352 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1353 }
1354
1355 /**
1356 * @brief Set APB2 prescaler
1357 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1358 * @param Prescaler This parameter can be one of the following values:
1359 * @arg @ref LL_RCC_APB2_DIV_1
1360 * @arg @ref LL_RCC_APB2_DIV_2
1361 * @arg @ref LL_RCC_APB2_DIV_4
1362 * @arg @ref LL_RCC_APB2_DIV_8
1363 * @arg @ref LL_RCC_APB2_DIV_16
1364 * @retval None
1365 */
1366 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1367 {
1368 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1369 }
1370
1371 /**
1372 * @brief Get AHB prescaler
1373 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1374 * @retval Returned value can be one of the following values:
1375 * @arg @ref LL_RCC_SYSCLK_DIV_1
1376 * @arg @ref LL_RCC_SYSCLK_DIV_2
1377 * @arg @ref LL_RCC_SYSCLK_DIV_4
1378 * @arg @ref LL_RCC_SYSCLK_DIV_8
1379 * @arg @ref LL_RCC_SYSCLK_DIV_16
1380 * @arg @ref LL_RCC_SYSCLK_DIV_64
1381 * @arg @ref LL_RCC_SYSCLK_DIV_128
1382 * @arg @ref LL_RCC_SYSCLK_DIV_256
1383 * @arg @ref LL_RCC_SYSCLK_DIV_512
1384 */
1385 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1386 {
1387 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1388 }
1389
1390 /**
1391 * @brief Get APB1 prescaler
1392 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1393 * @retval Returned value can be one of the following values:
1394 * @arg @ref LL_RCC_APB1_DIV_1
1395 * @arg @ref LL_RCC_APB1_DIV_2
1396 * @arg @ref LL_RCC_APB1_DIV_4
1397 * @arg @ref LL_RCC_APB1_DIV_8
1398 * @arg @ref LL_RCC_APB1_DIV_16
1399 */
1400 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1401 {
1402 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1403 }
1404
1405 /**
1406 * @brief Get APB2 prescaler
1407 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1408 * @retval Returned value can be one of the following values:
1409 * @arg @ref LL_RCC_APB2_DIV_1
1410 * @arg @ref LL_RCC_APB2_DIV_2
1411 * @arg @ref LL_RCC_APB2_DIV_4
1412 * @arg @ref LL_RCC_APB2_DIV_8
1413 * @arg @ref LL_RCC_APB2_DIV_16
1414 */
1415 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1416 {
1417 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1418 }
1419
1420 /**
1421 * @}
1422 */
1423
1424 /** @defgroup RCC_LL_EF_MCO MCO
1425 * @{
1426 */
1427
1428 /**
1429 * @brief Configure MCOx
1430 * @rmtoll CFGR MCO LL_RCC_ConfigMCO\n
1431 * CFGR MCOPRE LL_RCC_ConfigMCO\n
1432 * CFGR PLLNODIV LL_RCC_ConfigMCO
1433 * @param MCOxSource This parameter can be one of the following values:
1434 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1435 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1436 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1437 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1438 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1439 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1440 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK (*)
1441 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
1442 *
1443 * (*) value not defined in all devices
1444 * @param MCOxPrescaler This parameter can be one of the following values:
1445 * @arg @ref LL_RCC_MCO1_DIV_1
1446 * @arg @ref LL_RCC_MCO1_DIV_2 (*)
1447 * @arg @ref LL_RCC_MCO1_DIV_4 (*)
1448 * @arg @ref LL_RCC_MCO1_DIV_8 (*)
1449 * @arg @ref LL_RCC_MCO1_DIV_16 (*)
1450 * @arg @ref LL_RCC_MCO1_DIV_32 (*)
1451 * @arg @ref LL_RCC_MCO1_DIV_64 (*)
1452 * @arg @ref LL_RCC_MCO1_DIV_128 (*)
1453 *
1454 * (*) value not defined in all devices
1455 * @retval None
1456 */
1457 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1458 {
1459 #if defined(RCC_CFGR_MCOPRE)
1460 #if defined(RCC_CFGR_PLLNODIV)
1461 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE | RCC_CFGR_PLLNODIV, MCOxSource | MCOxPrescaler);
1462 #else
1463 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1464 #endif /* RCC_CFGR_PLLNODIV */
1465 #else
1466 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
1467 #endif /* RCC_CFGR_MCOPRE */
1468 }
1469
1470 /**
1471 * @}
1472 */
1473
1474 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1475 * @{
1476 */
1477
1478 /**
1479 * @brief Configure USARTx clock source
1480 * @rmtoll CFGR3 USART1SW LL_RCC_SetUSARTClockSource\n
1481 * CFGR3 USART2SW LL_RCC_SetUSARTClockSource\n
1482 * CFGR3 USART3SW LL_RCC_SetUSARTClockSource
1483 * @param USARTxSource This parameter can be one of the following values:
1484 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1485 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1486 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1487 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1488 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1489 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1490 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1491 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1492 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1493 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1494 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1495 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1496 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1497 *
1498 * (*) value not defined in all devices.
1499 * @retval None
1500 */
1501 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1502 {
1503 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_USART1SW << ((USARTxSource & 0xFF000000U) >> 24U)), (USARTxSource & 0x00FFFFFFU));
1504 }
1505
1506 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1507 /**
1508 * @brief Configure UARTx clock source
1509 * @rmtoll CFGR3 UART4SW LL_RCC_SetUARTClockSource\n
1510 * CFGR3 UART5SW LL_RCC_SetUARTClockSource
1511 * @param UARTxSource This parameter can be one of the following values:
1512 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1513 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1514 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1515 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1516 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1517 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1518 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1519 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1520 * @retval None
1521 */
1522 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1523 {
1524 MODIFY_REG(RCC->CFGR3, ((UARTxSource & 0x0000FFFFU) << 8U), (UARTxSource & (RCC_CFGR3_UART4SW | RCC_CFGR3_UART5SW)));
1525 }
1526 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1527
1528 /**
1529 * @brief Configure I2Cx clock source
1530 * @rmtoll CFGR3 I2C1SW LL_RCC_SetI2CClockSource\n
1531 * CFGR3 I2C2SW LL_RCC_SetI2CClockSource\n
1532 * CFGR3 I2C3SW LL_RCC_SetI2CClockSource
1533 * @param I2CxSource This parameter can be one of the following values:
1534 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1535 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1536 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1537 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1538 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1539 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1540 *
1541 * (*) value not defined in all devices.
1542 * @retval None
1543 */
1544 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1545 {
1546 MODIFY_REG(RCC->CFGR3, ((I2CxSource & 0xFF000000U) >> 24U), (I2CxSource & 0x00FFFFFFU));
1547 }
1548
1549 #if defined(RCC_CFGR_I2SSRC)
1550 /**
1551 * @brief Configure I2Sx clock source
1552 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
1553 * @param I2SxSource This parameter can be one of the following values:
1554 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1555 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1556 * @retval None
1557 */
1558 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1559 {
1560 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, I2SxSource);
1561 }
1562 #endif /* RCC_CFGR_I2SSRC */
1563
1564 #if defined(RCC_CFGR3_TIMSW)
1565 /**
1566 * @brief Configure TIMx clock source
1567 * @rmtoll CFGR3 TIM1SW LL_RCC_SetTIMClockSource\n
1568 * CFGR3 TIM8SW LL_RCC_SetTIMClockSource\n
1569 * CFGR3 TIM15SW LL_RCC_SetTIMClockSource\n
1570 * CFGR3 TIM16SW LL_RCC_SetTIMClockSource\n
1571 * CFGR3 TIM17SW LL_RCC_SetTIMClockSource\n
1572 * CFGR3 TIM20SW LL_RCC_SetTIMClockSource\n
1573 * CFGR3 TIM2SW LL_RCC_SetTIMClockSource\n
1574 * CFGR3 TIM34SW LL_RCC_SetTIMClockSource
1575 * @param TIMxSource This parameter can be one of the following values:
1576 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1577 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1578 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1579 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1580 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1581 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1582 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1583 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1584 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1585 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1586 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1587 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1588 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1589 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1590 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1591 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1592 *
1593 * (*) value not defined in all devices.
1594 * @retval None
1595 */
1596 __STATIC_INLINE void LL_RCC_SetTIMClockSource(uint32_t TIMxSource)
1597 {
1598 MODIFY_REG(RCC->CFGR3, (RCC_CFGR3_TIM1SW << (TIMxSource >> 27U)), (TIMxSource & 0x03FFFFFFU));
1599 }
1600 #endif /* RCC_CFGR3_TIMSW */
1601
1602 #if defined(HRTIM1)
1603 /**
1604 * @brief Configure HRTIMx clock source
1605 * @rmtoll CFGR3 HRTIMSW LL_RCC_SetHRTIMClockSource
1606 * @param HRTIMxSource This parameter can be one of the following values:
1607 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1608 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1609 * @retval None
1610 */
1611 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t HRTIMxSource)
1612 {
1613 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIMSW, HRTIMxSource);
1614 }
1615 #endif /* HRTIM1 */
1616
1617 #if defined(CEC)
1618 /**
1619 * @brief Configure CEC clock source
1620 * @rmtoll CFGR3 CECSW LL_RCC_SetCECClockSource
1621 * @param CECxSource This parameter can be one of the following values:
1622 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1623 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1624 * @retval None
1625 */
1626 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t CECxSource)
1627 {
1628 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, CECxSource);
1629 }
1630 #endif /* CEC */
1631
1632 #if defined(USB)
1633 /**
1634 * @brief Configure USB clock source
1635 * @rmtoll CFGR USBPRE LL_RCC_SetUSBClockSource
1636 * @param USBxSource This parameter can be one of the following values:
1637 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1638 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1639 * @retval None
1640 */
1641 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1642 {
1643 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
1644 }
1645 #endif /* USB */
1646
1647 #if defined(RCC_CFGR_ADCPRE)
1648 /**
1649 * @brief Configure ADC clock source
1650 * @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
1651 * @param ADCxSource This parameter can be one of the following values:
1652 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1653 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1654 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1655 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1656 * @retval None
1657 */
1658 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1659 {
1660 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
1661 }
1662
1663 #elif defined(RCC_CFGR2_ADC1PRES)
1664 /**
1665 * @brief Configure ADC clock source
1666 * @rmtoll CFGR2 ADC1PRES LL_RCC_SetADCClockSource
1667 * @param ADCxSource This parameter can be one of the following values:
1668 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1669 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1670 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1671 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1672 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1673 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1674 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1675 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1676 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1677 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1678 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1679 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1680 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1681 * @retval None
1682 */
1683 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1684 {
1685 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, ADCxSource);
1686 }
1687
1688 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
1689 /**
1690 * @brief Configure ADC clock source
1691 * @rmtoll CFGR2 ADCPRE12 LL_RCC_SetADCClockSource\n
1692 * CFGR2 ADCPRE34 LL_RCC_SetADCClockSource
1693 * @param ADCxSource This parameter can be one of the following values:
1694 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
1695 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
1696 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
1697 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
1698 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
1699 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
1700 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
1701 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
1702 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
1703 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
1704 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
1705 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
1706 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
1707 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
1708 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
1709 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
1710 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
1711 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
1712 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
1713 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
1714 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
1715 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
1716 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
1717 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
1718 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
1719 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
1720 *
1721 * (*) value not defined in all devices.
1722 * @retval None
1723 */
1724 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1725 {
1726 #if defined(RCC_CFGR2_ADCPRE34)
1727 MODIFY_REG(RCC->CFGR2, (ADCxSource >> 16U), (ADCxSource & 0x0000FFFFU));
1728 #else
1729 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, ADCxSource);
1730 #endif /* RCC_CFGR2_ADCPRE34 */
1731 }
1732 #endif /* RCC_CFGR_ADCPRE */
1733
1734 #if defined(RCC_CFGR_SDPRE)
1735 /**
1736 * @brief Configure SDADCx clock source
1737 * @rmtoll CFGR SDPRE LL_RCC_SetSDADCClockSource
1738 * @param SDADCxSource This parameter can be one of the following values:
1739 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
1740 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
1741 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
1742 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
1743 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
1744 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
1745 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
1746 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
1747 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
1748 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
1749 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
1750 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
1751 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
1752 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
1753 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
1754 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
1755 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
1756 * @retval None
1757 */
1758 __STATIC_INLINE void LL_RCC_SetSDADCClockSource(uint32_t SDADCxSource)
1759 {
1760 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDPRE, SDADCxSource);
1761 }
1762 #endif /* RCC_CFGR_SDPRE */
1763
1764 /**
1765 * @brief Get USARTx clock source
1766 * @rmtoll CFGR3 USART1SW LL_RCC_GetUSARTClockSource\n
1767 * CFGR3 USART2SW LL_RCC_GetUSARTClockSource\n
1768 * CFGR3 USART3SW LL_RCC_GetUSARTClockSource
1769 * @param USARTx This parameter can be one of the following values:
1770 * @arg @ref LL_RCC_USART1_CLKSOURCE
1771 * @arg @ref LL_RCC_USART2_CLKSOURCE (*)
1772 * @arg @ref LL_RCC_USART3_CLKSOURCE (*)
1773 *
1774 * (*) value not defined in all devices.
1775 * @retval Returned value can be one of the following values:
1776 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK1 (*)
1777 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 (*)
1778 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1779 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1780 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1781 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*)
1782 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*)
1783 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*)
1784 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*)
1785 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
1786 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
1787 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
1788 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
1789 *
1790 * (*) value not defined in all devices.
1791 */
1792 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1793 {
1794 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_USART1SW << USARTx)) | (USARTx << 24U));
1795 }
1796
1797 #if defined(RCC_CFGR3_UART4SW) || defined(RCC_CFGR3_UART5SW)
1798 /**
1799 * @brief Get UARTx clock source
1800 * @rmtoll CFGR3 UART4SW LL_RCC_GetUARTClockSource\n
1801 * CFGR3 UART5SW LL_RCC_GetUARTClockSource
1802 * @param UARTx This parameter can be one of the following values:
1803 * @arg @ref LL_RCC_UART4_CLKSOURCE
1804 * @arg @ref LL_RCC_UART5_CLKSOURCE
1805 * @retval Returned value can be one of the following values:
1806 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
1807 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
1808 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
1809 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
1810 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
1811 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
1812 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
1813 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
1814 */
1815 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1816 {
1817 return (uint32_t)(READ_BIT(RCC->CFGR3, UARTx) | (UARTx >> 8U));
1818 }
1819 #endif /* RCC_CFGR3_UART4SW || RCC_CFGR3_UART5SW */
1820
1821 /**
1822 * @brief Get I2Cx clock source
1823 * @rmtoll CFGR3 I2C1SW LL_RCC_GetI2CClockSource\n
1824 * CFGR3 I2C2SW LL_RCC_GetI2CClockSource\n
1825 * CFGR3 I2C3SW LL_RCC_GetI2CClockSource
1826 * @param I2Cx This parameter can be one of the following values:
1827 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1828 * @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
1829 * @arg @ref LL_RCC_I2C3_CLKSOURCE (*)
1830 *
1831 * (*) value not defined in all devices.
1832 * @retval Returned value can be one of the following values:
1833 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1834 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1835 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
1836 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
1837 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI (*)
1838 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK (*)
1839 *
1840 * (*) value not defined in all devices.
1841 */
1842 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1843 {
1844 return (uint32_t)(READ_BIT(RCC->CFGR3, I2Cx) | (I2Cx << 24U));
1845 }
1846
1847 #if defined(RCC_CFGR_I2SSRC)
1848 /**
1849 * @brief Get I2Sx clock source
1850 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
1851 * @param I2Sx This parameter can be one of the following values:
1852 * @arg @ref LL_RCC_I2S_CLKSOURCE
1853 * @retval Returned value can be one of the following values:
1854 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1855 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1856 */
1857 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1858 {
1859 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
1860 }
1861 #endif /* RCC_CFGR_I2SSRC */
1862
1863 #if defined(RCC_CFGR3_TIMSW)
1864 /**
1865 * @brief Get TIMx clock source
1866 * @rmtoll CFGR3 TIM1SW LL_RCC_GetTIMClockSource\n
1867 * CFGR3 TIM8SW LL_RCC_GetTIMClockSource\n
1868 * CFGR3 TIM15SW LL_RCC_GetTIMClockSource\n
1869 * CFGR3 TIM16SW LL_RCC_GetTIMClockSource\n
1870 * CFGR3 TIM17SW LL_RCC_GetTIMClockSource\n
1871 * CFGR3 TIM20SW LL_RCC_GetTIMClockSource\n
1872 * CFGR3 TIM2SW LL_RCC_GetTIMClockSource\n
1873 * CFGR3 TIM34SW LL_RCC_GetTIMClockSource
1874 * @param TIMx This parameter can be one of the following values:
1875 * @arg @ref LL_RCC_TIM1_CLKSOURCE
1876 * @arg @ref LL_RCC_TIM2_CLKSOURCE (*)
1877 * @arg @ref LL_RCC_TIM8_CLKSOURCE (*)
1878 * @arg @ref LL_RCC_TIM15_CLKSOURCE (*)
1879 * @arg @ref LL_RCC_TIM16_CLKSOURCE (*)
1880 * @arg @ref LL_RCC_TIM17_CLKSOURCE (*)
1881 * @arg @ref LL_RCC_TIM20_CLKSOURCE (*)
1882 * @arg @ref LL_RCC_TIM34_CLKSOURCE (*)
1883 *
1884 * (*) value not defined in all devices.
1885 * @retval Returned value can be one of the following values:
1886 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PCLK2
1887 * @arg @ref LL_RCC_TIM1_CLKSOURCE_PLL
1888 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PCLK2 (*)
1889 * @arg @ref LL_RCC_TIM8_CLKSOURCE_PLL (*)
1890 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PCLK2 (*)
1891 * @arg @ref LL_RCC_TIM15_CLKSOURCE_PLL (*)
1892 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PCLK2 (*)
1893 * @arg @ref LL_RCC_TIM16_CLKSOURCE_PLL (*)
1894 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PCLK2 (*)
1895 * @arg @ref LL_RCC_TIM17_CLKSOURCE_PLL (*)
1896 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PCLK2 (*)
1897 * @arg @ref LL_RCC_TIM20_CLKSOURCE_PLL (*)
1898 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PCLK1 (*)
1899 * @arg @ref LL_RCC_TIM2_CLKSOURCE_PLL (*)
1900 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PCLK1 (*)
1901 * @arg @ref LL_RCC_TIM34_CLKSOURCE_PLL (*)
1902 *
1903 * (*) value not defined in all devices.
1904 */
1905 __STATIC_INLINE uint32_t LL_RCC_GetTIMClockSource(uint32_t TIMx)
1906 {
1907 return (uint32_t)(READ_BIT(RCC->CFGR3, (RCC_CFGR3_TIM1SW << TIMx)) | (TIMx << 27U));
1908 }
1909 #endif /* RCC_CFGR3_TIMSW */
1910
1911 #if defined(HRTIM1)
1912 /**
1913 * @brief Get HRTIMx clock source
1914 * @rmtoll CFGR3 HRTIMSW LL_RCC_GetHRTIMClockSource
1915 * @param HRTIMx This parameter can be one of the following values:
1916 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE
1917 * @retval Returned value can be one of the following values:
1918 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PCLK2
1919 * @arg @ref LL_RCC_HRTIM1_CLKSOURCE_PLL
1920 */
1921 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(uint32_t HRTIMx)
1922 {
1923 return (uint32_t)(READ_BIT(RCC->CFGR3, HRTIMx));
1924 }
1925 #endif /* HRTIM1 */
1926
1927 #if defined(CEC)
1928 /**
1929 * @brief Get CEC clock source
1930 * @rmtoll CFGR3 CECSW LL_RCC_GetCECClockSource
1931 * @param CECx This parameter can be one of the following values:
1932 * @arg @ref LL_RCC_CEC_CLKSOURCE
1933 * @retval Returned value can be one of the following values:
1934 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV244
1935 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
1936 */
1937 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
1938 {
1939 return (uint32_t)(READ_BIT(RCC->CFGR3, CECx));
1940 }
1941 #endif /* CEC */
1942
1943 #if defined(USB)
1944 /**
1945 * @brief Get USBx clock source
1946 * @rmtoll CFGR USBPRE LL_RCC_GetUSBClockSource
1947 * @param USBx This parameter can be one of the following values:
1948 * @arg @ref LL_RCC_USB_CLKSOURCE
1949 * @retval Returned value can be one of the following values:
1950 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1951 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5
1952 */
1953 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1954 {
1955 return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
1956 }
1957 #endif /* USB */
1958
1959 #if defined(RCC_CFGR_ADCPRE)
1960 /**
1961 * @brief Get ADCx clock source
1962 * @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
1963 * @param ADCx This parameter can be one of the following values:
1964 * @arg @ref LL_RCC_ADC_CLKSOURCE
1965 * @retval Returned value can be one of the following values:
1966 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
1967 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
1968 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
1969 * @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
1970 */
1971 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1972 {
1973 return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
1974 }
1975
1976 #elif defined(RCC_CFGR2_ADC1PRES)
1977 /**
1978 * @brief Get ADCx clock source
1979 * @rmtoll CFGR2 ADC1PRES LL_RCC_GetADCClockSource
1980 * @param ADCx This parameter can be one of the following values:
1981 * @arg @ref LL_RCC_ADC1_CLKSOURCE
1982 * @retval Returned value can be one of the following values:
1983 * @arg @ref LL_RCC_ADC1_CLKSRC_HCLK
1984 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_1
1985 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_2
1986 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_4
1987 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_6
1988 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_8
1989 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_10
1990 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_12
1991 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_16
1992 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_32
1993 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_64
1994 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_128
1995 * @arg @ref LL_RCC_ADC1_CLKSRC_PLL_DIV_256
1996 */
1997 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1998 {
1999 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
2000 }
2001
2002 #elif defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34)
2003 /**
2004 * @brief Get ADCx clock source
2005 * @rmtoll CFGR2 ADCPRE12 LL_RCC_GetADCClockSource\n
2006 * CFGR2 ADCPRE34 LL_RCC_GetADCClockSource
2007 * @param ADCx This parameter can be one of the following values:
2008 * @arg @ref LL_RCC_ADC12_CLKSOURCE
2009 * @arg @ref LL_RCC_ADC34_CLKSOURCE (*)
2010 *
2011 * (*) value not defined in all devices.
2012 * @retval Returned value can be one of the following values:
2013 * @arg @ref LL_RCC_ADC12_CLKSRC_HCLK
2014 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_1
2015 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_2
2016 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_4
2017 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_6
2018 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_8
2019 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_10
2020 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_12
2021 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_16
2022 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_32
2023 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_64
2024 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_128
2025 * @arg @ref LL_RCC_ADC12_CLKSRC_PLL_DIV_256
2026 * @arg @ref LL_RCC_ADC34_CLKSRC_HCLK (*)
2027 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_1 (*)
2028 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_2 (*)
2029 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_4 (*)
2030 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_6 (*)
2031 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_8 (*)
2032 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_10 (*)
2033 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_12 (*)
2034 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_16 (*)
2035 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_32 (*)
2036 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_64 (*)
2037 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_128 (*)
2038 * @arg @ref LL_RCC_ADC34_CLKSRC_PLL_DIV_256 (*)
2039 *
2040 * (*) value not defined in all devices.
2041 */
2042 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
2043 {
2044 #if defined(RCC_CFGR2_ADCPRE34)
2045 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx) | (ADCx << 16U));
2046 #else
2047 return (uint32_t)(READ_BIT(RCC->CFGR2, ADCx));
2048 #endif /*RCC_CFGR2_ADCPRE34*/
2049 }
2050 #endif /* RCC_CFGR_ADCPRE */
2051
2052 #if defined(RCC_CFGR_SDPRE)
2053 /**
2054 * @brief Get SDADCx clock source
2055 * @rmtoll CFGR SDPRE LL_RCC_GetSDADCClockSource
2056 * @param SDADCx This parameter can be one of the following values:
2057 * @arg @ref LL_RCC_SDADC_CLKSOURCE
2058 * @retval Returned value can be one of the following values:
2059 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_1
2060 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_2
2061 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_4
2062 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_6
2063 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_8
2064 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_10
2065 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_12
2066 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_14
2067 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_16
2068 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_20
2069 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_24
2070 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_28
2071 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_32
2072 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_36
2073 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_40
2074 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_44
2075 * @arg @ref LL_RCC_SDADC_CLKSRC_SYS_DIV_48
2076 */
2077 __STATIC_INLINE uint32_t LL_RCC_GetSDADCClockSource(uint32_t SDADCx)
2078 {
2079 return (uint32_t)(READ_BIT(RCC->CFGR, SDADCx));
2080 }
2081 #endif /* RCC_CFGR_SDPRE */
2082
2083 /**
2084 * @}
2085 */
2086
2087 /** @defgroup RCC_LL_EF_RTC RTC
2088 * @{
2089 */
2090
2091 /**
2092 * @brief Set RTC Clock Source
2093 * @note Once the RTC clock source has been selected, it cannot be changed any more unless
2094 * the Backup domain is reset. The BDRST bit can be used to reset them.
2095 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2096 * @param Source This parameter can be one of the following values:
2097 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2098 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2099 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2100 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2101 * @retval None
2102 */
2103 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2104 {
2105 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2106 }
2107
2108 /**
2109 * @brief Get RTC Clock Source
2110 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2111 * @retval Returned value can be one of the following values:
2112 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2113 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2114 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2115 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
2116 */
2117 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2118 {
2119 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2120 }
2121
2122 /**
2123 * @brief Enable RTC
2124 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2125 * @retval None
2126 */
2127 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2128 {
2129 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2130 }
2131
2132 /**
2133 * @brief Disable RTC
2134 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2135 * @retval None
2136 */
2137 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2138 {
2139 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2140 }
2141
2142 /**
2143 * @brief Check if RTC has been enabled or not
2144 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2145 * @retval State of bit (1 or 0).
2146 */
2147 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2148 {
2149 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2150 }
2151
2152 /**
2153 * @brief Force the Backup domain reset
2154 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2155 * @retval None
2156 */
2157 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2158 {
2159 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2160 }
2161
2162 /**
2163 * @brief Release the Backup domain reset
2164 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2165 * @retval None
2166 */
2167 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2168 {
2169 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2170 }
2171
2172 /**
2173 * @}
2174 */
2175
2176 /** @defgroup RCC_LL_EF_PLL PLL
2177 * @{
2178 */
2179
2180 /**
2181 * @brief Enable PLL
2182 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2183 * @retval None
2184 */
2185 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2186 {
2187 SET_BIT(RCC->CR, RCC_CR_PLLON);
2188 }
2189
2190 /**
2191 * @brief Disable PLL
2192 * @note Cannot be disabled if the PLL clock is used as the system clock
2193 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2194 * @retval None
2195 */
2196 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2197 {
2198 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2199 }
2200
2201 /**
2202 * @brief Check if PLL Ready
2203 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2204 * @retval State of bit (1 or 0).
2205 */
2206 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2207 {
2208 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
2209 }
2210
2211 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
2212 /**
2213 * @brief Configure PLL used for SYSCLK Domain
2214 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2215 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2216 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2217 * @param Source This parameter can be one of the following values:
2218 * @arg @ref LL_RCC_PLLSOURCE_HSI
2219 * @arg @ref LL_RCC_PLLSOURCE_HSE
2220 * @param PLLMul This parameter can be one of the following values:
2221 * @arg @ref LL_RCC_PLL_MUL_2
2222 * @arg @ref LL_RCC_PLL_MUL_3
2223 * @arg @ref LL_RCC_PLL_MUL_4
2224 * @arg @ref LL_RCC_PLL_MUL_5
2225 * @arg @ref LL_RCC_PLL_MUL_6
2226 * @arg @ref LL_RCC_PLL_MUL_7
2227 * @arg @ref LL_RCC_PLL_MUL_8
2228 * @arg @ref LL_RCC_PLL_MUL_9
2229 * @arg @ref LL_RCC_PLL_MUL_10
2230 * @arg @ref LL_RCC_PLL_MUL_11
2231 * @arg @ref LL_RCC_PLL_MUL_12
2232 * @arg @ref LL_RCC_PLL_MUL_13
2233 * @arg @ref LL_RCC_PLL_MUL_14
2234 * @arg @ref LL_RCC_PLL_MUL_15
2235 * @arg @ref LL_RCC_PLL_MUL_16
2236 * @param PLLDiv This parameter can be one of the following values:
2237 * @arg @ref LL_RCC_PREDIV_DIV_1
2238 * @arg @ref LL_RCC_PREDIV_DIV_2
2239 * @arg @ref LL_RCC_PREDIV_DIV_3
2240 * @arg @ref LL_RCC_PREDIV_DIV_4
2241 * @arg @ref LL_RCC_PREDIV_DIV_5
2242 * @arg @ref LL_RCC_PREDIV_DIV_6
2243 * @arg @ref LL_RCC_PREDIV_DIV_7
2244 * @arg @ref LL_RCC_PREDIV_DIV_8
2245 * @arg @ref LL_RCC_PREDIV_DIV_9
2246 * @arg @ref LL_RCC_PREDIV_DIV_10
2247 * @arg @ref LL_RCC_PREDIV_DIV_11
2248 * @arg @ref LL_RCC_PREDIV_DIV_12
2249 * @arg @ref LL_RCC_PREDIV_DIV_13
2250 * @arg @ref LL_RCC_PREDIV_DIV_14
2251 * @arg @ref LL_RCC_PREDIV_DIV_15
2252 * @arg @ref LL_RCC_PREDIV_DIV_16
2253 * @retval None
2254 */
2255 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv)
2256 {
2257 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, Source | PLLMul);
2258 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, PLLDiv);
2259 }
2260
2261 #else
2262
2263 /**
2264 * @brief Configure PLL used for SYSCLK Domain
2265 * @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2266 * CFGR PLLMUL LL_RCC_PLL_ConfigDomain_SYS\n
2267 * CFGR2 PREDIV LL_RCC_PLL_ConfigDomain_SYS
2268 * @param Source This parameter can be one of the following values:
2269 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
2270 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
2271 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2
2272 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3
2273 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4
2274 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5
2275 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6
2276 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7
2277 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8
2278 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9
2279 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10
2280 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11
2281 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12
2282 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13
2283 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14
2284 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15
2285 * @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16
2286 * @param PLLMul This parameter can be one of the following values:
2287 * @arg @ref LL_RCC_PLL_MUL_2
2288 * @arg @ref LL_RCC_PLL_MUL_3
2289 * @arg @ref LL_RCC_PLL_MUL_4
2290 * @arg @ref LL_RCC_PLL_MUL_5
2291 * @arg @ref LL_RCC_PLL_MUL_6
2292 * @arg @ref LL_RCC_PLL_MUL_7
2293 * @arg @ref LL_RCC_PLL_MUL_8
2294 * @arg @ref LL_RCC_PLL_MUL_9
2295 * @arg @ref LL_RCC_PLL_MUL_10
2296 * @arg @ref LL_RCC_PLL_MUL_11
2297 * @arg @ref LL_RCC_PLL_MUL_12
2298 * @arg @ref LL_RCC_PLL_MUL_13
2299 * @arg @ref LL_RCC_PLL_MUL_14
2300 * @arg @ref LL_RCC_PLL_MUL_15
2301 * @arg @ref LL_RCC_PLL_MUL_16
2302 * @retval None
2303 */
2304 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
2305 {
2306 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL, (Source & RCC_CFGR_PLLSRC) | PLLMul);
2307 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (Source & RCC_CFGR2_PREDIV));
2308 }
2309 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
2310
2311 /**
2312 * @brief Get the oscillator used as PLL clock source.
2313 * @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource
2314 * @retval Returned value can be one of the following values:
2315 * @arg @ref LL_RCC_PLLSOURCE_HSI (*)
2316 * @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2 (*)
2317 * @arg @ref LL_RCC_PLLSOURCE_HSE
2318 *
2319 * (*) value not defined in all devices
2320 */
2321 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2322 {
2323 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
2324 }
2325
2326 /**
2327 * @brief Get PLL multiplication Factor
2328 * @rmtoll CFGR PLLMUL LL_RCC_PLL_GetMultiplicator
2329 * @retval Returned value can be one of the following values:
2330 * @arg @ref LL_RCC_PLL_MUL_2
2331 * @arg @ref LL_RCC_PLL_MUL_3
2332 * @arg @ref LL_RCC_PLL_MUL_4
2333 * @arg @ref LL_RCC_PLL_MUL_5
2334 * @arg @ref LL_RCC_PLL_MUL_6
2335 * @arg @ref LL_RCC_PLL_MUL_7
2336 * @arg @ref LL_RCC_PLL_MUL_8
2337 * @arg @ref LL_RCC_PLL_MUL_9
2338 * @arg @ref LL_RCC_PLL_MUL_10
2339 * @arg @ref LL_RCC_PLL_MUL_11
2340 * @arg @ref LL_RCC_PLL_MUL_12
2341 * @arg @ref LL_RCC_PLL_MUL_13
2342 * @arg @ref LL_RCC_PLL_MUL_14
2343 * @arg @ref LL_RCC_PLL_MUL_15
2344 * @arg @ref LL_RCC_PLL_MUL_16
2345 */
2346 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
2347 {
2348 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL));
2349 }
2350
2351 /**
2352 * @brief Get PREDIV division factor for the main PLL
2353 * @note They can be written only when the PLL is disabled
2354 * @rmtoll CFGR2 PREDIV LL_RCC_PLL_GetPrediv
2355 * @retval Returned value can be one of the following values:
2356 * @arg @ref LL_RCC_PREDIV_DIV_1
2357 * @arg @ref LL_RCC_PREDIV_DIV_2
2358 * @arg @ref LL_RCC_PREDIV_DIV_3
2359 * @arg @ref LL_RCC_PREDIV_DIV_4
2360 * @arg @ref LL_RCC_PREDIV_DIV_5
2361 * @arg @ref LL_RCC_PREDIV_DIV_6
2362 * @arg @ref LL_RCC_PREDIV_DIV_7
2363 * @arg @ref LL_RCC_PREDIV_DIV_8
2364 * @arg @ref LL_RCC_PREDIV_DIV_9
2365 * @arg @ref LL_RCC_PREDIV_DIV_10
2366 * @arg @ref LL_RCC_PREDIV_DIV_11
2367 * @arg @ref LL_RCC_PREDIV_DIV_12
2368 * @arg @ref LL_RCC_PREDIV_DIV_13
2369 * @arg @ref LL_RCC_PREDIV_DIV_14
2370 * @arg @ref LL_RCC_PREDIV_DIV_15
2371 * @arg @ref LL_RCC_PREDIV_DIV_16
2372 */
2373 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
2374 {
2375 return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV));
2376 }
2377
2378 /**
2379 * @}
2380 */
2381
2382 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2383 * @{
2384 */
2385
2386 /**
2387 * @brief Clear LSI ready interrupt flag
2388 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2389 * @retval None
2390 */
2391 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2392 {
2393 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
2394 }
2395
2396 /**
2397 * @brief Clear LSE ready interrupt flag
2398 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
2399 * @retval None
2400 */
2401 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2402 {
2403 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
2404 }
2405
2406 /**
2407 * @brief Clear HSI ready interrupt flag
2408 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2409 * @retval None
2410 */
2411 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2412 {
2413 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
2414 }
2415
2416 /**
2417 * @brief Clear HSE ready interrupt flag
2418 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
2419 * @retval None
2420 */
2421 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2422 {
2423 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
2424 }
2425
2426 /**
2427 * @brief Clear PLL ready interrupt flag
2428 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2429 * @retval None
2430 */
2431 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2432 {
2433 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
2434 }
2435
2436 /**
2437 * @brief Clear Clock security system interrupt flag
2438 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
2439 * @retval None
2440 */
2441 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2442 {
2443 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
2444 }
2445
2446 /**
2447 * @brief Check if LSI ready interrupt occurred or not
2448 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2449 * @retval State of bit (1 or 0).
2450 */
2451 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2452 {
2453 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
2454 }
2455
2456 /**
2457 * @brief Check if LSE ready interrupt occurred or not
2458 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2459 * @retval State of bit (1 or 0).
2460 */
2461 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2462 {
2463 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
2464 }
2465
2466 /**
2467 * @brief Check if HSI ready interrupt occurred or not
2468 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2469 * @retval State of bit (1 or 0).
2470 */
2471 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2472 {
2473 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
2474 }
2475
2476 /**
2477 * @brief Check if HSE ready interrupt occurred or not
2478 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2479 * @retval State of bit (1 or 0).
2480 */
2481 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2482 {
2483 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
2484 }
2485
2486 #if defined(RCC_CFGR_MCOF)
2487 /**
2488 * @brief Check if switch to new MCO source is effective or not
2489 * @rmtoll CFGR MCOF LL_RCC_IsActiveFlag_MCO1
2490 * @retval State of bit (1 or 0).
2491 */
2492 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MCO1(void)
2493 {
2494 return (READ_BIT(RCC->CFGR, RCC_CFGR_MCOF) == (RCC_CFGR_MCOF));
2495 }
2496 #endif /* RCC_CFGR_MCOF */
2497
2498 /**
2499 * @brief Check if PLL ready interrupt occurred or not
2500 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2501 * @retval State of bit (1 or 0).
2502 */
2503 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2504 {
2505 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
2506 }
2507
2508 /**
2509 * @brief Check if Clock security system interrupt occurred or not
2510 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
2511 * @retval State of bit (1 or 0).
2512 */
2513 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2514 {
2515 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
2516 }
2517
2518 /**
2519 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2520 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2521 * @retval State of bit (1 or 0).
2522 */
2523 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2524 {
2525 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
2526 }
2527
2528 /**
2529 * @brief Check if RCC flag Low Power reset is set or not.
2530 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2531 * @retval State of bit (1 or 0).
2532 */
2533 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2534 {
2535 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
2536 }
2537
2538 /**
2539 * @brief Check if RCC flag is set or not.
2540 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2541 * @retval State of bit (1 or 0).
2542 */
2543 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2544 {
2545 return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
2546 }
2547
2548 /**
2549 * @brief Check if RCC flag Pin reset is set or not.
2550 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2551 * @retval State of bit (1 or 0).
2552 */
2553 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2554 {
2555 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
2556 }
2557
2558 /**
2559 * @brief Check if RCC flag POR/PDR reset is set or not.
2560 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
2561 * @retval State of bit (1 or 0).
2562 */
2563 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
2564 {
2565 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
2566 }
2567
2568 /**
2569 * @brief Check if RCC flag Software reset is set or not.
2570 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2571 * @retval State of bit (1 or 0).
2572 */
2573 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2574 {
2575 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
2576 }
2577
2578 /**
2579 * @brief Check if RCC flag Window Watchdog reset is set or not.
2580 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2581 * @retval State of bit (1 or 0).
2582 */
2583 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2584 {
2585 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
2586 }
2587
2588 #if defined(RCC_CSR_V18PWRRSTF)
2589 /**
2590 * @brief Check if RCC Reset flag of the 1.8 V domain is set or not.
2591 * @rmtoll CSR V18PWRRSTF LL_RCC_IsActiveFlag_V18PWRRST
2592 * @retval State of bit (1 or 0).
2593 */
2594 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_V18PWRRST(void)
2595 {
2596 return (READ_BIT(RCC->CSR, RCC_CSR_V18PWRRSTF) == (RCC_CSR_V18PWRRSTF));
2597 }
2598 #endif /* RCC_CSR_V18PWRRSTF */
2599
2600 /**
2601 * @brief Set RMVF bit to clear the reset flags.
2602 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2603 * @retval None
2604 */
2605 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2606 {
2607 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2608 }
2609
2610 /**
2611 * @}
2612 */
2613
2614 /** @defgroup RCC_LL_EF_IT_Management IT Management
2615 * @{
2616 */
2617
2618 /**
2619 * @brief Enable LSI ready interrupt
2620 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
2621 * @retval None
2622 */
2623 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2624 {
2625 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2626 }
2627
2628 /**
2629 * @brief Enable LSE ready interrupt
2630 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
2631 * @retval None
2632 */
2633 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2634 {
2635 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2636 }
2637
2638 /**
2639 * @brief Enable HSI ready interrupt
2640 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
2641 * @retval None
2642 */
2643 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2644 {
2645 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2646 }
2647
2648 /**
2649 * @brief Enable HSE ready interrupt
2650 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
2651 * @retval None
2652 */
2653 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2654 {
2655 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2656 }
2657
2658 /**
2659 * @brief Enable PLL ready interrupt
2660 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
2661 * @retval None
2662 */
2663 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2664 {
2665 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2666 }
2667
2668 /**
2669 * @brief Disable LSI ready interrupt
2670 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
2671 * @retval None
2672 */
2673 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2674 {
2675 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
2676 }
2677
2678 /**
2679 * @brief Disable LSE ready interrupt
2680 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
2681 * @retval None
2682 */
2683 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2684 {
2685 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
2686 }
2687
2688 /**
2689 * @brief Disable HSI ready interrupt
2690 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
2691 * @retval None
2692 */
2693 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2694 {
2695 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
2696 }
2697
2698 /**
2699 * @brief Disable HSE ready interrupt
2700 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
2701 * @retval None
2702 */
2703 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2704 {
2705 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
2706 }
2707
2708 /**
2709 * @brief Disable PLL ready interrupt
2710 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
2711 * @retval None
2712 */
2713 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2714 {
2715 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
2716 }
2717
2718 /**
2719 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2720 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2721 * @retval State of bit (1 or 0).
2722 */
2723 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2724 {
2725 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
2726 }
2727
2728 /**
2729 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2730 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2731 * @retval State of bit (1 or 0).
2732 */
2733 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2734 {
2735 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
2736 }
2737
2738 /**
2739 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2740 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2741 * @retval State of bit (1 or 0).
2742 */
2743 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2744 {
2745 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
2746 }
2747
2748 /**
2749 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2750 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2751 * @retval State of bit (1 or 0).
2752 */
2753 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2754 {
2755 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
2756 }
2757
2758 /**
2759 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2760 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2761 * @retval State of bit (1 or 0).
2762 */
2763 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2764 {
2765 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
2766 }
2767
2768 /**
2769 * @}
2770 */
2771
2772 #if defined(USE_FULL_LL_DRIVER)
2773 /** @defgroup RCC_LL_EF_Init De-initialization function
2774 * @{
2775 */
2776 ErrorStatus LL_RCC_DeInit(void);
2777 /**
2778 * @}
2779 */
2780
2781 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2782 * @{
2783 */
2784 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2785 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2786 #if defined(UART4) || defined(UART5)
2787 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2788 #endif /* UART4 || UART5 */
2789 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2790 #if defined(RCC_CFGR_I2SSRC)
2791 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2792 #endif /* RCC_CFGR_I2SSRC */
2793 #if defined(USB_OTG_FS) || defined(USB)
2794 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2795 #endif /* USB_OTG_FS || USB */
2796 #if (defined(RCC_CFGR_ADCPRE) || defined(RCC_CFGR2_ADC1PRES) || defined(RCC_CFGR2_ADCPRE12) || defined(RCC_CFGR2_ADCPRE34))
2797 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2798 #endif /*RCC_CFGR_ADCPRE || RCC_CFGR2_ADC1PRES || RCC_CFGR2_ADCPRE12 || RCC_CFGR2_ADCPRE34 */
2799 #if defined(RCC_CFGR_SDPRE)
2800 uint32_t LL_RCC_GetSDADCClockFreq(uint32_t SDADCxSource);
2801 #endif /*RCC_CFGR_SDPRE */
2802 #if defined(CEC)
2803 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
2804 #endif /* CEC */
2805 #if defined(RCC_CFGR3_TIMSW)
2806 uint32_t LL_RCC_GetTIMClockFreq(uint32_t TIMxSource);
2807 #endif /*RCC_CFGR3_TIMSW*/
2808 uint32_t LL_RCC_GetHRTIMClockFreq(uint32_t HRTIMxSource);
2809 /**
2810 * @}
2811 */
2812 #endif /* USE_FULL_LL_DRIVER */
2813
2814 /**
2815 * @}
2816 */
2817
2818 /**
2819 * @}
2820 */
2821
2822 #endif /* RCC */
2823
2824 /**
2825 * @}
2826 */
2827
2828 #ifdef __cplusplus
2829 }
2830 #endif
2831
2832 #endif /* __STM32F3xx_LL_RCC_H */
2833
2834 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/