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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_ll_system.h
blobeaad3d3d4cbd1fa4d6bfa412156b6d0669c35bb5
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL SYSTEM driver contains a set of generic APIs that can be
12 used by user:
13 (+) Some of the FLASH features need to be handled in the SYSTEM file.
14 (+) Access to DBGCMU registers
15 (+) Access to SYSCFG registers
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
22 *
23 * Redistribution and use in source and binary forms, with or without modification,
24 * are permitted provided that the following conditions are met:
25 * 1. Redistributions of source code must retain the above copyright notice,
26 * this list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright notice,
28 * this list of conditions and the following disclaimer in the documentation
29 * and/or other materials provided with the distribution.
30 * 3. Neither the name of STMicroelectronics nor the names of its contributors
31 * may be used to endorse or promote products derived from this software
32 * without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
35 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
36 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
38 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
39 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
41 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
42 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 ******************************************************************************
46 */
47
48 /* Define to prevent recursive inclusion -------------------------------------*/
49 #ifndef __STM32F3xx_LL_SYSTEM_H
50 #define __STM32F3xx_LL_SYSTEM_H
51
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55
56 /* Includes ------------------------------------------------------------------*/
57 #include "stm32f3xx.h"
58
59 /** @addtogroup STM32F3xx_LL_Driver
60 * @{
61 */
62
63 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
64
65 /** @defgroup SYSTEM_LL SYSTEM
66 * @{
67 */
68
69 /* Private types -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71
72 /* Private constants ---------------------------------------------------------*/
73 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
74 * @{
75 */
76
77 /* Offset used to access to SYSCFG_CFGR1 and SYSCFG_CFGR3 registers */
78 #define SYSCFG_OFFSET_CFGR1 0x00000000U
79 #define SYSCFG_OFFSET_CFGR3 0x00000050U
80
81 /* Mask used for TIM breaks functions */
82 #if defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
83 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK | SYSCFG_CFGR2_PVD_LOCK)
84 #elif defined(SYSCFG_CFGR2_PVD_LOCK) && !defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
85 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK)
86 #elif !defined(SYSCFG_CFGR2_PVD_LOCK) && defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
87 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_SRAM_PARITY_LOCK)
88 #else
89 #define SYSCFG_MASK_TIM_BREAK (SYSCFG_CFGR2_LOCKUP_LOCK)
90 #endif /* SYSCFG_CFGR2_PVD_LOCK && SYSCFG_CFGR2_SRAM_PARITY_LOCK */
91
92 /**
93 * @}
94 */
95
96 /* Private macros ------------------------------------------------------------*/
97
98 /* Exported types ------------------------------------------------------------*/
99 /* Exported constants --------------------------------------------------------*/
100 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
101 * @{
102 */
103
104 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
105 * @{
106 */
107 #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /* Main Flash memory mapped at 0x00000000 */
108 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /* System Flash memory mapped at 0x00000000 */
109 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /* Embedded SRAM mapped at 0x00000000 */
110 #if defined(FMC_BANK1)
111 #define LL_SYSCFG_REMAP_FMC SYSCFG_CFGR1_MEM_MODE_2 /*<! FMC Bank (Only the first two banks) */
112 #endif /* FMC_BANK1 */
113 /**
114 * @}
115 */
116
117 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
118 /** @defgroup SYSTEM_LL_EC_SPI1_DMA_RMP_RX SYSCFG SPI1 RX/TX DMA1 request REMAP
119 * @{
120 */
121 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH2 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_RX mapped on DMA1 CH2 */
122 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH4 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0) /*!< SPI1_RX mapped on DMA1 CH4 */
123 #define LL_SYSCFG_SPI1RX_RMP_DMA1_CH6 (SYSCFG_CFGR3_SPI1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1) /*!< SPI1_RX mapped on DMA1 CH6 */
124 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH3 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< SPI1_TX mapped on DMA1 CH3 */
125 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH5 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0) /*!< SPI1_TX mapped on DMA1 CH5 */
126 #define LL_SYSCFG_SPI1TX_RMP_DMA1_CH7 (SYSCFG_CFGR3_SPI1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1) /*!< SPI1_TX mapped on DMA1 CH7 */
127 /**
128 * @}
129 */
130 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
131
132 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
133 /** @defgroup SYSTEM_LL_EC_I2C1_DMA_RMP_RX SYSCFG I2C1 RX/TX DMA1 request REMAP
134 * @{
135 */
136 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH7 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_RX mapped on DMA1 CH7 */
137 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH3 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0) /*!< I2C1_RX mapped on DMA1 CH3 */
138 #define LL_SYSCFG_I2C1RX_RMP_DMA1_CH5 (SYSCFG_CFGR3_I2C1_RX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1) /*!< I2C1_RX mapped on DMA1 CH5 */
139 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH6 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | (uint32_t)0x00000000U) /*!< I2C1_TX mapped on DMA1 CH6 */
140 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH2 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0) /*!< I2C1_TX mapped on DMA1 CH2 */
141 #define LL_SYSCFG_I2C1TX_RMP_DMA1_CH4 (SYSCFG_CFGR3_I2C1_TX_DMA_RMP << 16U | SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1) /*!< I2C1_TX mapped on DMA1 CH4 */
142 /**
143 * @}
144 */
145
146 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
147
148 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
149 /** @defgroup SYSTEM_LL_EC_ADC24_DMA_REMAP SYSCFG ADC DMA request REMAP
150 * @{
151 */
152 #if defined (SYSCFG_CFGR1_ADC24_DMA_RMP)
153 #define LL_SYSCFG_ADC24_RMP_DMA2_CH12 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | (uint32_t)0x00000000U) /*!< ADC24 DMA requests mapped on DMA2 channels 1 and 2 */
154 #define LL_SYSCFG_ADC24_RMP_DMA2_CH34 (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_ADC24_DMA_RMP << 8U | SYSCFG_CFGR1_ADC24_DMA_RMP) /*!< ADC24 DMA requests mapped on DMA2 channels 3 and 4 */
155 #endif /*SYSCFG_CFGR1_ADC24_DMA_RMP*/
156 #if defined (SYSCFG_CFGR3_ADC2_DMA_RMP)
157 #define LL_SYSCFG_ADC2_RMP_DMA1_CH2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA1 channel 2 */
158 #define LL_SYSCFG_ADC2_RMP_DMA1_CH4 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_0 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_0) /*!< ADC2 mapped on DMA1 channel 4 */
159 #define LL_SYSCFG_ADC2_RMP_DMA2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | (uint32_t)0x00000000U) /*!< ADC2 mapped on DMA2 */
160 #define LL_SYSCFG_ADC2_RMP_DMA1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_ADC2_DMA_RMP_1 << 8U | SYSCFG_CFGR3_ADC2_DMA_RMP_1) /*!< ADC2 mapped on DMA1 */
161 #endif /*SYSCFG_CFGR3_ADC2_DMA_RMP*/
162 /**
163 * @}
164 */
165
166 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
167
168 /** @defgroup SYSTEM_LL_EC_DAC1_DMA2_REMAP SYSCFG DAC1/2 DMA1/2 request REMAP
169 * @{
170 */
171 #define LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC_CH1 DMA requests mapped on DMA2 channel 3 */
172 #define LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< DAC_CH1 DMA requests mapped on DMA1 channel 3 */
173 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
174 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC1_OUT2 DMA requests mapped on DMA2 channel 4 */
175 #define LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< DAC1_OUT2 DMA requests mapped on DMA1 channel 4 */
176 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
177 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
178 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< DAC2_OUT1 DMA requests mapped on DMA2 channel 5 */
179 #define LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< DAC2_OUT1 DMA requests mapped on DMA1 channel 5 */
180 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
181 #if defined(SYSCFG_CFGR1_DAC2Ch1_DMA_RMP)
182 #define LL_SYSCFG_DAC2_CH1_RMP_NO ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< No remap */
183 #define LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 ((SYSCFG_CFGR1_DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_DAC2Ch1_DMA_RMP) /*!< DAC2_CH1 DMA requests mapped on DMA1 channel 5 */
184 #endif /*SYSCFG_CFGR1_DAC2Ch1_DMA_RMP*/
185 /**
186 * @}
187 */
188
189 /** @defgroup SYSTEM_LL_EC_TIM16_DMA1_REMAP SYSCFG TIM DMA request REMAP
190 * @{
191 */
192 #define LL_SYSCFG_TIM16_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 3 */
193 #define LL_SYSCFG_TIM16_RMP_DMA1_CH6 ((SYSCFG_CFGR1_TIM16_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6 */
194 #define LL_SYSCFG_TIM17_RMP_DMA1_CH1 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 1 */
195 #define LL_SYSCFG_TIM17_RMP_DMA1_CH7 ((SYSCFG_CFGR1_TIM17_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7 */
196 #define LL_SYSCFG_TIM6_RMP_DMA2_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM6 DMA requests mapped on DMA2 channel 3 */
197 #define LL_SYSCFG_TIM6_RMP_DMA1_CH3 ((SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP) /*!< TIM6 DMA requests mapped on DMA1 channel 3 */
198 #if defined(SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP)
199 #define LL_SYSCFG_TIM7_RMP_DMA2_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM7 DMA requests mapped on DMA2 channel 4 */
200 #define LL_SYSCFG_TIM7_RMP_DMA1_CH4 ((SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP) /*!< TIM7 DMA requests mapped on DMA1 channel 4 */
201 #endif /*SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP*/
202 #if defined(SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP)
203 #define LL_SYSCFG_TIM18_RMP_DMA2_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM18 DMA requests mapped on DMA2 channel 5 */
204 #define LL_SYSCFG_TIM18_RMP_DMA1_CH5 ((SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP << 8U) | SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP) /*!< TIM18 DMA requests mapped on DMA1 channel 5 */
205 #endif /*SYSCFG_CFGR1_TIM18DAC2Ch1_DMA_RMP*/
206 /**
207 * @}
208 */
209
210 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
211 /** @defgroup SYSTEM_LL_EC_TIM1_ITR3_RMP_TIM4 SYSCFG TIM REMAP
212 * @{
213 */
214 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP)
215 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | (uint32_t)0x00000000U) /*!< TIM1_ITR3 = TIM4_TRGO */
216 #define LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC ((SYSCFG_CFGR1_TIM1_ITR3_RMP << 8U) | SYSCFG_CFGR1_TIM1_ITR3_RMP) /*!< TIM1_ITR3 = TIM17_OC */
217 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP */
218 #if defined(SYSCFG_CFGR1_ENCODER_MODE)
219 #define LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION ((SYSCFG_CFGR1_ENCODER_MODE << 8U) | (uint32_t)0x00000000U) /*!< No redirection */
220 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM2 ((SYSCFG_CFGR1_ENCODER_MODE_0 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_0) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
221 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM3)
222 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM3 ((SYSCFG_CFGR1_ENCODER_MODE_TIM3 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM3) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
223 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM3 */
224 #if defined(SYSCFG_CFGR1_ENCODER_MODE_TIM4)
225 #define LL_SYSCFG_TIM15_ENCODEMODE_TIM4 ((SYSCFG_CFGR1_ENCODER_MODE_TIM4 << 8U) | SYSCFG_CFGR1_ENCODER_MODE_TIM4) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
226 #endif /* SYSCFG_CFGR1_ENCODER_MODE_TIM4 */
227 #endif /* SYSCFG_CFGR1_ENCODER_MODE */
228 /**
229 * @}
230 */
231
232 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
233
234 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
235 /** @defgroup SYSTEM_LL_EC_ADC12_EXT2_RMP_TIM1 SYSCFG ADC Trigger REMAP
236 * @{
237 */
238 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM1_CC3 */
239 #define LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_EXT2_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT2_RMP) /*!< Input trigger of ADC12 regular channel EXT2:Trigger source is TIM20_TRGO */
240 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM2_CC2 */
241 #define LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_EXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT3_RMP) /*!< Input trigger of ADC12 regular channel EXT3:Trigger source is TIM20_TRGO2 */
242 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM4_CC4 */
243 #define LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC12_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT5_RMP) /*!< Input trigger of ADC12 regular channel EXT5:Trigger source is TIM20_CC1 */
244 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM6_TRGO */
245 #define LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC12_EXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT13_RMP) /*!< Input trigger of ADC12 regular channel EXT13:Trigger source is TIM20_CC2 */
246 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM3_CC4 */
247 #define LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3 ((SYSCFG_CFGR4_ADC12_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC12_EXT15_RMP) /*!< Input trigger of ADC12 regular channel EXT15:Trigger source is TIM20_CC3 */
248 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM2_CC1 */
249 #define LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC12_JEXT3_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT3_RMP) /*!< Input trigger of ADC12 regular channel JEXT3:Trigger source is TIM20_TRGO */
250 #define LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is EXTI_LINE_15 */
251 #define LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC12_JEXT6_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT6_RMP) /*!< Input trigger of ADC12 regular channel JEXT6:Trigger source is TIM20_TRGO2 */
252 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM3_CC1 */
253 #define LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4 ((SYSCFG_CFGR4_ADC12_JEXT13_RMP << 16U) | SYSCFG_CFGR4_ADC12_JEXT13_RMP) /*!< Input trigger of ADC12 regular channel JEXT13:Trigger source is TIM20_CC4 */
254 #define LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2 ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is EXTI_LINE_2 */
255 #define LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_EXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT5_RMP) /*!< Input trigger of ADC34 regular channel EXT5:Trigger source is TIM20_TRGO */
256 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM4_CC1 */
257 #define LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_EXT6_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT6_RMP) /*!< Input trigger of ADC34 regular channel EXT6:Trigger source is TIM20_TRGO2 */
258 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM2_CC1 */
259 #define LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1 ((SYSCFG_CFGR4_ADC34_EXT15_RMP << 16U) | SYSCFG_CFGR4_ADC34_EXT15_RMP) /*!< Input trigger of ADC34 regular channel EXT15:Trigger source is TIM20_CC1 */
260 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3 ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM4_CC3 */
261 #define LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO ((SYSCFG_CFGR4_ADC34_JEXT5_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT5_RMP) /*!< Input trigger of ADC34 regular channel JEXT5:Trigger source is TIM20_TRGO */
262 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM1_CC3 */
263 #define LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2 ((SYSCFG_CFGR4_ADC34_JEXT11_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT11_RMP) /*!< Input trigger of ADC34 regular channel JEXT11:Trigger source is TIM20_TRGO2 */
264 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | (uint32_t)0x00000000U) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM7_TRGO */
265 #define LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2 ((SYSCFG_CFGR4_ADC34_JEXT14_RMP << 16U) | SYSCFG_CFGR4_ADC34_JEXT14_RMP) /*!< Input trigger of ADC34 regular channel JEXT14:Trigger source is TIM20_CC2 */
266 /**
267 * @}
268 */
269
270 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
271
272 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
273 /** @defgroup SYSTEM_LL_EC_DAC1_TRIG1_REMAP SYSCFG DAC1 Trigger REMAP
274 * @{
275 */
276 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP)
277 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap: DAC trigger TRIG1 is TIM8_TRGO */
278 #define LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (SYSCFG_OFFSET_CFGR1 << 24U | SYSCFG_CFGR1_DAC1_TRIG1_RMP << 4 | SYSCFG_CFGR1_DAC1_TRIG1_RMP) /*!< DAC trigger is TIM3_TRGO */
279 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP */
280 #if defined(SYSCFG_CFGR3_DAC1_TRG3_RMP)
281 #define LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | (uint32_t)0x00000000U) /*!< DAC trigger is TIM15_TRGO */
282 #define LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG3_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG3_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG1 */
283 #endif /* SYSCFG_CFGR3_DAC1_TRG3_RMP */
284 #if defined(SYSCFG_CFGR3_DAC1_TRG5_RMP)
285 #define LL_SYSCFG_DAC1_TRIG5_RMP_NO (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | (uint32_t)0x00000000U) /*!< No remap */
286 #define LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (SYSCFG_OFFSET_CFGR3 << 24U | SYSCFG_CFGR3_DAC1_TRG5_RMP << 4 | SYSCFG_CFGR3_DAC1_TRG5_RMP) /*!< DAC trigger is HRTIM1_DAC1_TRIG2 */
287 #endif /* SYSCFG_CFGR3_DAC1_TRG5_RMP */
288 /**
289 * @}
290 */
291
292 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
293
294 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
295 * @{
296 */
297 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
298 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
299 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
300 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
301 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< I2C1 Fast mode plus */
302 #if defined(SYSCFG_CFGR1_I2C2_FMP)
303 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< I2C2 Fast mode plus */
304 #endif /*SYSCFG_CFGR1_I2C2_FMP*/
305 #if defined(SYSCFG_CFGR1_I2C3_FMP)
306 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< I2C3 Fast mode plus */
307 #endif /*SYSCFG_CFGR1_I2C3_FMP*/
308 /**
309 * @}
310 */
311
312 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
313 * @{
314 */
315 #define LL_SYSCFG_EXTI_PORTA (uint32_t)0U /*!< EXTI PORT A */
316 #define LL_SYSCFG_EXTI_PORTB (uint32_t)1U /*!< EXTI PORT B */
317 #define LL_SYSCFG_EXTI_PORTC (uint32_t)2U /*!< EXTI PORT C */
318 #define LL_SYSCFG_EXTI_PORTD (uint32_t)3U /*!< EXTI PORT D */
319 #if defined(GPIOE)
320 #define LL_SYSCFG_EXTI_PORTE (uint32_t)4U /*!< EXTI PORT E */
321 #endif /* GPIOE */
322 #define LL_SYSCFG_EXTI_PORTF (uint32_t)5U /*!< EXTI PORT F */
323 #if defined(GPIOG)
324 #define LL_SYSCFG_EXTI_PORTG (uint32_t)6U /*!< EXTI PORT G */
325 #endif /* GPIOG */
326 #if defined(GPIOH)
327 #define LL_SYSCFG_EXTI_PORTH (uint32_t)7U /*!< EXTI PORT H */
328 #endif /* GPIOH */
329 /**
330 * @}
331 */
332
333 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
334 * @{
335 */
336 #define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16U | 0U) /* EXTI_POSITION_0 | EXTICR[0] */
337 #define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16U | 0U) /* EXTI_POSITION_4 | EXTICR[0] */
338 #define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16U | 0U) /* EXTI_POSITION_8 | EXTICR[0] */
339 #define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16U | 0U) /* EXTI_POSITION_12 | EXTICR[0] */
340 #define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16U | 1U) /* EXTI_POSITION_0 | EXTICR[1] */
341 #define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16U | 1U) /* EXTI_POSITION_4 | EXTICR[1] */
342 #define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16U | 1U) /* EXTI_POSITION_8 | EXTICR[1] */
343 #define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16U | 1U) /* EXTI_POSITION_12 | EXTICR[1] */
344 #define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16U | 2U) /* EXTI_POSITION_0 | EXTICR[2] */
345 #define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16U | 2U) /* EXTI_POSITION_4 | EXTICR[2] */
346 #define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16U | 2U) /* EXTI_POSITION_8 | EXTICR[2] */
347 #define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16U | 2U) /* EXTI_POSITION_12 | EXTICR[2] */
348 #define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16U | 3U) /* EXTI_POSITION_0 | EXTICR[3] */
349 #define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16U | 3U) /* EXTI_POSITION_4 | EXTICR[3] */
350 #define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16U | 3U) /* EXTI_POSITION_8 | EXTICR[3] */
351 #define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16U | 3U) /* EXTI_POSITION_12 | EXTICR[3] */
352 /**
353 * @}
354 */
355
356 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
357 * @{
358 */
359 #if defined(SYSCFG_CFGR2_PVD_LOCK)
360 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Enables and locks the PVD connection with TIMx Break Input and also the PVDE and PLS bits of the Power Control Interface */
361 #endif /*SYSCFG_CFGR2_PVD_LOCK*/
362 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
363 #define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMx */
364 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
365 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMx */
366 /**
367 * @}
368 */
369
370 #if defined(SYSCFG_RCR_PAGE0)
371 /** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCM SRAM WRP
372 * @{
373 */
374 #define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_RCR_PAGE0 /*!< ICODE SRAM Write protection page 0 */
375 #define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_RCR_PAGE1 /*!< ICODE SRAM Write protection page 1 */
376 #define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_RCR_PAGE2 /*!< ICODE SRAM Write protection page 2 */
377 #define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_RCR_PAGE3 /*!< ICODE SRAM Write protection page 3 */
378 #if defined(SYSCFG_RCR_PAGE4)
379 #define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_RCR_PAGE4 /*!< ICODE SRAM Write protection page 4 */
380 #define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_RCR_PAGE5 /*!< ICODE SRAM Write protection page 5 */
381 #define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_RCR_PAGE6 /*!< ICODE SRAM Write protection page 6 */
382 #define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_RCR_PAGE7 /*!< ICODE SRAM Write protection page 7 */
383 #endif
384 #if defined(SYSCFG_RCR_PAGE8)
385 #define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_RCR_PAGE8 /*!< ICODE SRAM Write protection page 8 */
386 #define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_RCR_PAGE9 /*!< ICODE SRAM Write protection page 9 */
387 #define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_RCR_PAGE10 /*!< ICODE SRAM Write protection page 10 */
388 #define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_RCR_PAGE11 /*!< ICODE SRAM Write protection page 11 */
389 #define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_RCR_PAGE12 /*!< ICODE SRAM Write protection page 12 */
390 #define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_RCR_PAGE13 /*!< ICODE SRAM Write protection page 13 */
391 #define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_RCR_PAGE14 /*!< ICODE SRAM Write protection page 14 */
392 #define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_RCR_PAGE15 /*!< ICODE SRAM Write protection page 15 */
393 #endif
394 /**
395 * @}
396 */
397
398 #endif /* SYSCFG_RCR_PAGE0 */
399
400 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
401 * @{
402 */
403 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
404 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
405 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
406 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
407 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
408 /**
409 * @}
410 */
411
412 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
413 * @{
414 */
415 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
416 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
417 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
418 #endif /*DBGMCU_APB1_FZ_DBG_TIM3_STOP*/
419 #if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
420 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
421 #endif /*DBGMCU_APB1_FZ_DBG_TIM4_STOP*/
422 #if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
423 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
424 #endif /*DBGMCU_APB1_FZ_DBG_TIM5_STOP*/
425 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
426 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
427 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
428 #endif /*DBGMCU_APB1_FZ_DBG_TIM7_STOP*/
429 #if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
430 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
431 #endif /*DBGMCU_APB1_FZ_DBG_TIM12_STOP*/
432 #if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
433 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
434 #endif /*DBGMCU_APB1_FZ_DBG_TIM13_STOP*/
435 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
436 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
437 #endif /*DBGMCU_APB1_FZ_DBG_TIM14_STOP*/
438 #if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
439 #define LL_DBGMCU_APB1_GRP1_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP /*!< TIM18 counter stopped when core is halted */
440 #endif /*DBGMCU_APB1_FZ_DBG_TIM18_STOP*/
441 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
442 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
443 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
444 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
445 #if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
446 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
447 #endif /*DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT*/
448 #if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
449 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
450 #endif /*DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT*/
451 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
452 #define LL_DBGMCU_APB1_GRP1_CAN_STOP DBGMCU_APB1_FZ_DBG_CAN_STOP /*!< CAN debug stopped when Core is halted */
453 #endif /*DBGMCU_APB1_FZ_DBG_CAN_STOP*/
454 /**
455 * @}
456 */
457
458 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
459 * @{
460 */
461 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
462 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
463 #endif /*DBGMCU_APB2_FZ_DBG_TIM1_STOP*/
464 #if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
465 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
466 #endif /*DBGMCU_APB2_FZ_DBG_TIM8_STOP*/
467 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */
468 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
469 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
470 #if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
471 #define LL_DBGMCU_APB2_GRP1_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP /*!< TIM19 counter stopped when core is halted */
472 #endif /*DBGMCU_APB2_FZ_DBG_TIM19_STOP*/
473 #if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
474 #define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2_FZ_DBG_TIM20_STOP /*!< TIM20 counter stopped when core is halted */
475 #endif /*DBGMCU_APB2_FZ_DBG_TIM20_STOP*/
476 #if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
477 #define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2_FZ_DBG_HRTIM1_STOP /*!< HRTIM1 counter stopped when core is halted */
478 #endif /*DBGMCU_APB2_FZ_DBG_HRTIM1_STOP*/
479 /**
480 * @}
481 */
482
483 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
484 * @{
485 */
486 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
487 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
488 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
489 /**
490 * @}
491 */
492
493 /**
494 * @}
495 */
496
497 /* Exported macro ------------------------------------------------------------*/
498
499 /* Exported functions --------------------------------------------------------*/
500 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
501 * @{
502 */
503
504 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
505 * @{
506 */
507
508 /**
509 * @brief Set memory mapping at address 0x00000000
510 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
511 * @param Memory This parameter can be one of the following values:
512 * @arg @ref LL_SYSCFG_REMAP_FLASH
513 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
514 * @arg @ref LL_SYSCFG_REMAP_SRAM
515 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
516 *
517 * (*) value not defined in all devices.
518 * @retval None
519 */
520 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
521 {
522 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
523 }
524
525 /**
526 * @brief Get memory mapping at address 0x00000000
527 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
528 * @retval Returned value can be one of the following values:
529 * @arg @ref LL_SYSCFG_REMAP_FLASH
530 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
531 * @arg @ref LL_SYSCFG_REMAP_SRAM
532 * @arg @ref LL_SYSCFG_REMAP_FMC (*)
533 *
534 * (*) value not defined in all devices.
535 */
536 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
537 {
538 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
539 }
540
541 #if defined(SYSCFG_CFGR3_SPI1_RX_DMA_RMP)
542 /**
543 * @brief Set DMA request remapping bits for SPI
544 * @rmtoll SYSCFG_CFGR3 SPI1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI\n
545 * SYSCFG_CFGR3 SPI1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_SPI
546 * @param Remap This parameter can be one of the following values:
547 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH2
548 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH4
549 * @arg @ref LL_SYSCFG_SPI1RX_RMP_DMA1_CH6
550 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH3
551 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH5
552 * @arg @ref LL_SYSCFG_SPI1TX_RMP_DMA1_CH7
553 * @retval None
554 */
555 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_SPI(uint32_t Remap)
556 {
557 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
558 }
559 #endif /* SYSCFG_CFGR3_SPI1_RX_DMA_RMP */
560
561 #if defined(SYSCFG_CFGR3_I2C1_RX_DMA_RMP)
562 /**
563 * @brief Set DMA request remapping bits for I2C
564 * @rmtoll SYSCFG_CFGR3 I2C1_RX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C\n
565 * SYSCFG_CFGR3 I2C1_TX_DMA_RMP LL_SYSCFG_SetRemapDMA_I2C
566 * @param Remap This parameter can be one of the following values:
567 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH7
568 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH3
569 * @arg @ref LL_SYSCFG_I2C1RX_RMP_DMA1_CH5
570 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH6
571 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH2
572 * @arg @ref LL_SYSCFG_I2C1TX_RMP_DMA1_CH4
573 * @retval None
574 */
575 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_I2C(uint32_t Remap)
576 {
577 MODIFY_REG(SYSCFG->CFGR3, (Remap >> 16U), (Remap & 0x0000FFFF));
578 }
579 #endif /* SYSCFG_CFGR3_I2C1_RX_DMA_RMP */
580
581 #if defined(SYSCFG_CFGR1_ADC24_DMA_RMP) || defined(SYSCFG_CFGR3_ADC2_DMA_RMP)
582 /**
583 * @brief Set DMA request remapping bits for ADC
584 * @rmtoll SYSCFG_CFGR1 ADC24_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC\n
585 * SYSCFG_CFGR3 ADC2_DMA_RMP LL_SYSCFG_SetRemapDMA_ADC
586 * @param Remap This parameter can be one of the following values:
587 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH12 (*)
588 * @arg @ref LL_SYSCFG_ADC24_RMP_DMA2_CH34 (*)
589 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH2 (*)
590 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1_CH4 (*)
591 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA2 (*)
592 * @arg @ref LL_SYSCFG_ADC2_RMP_DMA1 (*)
593 *
594 * (*) value not defined in all devices.
595 * @retval None
596 */
597 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_ADC(uint32_t Remap)
598 {
599 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
600 MODIFY_REG(*reg, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FFFFU));
601 }
602 #endif /* SYSCFG_CFGR1_ADC24_DMA_RMP || SYSCFG_CFGR3_ADC2_DMA_RMP */
603
604 /**
605 * @brief Set DMA request remapping bits for DAC
606 * @rmtoll SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC\n
607 * SYSCFG_CFGR1 DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_DAC
608 * @param Remap This parameter can be one of the following values:
609 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA2_CH3
610 * @arg @ref LL_SYSCFG_DAC1_CH1_RMP_DMA1_CH3
611 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA2_CH4 (*)
612 * @arg @ref LL_SYSCFG_DAC1_OUT2_RMP_DMA1_CH4 (*)
613 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA2_CH5 (*)
614 * @arg @ref LL_SYSCFG_DAC2_OUT1_RMP_DMA1_CH5 (*)
615 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_NO (*)
616 * @arg @ref LL_SYSCFG_DAC2_CH1_RMP_DMA1_CH5 (*)
617 *
618 * (*) value not defined in all devices.
619 * @retval None
620 */
621 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_DAC(uint32_t Remap)
622 {
623 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
624 }
625
626 /**
627 * @brief Set DMA request remapping bits for TIM
628 * @rmtoll SYSCFG_CFGR1 TIM16_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
629 * SYSCFG_CFGR1 TIM17_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
630 * SYSCFG_CFGR1 TIM6DAC1Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
631 * SYSCFG_CFGR1 TIM7DAC1Ch2_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM\n
632 * SYSCFG_CFGR1 TIM18DAC2Ch1_DMA_RMP LL_SYSCFG_SetRemapDMA_TIM
633 * @param Remap This parameter can be a combination of the following values:
634 * @arg @ref LL_SYSCFG_TIM16_RMP_DMA1_CH3 or @ref LL_SYSCFG_TIM16_RMP_DMA1_CH6
635 * @arg @ref LL_SYSCFG_TIM17_RMP_DMA1_CH1 or @ref LL_SYSCFG_TIM17_RMP_DMA1_CH7
636 * @arg @ref LL_SYSCFG_TIM6_RMP_DMA2_CH3 or @ref LL_SYSCFG_TIM6_RMP_DMA1_CH3
637 * @arg @ref LL_SYSCFG_TIM7_RMP_DMA2_CH4 or @ref LL_SYSCFG_TIM7_RMP_DMA1_CH4 (*)
638 * @arg @ref LL_SYSCFG_TIM18_RMP_DMA2_CH5 or @ref LL_SYSCFG_TIM18_RMP_DMA1_CH5 (*)
639 *
640 * (*) value not defined in all devices.
641 * @retval None
642 */
643 __STATIC_INLINE void LL_SYSCFG_SetRemapDMA_TIM(uint32_t Remap)
644 {
645 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0x00FF0000U) >> 8U, (Remap & 0x0000FF00U));
646 }
647
648 #if defined(SYSCFG_CFGR1_TIM1_ITR3_RMP) || defined(SYSCFG_CFGR1_ENCODER_MODE)
649 /**
650 * @brief Set Timer input remap
651 * @rmtoll SYSCFG_CFGR1 TIM1_ITR3_RMP LL_SYSCFG_SetRemapInput_TIM\n
652 * SYSCFG_CFGR1 ENCODER_MODE LL_SYSCFG_SetRemapInput_TIM
653 * @param Remap This parameter can be one of the following values:
654 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM4_TRGO (*)
655 * @arg @ref LL_SYSCFG_TIM1_ITR3_RMP_TIM17_OC (*)
656 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_NOREDIRECTION (*)
657 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM2 (*)
658 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM3 (*)
659 * @arg @ref LL_SYSCFG_TIM15_ENCODEMODE_TIM4 (*)
660 *
661 * (*) value not defined in all devices.
662 * @retval None
663 */
664 __STATIC_INLINE void LL_SYSCFG_SetRemapInput_TIM(uint32_t Remap)
665 {
666 MODIFY_REG(SYSCFG->CFGR1, (Remap & 0xFF00FF00U) >> 8U, (Remap & 0x00FF00FFU));
667 }
668 #endif /* SYSCFG_CFGR1_TIM1_ITR3_RMP || SYSCFG_CFGR1_ENCODER_MODE */
669
670 #if defined(SYSCFG_CFGR4_ADC12_EXT2_RMP)
671 /**
672 * @brief Set ADC Trigger remap
673 * @rmtoll SYSCFG_CFGR4 ADC12_EXT2_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
674 * SYSCFG_CFGR4 ADC12_EXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
675 * SYSCFG_CFGR4 ADC12_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
676 * SYSCFG_CFGR4 ADC12_EXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
677 * SYSCFG_CFGR4 ADC12_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
678 * SYSCFG_CFGR4 ADC12_JEXT3_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
679 * SYSCFG_CFGR4 ADC12_JEXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
680 * SYSCFG_CFGR4 ADC12_JEXT13_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
681 * SYSCFG_CFGR4 ADC34_EXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
682 * SYSCFG_CFGR4 ADC34_EXT6_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
683 * SYSCFG_CFGR4 ADC34_EXT15_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
684 * SYSCFG_CFGR4 ADC34_JEXT5_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
685 * SYSCFG_CFGR4 ADC34_JEXT11_RMP LL_SYSCFG_SetRemapTrigger_ADC\n
686 * SYSCFG_CFGR4 ADC34_JEXT14_RMP LL_SYSCFG_SetRemapTrigger_ADC
687 * @param Remap This parameter can be one of the following values:
688 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM1_CC3
689 * @arg @ref LL_SYSCFG_ADC12_EXT2_RMP_TIM20_TRGO
690 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM2_CC2
691 * @arg @ref LL_SYSCFG_ADC12_EXT3_RMP_TIM20_TRGO2
692 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM4_CC4
693 * @arg @ref LL_SYSCFG_ADC12_EXT5_RMP_TIM20_CC1
694 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM6_TRGO
695 * @arg @ref LL_SYSCFG_ADC12_EXT13_RMP_TIM20_CC2
696 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM3_CC4
697 * @arg @ref LL_SYSCFG_ADC12_EXT15_RMP_TIM20_CC3
698 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM2_CC1
699 * @arg @ref LL_SYSCFG_ADC12_JEXT3_RMP_TIM20_TRGO
700 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_EXTI_LINE_15
701 * @arg @ref LL_SYSCFG_ADC12_JEXT6_RMP_TIM20_TRGO2
702 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM3_CC1
703 * @arg @ref LL_SYSCFG_ADC12_JEXT13_RMP_TIM20_CC4
704 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_EXTI_LINE_2
705 * @arg @ref LL_SYSCFG_ADC34_EXT5_RMP_TIM20_TRGO
706 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM4_CC1
707 * @arg @ref LL_SYSCFG_ADC34_EXT6_RMP_TIM20_TRGO2
708 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM2_CC1
709 * @arg @ref LL_SYSCFG_ADC34_EXT15_RMP_TIM20_CC1
710 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM4_CC3
711 * @arg @ref LL_SYSCFG_ADC34_JEXT5_RMP_TIM20_TRGO
712 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM1_CC3
713 * @arg @ref LL_SYSCFG_ADC34_JEXT11_RMP_TIM20_TRGO2
714 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM7_TRGO
715 * @arg @ref LL_SYSCFG_ADC34_JEXT14_RMP_TIM20_CC2
716 * @retval None
717 */
718 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_ADC(uint32_t Remap)
719 {
720 MODIFY_REG(SYSCFG->CFGR4, (Remap & 0xFFFF0000U) >> 16U, (Remap & 0x0000FFFFU));
721 }
722 #endif /* SYSCFG_CFGR4_ADC12_EXT2_RMP */
723
724 #if defined(SYSCFG_CFGR1_DAC1_TRIG1_RMP) || defined(SYSCFG_CFGR3_TRIGGER_RMP)
725 /**
726 * @brief Set DAC Trigger remap
727 * @rmtoll SYSCFG_CFGR1 DAC1_TRIG1_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
728 * SYSCFG_CFGR3 DAC1_TRG3_RMP LL_SYSCFG_SetRemapTrigger_DAC\n
729 * SYSCFG_CFGR3 DAC1_TRG5_RMP LL_SYSCFG_SetRemapTrigger_DAC
730 * @param Remap This parameter can be one of the following values:
731 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM8_TRGO (*)
732 * @arg @ref LL_SYSCFG_DAC1_TRIG1_RMP_TIM3_TRGO (*)
733 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_TIM15_TRGO (*)
734 * @arg @ref LL_SYSCFG_DAC1_TRIG3_RMP_HRTIM1_DAC1_TRIG1 (*)
735 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_NO (*)
736 * @arg @ref LL_SYSCFG_DAC1_TRIG5_RMP_HRTIM1_DAC1_TRIG2 (*)
737 * (*) value not defined in all devices.
738 * @retval None
739 */
740 __STATIC_INLINE void LL_SYSCFG_SetRemapTrigger_DAC(uint32_t Remap)
741 {
742 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(SYSCFG_BASE + (Remap >> 24U));
743 MODIFY_REG(*reg, (Remap & 0x00F00F00U) >> 4U, (Remap & 0x000F00F0U));
744 }
745 #endif /* SYSCFG_CFGR1_DAC1_TRIG1_RMP || SYSCFG_CFGR3_TRIGGER_RMP */
746
747 #if defined(SYSCFG_CFGR1_USB_IT_RMP)
748 /**
749 * @brief Enable USB interrupt remap
750 * @note Remap the USB interrupts (USB_HP, USB_LP and USB_WKUP) on interrupt lines 74, 75 and 76
751 * respectively
752 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_EnableRemapIT_USB
753 * @retval None
754 */
755 __STATIC_INLINE void LL_SYSCFG_EnableRemapIT_USB(void)
756 {
757 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
758 }
759
760 /**
761 * @brief Disable USB interrupt remap
762 * @rmtoll SYSCFG_CFGR1 USB_IT_RMP LL_SYSCFG_DisableRemapIT_USB
763 * @retval None
764 */
765 __STATIC_INLINE void LL_SYSCFG_DisableRemapIT_USB(void)
766 {
767 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_USB_IT_RMP);
768 }
769 #endif /* SYSCFG_CFGR1_USB_IT_RMP */
770
771 #if defined(SYSCFG_CFGR1_VBAT)
772 /**
773 * @brief Enable VBAT monitoring (to enable the power switch to deliver VBAT voltage on ADC channel 18 input)
774 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_EnableVBATMonitoring
775 * @retval None
776 */
777 __STATIC_INLINE void LL_SYSCFG_EnableVBATMonitoring(void)
778 {
779 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
780 }
781
782 /**
783 * @brief Disable VBAT monitoring
784 * @rmtoll SYSCFG_CFGR1 VBAT LL_SYSCFG_DisableVBATMonitoring
785 * @retval None
786 */
787 __STATIC_INLINE void LL_SYSCFG_DisableVBATMonitoring(void)
788 {
789 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_VBAT);
790 }
791 #endif /* SYSCFG_CFGR1_VBAT */
792
793 /**
794 * @brief Enable the I2C fast mode plus driving capability.
795 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_EnableFastModePlus\n
796 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_EnableFastModePlus\n
797 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_EnableFastModePlus\n
798 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_EnableFastModePlus\n
799 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_EnableFastModePlus\n
800 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_EnableFastModePlus\n
801 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_EnableFastModePlus
802 * @param ConfigFastModePlus This parameter can be a combination of the following values:
803 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
804 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
805 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
806 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
807 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
808 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
809 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
810 *
811 * (*) value not defined in all devices.
812 * @retval None
813 */
814 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
815 {
816 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
817 }
818
819 /**
820 * @brief Disable the I2C fast mode plus driving capability.
821 * @rmtoll SYSCFG_CFGR1 I2C_PB6_FMP LL_SYSCFG_DisableFastModePlus\n
822 * SYSCFG_CFGR1 I2C_PB7_FMP LL_SYSCFG_DisableFastModePlus\n
823 * SYSCFG_CFGR1 I2C_PB8_FMP LL_SYSCFG_DisableFastModePlus\n
824 * SYSCFG_CFGR1 I2C_PB9_FMP LL_SYSCFG_DisableFastModePlus\n
825 * SYSCFG_CFGR1 I2C1_FMP LL_SYSCFG_DisableFastModePlus\n
826 * SYSCFG_CFGR1 I2C2_FMP LL_SYSCFG_DisableFastModePlus\n
827 * SYSCFG_CFGR1 I2C3_FMP LL_SYSCFG_DisableFastModePlus
828 * @param ConfigFastModePlus This parameter can be a combination of the following values:
829 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
830 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
831 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
832 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
833 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
834 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
835 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 (*)
836 *
837 * (*) value not defined in all devices.
838 * @retval None
839 */
840 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
841 {
842 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
843 }
844
845 /**
846 * @brief Enable Floating Point Unit Invalid operation Interrupt
847 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
848 * @retval None
849 */
850 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
851 {
852 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
853 }
854
855 /**
856 * @brief Enable Floating Point Unit Divide-by-zero Interrupt
857 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
858 * @retval None
859 */
860 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
861 {
862 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
863 }
864
865 /**
866 * @brief Enable Floating Point Unit Underflow Interrupt
867 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
868 * @retval None
869 */
870 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
871 {
872 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
873 }
874
875 /**
876 * @brief Enable Floating Point Unit Overflow Interrupt
877 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
878 * @retval None
879 */
880 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
881 {
882 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
883 }
884
885 /**
886 * @brief Enable Floating Point Unit Input denormal Interrupt
887 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
888 * @retval None
889 */
890 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
891 {
892 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
893 }
894
895 /**
896 * @brief Enable Floating Point Unit Inexact Interrupt
897 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
898 * @retval None
899 */
900 __STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
901 {
902 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
903 }
904
905 /**
906 * @brief Disable Floating Point Unit Invalid operation Interrupt
907 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
908 * @retval None
909 */
910 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
911 {
912 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
913 }
914
915 /**
916 * @brief Disable Floating Point Unit Divide-by-zero Interrupt
917 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
918 * @retval None
919 */
920 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
921 {
922 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
923 }
924
925 /**
926 * @brief Disable Floating Point Unit Underflow Interrupt
927 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
928 * @retval None
929 */
930 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
931 {
932 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
933 }
934
935 /**
936 * @brief Disable Floating Point Unit Overflow Interrupt
937 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
938 * @retval None
939 */
940 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
941 {
942 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
943 }
944
945 /**
946 * @brief Disable Floating Point Unit Input denormal Interrupt
947 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
948 * @retval None
949 */
950 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
951 {
952 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
953 }
954
955 /**
956 * @brief Disable Floating Point Unit Inexact Interrupt
957 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
958 * @retval None
959 */
960 __STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
961 {
962 CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
963 }
964
965 /**
966 * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
967 * @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
968 * @retval State of bit (1 or 0).
969 */
970 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
971 {
972 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0));
973 }
974
975 /**
976 * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
977 * @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
978 * @retval State of bit (1 or 0).
979 */
980 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
981 {
982 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1));
983 }
984
985 /**
986 * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
987 * @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
988 * @retval State of bit (1 or 0).
989 */
990 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
991 {
992 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2));
993 }
994
995 /**
996 * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
997 * @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
998 * @retval State of bit (1 or 0).
999 */
1000 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
1001 {
1002 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3));
1003 }
1004
1005 /**
1006 * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
1007 * @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
1008 * @retval State of bit (1 or 0).
1009 */
1010 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
1011 {
1012 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4));
1013 }
1014
1015 /**
1016 * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
1017 * @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
1018 * @retval State of bit (1 or 0).
1019 */
1020 __STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
1021 {
1022 return (READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5));
1023 }
1024
1025 /**
1026 * @brief Configure source input for the EXTI external interrupt.
1027 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_SetEXTISource\n
1028 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_SetEXTISource\n
1029 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_SetEXTISource\n
1030 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_SetEXTISource\n
1031 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_SetEXTISource\n
1032 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_SetEXTISource\n
1033 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_SetEXTISource\n
1034 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_SetEXTISource\n
1035 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_SetEXTISource\n
1036 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_SetEXTISource\n
1037 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_SetEXTISource\n
1038 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_SetEXTISource\n
1039 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_SetEXTISource\n
1040 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_SetEXTISource\n
1041 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_SetEXTISource\n
1042 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_SetEXTISource\n
1043 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_SetEXTISource\n
1044 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_SetEXTISource\n
1045 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_SetEXTISource\n
1046 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_SetEXTISource\n
1047 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_SetEXTISource\n
1048 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_SetEXTISource\n
1049 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_SetEXTISource\n
1050 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_SetEXTISource\n
1051 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_SetEXTISource\n
1052 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_SetEXTISource\n
1053 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_SetEXTISource\n
1054 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_SetEXTISource\n
1055 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_SetEXTISource\n
1056 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_SetEXTISource\n
1057 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_SetEXTISource\n
1058 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_SetEXTISource\n
1059 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_SetEXTISource\n
1060 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_SetEXTISource\n
1061 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_SetEXTISource\n
1062 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_SetEXTISource\n
1063 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_SetEXTISource\n
1064 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_SetEXTISource\n
1065 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_SetEXTISource\n
1066 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_SetEXTISource\n
1067 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_SetEXTISource\n
1068 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_SetEXTISource\n
1069 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_SetEXTISource\n
1070 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_SetEXTISource\n
1071 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_SetEXTISource\n
1072 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_SetEXTISource\n
1073 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_SetEXTISource\n
1074 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_SetEXTISource\n
1075 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_SetEXTISource\n
1076 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_SetEXTISource\n
1077 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_SetEXTISource\n
1078 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_SetEXTISource\n
1079 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_SetEXTISource\n
1080 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_SetEXTISource\n
1081 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_SetEXTISource\n
1082 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_SetEXTISource\n
1083 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_SetEXTISource\n
1084 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_SetEXTISource\n
1085 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_SetEXTISource\n
1086 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_SetEXTISource\n
1087 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_SetEXTISource\n
1088 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_SetEXTISource\n
1089 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_SetEXTISource\n
1090 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_SetEXTISource
1091 * @param Port This parameter can be one of the following values:
1092 * @arg @ref LL_SYSCFG_EXTI_PORTA
1093 * @arg @ref LL_SYSCFG_EXTI_PORTB
1094 * @arg @ref LL_SYSCFG_EXTI_PORTC
1095 * @arg @ref LL_SYSCFG_EXTI_PORTD
1096 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1097 * @arg @ref LL_SYSCFG_EXTI_PORTF
1098 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1099 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1100 *
1101 * (*) value not defined in all devices.
1102 * @param Line This parameter can be one of the following values:
1103 * @arg @ref LL_SYSCFG_EXTI_LINE0
1104 * @arg @ref LL_SYSCFG_EXTI_LINE1
1105 * @arg @ref LL_SYSCFG_EXTI_LINE2
1106 * @arg @ref LL_SYSCFG_EXTI_LINE3
1107 * @arg @ref LL_SYSCFG_EXTI_LINE4
1108 * @arg @ref LL_SYSCFG_EXTI_LINE5
1109 * @arg @ref LL_SYSCFG_EXTI_LINE6
1110 * @arg @ref LL_SYSCFG_EXTI_LINE7
1111 * @arg @ref LL_SYSCFG_EXTI_LINE8
1112 * @arg @ref LL_SYSCFG_EXTI_LINE9
1113 * @arg @ref LL_SYSCFG_EXTI_LINE10
1114 * @arg @ref LL_SYSCFG_EXTI_LINE11
1115 * @arg @ref LL_SYSCFG_EXTI_LINE12
1116 * @arg @ref LL_SYSCFG_EXTI_LINE13
1117 * @arg @ref LL_SYSCFG_EXTI_LINE14
1118 * @arg @ref LL_SYSCFG_EXTI_LINE15
1119 * @retval None
1120 */
1121 __STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
1122 {
1123 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U), Port << POSITION_VAL((Line >> 16U)));
1124 }
1125
1126 /**
1127 * @brief Get the configured defined for specific EXTI Line
1128 * @rmtoll SYSCFG_EXTICR1 EXTI0 LL_SYSCFG_GetEXTISource\n
1129 * SYSCFG_EXTICR1 EXTI1 LL_SYSCFG_GetEXTISource\n
1130 * SYSCFG_EXTICR1 EXTI2 LL_SYSCFG_GetEXTISource\n
1131 * SYSCFG_EXTICR1 EXTI3 LL_SYSCFG_GetEXTISource\n
1132 * SYSCFG_EXTICR1 EXTI4 LL_SYSCFG_GetEXTISource\n
1133 * SYSCFG_EXTICR1 EXTI5 LL_SYSCFG_GetEXTISource\n
1134 * SYSCFG_EXTICR1 EXTI6 LL_SYSCFG_GetEXTISource\n
1135 * SYSCFG_EXTICR1 EXTI7 LL_SYSCFG_GetEXTISource\n
1136 * SYSCFG_EXTICR1 EXTI8 LL_SYSCFG_GetEXTISource\n
1137 * SYSCFG_EXTICR1 EXTI9 LL_SYSCFG_GetEXTISource\n
1138 * SYSCFG_EXTICR1 EXTI10 LL_SYSCFG_GetEXTISource\n
1139 * SYSCFG_EXTICR1 EXTI11 LL_SYSCFG_GetEXTISource\n
1140 * SYSCFG_EXTICR1 EXTI12 LL_SYSCFG_GetEXTISource\n
1141 * SYSCFG_EXTICR1 EXTI13 LL_SYSCFG_GetEXTISource\n
1142 * SYSCFG_EXTICR1 EXTI14 LL_SYSCFG_GetEXTISource\n
1143 * SYSCFG_EXTICR1 EXTI15 LL_SYSCFG_GetEXTISource\n
1144 * SYSCFG_EXTICR2 EXTI0 LL_SYSCFG_GetEXTISource\n
1145 * SYSCFG_EXTICR2 EXTI1 LL_SYSCFG_GetEXTISource\n
1146 * SYSCFG_EXTICR2 EXTI2 LL_SYSCFG_GetEXTISource\n
1147 * SYSCFG_EXTICR2 EXTI3 LL_SYSCFG_GetEXTISource\n
1148 * SYSCFG_EXTICR2 EXTI4 LL_SYSCFG_GetEXTISource\n
1149 * SYSCFG_EXTICR2 EXTI5 LL_SYSCFG_GetEXTISource\n
1150 * SYSCFG_EXTICR2 EXTI6 LL_SYSCFG_GetEXTISource\n
1151 * SYSCFG_EXTICR2 EXTI7 LL_SYSCFG_GetEXTISource\n
1152 * SYSCFG_EXTICR2 EXTI8 LL_SYSCFG_GetEXTISource\n
1153 * SYSCFG_EXTICR2 EXTI9 LL_SYSCFG_GetEXTISource\n
1154 * SYSCFG_EXTICR2 EXTI10 LL_SYSCFG_GetEXTISource\n
1155 * SYSCFG_EXTICR2 EXTI11 LL_SYSCFG_GetEXTISource\n
1156 * SYSCFG_EXTICR2 EXTI12 LL_SYSCFG_GetEXTISource\n
1157 * SYSCFG_EXTICR2 EXTI13 LL_SYSCFG_GetEXTISource\n
1158 * SYSCFG_EXTICR2 EXTI14 LL_SYSCFG_GetEXTISource\n
1159 * SYSCFG_EXTICR2 EXTI15 LL_SYSCFG_GetEXTISource\n
1160 * SYSCFG_EXTICR3 EXTI0 LL_SYSCFG_GetEXTISource\n
1161 * SYSCFG_EXTICR3 EXTI1 LL_SYSCFG_GetEXTISource\n
1162 * SYSCFG_EXTICR3 EXTI2 LL_SYSCFG_GetEXTISource\n
1163 * SYSCFG_EXTICR3 EXTI3 LL_SYSCFG_GetEXTISource\n
1164 * SYSCFG_EXTICR3 EXTI4 LL_SYSCFG_GetEXTISource\n
1165 * SYSCFG_EXTICR3 EXTI5 LL_SYSCFG_GetEXTISource\n
1166 * SYSCFG_EXTICR3 EXTI6 LL_SYSCFG_GetEXTISource\n
1167 * SYSCFG_EXTICR3 EXTI7 LL_SYSCFG_GetEXTISource\n
1168 * SYSCFG_EXTICR3 EXTI8 LL_SYSCFG_GetEXTISource\n
1169 * SYSCFG_EXTICR3 EXTI9 LL_SYSCFG_GetEXTISource\n
1170 * SYSCFG_EXTICR3 EXTI10 LL_SYSCFG_GetEXTISource\n
1171 * SYSCFG_EXTICR3 EXTI11 LL_SYSCFG_GetEXTISource\n
1172 * SYSCFG_EXTICR3 EXTI12 LL_SYSCFG_GetEXTISource\n
1173 * SYSCFG_EXTICR3 EXTI13 LL_SYSCFG_GetEXTISource\n
1174 * SYSCFG_EXTICR3 EXTI14 LL_SYSCFG_GetEXTISource\n
1175 * SYSCFG_EXTICR3 EXTI15 LL_SYSCFG_GetEXTISource\n
1176 * SYSCFG_EXTICR4 EXTI0 LL_SYSCFG_GetEXTISource\n
1177 * SYSCFG_EXTICR4 EXTI1 LL_SYSCFG_GetEXTISource\n
1178 * SYSCFG_EXTICR4 EXTI2 LL_SYSCFG_GetEXTISource\n
1179 * SYSCFG_EXTICR4 EXTI3 LL_SYSCFG_GetEXTISource\n
1180 * SYSCFG_EXTICR4 EXTI4 LL_SYSCFG_GetEXTISource\n
1181 * SYSCFG_EXTICR4 EXTI5 LL_SYSCFG_GetEXTISource\n
1182 * SYSCFG_EXTICR4 EXTI6 LL_SYSCFG_GetEXTISource\n
1183 * SYSCFG_EXTICR4 EXTI7 LL_SYSCFG_GetEXTISource\n
1184 * SYSCFG_EXTICR4 EXTI8 LL_SYSCFG_GetEXTISource\n
1185 * SYSCFG_EXTICR4 EXTI9 LL_SYSCFG_GetEXTISource\n
1186 * SYSCFG_EXTICR4 EXTI10 LL_SYSCFG_GetEXTISource\n
1187 * SYSCFG_EXTICR4 EXTI11 LL_SYSCFG_GetEXTISource\n
1188 * SYSCFG_EXTICR4 EXTI12 LL_SYSCFG_GetEXTISource\n
1189 * SYSCFG_EXTICR4 EXTI13 LL_SYSCFG_GetEXTISource\n
1190 * SYSCFG_EXTICR4 EXTI14 LL_SYSCFG_GetEXTISource\n
1191 * SYSCFG_EXTICR4 EXTI15 LL_SYSCFG_GetEXTISource
1192 * @param Line This parameter can be one of the following values:
1193 * @arg @ref LL_SYSCFG_EXTI_LINE0
1194 * @arg @ref LL_SYSCFG_EXTI_LINE1
1195 * @arg @ref LL_SYSCFG_EXTI_LINE2
1196 * @arg @ref LL_SYSCFG_EXTI_LINE3
1197 * @arg @ref LL_SYSCFG_EXTI_LINE4
1198 * @arg @ref LL_SYSCFG_EXTI_LINE5
1199 * @arg @ref LL_SYSCFG_EXTI_LINE6
1200 * @arg @ref LL_SYSCFG_EXTI_LINE7
1201 * @arg @ref LL_SYSCFG_EXTI_LINE8
1202 * @arg @ref LL_SYSCFG_EXTI_LINE9
1203 * @arg @ref LL_SYSCFG_EXTI_LINE10
1204 * @arg @ref LL_SYSCFG_EXTI_LINE11
1205 * @arg @ref LL_SYSCFG_EXTI_LINE12
1206 * @arg @ref LL_SYSCFG_EXTI_LINE13
1207 * @arg @ref LL_SYSCFG_EXTI_LINE14
1208 * @arg @ref LL_SYSCFG_EXTI_LINE15
1209 * @retval Returned value can be one of the following values:
1210 * @arg @ref LL_SYSCFG_EXTI_PORTA
1211 * @arg @ref LL_SYSCFG_EXTI_PORTB
1212 * @arg @ref LL_SYSCFG_EXTI_PORTC
1213 * @arg @ref LL_SYSCFG_EXTI_PORTD
1214 * @arg @ref LL_SYSCFG_EXTI_PORTE (*)
1215 * @arg @ref LL_SYSCFG_EXTI_PORTF
1216 * @arg @ref LL_SYSCFG_EXTI_PORTG (*)
1217 * @arg @ref LL_SYSCFG_EXTI_PORTH (*)
1218 *
1219 * (*) value not defined in all devices.
1220 */
1221 __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
1222 {
1223 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16U)) >> POSITION_VAL(Line >> 16U));
1224 }
1225
1226 /**
1227 * @brief Set connections to TIMx Break inputs
1228 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1229 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_SetTIMBreakInputs\n
1230 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_SetTIMBreakInputs
1231 * @param Break This parameter can be a combination of the following values:
1232 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1233 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1234 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1235 *
1236 * (*) value not defined in all devices.
1237 * @retval None
1238 */
1239 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
1240 {
1241 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK, Break);
1242 }
1243
1244 /**
1245 * @brief Get connections to TIMx Break inputs
1246 * @rmtoll SYSCFG_CFGR2 LOCKUP_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1247 * SYSCFG_CFGR2 SRAM_PARITY_LOCK LL_SYSCFG_GetTIMBreakInputs\n
1248 * SYSCFG_CFGR2 PVD_LOCK LL_SYSCFG_GetTIMBreakInputs
1249 * @retval Returned value can be can be a combination of the following values:
1250 * @arg @ref LL_SYSCFG_TIMBREAK_PVD (*)
1251 * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY (*)
1252 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
1253 *
1254 * (*) value not defined in all devices.
1255 */
1256 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
1257 {
1258 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_MASK_TIM_BREAK));
1259 }
1260
1261 #if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
1262 /**
1263 * @brief Disable RAM Parity Check Disable
1264 * @rmtoll SYSCFG_CFGR2 BYP_ADDR_PAR LL_SYSCFG_DisableSRAMParityCheck
1265 * @retval None
1266 */
1267 __STATIC_INLINE void LL_SYSCFG_DisableSRAMParityCheck(void)
1268 {
1269 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_BYP_ADDR_PAR);
1270 }
1271 #endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
1272
1273 #if defined(SYSCFG_CFGR2_SRAM_PE)
1274 /**
1275 * @brief Check if SRAM parity error detected
1276 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_IsActiveFlag_SP
1277 * @retval State of bit (1 or 0).
1278 */
1279 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
1280 {
1281 return (READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE) == (SYSCFG_CFGR2_SRAM_PE));
1282 }
1283
1284 /**
1285 * @brief Clear SRAM parity error flag
1286 * @rmtoll SYSCFG_CFGR2 SRAM_PE LL_SYSCFG_ClearFlag_SP
1287 * @retval None
1288 */
1289 __STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
1290 {
1291 SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SRAM_PE);
1292 }
1293 #endif /* SYSCFG_CFGR2_SRAM_PE */
1294
1295 #if defined(SYSCFG_RCR_PAGE0)
1296 /**
1297 * @brief Enable CCM SRAM page write protection
1298 * @note Write protection is cleared only by a system reset
1299 * @rmtoll SYSCFG_RCR PAGE0 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1300 * SYSCFG_RCR PAGE1 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1301 * SYSCFG_RCR PAGE2 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1302 * SYSCFG_RCR PAGE3 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1303 * SYSCFG_RCR PAGE4 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1304 * SYSCFG_RCR PAGE5 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1305 * SYSCFG_RCR PAGE6 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1306 * SYSCFG_RCR PAGE7 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1307 * SYSCFG_RCR PAGE8 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1308 * SYSCFG_RCR PAGE9 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1309 * SYSCFG_RCR PAGE10 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1310 * SYSCFG_RCR PAGE11 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1311 * SYSCFG_RCR PAGE12 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1312 * SYSCFG_RCR PAGE13 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1313 * SYSCFG_RCR PAGE14 LL_SYSCFG_EnableCCM_SRAMPageWRP\n
1314 * SYSCFG_RCR PAGE15 LL_SYSCFG_EnableCCM_SRAMPageWRP
1315 * @param PageWRP This parameter can be a combination of the following values:
1316 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
1317 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
1318 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
1319 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
1320 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4 (*)
1321 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5 (*)
1322 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6 (*)
1323 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7 (*)
1324 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8 (*)
1325 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9 (*)
1326 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
1327 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
1328 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
1329 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
1330 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
1331 * @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
1332 *
1333 * (*) value not defined in all devices.
1334 * @retval None
1335 */
1336 __STATIC_INLINE void LL_SYSCFG_EnableCCM_SRAMPageWRP(uint32_t PageWRP)
1337 {
1338 SET_BIT(SYSCFG->RCR, PageWRP);
1339 }
1340 #endif /* SYSCFG_RCR_PAGE0 */
1341
1342 /**
1343 * @}
1344 */
1345
1346 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
1347 * @{
1348 */
1349
1350 /**
1351 * @brief Return the device identifier
1352 * @note For STM32F303xC, STM32F358xx and STM32F302xC devices, the device ID is 0x422
1353 * @note For STM32F373xx and STM32F378xx devices, the device ID is 0x432
1354 * @note For STM32F303x8, STM32F334xx and STM32F328xx devices, the device ID is 0x438.
1355 * @note For STM32F302x8, STM32F301x8 and STM32F318xx devices, the device ID is 0x439
1356 * @note For STM32F303xE, STM32F398xx and STM32F302xE devices, the device ID is 0x446
1357 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
1358 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
1359 */
1360 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1361 {
1362 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1363 }
1364
1365 /**
1366 * @brief Return the device revision identifier
1367 * @note This field indicates the revision of the device.
1368 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
1369 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
1370 */
1371 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1372 {
1373 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1374 }
1375
1376 /**
1377 * @brief Enable the Debug Module during SLEEP mode
1378 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
1379 * @retval None
1380 */
1381 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1382 {
1383 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1384 }
1385
1386 /**
1387 * @brief Disable the Debug Module during SLEEP mode
1388 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
1389 * @retval None
1390 */
1391 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1392 {
1393 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1394 }
1395
1396 /**
1397 * @brief Enable the Debug Module during STOP mode
1398 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
1399 * @retval None
1400 */
1401 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1402 {
1403 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1404 }
1405
1406 /**
1407 * @brief Disable the Debug Module during STOP mode
1408 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
1409 * @retval None
1410 */
1411 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1412 {
1413 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1414 }
1415
1416 /**
1417 * @brief Enable the Debug Module during STANDBY mode
1418 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
1419 * @retval None
1420 */
1421 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1422 {
1423 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1424 }
1425
1426 /**
1427 * @brief Disable the Debug Module during STANDBY mode
1428 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
1429 * @retval None
1430 */
1431 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1432 {
1433 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1434 }
1435
1436 /**
1437 * @brief Set Trace pin assignment control
1438 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
1439 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
1440 * @param PinAssignment This parameter can be one of the following values:
1441 * @arg @ref LL_DBGMCU_TRACE_NONE
1442 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1443 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1444 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1445 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1446 * @retval None
1447 */
1448 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1449 {
1450 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1451 }
1452
1453 /**
1454 * @brief Get Trace pin assignment control
1455 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
1456 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
1457 * @retval Returned value can be one of the following values:
1458 * @arg @ref LL_DBGMCU_TRACE_NONE
1459 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
1460 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
1461 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
1462 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
1463 */
1464 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1465 {
1466 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1467 }
1468
1469 /**
1470 * @brief Freeze APB1 peripherals (group1 peripherals)
1471 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1472 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1473 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1474 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1475 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1476 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1477 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1478 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1479 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1480 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1481 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1482 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1483 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1484 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1485 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1486 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
1487 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
1488 * @param Periphs This parameter can be a combination of the following values:
1489 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1490 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1491 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1492 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1493 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1494 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1495 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1496 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1497 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1498 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1499 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1500 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1501 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1502 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1503 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1504 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1505 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1506 *
1507 * (*) value not defined in all devices.
1508 * @retval None
1509 */
1510 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1511 {
1512 SET_BIT(DBGMCU->APB1FZ, Periphs);
1513 }
1514
1515 /**
1516 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1517 * @rmtoll APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1518 * APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1519 * APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1520 * APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1521 * APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1522 * APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1523 * APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1524 * APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1525 * APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1526 * APB1_FZ DBG_TIM18_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1527 * APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1528 * APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1529 * APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1530 * APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1531 * APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1532 * APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1533 * APB1_FZ DBG_CAN_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
1534 * @param Periphs This parameter can be a combination of the following values:
1535 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
1536 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
1537 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
1538 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
1539 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
1540 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
1541 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
1542 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
1543 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
1544 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM18_STOP (*)
1545 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1546 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1547 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1548 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1549 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*)
1550 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
1551 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN_STOP (*)
1552 *
1553 * (*) value not defined in all devices.
1554 * @retval None
1555 */
1556 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1557 {
1558 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1559 }
1560
1561 /**
1562 * @brief Freeze APB2 peripherals
1563 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1564 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1565 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1566 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1567 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1568 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1569 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1570 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1571 * @param Periphs This parameter can be a combination of the following values:
1572 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1573 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1574 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1575 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1576 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1577 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1578 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1579 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1580 *
1581 * (*) value not defined in all devices.
1582 * @retval None
1583 */
1584 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1585 {
1586 SET_BIT(DBGMCU->APB2FZ, Periphs);
1587 }
1588
1589 /**
1590 * @brief Unfreeze APB2 peripherals
1591 * @rmtoll APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1592 * APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1593 * APB2_FZ DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1594 * APB2_FZ DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1595 * APB2_FZ DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1596 * APB2_FZ DBG_TIM19_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1597 * APB2_FZ DBG_TIM20_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1598 * APB2_FZ DBG_HRTIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1599 * @param Periphs This parameter can be a combination of the following values:
1600 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP (*)
1601 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
1602 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
1603 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1604 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1605 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM19_STOP (*)
1606 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
1607 * @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
1608 *
1609 * (*) value not defined in all devices.
1610 * @retval None
1611 */
1612 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1613 {
1614 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1615 }
1616
1617 /**
1618 * @}
1619 */
1620
1621 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1622 * @{
1623 */
1624
1625 /**
1626 * @brief Set FLASH Latency
1627 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
1628 * @param Latency This parameter can be one of the following values:
1629 * @arg @ref LL_FLASH_LATENCY_0
1630 * @arg @ref LL_FLASH_LATENCY_1
1631 * @arg @ref LL_FLASH_LATENCY_2
1632 * @retval None
1633 */
1634 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1635 {
1636 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1637 }
1638
1639 /**
1640 * @brief Get FLASH Latency
1641 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
1642 * @retval Returned value can be one of the following values:
1643 * @arg @ref LL_FLASH_LATENCY_0
1644 * @arg @ref LL_FLASH_LATENCY_1
1645 * @arg @ref LL_FLASH_LATENCY_2
1646 */
1647 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1648 {
1649 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1650 }
1651
1652 /**
1653 * @brief Enable Prefetch
1654 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch
1655 * @retval None
1656 */
1657 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1658 {
1659 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1660 }
1661
1662 /**
1663 * @brief Disable Prefetch
1664 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch
1665 * @retval None
1666 */
1667 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1668 {
1669 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE );
1670 }
1671
1672 /**
1673 * @brief Check if Prefetch buffer is enabled
1674 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled
1675 * @retval State of bit (1 or 0).
1676 */
1677 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1678 {
1679 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS));
1680 }
1681
1682 #if defined(FLASH_ACR_HLFCYA)
1683 /**
1684 * @brief Enable Flash Half Cycle Access
1685 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess
1686 * @retval None
1687 */
1688 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void)
1689 {
1690 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1691 }
1692
1693 /**
1694 * @brief Disable Flash Half Cycle Access
1695 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess
1696 * @retval None
1697 */
1698 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void)
1699 {
1700 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA);
1701 }
1702
1703 /**
1704 * @brief Check if Flash Half Cycle Access is enabled or not
1705 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled
1706 * @retval State of bit (1 or 0).
1707 */
1708 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void)
1709 {
1710 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA));
1711 }
1712 #endif /* FLASH_ACR_HLFCYA */
1713
1714
1715
1716 /**
1717 * @}
1718 */
1719
1720 /**
1721 * @}
1722 */
1723
1724 /**
1725 * @}
1726 */
1727
1728 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1729
1730 /**
1731 * @}
1732 */
1733
1734 #ifdef __cplusplus
1735 }
1736 #endif
1737
1738 #endif /* __STM32F3xx_LL_SYSTEM_H */
1739
1740 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/