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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Src / stm32f3xx_hal_hrtim.c
blobe3a0039f6273bd344111fbdbd864d5ec3756f87b
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 @verbatim
54 ==============================================================================
55 ##### Simple mode v.s. waveform mode #####
56 ==============================================================================
57 [..] The HRTIM HAL API is split into 2 categories:
58 (#)Simple functions: these functions allow for using a HRTIM timer as a
59 general purpose timer with high resolution capabilities.
60 HRTIM simple modes are managed through the set of functions named
61 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
62 to the one defined for the TIM peripheral. When a HRTIM timer operates in
63 simple mode, only a very limited set of HRTIM features are used.
64 Following simple modes are proposed:
65 (++)Output compare mode,
66 (++)PWM output mode,
67 (++)Input capture mode,
68 (++)One pulse mode.
69 (#)Waveform functions: These functions allow taking advantage of the HRTIM
70 flexibility to produce numerous types of control signal. When a HRTIM timer
71 operates in waveform mode, all the HRTIM features are accessible without
72 any restriction. HRTIM waveform modes are managed through the set of
73 functions named HAL_HRTIM_Waveform<Function>
74 ##### How to use this driver #####
75 ==============================================================================
76 [..]
77 (#)Initialize the HRTIM low level resources by implementing the
78 HAL_HRTIM_MspInit() function:
79 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
80 (##)Connect HRTIM pins to MCU I/Os
81 (+++) Enable the clock for the HRTIM GPIOs using the following
82 function: __HAL_RCC_GPIOx_CLK_ENABLE()
83 (+++) Configure these GPIO pins in Alternate Function mode using
84 HAL_GPIO_Init()
85 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
86 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
87 (+++)Initialize the DMA handle
88 (+++)Associate the initialized DMA handle to the appropriate DMA
89 handle of the HRTIM handle using __HAL_LINKDMA()
90 (+++)Initialize the DMA channel using HAL_DMA_Init()
91 (+++)Configure the priority and enable the NVIC for the transfer
92 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
93 and HAL_NVIC_EnableIRQ()
94 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
95 (+++)Configure the priority and enable the NVIC for the concerned
96 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
97
98 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
99 structure (field of the HRTIM handle) specifies which global interrupt of
100 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
101 It also contains the HRTIM external synchronization configuration. HRTIM
102 can act as a master (generating a synchronization signal) or as a slave
103 (waiting for a trigger to be synchronized).
104
105 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
106 calibration is executed periodically and compensate for potential voltage
107 and temperature drifts. DLL calibration period is specified by the
108 CalibrationRate argument.
109
110 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
111 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
112 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
113 is still going on when timeout given as argument expires. DLL calibration
114 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
115 In that case an interrupt is generated when the DLL calibration is completed.
116 Note that as DLL calibration is executed on a periodic basis an interrupt
117 will be generated at the end of every DLL calibration operation
118 (worst case: one interrupt every 14 micro seconds !).
119
120 (#) Configure HRTIM resources shared by all HRTIM timers
121 (##)Burst Mode Controller:
122 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
123 controller: operating mode (continuous or one-shot mode), clock
124 (source, prescaler) , trigger(s), period, idle duration.
125 (##)External Events Conditionning:
126 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
127 external event channel: source, polarity, edge-sensitivity.
128 External event can be used as triggers (timer reset, input
129 capture, burst mode, ADC triggers, delayed protection)
130 They can also be used to set or reset timer outputs. Up to
131 10 event channels are available.
132 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
133 event sampling clock (used for digital filtering).
134 (##)Fault Conditionning:
135 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
136 fault channel: source, polarity, edge-sensitivity. Fault
137 channels are used to disable the outputs in case of an
138 abnormal operation. Up to 5 fault channels are available.
139 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
140 sampling clock (used for digital filtering).
141 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
142 circuitry. By default all fault inputs are disabled.
143 (##)ADC trigger:
144 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
145 the update of the ADC trigger register and the ADC trigger.
146 4 independent triggers are available to start both the regular
147 and the injected sequencers of the 2 ADCs
148
149 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
150 function must be called whatever the HRTIM timer operating mode is
151 (simple v.s. waveform). It configures mainly:
152 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
153 (##)The HRTIM timer clock prescaler
154 (##)The HRTIM timer period
155 (##)The HRTIM timer repetition counter
156
157 *** If the HRTIM timer operates in simple mode ***
158 ===================================================
159 [..]
160 (#) Start or Stop simple timers
161 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
162 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
163 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
164 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
165 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
166 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
167 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
168 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
169 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
170 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
171 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
172 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
173 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
174 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
175 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
176 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
177 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
178 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
179
180 *** If the HRTIM timer operates in waveform mode ***
181 ====================================================
182 [..]
183 (#) Completes waveform timer configuration
184 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
185 operating in wave form mode mainly consists in:
186 (+++)Enabling the HRTIM timer interrupts and DMA requests.
187 (+++)Enabling the half mode for the HRTIM timer.
188 (+++)Defining how the HRTIM timer reacts to external synchronization input.
189 (+++)Enabling the push-pull mode for the HRTIM timer.
190 (+++)Enabling the fault channels for the HRTIM timer.
191 (+++)Enabling the dead-time insertion for the HRTIM timer.
192 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
193 on which the delayed protection are applied).
194 (+++)Specifying the HRTIM timer update and reset triggers.
195 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
196 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
197 event blanking and windowing circuitry of a HRTIM timer:
198 (+++)Blanking: to mask external events during a defined time period a defined time period
199 (+++)Windowing, to enable external events only during a defined time period
200 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
201 unit for a HRTIM timer. Allows to generate a couple of
202 complementary signals from a single reference waveform,
203 with programmable delays between active state.
204 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
205 the high-frequency carrier signal added on top of the timing
206 unit output. Chopper mode can be enabled or disabled for each
207 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
208 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
209 controller. Allows having multiple HRTIM registers updated
210 with a single DMA request. The burst DMA operation is started
211 by calling HAL_HRTIM_BurstDMATransfer().
212 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
213 of a HRTIM timer. This operation consists in setting the
214 compare value and possibly specifying the auto delayed mode
215 for compare units 2 and 4 (allows to have compare events
216 generated relatively to capture events). Note that when auto
217 delayed mode is needed, the capture unit associated to the
218 compare unit must be configured separately.
219 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
220 of a HRTIM timer. This operation consists in specifying the
221 source(s) triggering the capture (timer register update event,
222 external event, timer output set/reset event, other HRTIM
223 timer related events).
224 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
225 output mainly consists in:
226 (+++)Setting the output polarity (active high or active low),
227 (+++)Defining the set/reset crossbar for the output,
228 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
229
230 (#) Set waveform timer output(s) level
231 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
232 active or inactive level. For example, when deadtime insertion
233 is enabled it is necessary to force the output level by software
234 to have the outputs in a complementary state as soon as the RUN mode is entered.
235
236 (#) Enable or Disable waveform timer output(s)
237 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
238
239 (#) Start or Stop waveform HRTIM timer(s).
240 (++)HAL_HRTIM_WaveformCounterStart(),HAL_HRTIM_WaveformCounterStop(),
241 (++)HAL_HRTIM_WaveformCounterStart_IT(),HAL_HRTIM_WaveformCounterStop_IT(),
242 (++)HAL_HRTIM_WaveformCounterStart()_DMA,HAL_HRTIM_WaveformCounterStop_DMA(),
243 (#) Burst mode controller enabling:
244 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
245 burst mode controller.
246
247 (#) Some HRTIM operations can be triggered by software:
248 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
249 trigs the burst operation.
250 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
251 capture of the HRTIM timer counter.
252 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
253 update of the pre-loadable registers of the HRTIM timer
254 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
255 HRTIM timer counter.
256
257 (#) Some functions can be used any time to retrieve HRTIM timer related
258 information
259 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
260 capture register of the designated capture unit.
261 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
262 (ACTIVE/INACTIVE) of the designated timer output.
263 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
264 (IDLE/RUN/FAULT) of the designated timer output.
265 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
266 (ACTIVE/INACTIVE) of the designated output when the delayed
267 protection was triggered.
268 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
269 (ACTIVE/INACTIVE) of the burst mode controller.
270 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
271 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
272 the push-pull status indicates on which output the signal is currently
273 active (e.g signal applied on output 1 and output 2 forced
274 inactive or vice versa).
275 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
276 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
277 the idle push-pull status indicates during which period the
278 delayed protection request occurred (e.g. protection occurred
279 when the output 1 was active and output 2 forced inactive or
280 vice versa).
281
282 (#) Some functions can be used any time to retrieve actual HRTIM status
283 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
284
285 @endverbatim
286
287 ******************************************************************************
288 * @attention
289 *
290 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
291 *
292 * Redistribution and use in source and binary forms, with or without modification,
293 * are permitted provided that the following conditions are met:
294 * 1. Redistributions of source code must retain the above copyright notice,
295 * this list of conditions and the following disclaimer.
296 * 2. Redistributions in binary form must reproduce the above copyright notice,
297 * this list of conditions and the following disclaimer in the documentation
298 * and/or other materials provided with the distribution.
299 * 3. Neither the name of STMicroelectronics nor the names of its contributors
300 * may be used to endorse or promote products derived from this software
301 * without specific prior written permission.
302 *
303 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
304 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
305 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
306 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
307 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
308 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
309 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
310 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
311 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
312 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
313 *
314 ******************************************************************************
315 */
316
317 /* Includes ------------------------------------------------------------------*/
318 #include "stm32f3xx_hal.h"
319
320 /** @addtogroup STM32F3xx_HAL_Driver
321 * @{
322 */
323
324 #ifdef HAL_HRTIM_MODULE_ENABLED
325
326 #if defined(STM32F334x8)
327
328 /** @defgroup HRTIM HRTIM
329 * @brief HRTIM HAL module driver
330 * @{
331 */
332
333 /* Private typedef -----------------------------------------------------------*/
334 /* Private define ------------------------------------------------------------*/
335 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
336 * @{
337 */
338 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
339 HRTIM_FLTR_FLT2EN |\
340 HRTIM_FLTR_FLT3EN |\
341 HRTIM_FLTR_FLT4EN | \
342 HRTIM_FLTR_FLT5EN)
343
344 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
345 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
346 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
347 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
348 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
349 HRTIM_TIMUPDATETRIGGER_TIMER_E)
350 /**
351 * @}
352 */
353
354 /* Private macro -------------------------------------------------------------*/
355 /* Private variables ---------------------------------------------------------*/
356 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
357 * @{
358 */
359 static uint32_t TimerIdxToTimerId[] =
360 {
361 HRTIM_TIMERID_TIMER_A,
362 HRTIM_TIMERID_TIMER_B,
363 HRTIM_TIMERID_TIMER_C,
364 HRTIM_TIMERID_TIMER_D,
365 HRTIM_TIMERID_TIMER_E,
366 HRTIM_TIMERID_MASTER,
367 };
368 /**
369 * @}
370 */
371
372 /* Private function prototypes -----------------------------------------------*/
373 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
374 * @{
375 */
376 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
377 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
378
379 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
380 uint32_t TimerIdx,
381 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
382
383 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
384 HRTIM_TimerCfgTypeDef * pTimerCfg);
385
386 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
387 uint32_t TimerIdx,
388 HRTIM_TimerCfgTypeDef * pTimerCfg);
389
390 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
391 uint32_t TimerIdx,
392 uint32_t CompareUnit,
393 HRTIM_CompareCfgTypeDef * pCompareCfg);
394
395 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
396 uint32_t TimerIdx,
397 uint32_t CaptureUnit,
398 uint32_t Event);
399
400 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
401 uint32_t TimerIdx,
402 uint32_t Output,
403 HRTIM_OutputCfgTypeDef * pOutputCfg);
404
405 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
406 uint32_t Event,
407 HRTIM_EventCfgTypeDef * pEventCfg);
408
409 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
410 uint32_t TimerIdx,
411 uint32_t Event);
412
413 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
414 uint32_t TimerIdx,
415 uint32_t OCChannel);
416
417 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
418 uint32_t TimerIdx,
419 uint32_t OCChannel);
420
421 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
422 uint32_t TimerIdx);
423
424 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma);
425
426 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
427 uint32_t TimerIdx);
428
429 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
430
431 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
432
433 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
434 uint32_t TimerIdx);
435
436 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
437
438 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
439
440 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
441
442 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
443 /**
444 * @}
445 */
446
447 /* Exported functions ---------------------------------------------------------*/
448 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
449 * @{
450 */
451
452 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
453 * @brief Initialization and Configuration functions
454 @verbatim
455 ===============================================================================
456 ##### Initialization and Time Base Configuration functions #####
457 ===============================================================================
458 [..] This section provides functions allowing to:
459 (+) Initialize a HRTIM instance
460 (+) De-initialize a HRTIM instance
461 (+) Initialize the HRTIM MSP
462 (+) De-initialize the HRTIM MSP
463 (+) Start the high-resolution unit (start DLL calibration)
464 (+) Check that the high resolution unit is ready (DLL calibration done)
465 (+) Configure the time base unit of a HRTIM timer
466
467 @endverbatim
468 * @{
469 */
470
471 /**
472 * @brief Initializes a HRTIM instance
473 * @param hhrtim pointer to HAL HRTIM handle
474 * @retval HAL status
475 */
476 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
477 {
478 uint8_t timer_idx;
479 uint32_t hrtim_mcr;
480
481 /* Check the HRTIM handle allocation */
482 if(hhrtim == NULL)
483 {
484 return HAL_ERROR;
485 }
486
487 /* Check the parameters */
488 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
489 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
490
491 /* Set the HRTIM state */
492 hhrtim->State = HAL_HRTIM_STATE_BUSY;
493
494 /* Initialize the DMA handles */
495 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
496 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
497 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
498 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
499 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
500 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
501
502 /* HRTIM output synchronization configuration (if required) */
503 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != RESET)
504 {
505 /* Check parameters */
506 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
507 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
508
509 /* The synchronization output initialization procedure must be done prior
510 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
511 */
512 if (hhrtim->Instance == HRTIM1)
513 {
514 /* Enable the HRTIM peripheral clock */
515 __HAL_RCC_HRTIM1_CLK_ENABLE();
516 }
517
518 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
519
520 /* Set the event to be sent on the synchronization output */
521 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
522 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
523
524 /* Set the polarity of the synchronization output */
525 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
526 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
527
528 /* Update the HRTIM registers */
529 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
530 }
531
532 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
533 HAL_HRTIM_MspInit(hhrtim);
534
535 /* HRTIM input synchronization configuration (if required) */
536 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != RESET)
537 {
538 /* Check parameters */
539 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
540
541 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
542
543 /* Set the synchronization input source */
544 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
545 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
546
547 /* Update the HRTIM registers */
548 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
549 }
550
551 /* Initialize the HRTIM state*/
552 hhrtim->State = HAL_HRTIM_STATE_READY;
553
554 /* Initialize the lock status of the HRTIM HAL API */
555 __HAL_UNLOCK(hhrtim);
556
557 /* Tnitialize timer related parameters */
558 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
559 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
560 timer_idx++)
561 {
562 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
563 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
564 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
565 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
566 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
567 hhrtim->TimerParam[timer_idx].DMASize = 0U;
568 }
569
570 return HAL_OK;
571 }
572
573 /**
574 * @brief De-initializes a HRTIM instance
575 * @param hhrtim pointer to HAL HRTIM handle
576 * @retval HAL status
577 */
578 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
579 {
580 /* Check the HRTIM handle allocation */
581 if(hhrtim == NULL)
582 {
583 return HAL_ERROR;
584 }
585
586 /* Check the parameters */
587 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
588
589 /* Set the HRTIM state */
590 hhrtim->State = HAL_HRTIM_STATE_BUSY;
591
592 /* DeInit the low level hardware */
593 HAL_HRTIM_MspDeInit(hhrtim);
594
595 hhrtim->State = HAL_HRTIM_STATE_READY;
596
597 return HAL_OK;
598 }
599
600 /**
601 * @brief MSP initialization for a HRTIM instance
602 * @param hhrtim pointer to HAL HRTIM handle
603 * @retval None
604 */
605 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
606 {
607 /* Prevent unused argument(s) compilation warning */
608 UNUSED(hhrtim);
609
610 /* NOTE: This function should not be modified, when the callback is needed,
611 the HAL_HRTIM_MspInit could be implemented in the user file
612 */
613 }
614
615 /**
616 * @brief MSP de-initialization for a for a HRTIM instance
617 * @param hhrtim pointer to HAL HRTIM handle
618 * @retval None
619 */
620 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
621 {
622 /* Prevent unused argument(s) compilation warning */
623 UNUSED(hhrtim);
624
625 /* NOTE: This function should not be modified, when the callback is needed,
626 the HAL_HRTIM_MspDeInit could be implemented in the user file
627 */
628 }
629
630 /**
631 * @brief Starts the DLL calibration
632 * @param hhrtim pointer to HAL HRTIM handle
633 * @param CalibrationRate DLL calibration period
634 * This parameter can be one of the following values:
635 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
636 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
637 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
638 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
639 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
640 * @retval HAL status
641 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
642 * within the HAL_HRTIM_PollForDLLCalibration function, just before
643 * exiting the function.
644 */
645 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
646 uint32_t CalibrationRate)
647 {
648 uint32_t hrtim_dllcr;
649
650 /* Check the parameters */
651 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
652
653 /* Process Locked */
654 __HAL_LOCK(hhrtim);
655
656 hhrtim->State = HAL_HRTIM_STATE_BUSY;
657
658 /* Configure DLL Calibration */
659 hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
660
661 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
662 {
663 /* One shot DLL calibration */
664 hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
665 hrtim_dllcr |= HRTIM_DLLCR_CAL;
666 }
667 else
668 {
669 /* Periodic DLL calibration */
670 hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
671 hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
672 }
673
674 /* Update HRTIM register */
675 hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
676
677 return HAL_OK;
678 }
679
680 /**
681 * @brief Starts the DLL calibration.
682 * DLL ready interrupt is enabled
683 * @param hhrtim pointer to HAL HRTIM handle
684 * @param CalibrationRate DLL calibration period
685 * This parameter can be one of the following values:
686 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
687 * @arg HRTIM_CALIBRATIONRATE_7300: Periodic DLL calibration. T=7.3 ms
688 * @arg HRTIM_CALIBRATIONRATE_910: Periodic DLL calibration. T=910 us
689 * @arg HRTIM_CALIBRATIONRATE_114: Periodic DLL calibration. T=114 us
690 * @arg HRTIM_CALIBRATIONRATE_14: Periodic DLL calibration. T=14 us
691 * @retval HAL status
692 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
693 * within the IRQ processing function when processing the DLL ready
694 * interrupt.
695 * @note If this function is called for periodic calibration, the DLLRDY
696 * interrupt is generated every time the calibration completes which
697 * will significantly increases the overall interrupt rate.
698 */
699 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
700 uint32_t CalibrationRate)
701 {
702 uint32_t hrtim_dllcr;
703
704 /* Check the parameters */
705 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
706
707 /* Process Locked */
708 __HAL_LOCK(hhrtim);
709
710 hhrtim->State = HAL_HRTIM_STATE_BUSY;
711
712 /* Enable DLL Ready interrupt flag */
713 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
714
715 /* Configure DLL Calibration */
716 hrtim_dllcr = hhrtim->Instance->sCommonRegs.DLLCR;
717
718 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
719 {
720 /* One shot DLL calibration */
721 hrtim_dllcr &= ~(HRTIM_DLLCR_CALEN);
722 hrtim_dllcr |= HRTIM_DLLCR_CAL;
723 }
724 else
725 {
726 /* Periodic DLL calibration */
727 hrtim_dllcr &= ~(HRTIM_DLLCR_CALRTE | HRTIM_DLLCR_CAL);
728 hrtim_dllcr |= (CalibrationRate | HRTIM_DLLCR_CALEN);
729 }
730
731 /* Update HRTIM register */
732 hhrtim->Instance->sCommonRegs.DLLCR = hrtim_dllcr;
733
734 return HAL_OK;
735 }
736
737 /**
738 * @brief Polls the DLL calibration ready flag and returns when the flag is
739 * set (DLL calibration completed) or upon timeout expiration
740 * @param hhrtim pointer to HAL HRTIM handle
741 * @param Timeout Timeout duration in millisecond
742 * @retval HAL status
743 */
744 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
745 uint32_t Timeout)
746 {
747 uint32_t tickstart=0U;
748
749 tickstart = HAL_GetTick();
750
751 /* Check End of conversion flag */
752 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == RESET)
753 {
754 if (Timeout != HAL_MAX_DELAY)
755 {
756 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
757 {
758 hhrtim->State = HAL_HRTIM_STATE_ERROR;
759 return HAL_TIMEOUT;
760 }
761 }
762 }
763
764 /* Set HRTIM State */
765 hhrtim->State = HAL_HRTIM_STATE_READY;
766
767 /* Process unlocked */
768 __HAL_UNLOCK(hhrtim);
769
770 return HAL_OK;
771 }
772
773 /**
774 * @brief Configures the time base unit of a timer
775 * @param hhrtim pointer to HAL HRTIM handle
776 * @param TimerIdx Timer index
777 * This parameter can be one of the following values:
778 * @arg HRTIM_TIMERINDEX_MASTER for master timer
779 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
780 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
781 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
782 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
783 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
784 * @param pTimeBaseCfg pointer to the time base configuration structure
785 * @note This function must be called prior starting the timer
786 * @note The time-base unit initialization parameters specify:
787 * The timer counter operating mode (continuous, one shot),
788 * The timer clock prescaler,
789 * The timer period ,
790 * The timer repetition counter.
791 * @retval HAL status
792 */
793 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
794 uint32_t TimerIdx,
795 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
796 {
797 /* Check the parameters */
798 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
799 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
800 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
801
802 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
803 {
804 return HAL_BUSY;
805 }
806
807 /* Set the HRTIM state */
808 hhrtim->State = HAL_HRTIM_STATE_BUSY;
809
810 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
811 {
812 /* Configure master timer time base unit */
813 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
814 }
815 else
816 {
817 /* Configure timing unit time base unit */
818 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
819 }
820
821 /* Set HRTIM state */
822 hhrtim->State = HAL_HRTIM_STATE_READY;
823
824 return HAL_OK;
825 }
826
827 /**
828 * @}
829 */
830
831 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
832 * @brief Simple time base mode functions.
833 @verbatim
834 ===============================================================================
835 ##### Simple time base mode functions #####
836 ===============================================================================
837 [..] This section provides functions allowing to:
838 (+) Start simple time base
839 (+) Stop simple time base
840 (+) Start simple time base and enable interrupt
841 (+) Stop simple time base and disable interrupt
842 (+) Start simple time base and enable DMA transfer
843 (+) Stop simple time base and disable DMA transfer
844 -@- When a HRTIM timer operates in simple time base mode, the timer
845 counter counts from 0 to the period value.
846
847 @endverbatim
848 * @{
849 */
850
851 /**
852 * @brief Starts the counter of a timer operating in simple time base mode.
853 * @param hhrtim pointer to HAL HRTIM handle
854 * @param TimerIdx Timer index.
855 * This parameter can be one of the following values:
856 * @arg HRTIM_TIMERINDEX_MASTER for master timer
857 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
858 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
859 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
860 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
861 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
862 * @retval HAL status
863 */
864 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
865 uint32_t TimerIdx)
866 {
867 /* Check the parameters */
868 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
869
870 /* Process Locked */
871 __HAL_LOCK(hhrtim);
872
873 hhrtim->State = HAL_HRTIM_STATE_BUSY;
874
875 /* Enable the timer counter */
876 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
877
878 hhrtim->State = HAL_HRTIM_STATE_READY;
879
880 /* Process Unlocked */
881 __HAL_UNLOCK(hhrtim);
882
883 return HAL_OK;
884 }
885
886 /**
887 * @brief Stops the counter of a timer operating in simple time base mode.
888 * @param hhrtim pointer to HAL HRTIM handle
889 * @param TimerIdx Timer index.
890 * This parameter can be one of the following values:
891 * @arg HRTIM_TIMERINDEX_MASTER for master timer
892 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
893 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
894 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
895 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
896 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
897 * @retval HAL status
898 */
899 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
900 uint32_t TimerIdx)
901 {
902 /* Check the parameters */
903 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
904
905 /* Process Locked */
906 __HAL_LOCK(hhrtim);
907
908 hhrtim->State = HAL_HRTIM_STATE_BUSY;
909
910 /* Disable the timer counter */
911 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
912
913 hhrtim->State = HAL_HRTIM_STATE_READY;
914
915 /* Process Unlocked */
916 __HAL_UNLOCK(hhrtim);
917
918 return HAL_OK;
919 }
920
921 /**
922 * @brief Starts the counter of a timer operating in simple time base mode
923 * (Timer repetition interrupt is enabled).
924 * @param hhrtim pointer to HAL HRTIM handle
925 * @param TimerIdx Timer index.
926 * This parameter can be one of the following values:
927 * @arg HRTIM_TIMERINDEX_MASTER for master timer
928 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
929 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
930 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
931 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
932 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
933 * @retval HAL status
934 */
935 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
936 uint32_t TimerIdx)
937 {
938 /* Check the parameters */
939 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
940
941 /* Process Locked */
942 __HAL_LOCK(hhrtim);
943
944 hhrtim->State = HAL_HRTIM_STATE_BUSY;
945
946 /* Enable the repetition interrupt */
947 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
948 {
949 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
950 }
951 else
952 {
953 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
954 }
955
956 /* Enable the timer counter */
957 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
958
959 hhrtim->State = HAL_HRTIM_STATE_READY;
960
961 /* Process Unlocked */
962 __HAL_UNLOCK(hhrtim);
963
964 return HAL_OK;
965 }
966
967 /**
968 * @brief Stops the counter of a timer operating in simple time base mode
969 * (Timer repetition interrupt is disabled).
970 * @param hhrtim pointer to HAL HRTIM handle
971 * @param TimerIdx Timer index.
972 * This parameter can be one of the following values:
973 * @arg HRTIM_TIMERINDEX_MASTER for master timer
974 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
975 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
976 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
977 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
978 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
979 * @retval HAL status
980 */
981 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
982 uint32_t TimerIdx)
983 {
984 /* Check the parameters */
985 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
986
987 /* Process Locked */
988 __HAL_LOCK(hhrtim);
989
990 hhrtim->State = HAL_HRTIM_STATE_BUSY;
991
992 /* Disable the repetition interrupt */
993 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
994 {
995 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
996 }
997 else
998 {
999 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1000 }
1001
1002 /* Disable the timer counter */
1003 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1004
1005 hhrtim->State = HAL_HRTIM_STATE_READY;
1006
1007 /* Process Unlocked */
1008 __HAL_UNLOCK(hhrtim);
1009
1010 return HAL_OK;
1011 }
1012
1013 /**
1014 * @brief Starts the counter of a timer operating in simple time base mode
1015 * (Timer repetition DMA request is enabled).
1016 * @param hhrtim pointer to HAL HRTIM handle
1017 * @param TimerIdx Timer index.
1018 * This parameter can be one of the following values:
1019 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1020 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1021 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1022 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1023 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1024 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1025 * @param SrcAddr DMA transfer source address
1026 * @param DestAddr DMA transfer destination address
1027 * @param Length The length of data items (data size) to be transferred
1028 * from source to destination
1029 */
1030 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1031 uint32_t TimerIdx,
1032 uint32_t SrcAddr,
1033 uint32_t DestAddr,
1034 uint32_t Length)
1035 {
1036 DMA_HandleTypeDef * hdma;
1037
1038 /* Check the parameters */
1039 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1040
1041 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1042 {
1043 return HAL_BUSY;
1044 }
1045 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1046 {
1047 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1048 {
1049 return HAL_ERROR;
1050 }
1051 else
1052 {
1053 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1054 }
1055 }
1056
1057 /* Process Locked */
1058 __HAL_LOCK(hhrtim);
1059
1060 /* Get the timer DMA handler */
1061 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1062 if (hdma == NULL)
1063 {
1064 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1065
1066 /* Process Unlocked */
1067 __HAL_UNLOCK(hhrtim);
1068
1069 return HAL_ERROR;
1070 }
1071 /* Set the DMA transfer completed callback */
1072 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1073 {
1074 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1075 }
1076 else
1077 {
1078 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1079 }
1080
1081 /* Set the DMA error callback */
1082 hdma->XferErrorCallback = HRTIM_DMAError ;
1083
1084 /* Enable the DMA channel */
1085 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
1086
1087 /* Enable the timer repetition DMA request */
1088 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1089 {
1090 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1091 }
1092 else
1093 {
1094 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1095 }
1096
1097 /* Enable the timer counter */
1098 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1099
1100 hhrtim->State = HAL_HRTIM_STATE_READY;
1101
1102 /* Process Unlocked */
1103 __HAL_UNLOCK(hhrtim);
1104
1105 return HAL_OK;
1106 }
1107
1108 /**
1109 * @brief Stops the counter of a timer operating in simple time base mode
1110 * (Timer repetition DMA request is disabled).
1111 * @param hhrtim pointer to HAL HRTIM handle
1112 * @param TimerIdx Timer index.
1113 * This parameter can be one of the following values:
1114 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1115 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1116 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1117 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1118 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1119 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1120 * @retval HAL status
1121 */
1122 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1123 uint32_t TimerIdx)
1124 {
1125 DMA_HandleTypeDef * hdma;
1126
1127 /* Check the parameters */
1128 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1129
1130 /* Process Locked */
1131 __HAL_LOCK(hhrtim);
1132
1133 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1134 {
1135 /* Disable the DMA */
1136 HAL_DMA_Abort(hhrtim->hdmaMaster);
1137
1138 /* Disable the timer repetition DMA request */
1139 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1140 }
1141 else
1142 {
1143 /* Get the timer DMA handler */
1144 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1145
1146 if (hdma == NULL)
1147 {
1148 /* Disable the timer repetition DMA request */
1149 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1150
1151 /* Disable the timer counter */
1152 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1153
1154 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1155
1156 /* Process Unlocked */
1157 __HAL_UNLOCK(hhrtim);
1158
1159 return HAL_ERROR;
1160 }
1161 else
1162 {
1163 /* Disable the DMA */
1164 HAL_DMA_Abort(hdma);
1165
1166 /* Disable the timer repetition DMA request */
1167 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1168 }
1169 }
1170
1171 /* Disable the timer counter */
1172 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1173
1174 hhrtim->State = HAL_HRTIM_STATE_READY;
1175
1176 /* Process Unlocked */
1177 __HAL_UNLOCK(hhrtim);
1178
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @}
1184 */
1185
1186 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1187 * @brief Simple output compare functions
1188 @verbatim
1189 ===============================================================================
1190 ##### Simple output compare functions #####
1191 ===============================================================================
1192 [..] This section provides functions allowing to:
1193 (+) Configure simple output channel
1194 (+) Start simple output compare
1195 (+) Stop simple output compare
1196 (+) Start simple output compare and enable interrupt
1197 (+) Stop simple output compare and disable interrupt
1198 (+) Start simple output compare and enable DMA transfer
1199 (+) Stop simple output compare and disable DMA transfer
1200 -@- When a HRTIM timer operates in simple output compare mode
1201 the output level is set to a programmable value when a match
1202 is found between the compare register and the counter.
1203 Compare unit 1 is automatically associated to output 1
1204 Compare unit 2 is automatically associated to output 2
1205 @endverbatim
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Configures an output in simple output compare mode
1211 * @param hhrtim pointer to HAL HRTIM handle
1212 * @param TimerIdx Timer index
1213 * This parameter can be one of the following values:
1214 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1215 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1216 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1217 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1218 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1219 * @param OCChannel Timer output
1220 * This parameter can be one of the following values:
1221 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1222 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1223 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1224 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1225 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1226 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1227 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1228 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1229 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1230 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1231 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1232 * @note When the timer operates in simple output compare mode:
1233 * Output 1 is implicitly controlled by the compare unit 1
1234 * Output 2 is implicitly controlled by the compare unit 2
1235 * Output Set/Reset crossbar is set according to the selected output compare mode:
1236 * Toggle: SETxyR = RSTxyR = CMPy
1237 * Active: SETxyR = CMPy, RSTxyR = 0
1238 * Inactive: SETxy =0, RSTxy = CMPy
1239 * @retval HAL status
1240 */
1241 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1242 uint32_t TimerIdx,
1243 uint32_t OCChannel,
1244 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1245 {
1246 uint32_t CompareUnit = 0xFFFFFFFFU;
1247 HRTIM_CompareCfgTypeDef CompareCfg = {0};
1248 HRTIM_OutputCfgTypeDef OutputCfg = {0};
1249
1250 /* Check parameters */
1251 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1252 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1253 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1254 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1255
1256 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1257 {
1258 return HAL_BUSY;
1259 }
1260
1261 /* Set HRTIM state */
1262 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1263
1264 /* Configure timer compare unit */
1265 switch (OCChannel)
1266 {
1267 case HRTIM_OUTPUT_TA1:
1268 case HRTIM_OUTPUT_TB1:
1269 case HRTIM_OUTPUT_TC1:
1270 case HRTIM_OUTPUT_TD1:
1271 case HRTIM_OUTPUT_TE1:
1272 {
1273 CompareUnit = HRTIM_COMPAREUNIT_1;
1274 }
1275 break;
1276 case HRTIM_OUTPUT_TA2:
1277 case HRTIM_OUTPUT_TB2:
1278 case HRTIM_OUTPUT_TC2:
1279 case HRTIM_OUTPUT_TD2:
1280 case HRTIM_OUTPUT_TE2:
1281 {
1282 CompareUnit = HRTIM_COMPAREUNIT_2;
1283 }
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 CompareCfg.CompareValue = pSimpleOCChannelCfg->Pulse;
1290 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1291 CompareCfg.AutoDelayedTimeout = 0U;
1292
1293 HRTIM_CompareUnitConfig(hhrtim,
1294 TimerIdx,
1295 CompareUnit,
1296 &CompareCfg);
1297
1298 /* Configure timer output */
1299 OutputCfg.Polarity = pSimpleOCChannelCfg->Polarity;
1300 OutputCfg.IdleLevel = pSimpleOCChannelCfg->IdleLevel;
1301 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1302 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1303 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1304 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1305
1306 switch (pSimpleOCChannelCfg->Mode)
1307 {
1308 case HRTIM_BASICOCMODE_TOGGLE:
1309 {
1310 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1311 {
1312 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1313 }
1314 else
1315 {
1316 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1317 }
1318 OutputCfg.ResetSource = OutputCfg.SetSource;
1319 }
1320 break;
1321 case HRTIM_BASICOCMODE_ACTIVE:
1322 {
1323 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1324 {
1325 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1326 }
1327 else
1328 {
1329 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1330 }
1331 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1332 }
1333 break;
1334 case HRTIM_BASICOCMODE_INACTIVE:
1335 {
1336 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1337 {
1338 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1339 }
1340 else
1341 {
1342 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1343 }
1344 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1345 }
1346 break;
1347 default:
1348 break;
1349 }
1350
1351 HRTIM_OutputConfig(hhrtim,
1352 TimerIdx,
1353 OCChannel,
1354 &OutputCfg);
1355
1356 /* Set HRTIM state */
1357 hhrtim->State = HAL_HRTIM_STATE_READY;
1358
1359 return HAL_OK;
1360 }
1361
1362 /**
1363 * @brief Starts the output compare signal generation on the designed timer output
1364 * @param hhrtim pointer to HAL HRTIM handle
1365 * @param TimerIdx Timer index
1366 * This parameter can be one of the following values:
1367 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1368 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1369 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1370 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1371 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1372 * @param OCChannel Timer output
1373 * This parameter can be one of the following values:
1374 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1375 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1376 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1377 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1378 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1379 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1380 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1381 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1382 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1383 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1384 * @retval HAL status
1385 */
1386 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1387 uint32_t TimerIdx,
1388 uint32_t OCChannel)
1389 {
1390 /* Check the parameters */
1391 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1392
1393 /* Process Locked */
1394 __HAL_LOCK(hhrtim);
1395
1396 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1397
1398 /* Enable the timer output */
1399 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1400
1401 /* Enable the timer counter */
1402 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1403
1404 hhrtim->State = HAL_HRTIM_STATE_READY;
1405
1406 /* Process Unlocked */
1407 __HAL_UNLOCK(hhrtim);
1408
1409 return HAL_OK;
1410 }
1411
1412 /**
1413 * @brief Stops the output compare signal generation on the designed timer output
1414 * @param hhrtim pointer to HAL HRTIM handle
1415 * @param TimerIdx Timer index
1416 * This parameter can be one of the following values:
1417 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1418 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1419 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1420 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1421 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1422 * @param OCChannel Timer output
1423 * This parameter can be one of the following values:
1424 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1425 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1426 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1427 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1428 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1429 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1430 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1431 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1432 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1433 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1434 * @retval HAL status
1435 */
1436 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1437 uint32_t TimerIdx,
1438 uint32_t OCChannel)
1439 {
1440 /* Check the parameters */
1441 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1442
1443 /* Process Locked */
1444 __HAL_LOCK(hhrtim);
1445
1446 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1447
1448 /* Disable the timer output */
1449 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1450
1451 /* Disable the timer counter */
1452 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1453
1454 hhrtim->State = HAL_HRTIM_STATE_READY;
1455
1456 /* Process Unlocked */
1457 __HAL_UNLOCK(hhrtim);
1458
1459 return HAL_OK;
1460 }
1461
1462 /**
1463 * @brief Starts the output compare signal generation on the designed timer output
1464 * (Interrupt is enabled (see note note below)).
1465 * @param hhrtim pointer to HAL HRTIM handle
1466 * @param TimerIdx Timer index
1467 * This parameter can be one of the following values:
1468 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1469 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1470 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1471 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1472 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1473 * @param OCChannel Timer output
1474 * This parameter can be one of the following values:
1475 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1476 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1477 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1478 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1479 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1480 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1481 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1482 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1483 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1484 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1485 * @note Interrupt enabling depends on the chosen output compare mode
1486 * Output toggle: compare match interrupt is enabled
1487 * Output set active: output set interrupt is enabled
1488 * Output set inactive: output reset interrupt is enabled
1489 * @retval HAL status
1490 */
1491 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1492 uint32_t TimerIdx,
1493 uint32_t OCChannel)
1494 {
1495 uint32_t interrupt;
1496
1497 /* Check the parameters */
1498 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1499
1500 /* Process Locked */
1501 __HAL_LOCK(hhrtim);
1502
1503 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1504
1505 /* Get the interrupt to enable (depends on the output compare mode) */
1506 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1507
1508 /* Enable the timer output */
1509 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1510
1511 /* Enable the timer interrupt (depends on the output compare mode) */
1512 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1513
1514 /* Enable the timer counter */
1515 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1516
1517 hhrtim->State = HAL_HRTIM_STATE_READY;
1518
1519 /* Process Unlocked */
1520 __HAL_UNLOCK(hhrtim);
1521
1522 return HAL_OK;
1523 }
1524
1525 /**
1526 * @brief Stops the output compare signal generation on the designed timer output
1527 * (Interrupt is disabled).
1528 * @param hhrtim pointer to HAL HRTIM handle
1529 * @param TimerIdx Timer index
1530 * This parameter can be one of the following values:
1531 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1532 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1533 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1534 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1535 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1536 * @param OCChannel Timer output
1537 * This parameter can be one of the following values:
1538 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1539 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1540 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1541 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1542 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1543 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1544 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1545 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1546 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1547 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1548 * @retval HAL status
1549 */
1550 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1551 uint32_t TimerIdx,
1552 uint32_t OCChannel)
1553 {
1554 uint32_t interrupt;
1555
1556 /* Check the parameters */
1557 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1558
1559 /* Process Locked */
1560 __HAL_LOCK(hhrtim);
1561
1562 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1563
1564 /* Disable the timer output */
1565 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1566
1567 /* Get the interrupt to disable (depends on the output compare mode) */
1568 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1569
1570 /* Disable the timer interrupt */
1571 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1572
1573 /* Disable the timer counter */
1574 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1575
1576 hhrtim->State = HAL_HRTIM_STATE_READY;
1577
1578 /* Process Unlocked */
1579 __HAL_UNLOCK(hhrtim);
1580
1581 return HAL_OK;
1582 }
1583
1584 /**
1585 * @brief Starts the output compare signal generation on the designed timer output
1586 * (DMA request is enabled (see note below)).
1587 * @param hhrtim pointer to HAL HRTIM handle
1588 * @param TimerIdx Timer index
1589 * This parameter can be one of the following values:
1590 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1591 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1592 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1593 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1594 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1595 * @param OCChannel Timer output
1596 * This parameter can be one of the following values:
1597 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1598 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1599 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1600 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1601 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1602 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1603 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1604 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1605 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1606 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1607 * @param SrcAddr DMA transfer source address
1608 * @param DestAddr DMA transfer destination address
1609 * @param Length The length of data items (data size) to be transferred
1610 * from source to destination
1611 * @note DMA request enabling depends on the chosen output compare mode
1612 * Output toggle: compare match DMA request is enabled
1613 * Output set active: output set DMA request is enabled
1614 * Output set inactive: output reset DMA request is enabled
1615 * @retval HAL status
1616 */
1617 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1618 uint32_t TimerIdx,
1619 uint32_t OCChannel,
1620 uint32_t SrcAddr,
1621 uint32_t DestAddr,
1622 uint32_t Length)
1623 {
1624 DMA_HandleTypeDef * hdma;
1625 uint32_t dma_request;
1626
1627 /* Check the parameters */
1628 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1629
1630 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1631 {
1632 return HAL_BUSY;
1633 }
1634 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1635 {
1636 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1637 {
1638 return HAL_ERROR;
1639 }
1640 else
1641 {
1642 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1643 }
1644 }
1645
1646 /* Process Locked */
1647 __HAL_LOCK(hhrtim);
1648
1649 /* Enable the timer output */
1650 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1651
1652 /* Get the DMA request to enable */
1653 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1654
1655 /* Get the timer DMA handler */
1656 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1657 if (hdma == NULL)
1658 {
1659 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1660
1661 /* Process Unlocked */
1662 __HAL_UNLOCK(hhrtim);
1663
1664 return HAL_ERROR;
1665 }
1666
1667 /* Set the DMA error callback */
1668 hdma->XferErrorCallback = HRTIM_DMAError ;
1669
1670 /* Set the DMA transfer completed callback */
1671 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1672
1673 /* Enable the DMA channel */
1674 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
1675
1676 /* Enable the timer DMA request */
1677 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1678
1679 /* Enable the timer counter */
1680 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1681
1682 hhrtim->State = HAL_HRTIM_STATE_READY;
1683
1684 /* Process Unlocked */
1685 __HAL_UNLOCK(hhrtim);
1686
1687 return HAL_OK;
1688 }
1689
1690 /**
1691 * @brief Stops the output compare signal generation on the designed timer output
1692 * (DMA request is disabled).
1693 * @param hhrtim pointer to HAL HRTIM handle
1694 * @param TimerIdx Timer index
1695 * This parameter can be one of the following values:
1696 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1697 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1698 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1699 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1700 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1701 * @param OCChannel Timer output
1702 * This parameter can be one of the following values:
1703 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1704 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1705 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1706 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1707 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1708 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1709 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1710 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1711 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1712 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1713 * @retval HAL status
1714 */
1715 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1716 uint32_t TimerIdx,
1717 uint32_t OCChannel)
1718 {
1719 DMA_HandleTypeDef * hdma;
1720 uint32_t dma_request;
1721
1722 /* Check the parameters */
1723 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1724
1725 /* Process Locked */
1726 __HAL_LOCK(hhrtim);
1727
1728 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1729
1730 /* Disable the timer output */
1731 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1732
1733 /* Get the timer DMA handler */
1734 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1735 if (hdma == NULL)
1736 {
1737 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1738
1739 /* Process Unlocked */
1740 __HAL_UNLOCK(hhrtim);
1741
1742 return HAL_ERROR;
1743 }
1744
1745 /* Disable the DMA */
1746 HAL_DMA_Abort(hdma);
1747
1748 /* Get the DMA request to disable */
1749 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1750
1751 /* Disable the timer DMA request */
1752 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1753
1754 /* Disable the timer counter */
1755 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1756
1757 hhrtim->State = HAL_HRTIM_STATE_READY;
1758
1759 /* Process Unlocked */
1760 __HAL_UNLOCK(hhrtim);
1761
1762 return HAL_OK;
1763 }
1764
1765 /**
1766 * @}
1767 */
1768
1769 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1770 * @brief Simple PWM output functions
1771 @verbatim
1772 ===============================================================================
1773 ##### Simple PWM output functions #####
1774 ===============================================================================
1775 [..] This section provides functions allowing to:
1776 (+) Configure simple PWM output channel
1777 (+) Start simple PWM output
1778 (+) Stop simple PWM output
1779 (+) Start simple PWM output and enable interrupt
1780 (+) Stop simple PWM output and disable interrupt
1781 (+) Start simple PWM output and enable DMA transfer
1782 (+) Stop simple PWM output and disable DMA transfer
1783 -@- When a HRTIM timer operates in simple PWM output mode
1784 the output level is set to a programmable value when a match is
1785 found between the compare register and the counter and reset when
1786 the timer period is reached. Duty cycle is determined by the
1787 comparison value.
1788 Compare unit 1 is automatically associated to output 1
1789 Compare unit 2 is automatically associated to output 2
1790 @endverbatim
1791 * @{
1792 */
1793
1794 /**
1795 * @brief Configures an output in simple PWM mode
1796 * @param hhrtim pointer to HAL HRTIM handle
1797 * @param TimerIdx Timer index
1798 * This parameter can be one of the following values:
1799 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1800 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1801 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1802 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1803 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1804 * @param PWMChannel Timer output
1805 * This parameter can be one of the following values:
1806 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1807 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1808 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1809 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1810 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1811 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1812 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1813 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1814 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1815 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1816 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1817 * @note When the timer operates in simple PWM output mode:
1818 * Output 1 is implicitly controlled by the compare unit 1
1819 * Output 2 is implicitly controlled by the compare unit 2
1820 * Output Set/Reset crossbar is set as follows:
1821 * Output 1: SETx1R = CMP1, RSTx1R = PER
1822 * Output 2: SETx2R = CMP2, RST2R = PER
1823 * @note When Simple PWM mode is used the registers preload mechanism is
1824 * enabled (otherwise the behavior is not guaranteed).
1825 * @retval HAL status
1826 */
1827 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1828 uint32_t TimerIdx,
1829 uint32_t PWMChannel,
1830 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
1831 {
1832 uint32_t CompareUnit = 0xFFFFFFFFU;
1833 HRTIM_CompareCfgTypeDef CompareCfg;
1834 HRTIM_OutputCfgTypeDef OutputCfg;
1835 uint32_t hrtim_timcr;
1836
1837 /* Check parameters */
1838 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1839 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
1840 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
1841
1842 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1843 {
1844 return HAL_BUSY;
1845 }
1846
1847 /* Process Locked */
1848 __HAL_LOCK(hhrtim); hhrtim->State = HAL_HRTIM_STATE_BUSY;
1849
1850 /* Configure timer compare unit */
1851 switch (PWMChannel)
1852 {
1853 case HRTIM_OUTPUT_TA1:
1854 case HRTIM_OUTPUT_TB1:
1855 case HRTIM_OUTPUT_TC1:
1856 case HRTIM_OUTPUT_TD1:
1857 case HRTIM_OUTPUT_TE1:
1858 {
1859 CompareUnit = HRTIM_COMPAREUNIT_1;
1860 }
1861 break;
1862 case HRTIM_OUTPUT_TA2:
1863 case HRTIM_OUTPUT_TB2:
1864 case HRTIM_OUTPUT_TC2:
1865 case HRTIM_OUTPUT_TD2:
1866 case HRTIM_OUTPUT_TE2:
1867 {
1868 CompareUnit = HRTIM_COMPAREUNIT_2;
1869 }
1870 break;
1871 default:
1872 break;
1873 }
1874
1875 CompareCfg.CompareValue = pSimplePWMChannelCfg->Pulse;
1876 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
1877 CompareCfg.AutoDelayedTimeout = 0U;
1878
1879 HRTIM_CompareUnitConfig(hhrtim,
1880 TimerIdx,
1881 CompareUnit,
1882 &CompareCfg);
1883
1884 /* Configure timer output */
1885 OutputCfg.Polarity = pSimplePWMChannelCfg->Polarity;
1886 OutputCfg.IdleLevel = pSimplePWMChannelCfg->IdleLevel;
1887 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1888 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1889 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1890 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1891
1892 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1893 {
1894 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1895 }
1896 else
1897 {
1898 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1899 }
1900 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
1901
1902 HRTIM_OutputConfig(hhrtim,
1903 TimerIdx,
1904 PWMChannel,
1905 &OutputCfg);
1906
1907 /* Enable the registers preload mechanism */
1908 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
1909 hrtim_timcr |= HRTIM_TIMCR_PREEN;
1910 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
1911
1912 hhrtim->State = HAL_HRTIM_STATE_READY;
1913
1914 /* Process Unlocked */
1915 __HAL_UNLOCK(hhrtim);
1916
1917 return HAL_OK;
1918 }
1919
1920 /**
1921 * @brief Starts the PWM output signal generation on the designed timer output
1922 * @param hhrtim pointer to HAL HRTIM handle
1923 * @param TimerIdx Timer index
1924 * This parameter can be one of the following values:
1925 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1926 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1927 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1928 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1929 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1930 * @param PWMChannel Timer output
1931 * This parameter can be one of the following values:
1932 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1933 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1934 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1935 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1936 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1937 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1938 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1939 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1940 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1941 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1942 * @retval HAL status
1943 */
1944 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
1945 uint32_t TimerIdx,
1946 uint32_t PWMChannel)
1947 {
1948 /* Check the parameters */
1949 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
1950
1951 /* Process Locked */
1952 __HAL_LOCK(hhrtim);
1953
1954 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1955
1956 /* Enable the timer output */
1957 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
1958
1959 /* Enable the timer counter */
1960 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1961
1962 hhrtim->State = HAL_HRTIM_STATE_READY;
1963
1964 /* Process Unlocked */
1965 __HAL_UNLOCK(hhrtim);
1966
1967 return HAL_OK;
1968 }
1969
1970 /**
1971 * @brief Stops the PWM output signal generation on the designed timer output
1972 * @param hhrtim pointer to HAL HRTIM handle
1973 * @param TimerIdx Timer index
1974 * This parameter can be one of the following values:
1975 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1976 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1977 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1978 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1979 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1980 * @param PWMChannel Timer output
1981 * This parameter can be one of the following values:
1982 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1983 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1984 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1985 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1986 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1987 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1988 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1989 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1990 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1991 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1992 * @retval HAL status
1993 */
1994 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
1995 uint32_t TimerIdx,
1996 uint32_t PWMChannel)
1997 {
1998 /* Check the parameters */
1999 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2000
2001 /* Process Locked */
2002 __HAL_LOCK(hhrtim);
2003
2004 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2005
2006 /* Disable the timer output */
2007 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2008
2009 /* Disable the timer counter */
2010 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2011
2012 hhrtim->State = HAL_HRTIM_STATE_READY;
2013
2014 /* Process Unlocked */
2015 __HAL_UNLOCK(hhrtim);
2016
2017 return HAL_OK;
2018 }
2019
2020 /**
2021 * @brief Starts the PWM output signal generation on the designed timer output
2022 * (The compare interrupt is enabled).
2023 * @param hhrtim pointer to HAL HRTIM handle
2024 * @param TimerIdx Timer index
2025 * This parameter can be one of the following values:
2026 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2027 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2028 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2029 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2030 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2031 * @param PWMChannel Timer output
2032 * This parameter can be one of the following values:
2033 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2034 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2035 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2036 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2037 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2038 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2039 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2040 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2041 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2042 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2043 * @retval HAL status
2044 */
2045 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2046 uint32_t TimerIdx,
2047 uint32_t PWMChannel)
2048 {
2049 /* Check the parameters */
2050 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2051
2052 /* Process Locked */
2053 __HAL_LOCK(hhrtim);
2054
2055 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2056
2057 /* Enable the timer output */
2058 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2059
2060 /* Enable the timer interrupt (depends on the PWM output) */
2061 switch (PWMChannel)
2062 {
2063 case HRTIM_OUTPUT_TA1:
2064 case HRTIM_OUTPUT_TB1:
2065 case HRTIM_OUTPUT_TC1:
2066 case HRTIM_OUTPUT_TD1:
2067 case HRTIM_OUTPUT_TE1:
2068 {
2069 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2070 }
2071 break;
2072 case HRTIM_OUTPUT_TA2:
2073 case HRTIM_OUTPUT_TB2:
2074 case HRTIM_OUTPUT_TC2:
2075 case HRTIM_OUTPUT_TD2:
2076 case HRTIM_OUTPUT_TE2:
2077 {
2078 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2079 }
2080 break;
2081 default:
2082 break;
2083 }
2084
2085 /* Enable the timer counter */
2086 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2087
2088 hhrtim->State = HAL_HRTIM_STATE_READY;
2089
2090 /* Process Unlocked */
2091 __HAL_UNLOCK(hhrtim);
2092
2093 return HAL_OK;
2094 }
2095
2096 /**
2097 * @brief Stops the PWM output signal generation on the designed timer output
2098 * (The compare interrupt is disabled).
2099 * @param hhrtim pointer to HAL HRTIM handle
2100 * @param TimerIdx Timer index
2101 * This parameter can be one of the following values:
2102 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2103 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2104 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2105 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2106 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2107 * @param PWMChannel Timer output
2108 * This parameter can be one of the following values:
2109 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2110 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2111 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2112 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2113 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2114 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2115 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2116 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2117 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2118 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2119 * @retval HAL status
2120 */
2121 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2122 uint32_t TimerIdx,
2123 uint32_t PWMChannel)
2124 {
2125 /* Check the parameters */
2126 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2127
2128 /* Process Locked */
2129 __HAL_LOCK(hhrtim);
2130
2131 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2132
2133 /* Disable the timer output */
2134 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2135
2136 /* Disable the timer interrupt (depends on the PWM output) */
2137 switch (PWMChannel)
2138 {
2139 case HRTIM_OUTPUT_TA1:
2140 case HRTIM_OUTPUT_TB1:
2141 case HRTIM_OUTPUT_TC1:
2142 case HRTIM_OUTPUT_TD1:
2143 case HRTIM_OUTPUT_TE1:
2144 {
2145 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2146 }
2147 break;
2148 case HRTIM_OUTPUT_TA2:
2149 case HRTIM_OUTPUT_TB2:
2150 case HRTIM_OUTPUT_TC2:
2151 case HRTIM_OUTPUT_TD2:
2152 case HRTIM_OUTPUT_TE2:
2153 {
2154 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2155 }
2156 break;
2157 default:
2158 break;
2159 }
2160
2161 /* Disable the timer counter */
2162 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2163
2164 hhrtim->State = HAL_HRTIM_STATE_READY;
2165
2166 /* Process Unlocked */
2167 __HAL_UNLOCK(hhrtim);
2168
2169 return HAL_OK;
2170 }
2171
2172 /**
2173 * @brief Starts the PWM output signal generation on the designed timer output
2174 * (The compare DMA request is enabled).
2175 * @param hhrtim pointer to HAL HRTIM handle
2176 * @param TimerIdx Timer index
2177 * This parameter can be one of the following values:
2178 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2179 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2180 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2181 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2182 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2183 * @param PWMChannel Timer output
2184 * This parameter can be one of the following values:
2185 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2186 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2187 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2188 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2189 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2190 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2191 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2192 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2193 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2194 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2195 * @param SrcAddr DMA transfer source address
2196 * @param DestAddr DMA transfer destination address
2197 * @param Length The length of data items (data size) to be transferred
2198 * from source to destination
2199 * @retval HAL status
2200 */
2201 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2202 uint32_t TimerIdx,
2203 uint32_t PWMChannel,
2204 uint32_t SrcAddr,
2205 uint32_t DestAddr,
2206 uint32_t Length)
2207 {
2208 DMA_HandleTypeDef * hdma;
2209
2210 /* Check the parameters */
2211 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2212
2213 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
2214 {
2215 return HAL_BUSY;
2216 }
2217 if((hhrtim->State == HAL_HRTIM_STATE_READY))
2218 {
2219 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2220 {
2221 return HAL_ERROR;
2222 }
2223 else
2224 {
2225 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2226 }
2227 }
2228
2229 /* Process Locked */
2230 __HAL_LOCK(hhrtim);
2231
2232 /* Enable the timer output */
2233 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2234
2235 /* Get the timer DMA handler */
2236 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2237 if (hdma == NULL)
2238 {
2239 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2240
2241 /* Process Unlocked */
2242 __HAL_UNLOCK(hhrtim);
2243
2244 return HAL_ERROR;
2245 }
2246
2247 /* Set the DMA error callback */
2248 hdma->XferErrorCallback = HRTIM_DMAError ;
2249
2250 /* Set the DMA transfer completed callback */
2251 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2252
2253 /* Enable the DMA channel */
2254 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
2255
2256 /* Enable the timer DMA request */
2257 switch (PWMChannel)
2258 {
2259 case HRTIM_OUTPUT_TA1:
2260 case HRTIM_OUTPUT_TB1:
2261 case HRTIM_OUTPUT_TC1:
2262 case HRTIM_OUTPUT_TD1:
2263 case HRTIM_OUTPUT_TE1:
2264 {
2265 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2266 }
2267 break;
2268 case HRTIM_OUTPUT_TA2:
2269 case HRTIM_OUTPUT_TB2:
2270 case HRTIM_OUTPUT_TC2:
2271 case HRTIM_OUTPUT_TD2:
2272 case HRTIM_OUTPUT_TE2:
2273 {
2274 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2275 }
2276 break;
2277 default:
2278 break;
2279 }
2280
2281 /* Enable the timer counter */
2282 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2283
2284 hhrtim->State = HAL_HRTIM_STATE_READY;
2285
2286 /* Process Unlocked */
2287 __HAL_UNLOCK(hhrtim);
2288
2289 return HAL_OK;
2290 }
2291
2292 /**
2293 * @brief Stops the PWM output signal generation on the designed timer output
2294 * (The compare DMA request is disabled).
2295 * @param hhrtim pointer to HAL HRTIM handle
2296 * @param TimerIdx Timer index
2297 * This parameter can be one of the following values:
2298 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2299 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2300 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2301 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2302 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2303 * @param PWMChannel Timer output
2304 * This parameter can be one of the following values:
2305 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2306 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2307 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2308 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2309 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2310 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2311 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2312 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2313 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2314 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2315 * @retval HAL status
2316 */
2317 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2318 uint32_t TimerIdx,
2319 uint32_t PWMChannel)
2320 {
2321 DMA_HandleTypeDef * hdma;
2322
2323 /* Check the parameters */
2324 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2325
2326 /* Process Locked */
2327 __HAL_LOCK(hhrtim);
2328
2329 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2330
2331 /* Disable the timer output */
2332 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2333
2334 /* Get the timer DMA handler */
2335 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2336 if (hdma == NULL)
2337 {
2338 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2339
2340 /* Process Unlocked */
2341 __HAL_UNLOCK(hhrtim);
2342
2343 return HAL_ERROR;
2344 }
2345
2346 /* Disable the DMA */
2347 HAL_DMA_Abort(hdma);
2348
2349 /* Disable the timer DMA request */
2350 switch (PWMChannel)
2351 {
2352 case HRTIM_OUTPUT_TA1:
2353 case HRTIM_OUTPUT_TB1:
2354 case HRTIM_OUTPUT_TC1:
2355 case HRTIM_OUTPUT_TD1:
2356 case HRTIM_OUTPUT_TE1:
2357 {
2358 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2359 }
2360 break;
2361 case HRTIM_OUTPUT_TA2:
2362 case HRTIM_OUTPUT_TB2:
2363 case HRTIM_OUTPUT_TC2:
2364 case HRTIM_OUTPUT_TD2:
2365 case HRTIM_OUTPUT_TE2:
2366 {
2367 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2368 }
2369 break;
2370 default:
2371 break;
2372 }
2373
2374 /* Disable the timer counter */
2375 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2376
2377 hhrtim->State = HAL_HRTIM_STATE_READY;
2378
2379 /* Process Unlocked */
2380 __HAL_UNLOCK(hhrtim);
2381
2382 return HAL_OK;
2383 }
2384
2385 /**
2386 * @}
2387 */
2388
2389 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2390 * @brief Simple input capture functions
2391 @verbatim
2392 ===============================================================================
2393 ##### Simple input capture functions #####
2394 ===============================================================================
2395 [..] This section provides functions allowing to:
2396 (+) Configure simple input capture channel
2397 (+) Start simple input capture
2398 (+) Stop simple input capture
2399 (+) Start simple input capture and enable interrupt
2400 (+) Stop simple input capture and disable interrupt
2401 (+) Start simple input capture and enable DMA transfer
2402 (+) Stop simple input capture and disable DMA transfer
2403 -@- When a HRTIM timer operates in simple input capture mode
2404 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2405 value of the timer counter counter after a transition detected
2406 on a given external event input.
2407 @endverbatim
2408 * @{
2409 */
2410
2411 /**
2412 * @brief Configures a simple capture
2413 * @param hhrtim pointer to HAL HRTIM handle
2414 * @param TimerIdx Timer index
2415 * This parameter can be one of the following values:
2416 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2417 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2418 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2419 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2420 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2421 * @param CaptureChannel Capture unit
2422 * This parameter can be one of the following values:
2423 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2424 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2425 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2426 * @note When the timer operates in simple capture mode the capture is trigerred
2427 * by the designated external event and GPIO input is implicitly used as event source.
2428 * The cature can be triggered by a rising edge, a falling edge or both
2429 * edges on event channel.
2430 * @retval HAL status
2431 */
2432 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2433 uint32_t TimerIdx,
2434 uint32_t CaptureChannel,
2435 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2436 {
2437 HRTIM_EventCfgTypeDef EventCfg;
2438
2439 /* Check parameters */
2440 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2441 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2442 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2443 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2444 pSimpleCaptureChannelCfg->EventPolarity));
2445 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2446 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2447 pSimpleCaptureChannelCfg->EventFilter));
2448
2449 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2450 {
2451 return HAL_BUSY;
2452 }
2453
2454 /* Process Locked */
2455 __HAL_LOCK(hhrtim);
2456
2457 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2458
2459 /* Configure external event channel */
2460 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2461 EventCfg.Filter = pSimpleCaptureChannelCfg->EventFilter;
2462 EventCfg.Polarity = pSimpleCaptureChannelCfg->EventPolarity;
2463 EventCfg.Sensitivity = pSimpleCaptureChannelCfg->EventSensitivity;
2464 EventCfg.Source = HRTIM_EVENTSRC_1;
2465
2466 HRTIM_EventConfig(hhrtim,
2467 pSimpleCaptureChannelCfg->Event,
2468 &EventCfg);
2469
2470 /* Memorize capture trigger (will be configured when the capture is started */
2471 HRTIM_CaptureUnitConfig(hhrtim,
2472 TimerIdx,
2473 CaptureChannel,
2474 pSimpleCaptureChannelCfg->Event);
2475
2476 hhrtim->State = HAL_HRTIM_STATE_READY;
2477
2478 /* Process Unlocked */
2479 __HAL_UNLOCK(hhrtim);
2480
2481 return HAL_OK;
2482 }
2483
2484 /**
2485 * @brief Enables a simple capture on the designed capture unit
2486 * @param hhrtim pointer to HAL HRTIM handle
2487 * @param TimerIdx Timer index
2488 * This parameter can be one of the following values:
2489 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2490 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2491 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2492 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2493 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2494 * @param CaptureChannel Timer output
2495 * This parameter can be one of the following values:
2496 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2497 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2498 * @retval HAL status
2499 * @note The external event triggering the capture is available for all timing
2500 * units. It can be used directly and is active as soon as the timing
2501 * unit counter is enabled.
2502 */
2503 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2504 uint32_t TimerIdx,
2505 uint32_t CaptureChannel)
2506 {
2507 /* Check the parameters */
2508 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2509 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2510
2511 /* Process Locked */
2512 __HAL_LOCK(hhrtim);
2513
2514 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2515
2516 /* Set the capture unit trigger */
2517 switch (CaptureChannel)
2518 {
2519 case HRTIM_CAPTUREUNIT_1:
2520 {
2521 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2522 }
2523 break;
2524 case HRTIM_CAPTUREUNIT_2:
2525 {
2526 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2527 }
2528 break;
2529 default:
2530 break;
2531 }
2532
2533 /* Enable the timer counter */
2534 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2535
2536 hhrtim->State = HAL_HRTIM_STATE_READY;
2537
2538 /* Process Unlocked */
2539 __HAL_UNLOCK(hhrtim);
2540
2541 return HAL_OK;
2542 }
2543
2544 /**
2545 * @brief Disables a simple capture on the designed capture unit
2546 * @param hhrtim pointer to HAL HRTIM handle
2547 * @param TimerIdx Timer index
2548 * This parameter can be one of the following values:
2549 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2550 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2551 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2552 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2553 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2554 * @param CaptureChannel Timer output
2555 * This parameter can be one of the following values:
2556 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2557 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2558 * @retval HAL status
2559 */
2560 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2561 uint32_t TimerIdx,
2562 uint32_t CaptureChannel)
2563 {
2564 /* Check the parameters */
2565 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2566 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2567
2568 /* Process Locked */
2569 __HAL_LOCK(hhrtim);
2570
2571 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2572
2573 /* Set the capture unit trigger */
2574 switch (CaptureChannel)
2575 {
2576 case HRTIM_CAPTUREUNIT_1:
2577 {
2578 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2579 }
2580 break;
2581 case HRTIM_CAPTUREUNIT_2:
2582 {
2583 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2584 }
2585 break;
2586 default:
2587 break;
2588 }
2589
2590 /* Disable the timer counter */
2591 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2592 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2593 {
2594 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2595 }
2596
2597 hhrtim->State = HAL_HRTIM_STATE_READY;
2598
2599 /* Process Unlocked */
2600 __HAL_UNLOCK(hhrtim);
2601
2602 return HAL_OK;
2603 }
2604
2605 /**
2606 * @brief Enables a simple capture on the designed capture unit
2607 * (Capture interrupt is enabled).
2608 * @param hhrtim pointer to HAL HRTIM handle
2609 * @param TimerIdx Timer index
2610 * This parameter can be one of the following values:
2611 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2612 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2613 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2614 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2615 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2616 * @param CaptureChannel Timer output
2617 * This parameter can be one of the following values:
2618 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2619 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2620 * @retval HAL status
2621 */
2622 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2623 uint32_t TimerIdx,
2624 uint32_t CaptureChannel)
2625 {
2626 /* Check the parameters */
2627 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2628 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2629
2630 /* Process Locked */
2631 __HAL_LOCK(hhrtim);
2632
2633 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2634
2635 /* Set the capture unit trigger */
2636 switch (CaptureChannel)
2637 {
2638 case HRTIM_CAPTUREUNIT_1:
2639 {
2640 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2641
2642 /* Enable the capture unit 1 interrupt */
2643 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2644 }
2645 break;
2646 case HRTIM_CAPTUREUNIT_2:
2647 {
2648 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2649
2650 /* Enable the capture unit 2 interrupt */
2651 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2652 }
2653 break;
2654 default:
2655 break;
2656 }
2657
2658 /* Enable the timer counter */
2659 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2660
2661 hhrtim->State = HAL_HRTIM_STATE_READY;
2662
2663 /* Process Unlocked */
2664 __HAL_UNLOCK(hhrtim);
2665
2666 return HAL_OK;
2667 }
2668
2669 /**
2670 * @brief Disables a simple capture on the designed capture unit
2671 * (Capture interrupt is disabled).
2672 * @param hhrtim pointer to HAL HRTIM handle
2673 * @param TimerIdx Timer index
2674 * This parameter can be one of the following values:
2675 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2676 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2677 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2678 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2679 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2680 * @param CaptureChannel Timer output
2681 * This parameter can be one of the following values:
2682 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2683 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2684 * @retval HAL status
2685 */
2686 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
2687 uint32_t TimerIdx,
2688 uint32_t CaptureChannel)
2689 {
2690 /* Check the parameters */
2691 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2692 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2693
2694 /* Process Locked */
2695 __HAL_LOCK(hhrtim);
2696
2697 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2698
2699 /* Set the capture unit trigger */
2700 switch (CaptureChannel)
2701 {
2702 case HRTIM_CAPTUREUNIT_1:
2703 {
2704 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2705
2706 /* Disable the capture unit 1 interrupt */
2707 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2708 }
2709 break;
2710 case HRTIM_CAPTUREUNIT_2:
2711 {
2712 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2713
2714 /* Disable the capture unit 2 interrupt */
2715 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2716 }
2717 break;
2718 default:
2719 break;
2720 }
2721
2722 /* Disable the timer counter */
2723 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2724 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2725 {
2726 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2727 }
2728
2729 hhrtim->State = HAL_HRTIM_STATE_READY;
2730
2731 /* Process Unlocked */
2732 __HAL_UNLOCK(hhrtim);
2733
2734 return HAL_OK;
2735 }
2736
2737 /**
2738 * @brief Enables a simple capture on the designed capture unit
2739 * (Capture DMA request is enabled).
2740 * @param hhrtim pointer to HAL HRTIM handle
2741 * @param TimerIdx Timer index
2742 * This parameter can be one of the following values:
2743 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2744 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2745 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2746 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2747 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2748 * @param CaptureChannel Timer output
2749 * This parameter can be one of the following values:
2750 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2751 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2752 * @param SrcAddr DMA transfer source address
2753 * @param DestAddr DMA transfer destination address
2754 * @param Length The length of data items (data size) to be transferred
2755 * from source to destination
2756 * @retval HAL status
2757 */
2758 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2759 uint32_t TimerIdx,
2760 uint32_t CaptureChannel,
2761 uint32_t SrcAddr,
2762 uint32_t DestAddr,
2763 uint32_t Length)
2764 {
2765 DMA_HandleTypeDef * hdma;
2766
2767 /* Check the parameters */
2768 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2769 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2770
2771 /* Process Locked */
2772 __HAL_LOCK(hhrtim);
2773
2774 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2775
2776 /* Get the timer DMA handler */
2777 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2778 if (hdma == NULL)
2779 {
2780 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2781
2782 /* Process Unlocked */
2783 __HAL_UNLOCK(hhrtim);
2784
2785 return HAL_ERROR;
2786 }
2787
2788 /* Set the DMA error callback */
2789 hdma->XferErrorCallback = HRTIM_DMAError ;
2790
2791 /* Set the DMA transfer completed callback */
2792 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2793
2794 /* Enable the DMA channel */
2795 HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length);
2796
2797 switch (CaptureChannel)
2798 {
2799 case HRTIM_CAPTUREUNIT_1:
2800 {
2801 /* Set the capture unit trigger */
2802 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2803
2804 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2805 }
2806 break;
2807 case HRTIM_CAPTUREUNIT_2:
2808 {
2809 /* Set the capture unit trigger */
2810 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2811
2812 /* Enable the timer DMA request */
2813 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2814 }
2815 break;
2816 default:
2817 break;
2818 }
2819
2820 /* Enable the timer counter */
2821 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2822
2823 hhrtim->State = HAL_HRTIM_STATE_READY;
2824
2825 /* Process Unlocked */
2826 __HAL_UNLOCK(hhrtim);
2827
2828 return HAL_OK;
2829 }
2830
2831 /**
2832 * @brief Disables a simple capture on the designed capture unit
2833 * (Capture DMA request is disabled).
2834 * @param hhrtim pointer to HAL HRTIM handle
2835 * @param TimerIdx Timer index
2836 * This parameter can be one of the following values:
2837 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2838 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2839 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2840 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2841 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2842 * @param CaptureChannel Timer output
2843 * This parameter can be one of the following values:
2844 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2845 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2846 * @retval HAL status
2847 */
2848 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2849 uint32_t TimerIdx,
2850 uint32_t CaptureChannel)
2851 {
2852 DMA_HandleTypeDef * hdma;
2853
2854 /* Check the parameters */
2855 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2856 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2857
2858 /* Process Locked */
2859 __HAL_LOCK(hhrtim);
2860
2861 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2862
2863 /* Get the timer DMA handler */
2864 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2865 if (hdma == NULL)
2866 {
2867 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2868
2869 /* Process Unlocked */
2870 __HAL_UNLOCK(hhrtim);
2871
2872 return HAL_ERROR;
2873 }
2874
2875 /* Disable the DMA */
2876 HAL_DMA_Abort(hdma);
2877
2878 switch (CaptureChannel)
2879 {
2880 case HRTIM_CAPTUREUNIT_1:
2881 {
2882 /* Reset the capture unit trigger */
2883 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2884
2885 /* Disable the capture unit 1 DMA request */
2886 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
2887 }
2888 break;
2889 case HRTIM_CAPTUREUNIT_2:
2890 {
2891 /* Reset the capture unit trigger */
2892 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2893
2894 /* Disable the capture unit 2 DMA request */
2895 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
2896 }
2897 break;
2898 default:
2899 break;
2900 }
2901
2902 /* Disable the timer counter */
2903 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
2904 (hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
2905 {
2906 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2907 }
2908
2909 hhrtim->State = HAL_HRTIM_STATE_READY;
2910
2911 /* Process Unlocked */
2912 __HAL_UNLOCK(hhrtim);
2913
2914 return HAL_OK;
2915 }
2916
2917 /**
2918 * @}
2919 */
2920
2921 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
2922 * @brief Simple one pulse functions
2923 @verbatim
2924 ===============================================================================
2925 ##### Simple one pulse functions #####
2926 ===============================================================================
2927 [..] This section provides functions allowing to:
2928 (+) Configure one pulse channel
2929 (+) Start one pulse generation
2930 (+) Stop one pulse generation
2931 (+) Start one pulse generation and enable interrupt
2932 (+) Stop one pulse generation and disable interrupt
2933 -@- When a HRTIM timer operates in simple one pulse mode
2934 the timer counter is started in response to transition detected
2935 on a given external event input to generate a pulse with a
2936 programmable length after a programmable delay.
2937 @endverbatim
2938 * @{
2939 */
2940
2941 /**
2942 * @brief Configures an output simple one pulse mode
2943 * @param hhrtim pointer to HAL HRTIM handle
2944 * @param TimerIdx Timer index
2945 * This parameter can be one of the following values:
2946 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2947 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2948 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2949 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2950 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2951 * @param OnePulseChannel Timer output
2952 * This parameter can be one of the following values:
2953 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2954 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2955 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2956 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2957 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2958 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2959 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2960 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2961 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2962 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2963 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
2964 * @note When the timer operates in simple one pulse mode:
2965 * the timer counter is implicitly started by the reset event,
2966 * the reset of the timer counter is triggered by the designated external event
2967 * GPIO input is implicitly used as event source,
2968 * Output 1 is implicitly controlled by the compare unit 1,
2969 * Output 2 is implicitly controlled by the compare unit 2.
2970 * Output Set/Reset crossbar is set as follows:
2971 * Output 1: SETx1R = CMP1, RSTx1R = PER
2972 * Output 2: SETx2R = CMP2, RST2R = PER
2973 * @retval HAL status
2974 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
2975 * outputs, the reset event related configuration data provided in the
2976 * second call will override the reset event related configuration data
2977 * provided in the first call.
2978 */
2979 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2980 uint32_t TimerIdx,
2981 uint32_t OnePulseChannel,
2982 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
2983 {
2984 uint32_t CompareUnit = 0xFFFFFFFFU;
2985 HRTIM_CompareCfgTypeDef CompareCfg;
2986 HRTIM_OutputCfgTypeDef OutputCfg;
2987 HRTIM_EventCfgTypeDef EventCfg;
2988
2989 /* Check parameters */
2990 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
2991 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
2992 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
2993 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
2994 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
2995 pSimpleOnePulseChannelCfg->EventPolarity));
2996 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
2997 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
2998 pSimpleOnePulseChannelCfg->EventFilter));
2999
3000 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3001 {
3002 return HAL_BUSY;
3003 }
3004
3005 /* Process Locked */
3006 __HAL_LOCK(hhrtim);
3007
3008 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3009
3010 /* Configure timer compare unit */
3011 switch (OnePulseChannel)
3012 {
3013 case HRTIM_OUTPUT_TA1:
3014 case HRTIM_OUTPUT_TB1:
3015 case HRTIM_OUTPUT_TC1:
3016 case HRTIM_OUTPUT_TD1:
3017 case HRTIM_OUTPUT_TE1:
3018 {
3019 CompareUnit = HRTIM_COMPAREUNIT_1;
3020 }
3021 break;
3022 case HRTIM_OUTPUT_TA2:
3023 case HRTIM_OUTPUT_TB2:
3024 case HRTIM_OUTPUT_TC2:
3025 case HRTIM_OUTPUT_TD2:
3026 case HRTIM_OUTPUT_TE2:
3027 {
3028 CompareUnit = HRTIM_COMPAREUNIT_2;
3029 }
3030 break;
3031 default:
3032 break;
3033 }
3034
3035 CompareCfg.CompareValue = pSimpleOnePulseChannelCfg->Pulse;
3036 CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
3037 CompareCfg.AutoDelayedTimeout = 0U;
3038
3039 HRTIM_CompareUnitConfig(hhrtim,
3040 TimerIdx,
3041 CompareUnit,
3042 &CompareCfg);
3043
3044 /* Configure timer output */
3045 OutputCfg.Polarity = pSimpleOnePulseChannelCfg->OutputPolarity;
3046 OutputCfg.IdleLevel = pSimpleOnePulseChannelCfg->OutputIdleLevel;
3047 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3048 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3049 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3050 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3051
3052 if (CompareUnit == HRTIM_COMPAREUNIT_1)
3053 {
3054 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3055 }
3056 else
3057 {
3058 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3059 }
3060 OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
3061
3062 HRTIM_OutputConfig(hhrtim,
3063 TimerIdx,
3064 OnePulseChannel,
3065 &OutputCfg);
3066
3067 /* Configure external event channel */
3068 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3069 EventCfg.Filter = pSimpleOnePulseChannelCfg->EventFilter;
3070 EventCfg.Polarity = pSimpleOnePulseChannelCfg->EventPolarity;
3071 EventCfg.Sensitivity = pSimpleOnePulseChannelCfg->EventSensitivity;
3072 EventCfg.Source = HRTIM_EVENTSRC_1;
3073
3074 HRTIM_EventConfig(hhrtim,
3075 pSimpleOnePulseChannelCfg->Event,
3076 &EventCfg);
3077
3078 /* Configure the timer reset register */
3079 HRTIM_TIM_ResetConfig(hhrtim,
3080 TimerIdx,
3081 pSimpleOnePulseChannelCfg->Event);
3082
3083 hhrtim->State = HAL_HRTIM_STATE_READY;
3084
3085 /* Process Unlocked */
3086 __HAL_UNLOCK(hhrtim);
3087
3088 return HAL_OK;
3089 }
3090
3091 /**
3092 * @brief Enables the simple one pulse signal generation on the designed output
3093 * @param hhrtim pointer to HAL HRTIM handle
3094 * @param TimerIdx Timer index
3095 * This parameter can be one of the following values:
3096 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3097 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3098 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3099 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3100 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3101 * @param OnePulseChannel Timer output
3102 * This parameter can be one of the following values:
3103 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3104 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3105 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3106 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3107 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3108 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3109 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3110 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3111 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3112 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3113 * @retval HAL status
3114 */
3115 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3116 uint32_t TimerIdx,
3117 uint32_t OnePulseChannel)
3118 {
3119 /* Check the parameters */
3120 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3121
3122 /* Process Locked */
3123 __HAL_LOCK(hhrtim);
3124
3125 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3126
3127 /* Enable the timer output */
3128 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3129
3130 /* Enable the timer counter */
3131 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3132
3133 hhrtim->State = HAL_HRTIM_STATE_READY;
3134
3135 /* Process Unlocked */
3136 __HAL_UNLOCK(hhrtim);
3137
3138 return HAL_OK;
3139 }
3140
3141 /**
3142 * @brief Disables the simple one pulse signal generation on the designed output
3143 * @param hhrtim pointer to HAL HRTIM handle
3144 * @param TimerIdx Timer index
3145 * This parameter can be one of the following values:
3146 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3147 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3148 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3149 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3150 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3151 * @param OnePulseChannel Timer output
3152 * This parameter can be one of the following values:
3153 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3154 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3155 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3156 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3157 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3158 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3159 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3160 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3161 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3162 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3163 * @retval HAL status
3164 */
3165 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3166 uint32_t TimerIdx,
3167 uint32_t OnePulseChannel)
3168 {
3169 /* Check the parameters */
3170 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3171
3172 /* Process Locked */
3173 __HAL_LOCK(hhrtim);
3174
3175 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3176
3177 /* Disable the timer output */
3178 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3179
3180 /* Disable the timer counter */
3181 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3182
3183 hhrtim->State = HAL_HRTIM_STATE_READY;
3184
3185 /* Process Unlocked */
3186 __HAL_UNLOCK(hhrtim);
3187
3188 return HAL_OK;
3189 }
3190
3191 /**
3192 * @brief Enables the simple one pulse signal generation on the designed output
3193 * (The compare interrupt is enabled (pulse start)).
3194 * @param hhrtim pointer to HAL HRTIM handle
3195 * @param TimerIdx Timer index
3196 * This parameter can be one of the following values:
3197 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3198 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3199 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3200 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3201 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3202 * @param OnePulseChannel Timer output
3203 * This parameter can be one of the following values:
3204 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3205 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3206 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3207 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3208 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3209 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3210 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3211 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3212 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3213 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3214 * @retval HAL status
3215 */
3216 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3217 uint32_t TimerIdx,
3218 uint32_t OnePulseChannel)
3219 {
3220 /* Check the parameters */
3221 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3222
3223 /* Process Locked */
3224 __HAL_LOCK(hhrtim);
3225
3226 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3227
3228 /* Enable the timer output */
3229 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3230
3231 /* Enable the timer interrupt (depends on the OnePulse output) */
3232 switch (OnePulseChannel)
3233 {
3234 case HRTIM_OUTPUT_TA1:
3235 case HRTIM_OUTPUT_TB1:
3236 case HRTIM_OUTPUT_TC1:
3237 case HRTIM_OUTPUT_TD1:
3238 case HRTIM_OUTPUT_TE1:
3239 {
3240 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3241 }
3242 break;
3243 case HRTIM_OUTPUT_TA2:
3244 case HRTIM_OUTPUT_TB2:
3245 case HRTIM_OUTPUT_TC2:
3246 case HRTIM_OUTPUT_TD2:
3247 case HRTIM_OUTPUT_TE2:
3248 {
3249 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3250 }
3251 break;
3252 default:
3253 break;
3254 }
3255
3256 /* Enable the timer counter */
3257 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3258
3259 hhrtim->State = HAL_HRTIM_STATE_READY;
3260
3261 /* Process Unlocked */
3262 __HAL_UNLOCK(hhrtim);
3263
3264 return HAL_OK;
3265 }
3266
3267 /**
3268 * @brief Disables the simple one pulse signal generation on the designed output
3269 * (The compare interrupt is disabled).
3270 * @param hhrtim pointer to HAL HRTIM handle
3271 * @param TimerIdx Timer index
3272 * This parameter can be one of the following values:
3273 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3274 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3275 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3276 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3277 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3278 * @param OnePulseChannel Timer output
3279 * This parameter can be one of the following values:
3280 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3281 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3282 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3283 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3284 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3285 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3286 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3287 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3288 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3289 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3290 * @retval HAL status
3291 */
3292 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3293 uint32_t TimerIdx,
3294 uint32_t OnePulseChannel)
3295 {
3296 /* Check the parameters */
3297 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3298
3299 /* Process Locked */
3300 __HAL_LOCK(hhrtim);
3301
3302 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3303
3304 /* Disable the timer output */
3305 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3306
3307 /* Disable the timer interrupt (depends on the OnePulse output) */
3308 switch (OnePulseChannel)
3309 {
3310 case HRTIM_OUTPUT_TA1:
3311 case HRTIM_OUTPUT_TB1:
3312 case HRTIM_OUTPUT_TC1:
3313 case HRTIM_OUTPUT_TD1:
3314 case HRTIM_OUTPUT_TE1:
3315 {
3316 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3317 }
3318 break;
3319 case HRTIM_OUTPUT_TA2:
3320 case HRTIM_OUTPUT_TB2:
3321 case HRTIM_OUTPUT_TC2:
3322 case HRTIM_OUTPUT_TD2:
3323 case HRTIM_OUTPUT_TE2:
3324 {
3325 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3326 }
3327 break;
3328 default:
3329 break;
3330 }
3331
3332 /* Disable the timer counter */
3333 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3334
3335 hhrtim->State = HAL_HRTIM_STATE_READY;
3336
3337 /* Process Unlocked */
3338 __HAL_UNLOCK(hhrtim);
3339
3340 return HAL_OK;
3341 }
3342
3343 /**
3344 * @}
3345 */
3346
3347 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3348 * @brief HRTIM configuration functions
3349 @verbatim
3350 ===============================================================================
3351 ##### HRTIM configuration functions #####
3352 ===============================================================================
3353 [..] This section provides functions allowing to configure the HRTIM
3354 resources shared by all the HRTIM timers operating in waveform mode:
3355 (+) Configure the burst mode controller
3356 (+) Configure an external event conditionning
3357 (+) Configure the external events sampling clock
3358 (+) Configure a fault conditionning
3359 (+) Enable or disable fault inputs
3360 (+) Configure the faults sampling clock
3361 (+) Configure an ADC trigger
3362
3363 @endverbatim
3364 * @{
3365 */
3366
3367 /**
3368 * @brief Configures the burst mode feature of the HRTIM
3369 * @param hhrtim pointer to HAL HRTIM handle
3370 * @param pBurstModeCfg pointer to the burst mode configuration structure
3371 * @retval HAL status
3372 * @note This function must be called before starting the burst mode
3373 * controller
3374 */
3375 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3376 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3377 {
3378 uint32_t hrtim_bmcr;
3379
3380 /* Check parameters */
3381 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3382 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3383 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3384 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3385 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3386
3387 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3388 {
3389 return HAL_BUSY;
3390 }
3391
3392 /* Process Locked */
3393 __HAL_LOCK(hhrtim);
3394
3395 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3396
3397 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3398
3399 /* Set the burst mode operating mode */
3400 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3401 hrtim_bmcr |= pBurstModeCfg->Mode;
3402
3403 /* Set the burst mode clock source */
3404 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3405 hrtim_bmcr |= pBurstModeCfg->ClockSource;
3406
3407 /* Set the burst mode prescaler */
3408 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3409 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3410
3411 /* Enable/disable burst mode registers preload */
3412 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3413 hrtim_bmcr |= pBurstModeCfg->PreloadEnable;
3414
3415 /* Set the burst mode trigger */
3416 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3417
3418 /* Set the burst mode compare value */
3419 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3420
3421 /* Set the burst mode period */
3422 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3423
3424 /* Update the HRTIM registers */
3425 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3426
3427 hhrtim->State = HAL_HRTIM_STATE_READY;
3428
3429 /* Process Unlocked */
3430 __HAL_UNLOCK(hhrtim);
3431
3432 return HAL_OK;
3433 }
3434
3435 /**
3436 * @brief Configures the conditioning of an external event
3437 * @param hhrtim pointer to HAL HRTIM handle
3438 * @param Event external event to configure
3439 * This parameter can be one of the following values:
3440 * @arg HRTIM_EVENT_1: External event 1
3441 * @arg HRTIM_EVENT_2: External event 2
3442 * @arg HRTIM_EVENT_3: External event 3
3443 * @arg HRTIM_EVENT_4: External event 4
3444 * @arg HRTIM_EVENT_5: External event 5
3445 * @arg HRTIM_EVENT_6: External event 6
3446 * @arg HRTIM_EVENT_7: External event 7
3447 * @arg HRTIM_EVENT_8: External event 8
3448 * @arg HRTIM_EVENT_9: External event 9
3449 * @arg HRTIM_EVENT_10: External event 10
3450 * @param pEventCfg pointer to the event conditioning configuration structure
3451 * @note This function must be called before starting the timer
3452 * @retval HAL status
3453 */
3454 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3455 uint32_t Event,
3456 HRTIM_EventCfgTypeDef* pEventCfg)
3457 {
3458 /* Check parameters */
3459 assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
3460 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3461 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3462 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3463 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3464
3465 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3466 {
3467 return HAL_BUSY;
3468 }
3469
3470 /* Process Locked */
3471 __HAL_LOCK(hhrtim);
3472
3473 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3474
3475 /* Configure the event channel */
3476 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3477
3478 hhrtim->State = HAL_HRTIM_STATE_READY;
3479
3480 /* Process Unlocked */
3481 __HAL_UNLOCK(hhrtim);
3482
3483 return HAL_OK;
3484 }
3485
3486 /**
3487 * @brief Configures the external event conditioning block prescaler
3488 * @param hhrtim pointer to HAL HRTIM handle
3489 * @param Prescaler Prescaler value
3490 * This parameter can be one of the following values:
3491 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3492 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3493 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3494 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3495 * @note This function must be called before starting the timer
3496 * @retval HAL status
3497 */
3498 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3499 uint32_t Prescaler)
3500 {
3501 uint32_t hrtim_eecr3;
3502
3503 /* Check parameters */
3504 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3505
3506 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3507 {
3508 return HAL_BUSY;
3509 }
3510
3511 /* Process Locked */
3512 __HAL_LOCK(hhrtim);
3513
3514 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3515
3516 /* Set the external event prescaler */
3517 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
3518 hrtim_eecr3 &= ~(HRTIM_EECR3_EEVSD);
3519 hrtim_eecr3 |= Prescaler;
3520
3521 /* Update the HRTIM registers */
3522 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
3523
3524 hhrtim->State = HAL_HRTIM_STATE_READY;
3525
3526 /* Process Unlocked */
3527 __HAL_UNLOCK(hhrtim);
3528
3529 return HAL_OK;
3530 }
3531
3532 /**
3533 * @brief Configures the conditioning of fault input
3534 * @param hhrtim pointer to HAL HRTIM handle
3535 * @param Fault fault input to configure
3536 * This parameter can be one of the following values:
3537 * @arg HRTIM_FAULT_1: Fault input 1
3538 * @arg HRTIM_FAULT_2: Fault input 2
3539 * @arg HRTIM_FAULT_3: Fault input 3
3540 * @arg HRTIM_FAULT_4: Fault input 4
3541 * @arg HRTIM_FAULT_5: Fault input 5
3542 * @param pFaultCfg pointer to the fault conditioning configuration structure
3543 * @note This function must be called before starting the timer and before
3544 * enabling faults inputs
3545 * @retval HAL status
3546 */
3547 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3548 uint32_t Fault,
3549 HRTIM_FaultCfgTypeDef* pFaultCfg)
3550 {
3551 uint32_t hrtim_fltinr1;
3552 uint32_t hrtim_fltinr2;
3553
3554 /* Check parameters */
3555 assert_param(IS_HRTIM_FAULT(Fault));
3556 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3557 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3558 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3559 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3560
3561 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3562 {
3563 return HAL_BUSY;
3564 }
3565
3566 /* Process Locked */
3567 __HAL_LOCK(hhrtim);
3568
3569 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3570
3571 /* Configure fault channel */
3572 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3573 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3574
3575 switch (Fault)
3576 {
3577 case HRTIM_FAULT_1:
3578 {
3579 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
3580 hrtim_fltinr1 |= pFaultCfg->Polarity;
3581 hrtim_fltinr1 |= pFaultCfg->Source;
3582 hrtim_fltinr1 |= pFaultCfg->Filter;
3583 hrtim_fltinr1 |= pFaultCfg->Lock;
3584 }
3585 break;
3586 case HRTIM_FAULT_2:
3587 {
3588 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
3589 hrtim_fltinr1 |= (pFaultCfg->Polarity << 8U);
3590 hrtim_fltinr1 |= (pFaultCfg->Source << 8U);
3591 hrtim_fltinr1 |= (pFaultCfg->Filter << 8U);
3592 hrtim_fltinr1 |= (pFaultCfg->Lock << 8U);
3593 }
3594 break;
3595 case HRTIM_FAULT_3:
3596 {
3597 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
3598 hrtim_fltinr1 |= (pFaultCfg->Polarity << 16U);
3599 hrtim_fltinr1 |= (pFaultCfg->Source << 16U);
3600 hrtim_fltinr1 |= (pFaultCfg->Filter << 16U);
3601 hrtim_fltinr1 |= (pFaultCfg->Lock << 16U);
3602 }
3603 break;
3604 case HRTIM_FAULT_4:
3605 {
3606 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
3607 hrtim_fltinr1 |= (pFaultCfg->Polarity << 24U);
3608 hrtim_fltinr1 |= (pFaultCfg->Source << 24U);
3609 hrtim_fltinr1 |= (pFaultCfg->Filter << 24U);
3610 hrtim_fltinr1 |= (pFaultCfg->Lock << 24U);
3611 }
3612 break;
3613 case HRTIM_FAULT_5:
3614 {
3615 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
3616 hrtim_fltinr2 |= pFaultCfg->Polarity;
3617 hrtim_fltinr2 |= pFaultCfg->Source;
3618 hrtim_fltinr2 |= pFaultCfg->Filter;
3619 hrtim_fltinr2 |= pFaultCfg->Lock;
3620 }
3621 break;
3622 default:
3623 break;
3624 }
3625
3626 /* Update the HRTIM registers */
3627 hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
3628 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3629
3630 hhrtim->State = HAL_HRTIM_STATE_READY;
3631
3632 /* Process Unlocked */
3633 __HAL_UNLOCK(hhrtim);
3634
3635 return HAL_OK;
3636 }
3637
3638 /**
3639 * @brief Configures the fault conditioning block prescaler
3640 * @param hhrtim pointer to HAL HRTIM handle
3641 * @param Prescaler Prescaler value
3642 * This parameter can be one of the following values:
3643 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
3644 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
3645 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
3646 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
3647 * @retval HAL status
3648 * @note This function must be called before starting the timer and before
3649 * enabling faults inputs
3650 */
3651 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3652 uint32_t Prescaler)
3653 {
3654 uint32_t hrtim_fltinr2;
3655
3656 /* Check parameters */
3657 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
3658
3659 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3660 {
3661 return HAL_BUSY;
3662 }
3663
3664 /* Process Locked */
3665 __HAL_LOCK(hhrtim);
3666
3667 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3668
3669 /* Set the external event prescaler */
3670 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3671 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
3672 hrtim_fltinr2 |= Prescaler;
3673
3674 /* Update the HRTIM registers */
3675 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3676
3677 hhrtim->State = HAL_HRTIM_STATE_READY;
3678
3679 /* Process Unlocked */
3680 __HAL_UNLOCK(hhrtim);
3681
3682 return HAL_OK;
3683 }
3684
3685 /**
3686 * @brief Enables or disables the HRTIMx Fault mode.
3687 * @param hhrtim pointer to HAL HRTIM handle
3688 * @param Faults fault input(s) to enable or disable
3689 * This parameter can be any combination of the following values:
3690 * @arg HRTIM_FAULT_1: Fault input 1
3691 * @arg HRTIM_FAULT_2: Fault input 2
3692 * @arg HRTIM_FAULT_3: Fault input 3
3693 * @arg HRTIM_FAULT_4: Fault input 4
3694 * @arg HRTIM_FAULT_5: Fault input 5
3695 * @param Enable Fault(s) enabling
3696 * This parameter can be one of the following values:
3697 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
3698 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
3699 * @retval None
3700 */
3701 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
3702 uint32_t Faults,
3703 uint32_t Enable)
3704 {
3705 uint32_t hrtim_fltinr1;
3706 uint32_t hrtim_fltinr2;
3707
3708 /* Check parameters */
3709 assert_param(IS_HRTIM_FAULT(Faults));
3710 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
3711
3712 /* Configure fault channel */
3713 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3714 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3715
3716 if ((Faults & HRTIM_FAULT_1) != RESET)
3717 {
3718 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
3719 hrtim_fltinr1 |= Enable;
3720 }
3721 if ((Faults & HRTIM_FAULT_2) != RESET)
3722 {
3723 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
3724 hrtim_fltinr1 |= (Enable << 8U);
3725 }
3726 if ((Faults & HRTIM_FAULT_3) != RESET)
3727 {
3728 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
3729 hrtim_fltinr1 |= (Enable << 16U);
3730 }
3731 if ((Faults & HRTIM_FAULT_4) != RESET)
3732 {
3733 hrtim_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
3734 hrtim_fltinr1 |= (Enable << 24U);
3735 }
3736 if ((Faults & HRTIM_FAULT_5) != RESET)
3737 {
3738 hrtim_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
3739 hrtim_fltinr2 |= Enable;
3740 }
3741
3742 /* Update the HRTIMx registers */
3743 hhrtim->Instance->sCommonRegs.FLTINR1 = hrtim_fltinr1;
3744 hhrtim->Instance->sCommonRegs.FLTINR2 = hrtim_fltinr2;
3745 }
3746
3747 /**
3748 * @brief Configures both the ADC trigger register update source and the ADC
3749 * trigger source.
3750 * @param hhrtim pointer to HAL HRTIM handle
3751 * @param ADCTrigger ADC trigger to configure
3752 * This parameter can be one of the following values:
3753 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
3754 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
3755 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
3756 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
3757 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
3758 * @retval HAL status
3759 * @note This function must be called before starting the timer
3760 */
3761 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
3762 uint32_t ADCTrigger,
3763 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
3764 {
3765 uint32_t hrtim_cr1;
3766
3767 /* Check parameters */
3768 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
3769 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
3770
3771 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3772 {
3773 return HAL_BUSY;
3774 }
3775
3776 /* Process Locked */
3777 __HAL_LOCK(hhrtim);
3778
3779 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3780
3781 /* Set the ADC trigger update source */
3782 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
3783
3784 switch (ADCTrigger)
3785 {
3786 case HRTIM_ADCTRIGGER_1:
3787 {
3788 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
3789 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
3790
3791 /* Set the ADC trigger 1 source */
3792 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
3793 }
3794 break;
3795 case HRTIM_ADCTRIGGER_2:
3796 {
3797 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
3798 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
3799
3800 /* Set the ADC trigger 2 source */
3801 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
3802 }
3803 break;
3804 case HRTIM_ADCTRIGGER_3:
3805 {
3806 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
3807 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
3808
3809 /* Set the ADC trigger 3 source */
3810 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
3811 }
3812 break;
3813 case HRTIM_ADCTRIGGER_4:
3814 {
3815 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
3816 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
3817
3818 /* Set the ADC trigger 4 source */
3819 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
3820 }
3821 break;
3822 default:
3823 break;
3824 }
3825
3826 /* Update the HRTIM registers */
3827 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
3828
3829 hhrtim->State = HAL_HRTIM_STATE_READY;
3830
3831 /* Process Unlocked */
3832 __HAL_UNLOCK(hhrtim);
3833
3834 return HAL_OK;
3835 }
3836
3837 /**
3838 * @}
3839 */
3840
3841 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
3842 * @brief HRTIM timer configuration and control functions
3843 @verbatim
3844 ===============================================================================
3845 ##### HRTIM timer configuration and control functions #####
3846 ===============================================================================
3847 [..] This section provides functions used to configure and control a
3848 HRTIM timer operating in waveform mode:
3849 (+) Configure HRTIM timer general behavior
3850 (+) Configure HRTIM timer event filtering
3851 (+) Configure HRTIM timer deadtime insertion
3852 (+) Configure HRTIM timer chopper mode
3853 (+) Configure HRTIM timer burst DMA
3854 (+) Configure HRTIM timer compare unit
3855 (+) Configure HRTIM timer capture unit
3856 (+) Configure HRTIM timer output
3857 (+) Set HRTIM timer output level
3858 (+) Enable HRTIM timer output
3859 (+) Disable HRTIM timer output
3860 (+) Start HRTIM timer
3861 (+) Stop HRTIM timer
3862 (+) Start HRTIM timer and enable interrupt
3863 (+) Stop HRTIM timer and disable interrupt
3864 (+) Start HRTIM timer and enable DMA transfer
3865 (+) Stop HRTIM timer and disable DMA transfer
3866 (+) Enable or disable the burst mode controller
3867 (+) Start the burst mode controller (by software)
3868 (+) Trigger a Capture (by software)
3869 (+) Update the HRTIM timer preloadable registers (by software)
3870 (+) Reset the HRTIM timer counter (by software)
3871 (+) Start a burst DMA transfer
3872 (+) Enable timer register update
3873 (+) Disable timer register update
3874
3875 @endverbatim
3876 * @{
3877 */
3878
3879 /**
3880 * @brief Configures the general behavior of a timer operating in waveform mode
3881 * @param hhrtim pointer to HAL HRTIM handle
3882 * @param TimerIdx Timer index
3883 * This parameter can be one of the following values:
3884 * @arg HRTIM_TIMERINDEX_MASTER for master timer
3885 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3886 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3887 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3888 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3889 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3890 * @param pTimerCfg pointer to the timer configuration structure
3891 * @note When the timer operates in waveform mode, all the features supported by
3892 * the HRTIM are available without any limitation.
3893 * @retval HAL status
3894 * @note This function must be called before starting the timer
3895 */
3896 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
3897 uint32_t TimerIdx,
3898 HRTIM_TimerCfgTypeDef * pTimerCfg)
3899 {
3900 /* Check parameters */
3901 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
3902
3903 /* Relevant for all HRTIM timers, including the master */
3904 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
3905 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
3906 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
3907 assert_param(IS_HHRTIM_DACSYNC(pTimerCfg->DACSynchro));
3908 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
3909 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
3910 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
3911
3912 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3913 {
3914 return HAL_BUSY;
3915 }
3916
3917 /* Process Locked */
3918 __HAL_LOCK(hhrtim);
3919
3920 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3921
3922 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
3923 {
3924 /* Check parameters */
3925 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
3926 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
3927 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
3928
3929 /* Configure master timer */
3930 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
3931 }
3932 else
3933 {
3934 /* Check parameters */
3935 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
3936 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
3937 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
3938 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
3939 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
3940 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
3941 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
3942 pTimerCfg->DeadTimeInsertion));
3943 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
3944 pTimerCfg->DelayedProtectionMode));
3945 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
3946 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
3947 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
3948
3949 /* Configure timing unit */
3950 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
3951 }
3952
3953 /* Update timer parameters */
3954 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
3955 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
3956 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
3957 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
3958 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
3959
3960 /* Force a software update */
3961 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
3962
3963 hhrtim->State = HAL_HRTIM_STATE_READY;
3964
3965 /* Process Unlocked */
3966 __HAL_UNLOCK(hhrtim);
3967
3968 return HAL_OK;
3969 }
3970
3971 /**
3972 * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
3973 * @param hhrtim pointer to HAL HRTIM handle
3974 * @param TimerIdx Timer index
3975 * This parameter can be one of the following values:
3976 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3977 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3978 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3979 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3980 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3981 * @param Event external event for which timer event filtering must be configured
3982 * This parameter can be one of the following values:
3983 * @arg HRTIM_EVENT_NONE: Reset timer event filtering configuration
3984 * @arg HRTIM_EVENT_1: External event 1
3985 * @arg HRTIM_EVENT_2: External event 2
3986 * @arg HRTIM_EVENT_3: External event 3
3987 * @arg HRTIM_EVENT_4: External event 4
3988 * @arg HRTIM_EVENT_5: External event 5
3989 * @arg HRTIM_EVENT_6: External event 6
3990 * @arg HRTIM_EVENT_7: External event 7
3991 * @arg HRTIM_EVENT_8: External event 8
3992 * @arg HRTIM_EVENT_9: External event 9
3993 * @arg HRTIM_EVENT_10: External event 10
3994 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
3995 * @note This function must be called before starting the timer
3996 * @retval HAL status
3997 */
3998 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
3999 uint32_t TimerIdx,
4000 uint32_t Event,
4001 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
4002 {
4003 uint32_t hrtim_eefr;
4004
4005 /* Check parameters */
4006 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4007 assert_param(IS_HRTIM_EVENT(Event));
4008 assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
4009 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
4010
4011 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4012 {
4013 return HAL_BUSY;
4014 }
4015
4016 /* Process Locked */
4017 __HAL_LOCK(hhrtim);
4018
4019 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4020
4021 /* Configure timer event filtering capabilities */
4022 switch (Event)
4023 {
4024 case HRTIM_EVENT_NONE:
4025 {
4026 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = 0U;
4027 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = 0U;
4028 }
4029 break;
4030 case HRTIM_EVENT_1:
4031 {
4032 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
4033 hrtim_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
4034 hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
4035 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
4036 }
4037 break;
4038 case HRTIM_EVENT_2:
4039 {
4040 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
4041 hrtim_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
4042 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
4043 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
4044 }
4045 break;
4046 case HRTIM_EVENT_3:
4047 {
4048 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
4049 hrtim_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
4050 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
4051 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
4052 }
4053 break;
4054 case HRTIM_EVENT_4:
4055 {
4056 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
4057 hrtim_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
4058 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
4059 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
4060 }
4061 break;
4062 case HRTIM_EVENT_5:
4063 {
4064 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1;
4065 hrtim_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
4066 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
4067 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1 = hrtim_eefr;
4068 }
4069 break;
4070 case HRTIM_EVENT_6:
4071 {
4072 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
4073 hrtim_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
4074 hrtim_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
4075 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
4076 }
4077 break;
4078 case HRTIM_EVENT_7:
4079 {
4080 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
4081 hrtim_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
4082 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U);
4083 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
4084 }
4085 break;
4086 case HRTIM_EVENT_8:
4087 {
4088 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
4089 hrtim_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
4090 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U);
4091 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
4092 }
4093 break;
4094 case HRTIM_EVENT_9:
4095 {
4096 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
4097 hrtim_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
4098 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U);
4099 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
4100 }
4101 break;
4102 case HRTIM_EVENT_10:
4103 {
4104 hrtim_eefr = hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2;
4105 hrtim_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
4106 hrtim_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U);
4107 hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2 = hrtim_eefr;
4108 }
4109 break;
4110 default:
4111 break;
4112 }
4113
4114 hhrtim->State = HAL_HRTIM_STATE_READY;
4115
4116 /* Process Unlocked */
4117 __HAL_UNLOCK(hhrtim);
4118
4119 return HAL_OK;
4120 }
4121
4122 /**
4123 * @brief Configures the deadtime insertion feature for a timer
4124 * @param hhrtim pointer to HAL HRTIM handle
4125 * @param TimerIdx Timer index
4126 * This parameter can be one of the following values:
4127 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4128 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4129 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4130 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4131 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4132 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
4133 * @retval HAL status
4134 * @note This function must be called before starting the timer
4135 */
4136 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
4137 uint32_t TimerIdx,
4138 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
4139 {
4140 uint32_t hrtim_dtr;
4141
4142 /* Check parameters */
4143 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4144 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
4145 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
4146 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
4147 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
4148 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
4149 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
4150 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
4151
4152 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4153 {
4154 return HAL_BUSY;
4155 }
4156
4157 /* Process Locked */
4158 __HAL_LOCK(hhrtim);
4159
4160 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4161
4162 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
4163
4164 /* Clear timer deadtime configuration */
4165 hrtim_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
4166 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
4167 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
4168
4169 /* Set timer deadtime configuration */
4170 hrtim_dtr |= pDeadTimeCfg->Prescaler;
4171 hrtim_dtr |= pDeadTimeCfg->RisingValue;
4172 hrtim_dtr |= pDeadTimeCfg->RisingSign;
4173 hrtim_dtr |= pDeadTimeCfg->RisingSignLock;
4174 hrtim_dtr |= pDeadTimeCfg->RisingLock;
4175 hrtim_dtr |= (pDeadTimeCfg->FallingValue << 16U);
4176 hrtim_dtr |= pDeadTimeCfg->FallingSign;
4177 hrtim_dtr |= pDeadTimeCfg->FallingSignLock;
4178 hrtim_dtr |= pDeadTimeCfg->FallingLock;
4179
4180 /* Update the HRTIM registers */
4181 hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR = hrtim_dtr;
4182
4183 hhrtim->State = HAL_HRTIM_STATE_READY;
4184
4185 /* Process Unlocked */
4186 __HAL_UNLOCK(hhrtim);
4187
4188 return HAL_OK;
4189 }
4190
4191 /**
4192 * @brief Configures the chopper mode feature for a timer
4193 * @param hhrtim pointer to HAL HRTIM handle
4194 * @param TimerIdx Timer index
4195 * This parameter can be one of the following values:
4196 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4197 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4198 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4199 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4200 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4201 * @param pChopperModeCfg pointer to the chopper mode configuration structure
4202 * @retval HAL status
4203 * @note This function must be called before configuring the timer output(s)
4204 */
4205 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
4206 uint32_t TimerIdx,
4207 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
4208 {
4209 uint32_t hrtim_chpr;
4210
4211 /* Check parameters */
4212 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4213 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
4214 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
4215 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
4216
4217 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4218 {
4219 return HAL_BUSY;
4220 }
4221
4222 /* Process Locked */
4223 __HAL_LOCK(hhrtim);
4224
4225 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4226
4227 hrtim_chpr = hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR;
4228
4229 /* Clear timer chopper mode configuration */
4230 hrtim_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
4231
4232 /* Set timer choppe mode configuration */
4233 hrtim_chpr |= pChopperModeCfg->CarrierFreq;
4234 hrtim_chpr |= (pChopperModeCfg->DutyCycle);
4235 hrtim_chpr |= (pChopperModeCfg->StartPulse);
4236
4237 /* Update the HRTIM registers */
4238 hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR = hrtim_chpr;
4239
4240 hhrtim->State = HAL_HRTIM_STATE_READY;
4241
4242 /* Process Unlocked */
4243 __HAL_UNLOCK(hhrtim);
4244
4245 return HAL_OK;
4246 }
4247
4248 /**
4249 * @brief Configures the burst DMA controller for a timer
4250 * @param hhrtim pointer to HAL HRTIM handle
4251 * @param TimerIdx Timer index
4252 * This parameter can be one of the following values:
4253 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4254 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4255 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4256 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4257 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4258 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4259 * @param RegistersToUpdate registers to be written by DMA
4260 * This parameter can be any combination of the following values:
4261 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
4262 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
4263 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
4264 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
4265 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
4266 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
4267 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
4268 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
4269 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
4270 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
4271 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
4272 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
4273 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
4274 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
4275 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
4276 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
4277 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
4278 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
4279 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
4280 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
4281 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
4282 * @retval HAL status
4283 * @note This function must be called before starting the timer
4284 */
4285 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
4286 uint32_t TimerIdx,
4287 uint32_t RegistersToUpdate)
4288 {
4289 /* Check parameters */
4290 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
4291
4292 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4293 {
4294 return HAL_BUSY;
4295 }
4296
4297 /* Process Locked */
4298 __HAL_LOCK(hhrtim);
4299
4300 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4301
4302 /* Set the burst DMA timer update register */
4303 switch (TimerIdx)
4304 {
4305 case HRTIM_TIMERINDEX_TIMER_A:
4306 {
4307 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
4308 }
4309 break;
4310 case HRTIM_TIMERINDEX_TIMER_B:
4311 {
4312 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
4313 }
4314 break;
4315 case HRTIM_TIMERINDEX_TIMER_C:
4316 {
4317 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
4318 }
4319 break;
4320 case HRTIM_TIMERINDEX_TIMER_D:
4321 {
4322 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
4323 }
4324 break;
4325 case HRTIM_TIMERINDEX_TIMER_E:
4326 {
4327 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
4328 }
4329 break;
4330 case HRTIM_TIMERINDEX_MASTER:
4331 {
4332 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
4333 }
4334 break;
4335 default:
4336 break;
4337 }
4338
4339 hhrtim->State = HAL_HRTIM_STATE_READY;
4340
4341 /* Process Unlocked */
4342 __HAL_UNLOCK(hhrtim);
4343
4344 return HAL_OK;
4345 }
4346
4347 /**
4348 * @brief Configures the compare unit of a timer operating in waveform mode
4349 * @param hhrtim pointer to HAL HRTIM handle
4350 * @param TimerIdx Timer index
4351 * This parameter can be one of the following values:
4352 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4353 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4354 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4355 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4356 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4357 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4358 * @param CompareUnit Compare unit to configure
4359 * This parameter can be one of the following values:
4360 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
4361 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
4362 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
4363 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
4364 * @param pCompareCfg pointer to the compare unit configuration structure
4365 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
4366 * application has to configure separately the capture unit. Capture unit
4367 * to configure in that case depends on the compare unit auto delayed mode
4368 * is applied to (see below):
4369 * Auto delayed on output compare 2: capture unit 1 must be configured
4370 * Auto delayed on output compare 4: capture unit 2 must be configured
4371 * @retval HAL status
4372 * @note This function must be called before starting the timer
4373 */
4374 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
4375 uint32_t TimerIdx,
4376 uint32_t CompareUnit,
4377 HRTIM_CompareCfgTypeDef* pCompareCfg)
4378 {
4379 /* Check parameters */
4380 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4381
4382 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4383 {
4384 return HAL_BUSY;
4385 }
4386
4387 /* Process Locked */
4388 __HAL_LOCK(hhrtim);
4389
4390 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4391
4392 /* Configure the compare unit */
4393 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4394 {
4395 switch (CompareUnit)
4396 {
4397 case HRTIM_COMPAREUNIT_1:
4398 {
4399 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
4400 }
4401 break;
4402 case HRTIM_COMPAREUNIT_2:
4403 {
4404 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
4405 }
4406 break;
4407 case HRTIM_COMPAREUNIT_3:
4408 {
4409 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
4410 }
4411 break;
4412 case HRTIM_COMPAREUNIT_4:
4413 {
4414 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
4415 }
4416 break;
4417 default:
4418 break;
4419 }
4420 }
4421 else
4422 {
4423 switch (CompareUnit)
4424 {
4425 case HRTIM_COMPAREUNIT_1:
4426 {
4427 /* Set the compare value */
4428 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
4429 }
4430 break;
4431 case HRTIM_COMPAREUNIT_2:
4432 {
4433 /* Check parameters */
4434 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4435
4436 /* Set the compare value */
4437 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
4438
4439 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4440 {
4441 /* Configure auto-delayed mode */
4442 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
4443 /* to the other to reinitialize properly the auto-delayed mechanism */
4444 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
4445 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
4446
4447 /* Set the compare value for timeout compare unit (if any) */
4448 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4449 {
4450 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4451 }
4452 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4453 {
4454 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4455 }
4456 }
4457 }
4458 break;
4459 case HRTIM_COMPAREUNIT_3:
4460 {
4461 /* Set the compare value */
4462 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
4463 }
4464 break;
4465 case HRTIM_COMPAREUNIT_4:
4466 {
4467 /* Check parameters */
4468 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
4469
4470 /* Set the compare value */
4471 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
4472
4473 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
4474 {
4475 /* Configure auto-delayed mode */
4476 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
4477 /* to the other to reinitialize properly the auto-delayed mechanism */
4478 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
4479 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
4480
4481 /* Set the compare value for timeout compare unit (if any) */
4482 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
4483 {
4484 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
4485 }
4486 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
4487 {
4488 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
4489 }
4490 }
4491 }
4492 break;
4493 default:
4494 break;
4495 }
4496 }
4497 hhrtim->State = HAL_HRTIM_STATE_READY;
4498
4499 /* Process Unlocked */
4500 __HAL_UNLOCK(hhrtim);
4501
4502 return HAL_OK;
4503 }
4504
4505 /**
4506 * @brief Configures the capture unit of a timer operating in waveform mode
4507 * @param hhrtim pointer to HAL HRTIM handle
4508 * @param TimerIdx Timer index
4509 * This parameter can be one of the following values:
4510 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4511 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4512 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4513 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4514 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4515 * @param CaptureUnit Capture unit to configure
4516 * This parameter can be one of the following values:
4517 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
4518 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
4519 * @param pCaptureCfg pointer to the compare unit configuration structure
4520 * @retval HAL status
4521 * @note This function must be called before starting the timer
4522 */
4523 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
4524 uint32_t TimerIdx,
4525 uint32_t CaptureUnit,
4526 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
4527 {
4528 /* Check parameters */
4529 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, pCaptureCfg->Trigger));
4530
4531 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4532 {
4533 return HAL_BUSY;
4534 }
4535
4536 /* Process Locked */
4537 __HAL_LOCK(hhrtim);
4538
4539 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4540
4541 /* Configure the capture unit */
4542 switch (CaptureUnit)
4543 {
4544 case HRTIM_CAPTUREUNIT_1:
4545 {
4546 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
4547 }
4548 break;
4549 case HRTIM_CAPTUREUNIT_2:
4550 {
4551 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
4552 }
4553 break;
4554 default:
4555 break;
4556 }
4557
4558 hhrtim->State = HAL_HRTIM_STATE_READY;
4559
4560 /* Process Unlocked */
4561 __HAL_UNLOCK(hhrtim);
4562
4563 return HAL_OK;
4564 }
4565
4566 /**
4567 * @brief Configures the output of a timer operating in waveform mode
4568 * @param hhrtim pointer to HAL HRTIM handle
4569 * @param TimerIdx Timer index
4570 * This parameter can be one of the following values:
4571 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4572 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4573 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4574 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4575 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4576 * @param Output Timer output
4577 * This parameter can be one of the following values:
4578 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4579 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4580 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4581 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4582 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4583 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4584 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4585 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4586 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4587 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4588 * @param pOutputCfg pointer to the timer output configuration structure
4589 * @retval HAL status
4590 * @note This function must be called before configuring the timer and after
4591 * configuring the deadtime insertion feature (if required).
4592 */
4593 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
4594 uint32_t TimerIdx,
4595 uint32_t Output,
4596 HRTIM_OutputCfgTypeDef * pOutputCfg)
4597 {
4598 /* Check parameters */
4599 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4600 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
4601 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
4602 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
4603 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
4604 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
4605 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
4606
4607 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4608 {
4609 return HAL_BUSY;
4610 }
4611
4612 /* Process Locked */
4613 __HAL_LOCK(hhrtim);
4614
4615 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4616
4617 /* Configure the timer output */
4618 HRTIM_OutputConfig(hhrtim,
4619 TimerIdx,
4620 Output,
4621 pOutputCfg);
4622
4623 hhrtim->State = HAL_HRTIM_STATE_READY;
4624
4625 /* Process Unlocked */
4626 __HAL_UNLOCK(hhrtim);
4627
4628 return HAL_OK;
4629 }
4630
4631 /**
4632 * @brief Forces the timer output to its active or inactive state
4633 * @param hhrtim pointer to HAL HRTIM handle
4634 * @param TimerIdx Timer index
4635 * This parameter can be one of the following values:
4636 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4637 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4638 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4639 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4640 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4641 * @param Output Timer output
4642 * This parameter can be one of the following values:
4643 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4644 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4645 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4646 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4647 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4648 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4649 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4650 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4651 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4652 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4653 * @param OutputLevel indicates whether the output is forced to its active or inactive level
4654 * This parameter can be one of the following values:
4655 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
4656 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
4657 * @retval HAL status
4658 * @note The 'software set/reset trigger' bit in the output set/reset registers
4659 * is automatically reset by hardware
4660 */
4661 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
4662 uint32_t TimerIdx,
4663 uint32_t Output,
4664 uint32_t OutputLevel)
4665 {
4666 /* Check parameters */
4667 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
4668 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
4669
4670 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4671 {
4672 return HAL_BUSY;
4673 }
4674
4675 /* Process Locked */
4676 __HAL_LOCK(hhrtim);
4677
4678 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4679
4680 /* Force timer output level */
4681 switch (Output)
4682 {
4683 case HRTIM_OUTPUT_TA1:
4684 case HRTIM_OUTPUT_TB1:
4685 case HRTIM_OUTPUT_TC1:
4686 case HRTIM_OUTPUT_TD1:
4687 case HRTIM_OUTPUT_TE1:
4688 {
4689 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4690 {
4691 /* Force output to its active state */
4692 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
4693 }
4694 else
4695 {
4696 /* Force output to its inactive state */
4697 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
4698 }
4699 }
4700 break;
4701 case HRTIM_OUTPUT_TA2:
4702 case HRTIM_OUTPUT_TB2:
4703 case HRTIM_OUTPUT_TC2:
4704 case HRTIM_OUTPUT_TD2:
4705 case HRTIM_OUTPUT_TE2:
4706 {
4707 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
4708 {
4709 /* Force output to its active state */
4710 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
4711 }
4712 else
4713 {
4714 /* Force output to its inactive state */
4715 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
4716 }
4717 }
4718 break;
4719 default:
4720 break;
4721 }
4722
4723 hhrtim->State = HAL_HRTIM_STATE_READY;
4724
4725 /* Process Unlocked */
4726 __HAL_UNLOCK(hhrtim);
4727
4728 return HAL_OK;
4729 }
4730
4731 /**
4732 * @brief Enables the generation of the waveform signal on the designated output(s)
4733 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
4734 * @param hhrtim pointer to HAL HRTIM handle
4735 * @param OutputsToStart Timer output(s) to enable
4736 * This parameter can be any combination of the following values:
4737 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4738 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4739 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4740 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4741 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4742 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4743 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4744 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4745 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4746 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4747 * @retval HAL status
4748 */
4749 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
4750 uint32_t OutputsToStart)
4751 {
4752 /* Check the parameters */
4753 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
4754
4755 /* Process Locked */
4756 __HAL_LOCK(hhrtim);
4757
4758 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4759
4760 /* Enable the HRTIM outputs */
4761 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
4762
4763 hhrtim->State = HAL_HRTIM_STATE_READY;
4764
4765 /* Process Unlocked */
4766 __HAL_UNLOCK(hhrtim);
4767
4768 return HAL_OK;
4769 }
4770
4771 /**
4772 * @brief Disables the generation of the waveform signal on the designated output(s)
4773 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
4774 * @param hhrtim pointer to HAL HRTIM handle
4775 * @param OutputsToStop Timer output(s) to disable
4776 * This parameter can be any combination of the following values:
4777 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
4778 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
4779 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
4780 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
4781 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
4782 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
4783 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
4784 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
4785 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
4786 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
4787 * @retval HAL status
4788 */
4789 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
4790 uint32_t OutputsToStop)
4791 {
4792 /* Check the parameters */
4793 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
4794
4795 /* Process Locked */
4796 __HAL_LOCK(hhrtim);
4797
4798 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4799
4800 /* Enable the HRTIM outputs */
4801 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
4802
4803 hhrtim->State = HAL_HRTIM_STATE_READY;
4804
4805 /* Process Unlocked */
4806 __HAL_UNLOCK(hhrtim);
4807
4808 return HAL_OK;
4809 }
4810
4811 /**
4812 * @brief Starts the counter of the designated timer(s) operating in waveform mode
4813 * Timers can be combined (ORed) to allow for simultaneous counter start.
4814 * @param hhrtim pointer to HAL HRTIM handle
4815 * @param Timers Timer counter(s) to start
4816 * This parameter can be any combination of the following values:
4817 * @arg HRTIM_TIMERID_MASTER
4818 * @arg HRTIM_TIMERID_TIMER_A
4819 * @arg HRTIM_TIMERID_TIMER_B
4820 * @arg HRTIM_TIMERID_TIMER_C
4821 * @arg HRTIM_TIMERID_TIMER_D
4822 * @arg HRTIM_TIMERID_TIMER_E
4823 * @retval HAL status
4824 */
4825 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart(HRTIM_HandleTypeDef * hhrtim,
4826 uint32_t Timers)
4827 {
4828 /* Check the parameters */
4829 assert_param(IS_HRTIM_TIMERID(Timers));
4830
4831 /* Process Locked */
4832 __HAL_LOCK(hhrtim);
4833
4834 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4835
4836 /* Enable timer(s) counter */
4837 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
4838
4839 hhrtim->State = HAL_HRTIM_STATE_READY;
4840
4841 /* Process Unlocked */
4842 __HAL_UNLOCK(hhrtim);
4843
4844 return HAL_OK;
4845 }
4846
4847 /**
4848 * @brief Stops the counter of the designated timer(s) operating in waveform mode
4849 * Timers can be combined (ORed) to allow for simultaneous counter stop.
4850 * @param hhrtim pointer to HAL HRTIM handle
4851 * @param Timers Timer counter(s) to stop
4852 * This parameter can be any combination of the following values:
4853 * @arg HRTIM_TIMERID_MASTER
4854 * @arg HRTIM_TIMERID_A
4855 * @arg HRTIM_TIMERID_B
4856 * @arg HRTIM_TIMERID_C
4857 * @arg HRTIM_TIMERID_D
4858 * @arg HRTIM_TIMERID_E
4859 * @retval HAL status
4860 * @note The counter of a timer is stopped only if all timer outputs are disabled
4861 */
4862 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop(HRTIM_HandleTypeDef * hhrtim,
4863 uint32_t Timers)
4864 {
4865 /* Check the parameters */
4866 assert_param(IS_HRTIM_TIMERID(Timers));
4867
4868 /* Process Locked */
4869 __HAL_LOCK(hhrtim);
4870
4871 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4872
4873 /* Disable timer(s) counter */
4874 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
4875
4876 hhrtim->State = HAL_HRTIM_STATE_READY;
4877
4878 /* Process Unlocked */
4879 __HAL_UNLOCK(hhrtim);
4880
4881 return HAL_OK;
4882 }
4883
4884 /**
4885 * @brief Starts the counter of the designated timer(s) operating in waveform mode
4886 * Timers can be combined (ORed) to allow for simultaneous counter start.
4887 * @param hhrtim pointer to HAL HRTIM handle
4888 * @param Timers Timer counter(s) to start
4889 * This parameter can be any combination of the following values:
4890 * @arg HRTIM_TIMERID_MASTER
4891 * @arg HRTIM_TIMERID_A
4892 * @arg HRTIM_TIMERID_B
4893 * @arg HRTIM_TIMERID_C
4894 * @arg HRTIM_TIMERID_D
4895 * @arg HRTIM_TIMERID_E
4896 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
4897 * to the timers to start are enabled within this function.
4898 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
4899 * function.
4900 * @retval HAL status
4901 */
4902 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_IT(HRTIM_HandleTypeDef * hhrtim,
4903 uint32_t Timers)
4904 {
4905 uint8_t timer_idx;
4906
4907 /* Check the parameters */
4908 assert_param(IS_HRTIM_TIMERID(Timers));
4909
4910 /* Process Locked */
4911 __HAL_LOCK(hhrtim);
4912
4913 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4914
4915 /* Enable HRTIM interrupts (if required) */
4916 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
4917
4918 /* Enable master timer related interrupts (if required) */
4919 if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
4920 {
4921 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
4922 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
4923 }
4924
4925 /* Enable timing unit related interrupts (if required) */
4926 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
4927 timer_idx < HRTIM_TIMERINDEX_MASTER ;
4928 timer_idx++)
4929 {
4930 if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
4931 {
4932 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
4933 timer_idx,
4934 hhrtim->TimerParam[timer_idx].InterruptRequests);
4935 }
4936 }
4937
4938 /* Enable timer(s) counter */
4939 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
4940
4941 hhrtim->State = HAL_HRTIM_STATE_READY;
4942
4943 /* Process Unlocked */
4944 __HAL_UNLOCK(hhrtim);
4945
4946 return HAL_OK;}
4947
4948 /**
4949 * @brief Stops the counter of the designated timer(s) operating in waveform mode
4950 * Timers can be combined (ORed) to allow for simultaneous counter stop.
4951 * @param hhrtim pointer to HAL HRTIM handle
4952 * @param Timers Timer counter(s) to stop
4953 * This parameter can be any combination of the following values:
4954 * @arg HRTIM_TIMERID_MASTER
4955 * @arg HRTIM_TIMERID_A
4956 * @arg HRTIM_TIMERID_B
4957 * @arg HRTIM_TIMERID_C
4958 * @arg HRTIM_TIMERID_D
4959 * @arg HRTIM_TIMERID_E
4960 * @retval HAL status
4961 * @note The counter of a timer is stopped only if all timer outputs are disabled
4962 * @note All enabled timer related interrupts are disabled.
4963 */
4964 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_IT(HRTIM_HandleTypeDef * hhrtim,
4965 uint32_t Timers)
4966 {
4967 /* ++ WA */
4968 __IO uint32_t delai = (uint32_t)(0x17FU);
4969 /* -- WA */
4970
4971 uint8_t timer_idx;
4972
4973 /* Check the parameters */
4974 assert_param(IS_HRTIM_TIMERID(Timers));
4975
4976 /* Process Locked */
4977 __HAL_LOCK(hhrtim);
4978
4979 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4980
4981 /* Disable HRTIM interrupts (if required) */
4982 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
4983
4984 /* Disable master timer related interrupts (if required) */
4985 if ((Timers & HRTIM_TIMERID_MASTER) != RESET)
4986 {
4987 /* Interrupts enable flag must be cleared one by one */
4988 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
4989 }
4990
4991 /* Disable timing unit related interrupts (if required) */
4992 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
4993 timer_idx < HRTIM_TIMERINDEX_MASTER ;
4994 timer_idx++)
4995 {
4996 if ((Timers & TimerIdxToTimerId[timer_idx]) != RESET)
4997 {
4998 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
4999 }
5000 }
5001
5002 /* ++ WA */
5003 do { delai--; } while (delai != 0U);
5004 /* -- WA */
5005
5006 /* Disable timer(s) counter */
5007 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
5008
5009 hhrtim->State = HAL_HRTIM_STATE_READY;
5010
5011 /* Process Unlocked */
5012 __HAL_UNLOCK(hhrtim);
5013
5014 return HAL_OK;
5015 }
5016
5017 /**
5018 * @brief Starts the counter of the designated timer(s) operating in waveform mode
5019 * Timers can be combined (ORed) to allow for simultaneous counter start.
5020 * @param hhrtim pointer to HAL HRTIM handle
5021 * @param Timers Timer counter(s) to start
5022 * This parameter can be any combination of the following values:
5023 * HRTIM_TIMERID_MASTER
5024 * @arg HRTIM_TIMERID_A
5025 * @arg HRTIM_TIMERID_B
5026 * @arg HRTIM_TIMERID_C
5027 * @arg HRTIM_TIMERID_D
5028 * @arg HRTIM_TIMERID_E
5029 * @retval HAL status
5030 * @note This function enables the dma request(s) mentionned in the timer
5031 * configuration data structure for every timers to start.
5032 * @note The source memory address, the destination memory address and the
5033 * size of each DMA transfer are specified at timer configuration time
5034 * (see HAL_HRTIM_WaveformTimerConfig)
5035 */
5036 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStart_DMA(HRTIM_HandleTypeDef * hhrtim,
5037 uint32_t Timers)
5038 {
5039 uint8_t timer_idx;
5040 DMA_HandleTypeDef * hdma;
5041
5042 /* Check the parameters */
5043 assert_param(IS_HRTIM_TIMERID(Timers));
5044
5045 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
5046 {
5047 return HAL_BUSY;
5048 }
5049
5050 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5051
5052 /* Process Locked */
5053 __HAL_LOCK(hhrtim);
5054
5055 if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
5056 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5057 {
5058 /* Set the DMA error callback */
5059 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
5060
5061 /* Set the DMA transfer completed callback */
5062 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
5063
5064 /* Enable the DMA channel */
5065 HAL_DMA_Start_IT(hhrtim->hdmaMaster,
5066 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
5067 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
5068 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize);
5069
5070 /* Enable the timer DMA request */
5071 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
5072 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5073 }
5074
5075 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5076 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5077 timer_idx++)
5078 {
5079 if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
5080 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5081 {
5082 /* Get the timer DMA handler */
5083 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5084 if (hdma == NULL)
5085 {
5086 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5087
5088 /* Process Unlocked */
5089 __HAL_UNLOCK(hhrtim);
5090
5091 return HAL_ERROR;
5092 }
5093
5094 /* Set the DMA error callback */
5095 hdma->XferErrorCallback = HRTIM_DMAError ;
5096
5097 /* Set the DMA transfer completed callback */
5098 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
5099
5100 /* Enable the DMA channel */
5101 HAL_DMA_Start_IT(hdma,
5102 hhrtim->TimerParam[timer_idx].DMASrcAddress,
5103 hhrtim->TimerParam[timer_idx].DMADstAddress,
5104 hhrtim->TimerParam[timer_idx].DMASize);
5105
5106 /* Enable the timer DMA request */
5107 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
5108 timer_idx,
5109 hhrtim->TimerParam[timer_idx].DMARequests);
5110 }
5111 }
5112
5113 /* Enable the timer counter */
5114 __HAL_HRTIM_ENABLE(hhrtim, Timers);
5115
5116 hhrtim->State = HAL_HRTIM_STATE_READY;
5117
5118 /* Process Unlocked */
5119 __HAL_UNLOCK(hhrtim);
5120
5121 return HAL_OK;
5122 }
5123
5124 /**
5125 * @brief Stops the counter of the designated timer(s) operating in waveform mode
5126 * Timers can be combined (ORed) to allow for simultaneous counter stop.
5127 * @param hhrtim pointer to HAL HRTIM handle
5128 * @param Timers Timer counter(s) to stop
5129 * This parameter can be any combination of the following values:
5130 * @arg HRTIM_TIMERID_MASTER
5131 * @arg HRTIM_TIMERID_A
5132 * @arg HRTIM_TIMERID_B
5133 * @arg HRTIM_TIMERID_C
5134 * @arg HRTIM_TIMERID_D
5135 * @arg HRTIM_TIMERID_E
5136 * @retval HAL status
5137 * @note The counter of a timer is stopped only if all timer outputs are disabled
5138 * @note All enabled timer related DMA requests are disabled.
5139 */
5140 HAL_StatusTypeDef HAL_HRTIM_WaveformCounterStop_DMA(HRTIM_HandleTypeDef * hhrtim,
5141 uint32_t Timers)
5142 {
5143 uint8_t timer_idx;
5144 DMA_HandleTypeDef * hdma;
5145
5146 /* Check the parameters */
5147 assert_param(IS_HRTIM_TIMERID(Timers));
5148
5149 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5150
5151 if (((Timers & HRTIM_TIMERID_MASTER) != RESET) &&
5152 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
5153 {
5154 /* Disable the DMA */
5155 HAL_DMA_Abort(hhrtim->hdmaMaster);
5156
5157 /* Disable the DMA request(s) */
5158 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
5159 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
5160 }
5161
5162 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
5163 timer_idx < HRTIM_TIMERINDEX_MASTER ;
5164 timer_idx++)
5165 {
5166 if (((Timers & TimerIdxToTimerId[timer_idx]) != RESET) &&
5167 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
5168 {
5169 /* Get the timer DMA handler */
5170 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
5171 if (hdma == NULL)
5172 {
5173 /* Disable the DMA request(s) */
5174 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5175 timer_idx,
5176 hhrtim->TimerParam[timer_idx].DMARequests);
5177
5178 /* Disable the timer counter */
5179 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5180
5181 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5182
5183 return HAL_ERROR;
5184 }
5185
5186 /* Disable the DMA */
5187 HAL_DMA_Abort(hdma);
5188
5189 /* Disable the DMA request(s) */
5190 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
5191 timer_idx,
5192 hhrtim->TimerParam[timer_idx].DMARequests);
5193 }
5194 }
5195
5196 /* Disable the timer counter */
5197 __HAL_HRTIM_DISABLE(hhrtim, Timers);
5198
5199 hhrtim->State = HAL_HRTIM_STATE_READY;
5200
5201 return HAL_OK;
5202 }
5203
5204 /**
5205 * @brief Enables or disables the HRTIM burst mode controller.
5206 * @param hhrtim pointer to HAL HRTIM handle
5207 * @param Enable Burst mode controller enabling
5208 * This parameter can be one of the following values:
5209 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
5210 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
5211 * @retval HAL status
5212 * @note This function must be called after starting the timer(s)
5213 */
5214 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
5215 uint32_t Enable)
5216 {
5217 uint32_t hrtim_bmcr;
5218
5219 /* Check parameters */
5220 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
5221
5222 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5223 {
5224 return HAL_BUSY;
5225 }
5226
5227 /* Process Locked */
5228 __HAL_LOCK(hhrtim);
5229
5230 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5231
5232 /* Enable/Disable the burst mode controller */
5233 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
5234 hrtim_bmcr &= ~(HRTIM_BMCR_BME);
5235 hrtim_bmcr |= Enable;
5236
5237 /* Update the HRTIM registers */
5238 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
5239
5240 hhrtim->State = HAL_HRTIM_STATE_READY;
5241
5242 /* Process Unlocked */
5243 __HAL_UNLOCK(hhrtim);
5244
5245 return HAL_OK;
5246 }
5247
5248 /**
5249 * @brief Triggers the burst mode operation.
5250 * @param hhrtim pointer to HAL HRTIM handle
5251 * @retval HAL status
5252 */
5253 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
5254 {
5255 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5256 {
5257 return HAL_BUSY;
5258 }
5259
5260 /* Process Locked */
5261 __HAL_LOCK(hhrtim);
5262
5263 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5264
5265 /* Software trigger of the burst mode controller */
5266 hhrtim->Instance->sCommonRegs.BMTRGR |= HRTIM_BMTRGR_SW;
5267
5268 hhrtim->State = HAL_HRTIM_STATE_READY;
5269
5270 /* Process Unlocked */
5271 __HAL_UNLOCK(hhrtim);
5272
5273 return HAL_OK;
5274 }
5275
5276 /**
5277 * @brief Triggers a software capture on the designed capture unit
5278 * @param hhrtim pointer to HAL HRTIM handle
5279 * @param TimerIdx Timer index
5280 * This parameter can be one of the following values:
5281 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5282 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5283 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5284 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5285 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5286 * @param CaptureUnit Capture unit to trig
5287 * This parameter can be one of the following values:
5288 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5289 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5290 * @retval HAL status
5291 * @note The 'software capture' bit in the capure configuration register is
5292 * automatically reset by hardware
5293 */
5294 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
5295 uint32_t TimerIdx,
5296 uint32_t CaptureUnit)
5297 {
5298 /* Check parameters */
5299 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5300 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5301
5302 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5303 {
5304 return HAL_BUSY;
5305 }
5306
5307 /* Process Locked */
5308 __HAL_LOCK(hhrtim);
5309
5310 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5311
5312 /* Force a software capture on concerned capture unit */
5313 switch (CaptureUnit)
5314 {
5315 case HRTIM_CAPTUREUNIT_1:
5316 {
5317 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
5318 }
5319 break;
5320 case HRTIM_CAPTUREUNIT_2:
5321 {
5322 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
5323 }
5324 break;
5325 default:
5326 break;
5327 }
5328
5329 hhrtim->State = HAL_HRTIM_STATE_READY;
5330
5331 /* Process Unlocked */
5332 __HAL_UNLOCK(hhrtim);
5333
5334 return HAL_OK;
5335 }
5336
5337 /**
5338 * @brief Triggers the update of the registers of one or several timers
5339 * @param hhrtim pointer to HAL HRTIM handle
5340 * @param Timers timers concerned with the software register update
5341 * This parameter can be any combination of the following values:
5342 * @arg HRTIM_TIMERUPDATE_MASTER
5343 * @arg HRTIM_TIMERUPDATE_A
5344 * @arg HRTIM_TIMERUPDATE_B
5345 * @arg HRTIM_TIMERUPDATE_C
5346 * @arg HRTIM_TIMERUPDATE_D
5347 * @arg HRTIM_TIMERUPDATE_E
5348 * @retval HAL status
5349 * @note The 'software update' bits in the HRTIM conrol register 2 register are
5350 * automatically reset by hardware
5351 */
5352 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
5353 uint32_t Timers)
5354 {
5355 /* Check parameters */
5356 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5357
5358 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5359 {
5360 return HAL_BUSY;
5361 }
5362
5363 /* Process Locked */
5364 __HAL_LOCK(hhrtim);
5365
5366 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5367
5368 /* Force timer(s) registers update */
5369 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
5370
5371 hhrtim->State = HAL_HRTIM_STATE_READY;
5372
5373 /* Process Unlocked */
5374 __HAL_UNLOCK(hhrtim);
5375
5376 return HAL_OK;
5377 }
5378
5379 /**
5380 * @brief Triggers the reset of one or several timers
5381 * @param hhrtim pointer to HAL HRTIM handle
5382 * @param Timers timers concerned with the software counter reset
5383 * This parameter can be any combination of the following values:
5384 * @arg HRTIM_TIMERRESET_MASTER
5385 * @arg HRTIM_TIMERRESET_TIMER_A
5386 * @arg HRTIM_TIMERRESET_TIMER_B
5387 * @arg HRTIM_TIMERRESET_TIMER_C
5388 * @arg HRTIM_TIMERRESET_TIMER_D
5389 * @arg HRTIM_TIMERRESET_TIMER_E
5390 * @retval HAL status
5391 * @note The 'software reset' bits in the HRTIM conrol register 2 are
5392 * automatically reset by hardware
5393 */
5394 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
5395 uint32_t Timers)
5396 {
5397 /* Check parameters */
5398 assert_param(IS_HRTIM_TIMERRESET(Timers));
5399
5400 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5401 {
5402 return HAL_BUSY;
5403 }
5404
5405 /* Process Locked */
5406 __HAL_LOCK(hhrtim);
5407
5408 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5409
5410 /* Force timer(s) registers reset */
5411 hhrtim->Instance->sCommonRegs.CR2 = Timers;
5412
5413 hhrtim->State = HAL_HRTIM_STATE_READY;
5414
5415 /* Process Unlocked */
5416 __HAL_UNLOCK(hhrtim);
5417
5418 return HAL_OK;
5419 }
5420
5421 /**
5422 * @brief Starts a burst DMA operation to update HRTIM control registers content
5423 * @param hhrtim pointer to HAL HRTIM handle
5424 * @param TimerIdx Timer index
5425 * This parameter can be one of the following values:
5426 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5427 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5428 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5429 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5430 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5431 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5432 * @param BurstBufferAddress address of the buffer the HRTIM control registers
5433 * content will be updated from.
5434 * @param BurstBufferLength size (in WORDS) of the burst buffer.
5435 * @retval HAL status
5436 * @note The TimerIdx parameter determines the dma channel to be used by the
5437 * DMA burst controller (see below)
5438 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
5439 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
5440 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
5441 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
5442 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
5443 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
5444 */
5445 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
5446 uint32_t TimerIdx,
5447 uint32_t BurstBufferAddress,
5448 uint32_t BurstBufferLength)
5449 {
5450 DMA_HandleTypeDef * hdma;
5451
5452 /* Check the parameters */
5453 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5454
5455 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
5456 {
5457 return HAL_BUSY;
5458 }
5459 if((hhrtim->State == HAL_HRTIM_STATE_READY))
5460 {
5461 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
5462 {
5463 return HAL_ERROR;
5464 }
5465 else
5466 {
5467 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5468 }
5469 }
5470
5471 /* Process Locked */
5472 __HAL_LOCK(hhrtim);
5473
5474 /* Get the timer DMA handler */
5475 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
5476 if (hdma == NULL)
5477 {
5478 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5479
5480 /* Process Unlocked */
5481 __HAL_UNLOCK(hhrtim);
5482
5483 return HAL_ERROR;
5484 }
5485
5486 /* Set the DMA transfer completed callback */
5487 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
5488
5489 /* Set the DMA error callback */
5490 hdma->XferErrorCallback = HRTIM_DMAError ;
5491
5492 /* Enable the DMA channel */
5493 HAL_DMA_Start_IT(hdma,
5494 BurstBufferAddress,
5495 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
5496 BurstBufferLength);
5497
5498 hhrtim->State = HAL_HRTIM_STATE_READY;
5499
5500 /* Process Unlocked */
5501 __HAL_UNLOCK(hhrtim);
5502
5503 return HAL_OK;
5504 }
5505
5506 /**
5507 * @brief Enables the transfer from preload to active registers for one
5508 * or several timing units (including master timer).
5509 * @param hhrtim pointer to HAL HRTIM handle
5510 * @param Timers Timer(s) concerned by the register preload enabling command
5511 * This parameter can be any combination of the following values:
5512 * @arg HRTIM_TIMERUPDATE_MASTER
5513 * @arg HRTIM_TIMERUPDATE_A
5514 * @arg HRTIM_TIMERUPDATE_B
5515 * @arg HRTIM_TIMERUPDATE_C
5516 * @arg HRTIM_TIMERUPDATE_D
5517 * @arg HRTIM_TIMERUPDATE_E
5518 * @retval HAL status
5519 */
5520 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
5521 uint32_t Timers)
5522 {
5523 /* Check the parameters */
5524 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5525
5526 /* Process Locked */
5527 __HAL_LOCK(hhrtim);
5528
5529 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5530
5531 /* Enable timer(s) registers update */
5532 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
5533
5534 hhrtim->State = HAL_HRTIM_STATE_READY;
5535
5536 /* Process Unlocked */
5537 __HAL_UNLOCK(hhrtim);
5538
5539 return HAL_OK;
5540 }
5541
5542 /**
5543 * @brief Disables the transfer from preload to active registers for one
5544 * or several timing units (including master timer).
5545 * @param hhrtim pointer to HAL HRTIM handle
5546 * @param Timers Timer(s) concerned by the register preload disabling command
5547 * This parameter can be any combination of the following values:
5548 * @arg HRTIM_TIMERUPDATE_MASTER
5549 * @arg HRTIM_TIMERUPDATE_A
5550 * @arg HRTIM_TIMERUPDATE_B
5551 * @arg HRTIM_TIMERUPDATE_C
5552 * @arg HRTIM_TIMERUPDATE_D
5553 * @arg HRTIM_TIMERUPDATE_E
5554 * @retval HAL status
5555 */
5556 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
5557 uint32_t Timers)
5558 {
5559 /* Check the parameters */
5560 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
5561
5562 /* Process Locked */
5563 __HAL_LOCK(hhrtim);
5564
5565 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5566
5567 /* Enable timer(s) registers update */
5568 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
5569
5570 hhrtim->State = HAL_HRTIM_STATE_READY;
5571
5572 /* Process Unlocked */
5573 __HAL_UNLOCK(hhrtim);
5574
5575 return HAL_OK;
5576 }
5577
5578 /**
5579 * @}
5580 */
5581
5582 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
5583 * @brief Peripheral State functions
5584 @verbatim
5585 ===============================================================================
5586 ##### Peripheral State functions #####
5587 ===============================================================================
5588 [..] This section provides functions used to get HRTIM or HRTIM timer
5589 specific information:
5590 (+) Get HRTIM HAL state
5591 (+) Get captured value
5592 (+) Get HRTIM timer output level
5593 (+) Get HRTIM timer output state
5594 (+) Get delayed protection status
5595 (+) Get burst status
5596 (+) Get current push-pull status
5597 (+) Get idle push-pull status
5598
5599 @endverbatim
5600 * @{
5601 */
5602
5603 /**
5604 * @brief return the HRTIM HAL state
5605 * @param hhrtim pointer to HAL HRTIM handle
5606 * @retval HAL state
5607 */
5608 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
5609 {
5610 /* Return ADC state */
5611 return hhrtim->State;
5612 }
5613
5614 /**
5615 * @brief Returns actual value of the capture register of the designated capture unit
5616 * @param hhrtim pointer to HAL HRTIM handle
5617 * @param TimerIdx Timer index
5618 * This parameter can be one of the following values:
5619 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5620 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5621 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5622 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5623 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5624 * @param CaptureUnit Capture unit to trig
5625 * This parameter can be one of the following values:
5626 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5627 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5628 * @retval Captured value
5629 */
5630 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
5631 uint32_t TimerIdx,
5632 uint32_t CaptureUnit)
5633 {
5634 uint32_t captured_value = 0U;
5635
5636 /* Check parameters */
5637 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5638 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
5639
5640 /* Read captured value */
5641 switch (CaptureUnit)
5642 {
5643 case HRTIM_CAPTUREUNIT_1:
5644 {
5645 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
5646 }
5647 break;
5648 case HRTIM_CAPTUREUNIT_2:
5649 {
5650 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
5651 }
5652 break;
5653 default:
5654 break;
5655 }
5656
5657 return captured_value;
5658 }
5659
5660 /**
5661 * @brief Returns actual level (active or inactive) of the designated output
5662 * @param hhrtim pointer to HAL HRTIM handle
5663 * @param TimerIdx Timer index
5664 * This parameter can be one of the following values:
5665 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5666 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5667 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5668 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5669 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5670 * @param Output Timer output
5671 * This parameter can be one of the following values:
5672 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5673 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5674 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5675 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5676 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5677 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5678 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5679 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5680 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5681 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5682 * @retval Output level
5683 * @note Returned output level is taken before the output stage (chopper,
5684 * polarity).
5685 */
5686 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
5687 uint32_t TimerIdx,
5688 uint32_t Output)
5689 {
5690 uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5691
5692 /* Check parameters */
5693 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5694
5695 /* Read the output level */
5696 switch (Output)
5697 {
5698 case HRTIM_OUTPUT_TA1:
5699 case HRTIM_OUTPUT_TB1:
5700 case HRTIM_OUTPUT_TC1:
5701 case HRTIM_OUTPUT_TD1:
5702 case HRTIM_OUTPUT_TE1:
5703 {
5704 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
5705 {
5706 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
5707 }
5708 else
5709 {
5710 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5711 }
5712 }
5713 break;
5714 case HRTIM_OUTPUT_TA2:
5715 case HRTIM_OUTPUT_TB2:
5716 case HRTIM_OUTPUT_TC2:
5717 case HRTIM_OUTPUT_TD2:
5718 case HRTIM_OUTPUT_TE2:
5719 {
5720 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
5721 {
5722 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
5723 }
5724 else
5725 {
5726 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
5727 }
5728 }
5729 break;
5730 default:
5731 break;
5732 }
5733
5734 return output_level;
5735 }
5736
5737 /**
5738 * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
5739 * @param hhrtim pointer to HAL HRTIM handle
5740 * @param TimerIdx Timer index
5741 * This parameter can be one of the following values:
5742 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5743 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5744 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5745 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5746 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5747 * @param Output Timer output
5748 * This parameter can be one of the following values:
5749 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5750 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5751 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5752 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5753 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5754 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5755 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5756 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5757 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
5758 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
5759 * @retval Output state
5760 */
5761 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
5762 uint32_t TimerIdx,
5763 uint32_t Output)
5764 {
5765 uint32_t output_bit = 0U;
5766 uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
5767
5768 /* Check parameters */
5769 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5770
5771 /* Set output state according to output control status and output disable status */
5772 switch (Output)
5773 {
5774 case HRTIM_OUTPUT_TA1:
5775 {
5776 output_bit = HRTIM_OENR_TA1OEN;
5777 }
5778 break;
5779 case HRTIM_OUTPUT_TA2:
5780 {
5781 output_bit = HRTIM_OENR_TA2OEN;
5782 }
5783 break;
5784 case HRTIM_OUTPUT_TB1:
5785 {
5786 output_bit = HRTIM_OENR_TB1OEN;
5787 }
5788 break;
5789 case HRTIM_OUTPUT_TB2:
5790 {
5791 output_bit = HRTIM_OENR_TB2OEN;
5792 }
5793 break;
5794 case HRTIM_OUTPUT_TC1:
5795 {
5796 output_bit = HRTIM_OENR_TC1OEN;
5797 }
5798 break;
5799 case HRTIM_OUTPUT_TC2:
5800 {
5801 output_bit = HRTIM_OENR_TC2OEN;
5802 }
5803 break;
5804 case HRTIM_OUTPUT_TD1:
5805 {
5806 output_bit = HRTIM_OENR_TD1OEN;
5807 }
5808 break;
5809 case HRTIM_OUTPUT_TD2:
5810 {
5811 output_bit = HRTIM_OENR_TD2OEN;
5812 }
5813 break;
5814 case HRTIM_OUTPUT_TE1:
5815 {
5816 output_bit = HRTIM_OENR_TE1OEN;
5817 }
5818 break;
5819 case HRTIM_OUTPUT_TE2:
5820 {
5821 output_bit = HRTIM_OENR_TE2OEN;
5822 }
5823 break;
5824 default:
5825 break;
5826 }
5827
5828 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != RESET)
5829 {
5830 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
5831 output_state = HRTIM_OUTPUTSTATE_RUN;
5832 }
5833 else
5834 {
5835 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != RESET)
5836 {
5837 /* Output is disabled: output in FAULT state */
5838 output_state = HRTIM_OUTPUTSTATE_FAULT;
5839 }
5840 else
5841 {
5842 /* Output is disabled: output in IDLE state */
5843 output_state = HRTIM_OUTPUTSTATE_IDLE;
5844 }
5845 }
5846
5847 return(output_state);
5848 }
5849
5850 /**
5851 * @brief Returns the level (active or inactive) of the designated output
5852 * when the delayed protection was triggered.
5853 * @param hhrtim pointer to HAL HRTIM handle
5854 * @param TimerIdx Timer index
5855 * This parameter can be one of the following values:
5856 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5857 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5858 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5859 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5860 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5861 * @param Output Timer output
5862 * This parameter can be one of the following values:
5863 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
5864 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
5865 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
5866 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
5867 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
5868 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
5869 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
5870 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
5871 * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
5872 * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
5873 * @retval Delayed protection status
5874 */
5875 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
5876 uint32_t TimerIdx,
5877 uint32_t Output)
5878 {
5879 uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5880
5881 /* Check parameters */
5882 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
5883
5884 /* Read the delayed protection status */
5885 switch (Output)
5886 {
5887 case HRTIM_OUTPUT_TA1:
5888 case HRTIM_OUTPUT_TB1:
5889 case HRTIM_OUTPUT_TC1:
5890 case HRTIM_OUTPUT_TD1:
5891 case HRTIM_OUTPUT_TE1:
5892 {
5893 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
5894 {
5895 /* Output 1 was active when the delayed idle protection was triggered */
5896 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
5897 }
5898 else
5899 {
5900 /* Output 1 was inactive when the delayed idle protection was triggered */
5901 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5902 }
5903 }
5904 break;
5905 case HRTIM_OUTPUT_TA2:
5906 case HRTIM_OUTPUT_TB2:
5907 case HRTIM_OUTPUT_TC2:
5908 case HRTIM_OUTPUT_TD2:
5909 case HRTIM_OUTPUT_TE2:
5910 {
5911 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
5912 {
5913 /* Output 2 was active when the delayed idle protection was triggered */
5914 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
5915 }
5916 else
5917 {
5918 /* Output 2 was inactive when the delayed idle protection was triggered */
5919 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
5920 }
5921 }
5922 break;
5923 default:
5924 break;
5925 }
5926
5927 return delayed_protection_status;
5928 }
5929
5930 /**
5931 * @brief Returns the actual status (active or inactive) of the burst mode controller
5932 * @param hhrtim pointer to HAL HRTIM handle
5933 * @retval Burst mode controller status
5934 */
5935 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
5936 {
5937 uint32_t burst_mode_status;
5938
5939 /* Read burst mode status */
5940 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
5941
5942 return burst_mode_status;
5943 }
5944
5945 /**
5946 * @brief Indicates on which output the signal is currently active (when the
5947 * push pull mode is enabled).
5948 * @param hhrtim pointer to HAL HRTIM handle
5949 * @param TimerIdx Timer index
5950 * This parameter can be one of the following values:
5951 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5952 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5953 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5954 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5955 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5956 * @retval Burst mode controller status
5957 */
5958 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
5959 uint32_t TimerIdx)
5960 {
5961 uint32_t current_pushpull_status;
5962
5963 /* Check the parameters */
5964 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5965
5966 /* Read current push pull status */
5967 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
5968
5969 return current_pushpull_status;
5970 }
5971
5972
5973 /**
5974 * @brief Indicates on which output the signal was applied, in push-pull mode,
5975 balanced fault mode or delayed idle mode, when the protection was triggered.
5976 * @param hhrtim pointer to HAL HRTIM handle
5977 * @param TimerIdx Timer index
5978 * This parameter can be one of the following values:
5979 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5980 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5981 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5982 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5983 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5984 * @retval Idle Push Pull Status
5985 */
5986 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
5987 uint32_t TimerIdx)
5988 {
5989 uint32_t idle_pushpull_status;
5990
5991 /* Check the parameters */
5992 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5993
5994 /* Read current push pull status */
5995 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
5996
5997 return idle_pushpull_status;
5998 }
5999
6000 /**
6001 * @}
6002 */
6003
6004 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
6005 * @brief Functions called when HRTIM generates an interrupt
6006 * 7 interrupts can be generated by the master timer:
6007 * - Master timer registers update
6008 * - Synchronization event received
6009 * - Master timer repetition event
6010 * - Master Compare 1 to 4 event
6011 * 14 interrupts can be generated by each timing unit:
6012 * - Delayed protection triggered
6013 * - Counter reset or roll-over event
6014 * - Output 1 and output 2 reset (transition active to inactive)
6015 * - Output 1 and output 2 set (transition inactive to active)
6016 * - Capture 1 and 2 events
6017 * - Timing unit registers update
6018 * - Repetition event
6019 * - Compare 1 to 4 event
6020 * 8 global interrupts are generated for the whole HRTIM:
6021 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
6022 * - DLL calibration done
6023 * - Burst mode period completed
6024 @verbatim
6025 ===============================================================================
6026 ##### HRTIM interrupts handling #####
6027 ===============================================================================
6028 [..]
6029 This subsection provides a set of functions allowing to manage the HRTIM
6030 interrupts:
6031 (+) HRTIM interrupt handler
6032 (+) Callback function called when Fault1 interrupt occurs
6033 (+) Callback function called when Fault2 interrupt occurs
6034 (+) Callback function called when Fault3 interrupt occurs
6035 (+) Callback function called when Fault4 interrupt occurs
6036 (+) Callback function called when Fault5 interrupt occurs
6037 (+) Callback function called when system Fault interrupt occurs
6038 (+) Callback function called when DLL ready interrupt occurs
6039 (+) Callback function called when burst mode period interrupt occurs
6040 (+) Callback function called when synchronization input interrupt occurs
6041 (+) Callback function called when a timer register update interrupt occurs
6042 (+) Callback function called when a timer repetition interrupt occurs
6043 (+) Callback function called when a compare 1 match interrupt occurs
6044 (+) Callback function called when a compare 2 match interrupt occurs
6045 (+) Callback function called when a compare 3 match interrupt occurs
6046 (+) Callback function called when a compare 4 match interrupt occurs
6047 (+) Callback function called when a capture 1 interrupt occurs
6048 (+) Callback function called when a capture 2 interrupt occurs
6049 (+) Callback function called when a delayed protection interrupt occurs
6050 (+) Callback function called when a timer counter reset interrupt occurs
6051 (+) Callback function called when a timer output 1 set interrupt occurs
6052 (+) Callback function called when a timer output 1 reset interrupt occurs
6053 (+) Callback function called when a timer output 2 set interrupt occurs
6054 (+) Callback function called when a timer output 2 reset interrupt occurs
6055 (+) Callback function called when a timer output 2 reset interrupt occurs
6056 (+) Callback function called upon completion of a burst DMA transfer
6057
6058 @endverbatim
6059 * @{
6060 */
6061
6062 /**
6063 * @brief This function handles HRTIM interrupt request.
6064 * @param hhrtim pointer to HAL HRTIM handle
6065 * @param TimerIdx Timer index
6066 * This parameter can be any value of @ref HRTIM_Timer_Index
6067 * @retval None
6068 */
6069 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
6070 uint32_t TimerIdx)
6071 {
6072 /* HRTIM interrupts handling */
6073 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
6074 {
6075 HRTIM_HRTIM_ISR(hhrtim);
6076 }
6077 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6078 {
6079 /* Master related interrupts handling */
6080 HRTIM_Master_ISR(hhrtim);
6081 }
6082 else
6083 {
6084 /* Timing unit related interrupts handling */
6085 HRTIM_Timer_ISR(hhrtim, TimerIdx);
6086 }
6087
6088 }
6089
6090 /**
6091 * @brief Callback function invoked when a fault 1 interrupt occured
6092 * @param hhrtim pointer to HAL HRTIM handle * @retval None
6093 * @retval None
6094 */
6095 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
6096 {
6097 /* Prevent unused argument(s) compilation warning */
6098 UNUSED(hhrtim);
6099
6100 /* NOTE : This function should not be modified, when the callback is needed,
6101 the HAL_HRTIM_Fault1Callback could be implenetd in the user file
6102 */
6103 }
6104
6105 /**
6106 * @brief Callback function invoked when a fault 2 interrupt occured
6107 * @param hhrtim pointer to HAL HRTIM handle
6108 * @retval None
6109 */
6110 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
6111 {
6112 /* Prevent unused argument(s) compilation warning */
6113 UNUSED(hhrtim);
6114
6115 /* NOTE : This function should not be modified, when the callback is needed,
6116 the HAL_HRTIM_Fault2Callback could be implenetd in the user file
6117 */
6118 }
6119
6120 /**
6121 * @brief Callback function invoked when a fault 3 interrupt occured
6122 * @param hhrtim pointer to HAL HRTIM handle
6123 * @retval None
6124 */
6125 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
6126 {
6127 /* Prevent unused argument(s) compilation warning */
6128 UNUSED(hhrtim);
6129
6130 /* NOTE : This function should not be modified, when the callback is needed,
6131 the HAL_HRTIM_Fault3Callback could be implenetd in the user file
6132 */
6133 }
6134
6135 /**
6136 * @brief Callback function invoked when a fault 4 interrupt occured
6137 * @param hhrtim pointer to HAL HRTIM handle
6138 * @retval None
6139 */
6140 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
6141 {
6142 /* Prevent unused argument(s) compilation warning */
6143 UNUSED(hhrtim);
6144
6145 /* NOTE : This function should not be modified, when the callback is needed,
6146 the HAL_HRTIM_Fault4Callback could be implenetd in the user file
6147 */
6148 }
6149
6150 /**
6151 * @brief Callback function invoked when a fault 5 interrupt occured
6152 * @param hhrtim pointer to HAL HRTIM handle
6153 * @retval None
6154 */
6155 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
6156 {
6157 /* Prevent unused argument(s) compilation warning */
6158 UNUSED(hhrtim);
6159
6160 /* NOTE : This function should not be modified, when the callback is needed,
6161 the HAL_HRTIM_Fault5Callback could be implenetd in the user file
6162 */
6163 }
6164
6165 /**
6166 * @brief Callback function invoked when a system fault interrupt occured
6167 * @param hhrtim pointer to HAL HRTIM handle
6168 * @retval None
6169 */
6170 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
6171 {
6172 /* Prevent unused argument(s) compilation warning */
6173 UNUSED(hhrtim);
6174
6175 /* NOTE : This function should not be modified, when the callback is needed,
6176 the HAL_HRTIM_SystemFaultCallback could be implenetd in the user file
6177 */
6178 }
6179
6180 /**
6181 * @brief Callback function invoked when the DLL calibration is completed
6182 * @param hhrtim pointer to HAL HRTIM handle
6183 * @retval None
6184 */
6185 __weak void HAL_HRTIM_DLLCalbrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
6186 {
6187 /* Prevent unused argument(s) compilation warning */
6188 UNUSED(hhrtim);
6189
6190 /* NOTE : This function should not be modified, when the callback is needed,
6191 the HAL_HRTIM_DLLCalbrationCallback could be implenetd in the user file
6192 */
6193 }
6194
6195 /**
6196 * @brief Callback function invoked when the end of the burst mode period is reached
6197 * @param hhrtim pointer to HAL HRTIM handle
6198 * @retval None
6199 */
6200 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
6201 {
6202 /* Prevent unused argument(s) compilation warning */
6203 UNUSED(hhrtim);
6204
6205 /* NOTE : This function should not be modified, when the callback is needed,
6206 the HAL_HRTIM_BurstModeCallback could be implenetd in the user file
6207 */
6208 }
6209
6210 /**
6211 * @brief Callback function invoked when a synchronization input event is received
6212 * @param hhrtim pointer to HAL HRTIM handle
6213 * @retval None
6214 */
6215 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
6216 {
6217 /* Prevent unused argument(s) compilation warning */
6218 UNUSED(hhrtim);
6219
6220 /* NOTE : This function should not be modified, when the callback is needed,
6221 the HAL_HRTIM_Master_SynchronizationEventCallback could be implenetd in the user file
6222 */
6223 }
6224
6225 /**
6226 * @brief Callback function invoked when timer registers are updated
6227 * @param hhrtim pointer to HAL HRTIM handle
6228 * @param TimerIdx Timer index
6229 * This parameter can be one of the following values:
6230 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6231 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6232 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6233 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6234 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6235 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6236 * @retval None
6237 */
6238 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
6239 uint32_t TimerIdx)
6240 {
6241 /* Prevent unused argument(s) compilation warning */
6242 UNUSED(hhrtim);
6243 UNUSED(TimerIdx);
6244
6245 /* NOTE : This function should not be modified, when the callback is needed,
6246 the HAL_HRTIM_Master_RegistersUpdateCallback could be implenetd in the user file
6247 */
6248 }
6249
6250 /**
6251 * @brief Callback function invoked when timer repetition period has elapsed
6252 * @param hhrtim pointer to HAL HRTIM handle
6253 * @param TimerIdx Timer index
6254 * This parameter can be one of the following values:
6255 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6256 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6257 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6258 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6259 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6260 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6261 * @retval None
6262 */
6263 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
6264 uint32_t TimerIdx)
6265 {
6266 /* Prevent unused argument(s) compilation warning */
6267 UNUSED(hhrtim);
6268 UNUSED(TimerIdx);
6269
6270 /* NOTE : This function should not be modified, when the callback is needed,
6271 the HAL_HRTIM_Master_RepetitionEventCallback could be implenetd in the user file
6272 */
6273 }
6274
6275 /**
6276 * @brief Callback function invoked when the timer counter matches the value
6277 * programmed in the compare 1 register
6278 * @param hhrtim pointer to HAL HRTIM handle
6279 * @param TimerIdx Timer index
6280 * This parameter can be one of the following values:
6281 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6282 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6283 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6284 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6285 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6286 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6287 * @retval None
6288 */
6289 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6290 uint32_t TimerIdx)
6291 {
6292 /* Prevent unused argument(s) compilation warning */
6293 UNUSED(hhrtim);
6294 UNUSED(TimerIdx);
6295
6296 /* NOTE : This function should not be modified, when the callback is needed,
6297 the HAL_HRTIM_Master_Compare1EventCallback could be implenetd in the user file
6298 */
6299 }
6300
6301 /**
6302 * @brief Callback function invoked when the timer counter matches the value
6303 * programmed in the compare 2 register
6304 * @param hhrtim pointer to HAL HRTIM handle
6305 * @retval None
6306 * @param TimerIdx Timer index
6307 * This parameter can be one of the following values:
6308 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6309 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6310 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6311 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6312 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6313 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6314 */
6315 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6316 uint32_t TimerIdx)
6317 {
6318 /* Prevent unused argument(s) compilation warning */
6319 UNUSED(hhrtim);
6320 UNUSED(TimerIdx);
6321
6322 /* NOTE : This function should not be modified, when the callback is needed,
6323 the HAL_HRTIM_Master_Compare2EventCallback could be implenetd in the user file
6324 */
6325 }
6326
6327 /**
6328 * @brief Callback function invoked when the timer counter matches the value
6329 * programmed in the compare 3 register
6330 * @param hhrtim pointer to HAL HRTIM handle
6331 * @param TimerIdx Timer index
6332 * This parameter can be one of the following values:
6333 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6334 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6335 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6336 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6337 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6338 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6339 * @retval None
6340 */
6341 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
6342 uint32_t TimerIdx)
6343 {
6344 /* Prevent unused argument(s) compilation warning */
6345 UNUSED(hhrtim);
6346 UNUSED(TimerIdx);
6347
6348 /* NOTE : This function should not be modified, when the callback is needed,
6349 the HAL_HRTIM_Master_Compare3EventCallback could be implenetd in the user file
6350 */
6351 }
6352
6353 /**
6354 * @brief Callback function invoked when the timer counter matches the value
6355 * programmed in the compare 4 register.
6356 * @param hhrtim pointer to HAL HRTIM handle
6357 * @param TimerIdx Timer index
6358 * This parameter can be one of the following values:
6359 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6360 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6361 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6362 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6363 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6364 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6365 * @retval None
6366 */
6367 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
6368 uint32_t TimerIdx)
6369 {
6370 /* Prevent unused argument(s) compilation warning */
6371 UNUSED(hhrtim);
6372 UNUSED(TimerIdx);
6373
6374 /* NOTE : This function should not be modified, when the callback is needed,
6375 the HAL_HRTIM_Master_Compare4EventCallback could be implenetd in the user file
6376 */
6377 }
6378
6379 /**
6380 * @brief Callback function invoked when the timer x capture 1 event occurs
6381 * @param hhrtim pointer to HAL HRTIM handle
6382 * @param TimerIdx Timer index
6383 * This parameter can be one of the following values:
6384 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6385 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6386 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6387 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6388 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6389 * @retval None
6390 */
6391 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
6392 uint32_t TimerIdx)
6393 {
6394 /* Prevent unused argument(s) compilation warning */
6395 UNUSED(hhrtim);
6396 UNUSED(TimerIdx);
6397
6398 /* NOTE : This function should not be modified, when the callback is needed,
6399 the HAL_HRTIM_Timer_Capture1EventCallback could be implenetd in the user file
6400 */
6401 }
6402
6403 /**
6404 * @brief Callback function invoked when the timer x capture 2 event occurs
6405 * @param hhrtim pointer to HAL HRTIM handle
6406 * @param TimerIdx Timer index
6407 * This parameter can be one of the following values:
6408 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6409 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6410 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6411 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6412 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6413 * @retval None
6414 */
6415 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
6416 uint32_t TimerIdx)
6417 {
6418 /* Prevent unused argument(s) compilation warning */
6419 UNUSED(hhrtim);
6420 UNUSED(TimerIdx);
6421
6422 /* NOTE : This function should not be modified, when the callback is needed,
6423 the HAL_HRTIM_Timer_Capture2EventCallback could be implenetd in the user file
6424 */
6425 }
6426
6427 /**
6428 * @brief Callback function invoked when the delayed idle or balanced idle mode is
6429 * entered.
6430 * @param hhrtim pointer to HAL HRTIM handle
6431 * @param TimerIdx Timer index
6432 * This parameter can be one of the following values:
6433 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6434 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6435 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6436 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6437 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6438 * @retval None
6439 */
6440 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
6441 uint32_t TimerIdx)
6442 {
6443 /* Prevent unused argument(s) compilation warning */
6444 UNUSED(hhrtim);
6445 UNUSED(TimerIdx);
6446
6447 /* NOTE : This function should not be modified, when the callback is needed,
6448 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implenetd in the user file
6449 */
6450 }
6451
6452 /**
6453 * @brief Callback function invoked when the timer x counter reset/roll-over
6454 * event occurs.
6455 * @param hhrtim pointer to HAL HRTIM handle
6456 * @param TimerIdx Timer index
6457 * This parameter can be one of the following values:
6458 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6459 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6460 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6461 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6462 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6463 * @retval None
6464 */
6465 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
6466 uint32_t TimerIdx)
6467 {
6468 /* Prevent unused argument(s) compilation warning */
6469 UNUSED(hhrtim);
6470 UNUSED(TimerIdx);
6471
6472 /* NOTE : This function should not be modified, when the callback is needed,
6473 the HAL_HRTIM_Timer_CounterResetCallback could be implenetd in the user file
6474 */
6475 }
6476
6477 /**
6478 * @brief Callback function invoked when the timer x output 1 is set
6479 * @param hhrtim pointer to HAL HRTIM handle
6480 * @param TimerIdx Timer index
6481 * This parameter can be one of the following values:
6482 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6483 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6484 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6485 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6486 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6487 * @retval None
6488 */
6489 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
6490 uint32_t TimerIdx)
6491 {
6492 /* Prevent unused argument(s) compilation warning */
6493 UNUSED(hhrtim);
6494 UNUSED(TimerIdx);
6495
6496 /* NOTE : This function should not be modified, when the callback is needed,
6497 the HAL_HRTIM_Timer_Output1SetCallback could be implenetd in the user file
6498 */
6499 }
6500
6501 /**
6502 * @brief Callback function invoked when the timer x output 1 is reset
6503 * @param hhrtim pointer to HAL HRTIM handle
6504 * @param TimerIdx Timer index
6505 * This parameter can be one of the following values:
6506 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6507 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6508 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6509 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6510 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6511 * @retval None
6512 */
6513 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6514 uint32_t TimerIdx)
6515 {
6516 /* Prevent unused argument(s) compilation warning */
6517 UNUSED(hhrtim);
6518 UNUSED(TimerIdx);
6519
6520 /* NOTE : This function should not be modified, when the callback is needed,
6521 the HAL_HRTIM_Timer_Output1ResetCallback could be implenetd in the user file
6522 */
6523 }
6524
6525 /**
6526 * @brief Callback function invoked when the timer x output 2 is set
6527 * @param hhrtim pointer to HAL HRTIM handle
6528 * @param TimerIdx Timer index
6529 * This parameter can be one of the following values:
6530 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6531 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6532 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6533 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6534 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6535 * @retval None
6536 */
6537 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
6538 uint32_t TimerIdx)
6539 {
6540 /* Prevent unused argument(s) compilation warning */
6541 UNUSED(hhrtim);
6542 UNUSED(TimerIdx);
6543
6544 /* NOTE : This function should not be modified, when the callback is needed,
6545 the HAL_HRTIM_Timer_Output2SetCallback could be implenetd in the user file
6546 */
6547 }
6548
6549 /**
6550 * @brief Callback function invoked when the timer x output 2 is reset
6551 * @param hhrtim pointer to HAL HRTIM handle
6552 * @param TimerIdx Timer index
6553 * This parameter can be one of the following values:
6554 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6555 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6556 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6557 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6558 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6559 * @retval None
6560 */
6561 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
6562 uint32_t TimerIdx)
6563 {
6564 /* Prevent unused argument(s) compilation warning */
6565 UNUSED(hhrtim);
6566 UNUSED(TimerIdx);
6567
6568 /* NOTE : This function should not be modified, when the callback is needed,
6569 the HAL_HRTIM_Timer_Output2ResetCallback could be implenetd in the user file
6570 */
6571 }
6572
6573 /**
6574 * @brief Callback function invoked when a DMA burst transfer is completed
6575 * @param hhrtim pointer to HAL HRTIM handle
6576 * @param TimerIdx Timer index
6577 * This parameter can be one of the following values:
6578 * @arg HRTIM_TIMERINDEX_MASTER for master timer
6579 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6580 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6581 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6582 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6583 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6584 * @retval None
6585 */
6586 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
6587 uint32_t TimerIdx)
6588 {
6589 /* Prevent unused argument(s) compilation warning */
6590 UNUSED(hhrtim);
6591 UNUSED(TimerIdx);
6592
6593 /* NOTE : This function should not be modified, when the callback is needed,
6594 the HAL_HRTIM_BurstDMATransferCallback could be implenetd in the user file
6595 */
6596 }
6597
6598 /**
6599 * @brief Callback function invoked when a DMA error occurs
6600 * @param hhrtim pointer to HAL HRTIM handle
6601 * @retval None
6602 */
6603 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
6604 {
6605 /* Prevent unused argument(s) compilation warning */
6606 UNUSED(hhrtim);
6607
6608 /* NOTE : This function should not be modified, when the callback is needed,
6609 the HAL_HRTIM_ErrorCallback could be implenetd in the user file
6610 */
6611 }
6612
6613 /**
6614 * @}
6615 */
6616
6617 /**
6618 * @}
6619 */
6620
6621 /** @addtogroup HRTIM_Private_Functions HRTIM Private Functions
6622 * @{
6623 */
6624
6625 /**
6626 * @brief Configures the master timer time base
6627 * @param hhrtim pointer to HAL HRTIM handle
6628 * @param pTimeBaseCfg pointer to the time base configuration structure
6629 * @retval None
6630 */
6631 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
6632 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
6633 {
6634 uint32_t hrtim_mcr;
6635
6636 /* Configure master timer */
6637 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
6638
6639 /* Set the prescaler ratio */
6640 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
6641 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
6642
6643 /* Set the operating mode */
6644 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
6645 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
6646
6647 /* Update the HRTIM registers */
6648 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
6649 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
6650 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
6651 }
6652
6653 /**
6654 * @brief Configures timing unit (timer A to timer E) time base
6655 * @param hhrtim pointer to HAL HRTIM handle
6656 * @param TimerIdx Timer index
6657 * @param pTimeBaseCfg pointer to the time base configuration structure
6658 * @retval None
6659 */
6660 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
6661 uint32_t TimerIdx ,
6662 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
6663 {
6664 uint32_t hrtim_timcr;
6665
6666 /* Configure master timing unit */
6667 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
6668
6669 /* Set the prescaler ratio */
6670 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
6671 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
6672
6673 /* Set the operating mode */
6674 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
6675 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
6676
6677 /* Update the HRTIM registers */
6678 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
6679 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
6680 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
6681 }
6682
6683 /**
6684 * @brief Configures the master timer in waveform mode
6685 * @param hhrtim pointer to HAL HRTIM handle
6686 * @param pTimerCfg pointer to the timer configuration data structure
6687 * @retval None
6688 */
6689 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
6690 HRTIM_TimerCfgTypeDef * pTimerCfg)
6691 {
6692 uint32_t hrtim_mcr;
6693 uint32_t hrtim_bmcr;
6694
6695 /* Configure master timer */
6696 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
6697 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
6698
6699 /* Enable/Disable the half mode */
6700 hrtim_mcr &= ~(HRTIM_MCR_HALF);
6701 hrtim_mcr |= pTimerCfg->HalfModeEnable;
6702
6703 /* Enable/Disable the timer start upon synchronization event reception */
6704 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
6705 hrtim_mcr |= pTimerCfg->StartOnSync;
6706
6707 /* Enable/Disable the timer reset upon synchronization event reception */
6708 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
6709 hrtim_mcr |= pTimerCfg->ResetOnSync;
6710
6711 /* Enable/Disable the DAC synchronization event generation */
6712 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
6713 hrtim_mcr |= pTimerCfg->DACSynchro;
6714
6715 /* Enable/Disable preload meachanism for timer registers */
6716 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
6717 hrtim_mcr |= pTimerCfg->PreloadEnable;
6718
6719 /* Master timer registers update handling */
6720 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
6721 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
6722
6723 /* Enable/Disable registers update on repetition */
6724 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
6725 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
6726
6727 /* Set the timer burst mode */
6728 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
6729 hrtim_bmcr |= pTimerCfg->BurstMode;
6730
6731 /* Update the HRTIM registers */
6732 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
6733 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
6734 }
6735
6736 /**
6737 * @brief Configures timing unit (timer A to timer E) in waveform mode
6738 * @param hhrtim pointer to HAL HRTIM handle
6739 * @param TimerIdx Timer index
6740 * @param pTimerCfg pointer to the timer configuration data structure
6741 * @retval None
6742 */
6743 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
6744 uint32_t TimerIdx,
6745 HRTIM_TimerCfgTypeDef * pTimerCfg)
6746 {
6747 uint32_t hrtim_timcr;
6748 uint32_t hrtim_timfltr;
6749 uint32_t hrtim_timoutr;
6750 uint32_t hrtim_timrstr;
6751 uint32_t hrtim_bmcr;
6752
6753 /* UPDGAT bitfield must be reset before programming a new value */
6754 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
6755
6756 /* Configure timing unit (Timer A to Timer E) */
6757 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
6758 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
6759 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
6760 hrtim_timrstr = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR;
6761 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
6762
6763 /* Enable/Disable the half mode */
6764 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
6765 hrtim_timcr |= pTimerCfg->HalfModeEnable;
6766
6767 /* Enable/Disable the timer start upon synchronization event reception */
6768 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
6769 hrtim_timcr |= pTimerCfg->StartOnSync;
6770
6771 /* Enable/Disable the timer reset upon synchronization event reception */
6772 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
6773 hrtim_timcr |= pTimerCfg->ResetOnSync;
6774
6775 /* Enable/Disable the DAC synchronization event generation */
6776 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
6777 hrtim_timcr |= pTimerCfg->DACSynchro;
6778
6779 /* Enable/Disable preload meachanism for timer registers */
6780 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
6781 hrtim_timcr |= pTimerCfg->PreloadEnable;
6782
6783 /* Timing unit registers update handling */
6784 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
6785 hrtim_timcr |= pTimerCfg->UpdateGating;
6786
6787 /* Enable/Disable registers update on repetition */
6788 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
6789 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
6790 {
6791 hrtim_timcr |= HRTIM_TIMCR_TREPU;
6792 }
6793
6794 /* Set the push-pull mode */
6795 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
6796 hrtim_timcr |= pTimerCfg->PushPull;
6797
6798 /* Enable/Disable registers update on timer counter reset */
6799 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
6800 hrtim_timcr |= pTimerCfg->ResetUpdate;
6801
6802 /* Set the timer update trigger */
6803 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
6804 hrtim_timcr |= pTimerCfg->UpdateTrigger;
6805
6806
6807 /* Enable/Disable the fault channel at timer level */
6808 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
6809 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
6810
6811 /* Lock/Unlock fault sources at timer level */
6812 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
6813 hrtim_timfltr |= pTimerCfg->FaultLock;
6814
6815 /* The deadtime cannot be used simultaneously with the push-pull mode */
6816 if (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_DISABLED)
6817 {
6818 /* Enable/Disable dead time insertion at timer level */
6819 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
6820 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
6821 }
6822
6823 /* Enable/Disable delayed protection at timer level
6824 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
6825 Balanced Idle is only available in push-pull mode
6826 */
6827 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
6828 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
6829 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
6830 {
6831 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
6832 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
6833 }
6834
6835 /* Set the timer counter reset trigger */
6836 hrtim_timrstr = pTimerCfg->ResetTrigger;
6837
6838 /* Set the timer burst mode */
6839 switch (TimerIdx)
6840 {
6841 case HRTIM_TIMERINDEX_TIMER_A:
6842 {
6843 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
6844 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
6845 }
6846 break;
6847 case HRTIM_TIMERINDEX_TIMER_B:
6848 {
6849 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
6850 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
6851 }
6852 break;
6853 case HRTIM_TIMERINDEX_TIMER_C:
6854 {
6855 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
6856 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
6857 }
6858 break;
6859 case HRTIM_TIMERINDEX_TIMER_D:
6860 {
6861 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
6862 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
6863 }
6864 break;
6865 case HRTIM_TIMERINDEX_TIMER_E:
6866 {
6867 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
6868 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
6869 }
6870 break;
6871 default:
6872 break;
6873 }
6874
6875 /* Update the HRTIM registers */
6876 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
6877 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
6878 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
6879 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
6880 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
6881 }
6882
6883 /**
6884 * @brief Configures a compare unit
6885 * @param hhrtim pointer to HAL HRTIM handle
6886 * @param TimerIdx Timer index
6887 * @param CompareUnit Compare unit identifier
6888 * @param pCompareCfg pointer to the compare unit configuration data structure
6889 * @retval None
6890 */
6891 static void HRTIM_CompareUnitConfig(HRTIM_HandleTypeDef * hhrtim,
6892 uint32_t TimerIdx,
6893 uint32_t CompareUnit,
6894 HRTIM_CompareCfgTypeDef * pCompareCfg)
6895 {
6896 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
6897 {
6898 /* Configure the compare unit of the master timer */
6899 switch (CompareUnit)
6900 {
6901 case HRTIM_COMPAREUNIT_1:
6902 {
6903 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
6904 }
6905 break;
6906 case HRTIM_COMPAREUNIT_2:
6907 {
6908 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
6909 }
6910 break;
6911 case HRTIM_COMPAREUNIT_3:
6912 {
6913 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
6914 }
6915 break;
6916 case HRTIM_COMPAREUNIT_4:
6917 {
6918 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
6919 }
6920 break;
6921 default:
6922 break;
6923 }
6924 }
6925 else
6926 {
6927 /* Configure the compare unit of the timing unit */
6928 switch (CompareUnit)
6929 {
6930 case HRTIM_COMPAREUNIT_1:
6931 {
6932 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
6933 }
6934 break;
6935 case HRTIM_COMPAREUNIT_2:
6936 {
6937 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
6938 }
6939 break;
6940 case HRTIM_COMPAREUNIT_3:
6941 {
6942 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
6943 }
6944 break;
6945 case HRTIM_COMPAREUNIT_4:
6946 {
6947 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
6948 }
6949 break;
6950 default:
6951 break;
6952 }
6953 }
6954 }
6955
6956 /**
6957 * @brief Configures a capture unit
6958 * @param hhrtim pointer to HAL HRTIM handle
6959 * @param TimerIdx Timer index
6960 * @param CaptureUnit Capture unit identifier
6961 * @param Event Event reference
6962 * @retval None
6963 */
6964 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
6965 uint32_t TimerIdx,
6966 uint32_t CaptureUnit,
6967 uint32_t Event)
6968 {
6969 uint32_t CaptureTrigger = 0xFFFFFFFFU;
6970
6971 switch (Event)
6972 {
6973 case HRTIM_EVENT_1:
6974 {
6975 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
6976 }
6977 break;
6978 case HRTIM_EVENT_2:
6979 {
6980 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
6981 }
6982 break;
6983 case HRTIM_EVENT_3:
6984 {
6985 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
6986 }
6987 break;
6988 case HRTIM_EVENT_4:
6989 {
6990 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
6991 }
6992 break;
6993 case HRTIM_EVENT_5:
6994 {
6995 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
6996 }
6997 break;
6998 case HRTIM_EVENT_6:
6999 {
7000 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
7001 }
7002 break;
7003 case HRTIM_EVENT_7:
7004 {
7005 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
7006 }
7007 break;
7008 case HRTIM_EVENT_8:
7009 {
7010 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
7011 }
7012 break;
7013 case HRTIM_EVENT_9:
7014 {
7015 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
7016 }
7017 break;
7018 case HRTIM_EVENT_10:
7019 {
7020 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
7021 }
7022 break;
7023 default:
7024 break;
7025 }
7026
7027 switch (CaptureUnit)
7028 {
7029 case HRTIM_CAPTUREUNIT_1:
7030 {
7031 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
7032 }
7033 break;
7034 case HRTIM_CAPTUREUNIT_2:
7035 {
7036 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
7037 }
7038 break;
7039 default:
7040 break;
7041 }
7042 }
7043
7044 /**
7045 * @brief Configures the output of a timing unit
7046 * @param hhrtim pointer to HAL HRTIM handle
7047 * @param TimerIdx Timer index
7048 * @param Output timing unit output identifier
7049 * @param pOutputCfg pointer to the output configuration data structure
7050 * @retval None
7051 */
7052 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
7053 uint32_t TimerIdx,
7054 uint32_t Output,
7055 HRTIM_OutputCfgTypeDef * pOutputCfg)
7056 {
7057 uint32_t hrtim_outr;
7058 uint32_t hrtim_dtr;
7059
7060 uint32_t shift = 0xFFFFFFFFU;
7061
7062 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
7063 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
7064
7065 switch (Output)
7066 {
7067 case HRTIM_OUTPUT_TA1:
7068 case HRTIM_OUTPUT_TB1:
7069 case HRTIM_OUTPUT_TC1:
7070 case HRTIM_OUTPUT_TD1:
7071 case HRTIM_OUTPUT_TE1:
7072 {
7073 /* Set the output set/reset crossbar */
7074 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
7075 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
7076
7077 shift = 0U;
7078 }
7079 break;
7080 case HRTIM_OUTPUT_TA2:
7081 case HRTIM_OUTPUT_TB2:
7082 case HRTIM_OUTPUT_TC2:
7083 case HRTIM_OUTPUT_TD2:
7084 case HRTIM_OUTPUT_TE2:
7085 {
7086 /* Set the output set/reset crossbar */
7087 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
7088 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
7089
7090 shift = 16U;
7091 }
7092 break;
7093 default:
7094 break;
7095 }
7096
7097 /* Clear output config */
7098 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
7099 HRTIM_OUTR_IDLM1 |
7100 HRTIM_OUTR_IDLES1|
7101 HRTIM_OUTR_FAULT1|
7102 HRTIM_OUTR_CHP1 |
7103 HRTIM_OUTR_DIDL1) << shift);
7104
7105 /* Set the polarity */
7106 hrtim_outr |= (pOutputCfg->Polarity << shift);
7107
7108 /* Set the IDLE mode */
7109 hrtim_outr |= (pOutputCfg->IdleMode << shift);
7110
7111 /* Set the IDLE state */
7112 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
7113
7114 /* Set the FAULT state */
7115 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
7116
7117 /* Set the chopper mode */
7118 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
7119
7120 /* Set the burst mode entry mode : deadtime insertion when entering the idle
7121 state during a burst mode operation is allowed only under the following
7122 conditions:
7123 - the outputs is active during the burst mode (IDLES=1U)
7124 - positive deadtimes (SDTR/SDTF set to 0U)
7125 */
7126 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
7127 ((hrtim_dtr & HRTIM_DTR_SDTR) == RESET) &&
7128 ((hrtim_dtr & HRTIM_DTR_SDTF) == RESET))
7129 {
7130 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
7131 }
7132
7133 /* Update HRTIM register */
7134 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
7135 }
7136
7137 /**
7138 * @brief Configures an external event channel
7139 * @param hhrtim pointer to HAL HRTIM handle
7140 * @param Event Event channel identifier
7141 * @param pEventCfg pointer to the event channel configuration data structure
7142 * @retval None
7143 */
7144 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
7145 uint32_t Event,
7146 HRTIM_EventCfgTypeDef *pEventCfg)
7147 {
7148 uint32_t hrtim_eecr1;
7149 uint32_t hrtim_eecr2;
7150 uint32_t hrtim_eecr3;
7151
7152 /* Configure external event channel */
7153 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
7154 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
7155 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
7156
7157 switch (Event)
7158 {
7159 case HRTIM_EVENT_1:
7160 {
7161 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
7162 hrtim_eecr1 |= pEventCfg->Source;
7163 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
7164 hrtim_eecr1 |= pEventCfg->Sensitivity;
7165 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
7166 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7167 /* Update the HRTIM registers (EE1FAST bit) */
7168 hrtim_eecr1 |= pEventCfg->FastMode;
7169 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7170 }
7171 break;
7172 case HRTIM_EVENT_2:
7173 {
7174 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
7175 hrtim_eecr1 |= (pEventCfg->Source << 6U);
7176 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR1_EE2POL));
7177 hrtim_eecr1 |= (pEventCfg->Sensitivity << 6U);
7178 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
7179 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7180 /* Update the HRTIM registers (EE2FAST bit) */
7181 hrtim_eecr1 |= (pEventCfg->FastMode << 6U);
7182 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7183 }
7184 break;
7185 case HRTIM_EVENT_3:
7186 {
7187 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
7188 hrtim_eecr1 |= (pEventCfg->Source << 12U);
7189 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR1_EE3POL));
7190 hrtim_eecr1 |= (pEventCfg->Sensitivity << 12U);
7191 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
7192 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7193 /* Update the HRTIM registers (EE3FAST bit) */
7194 hrtim_eecr1 |= (pEventCfg->FastMode << 12U);
7195 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7196 }
7197 break;
7198 case HRTIM_EVENT_4:
7199 {
7200 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
7201 hrtim_eecr1 |= (pEventCfg->Source << 18U);
7202 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR1_EE4POL));
7203 hrtim_eecr1 |= (pEventCfg->Sensitivity << 18U);
7204 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
7205 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7206 /* Update the HRTIM registers (EE4FAST bit) */
7207 hrtim_eecr1 |= (pEventCfg->FastMode << 18U);
7208 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7209 }
7210 break;
7211 case HRTIM_EVENT_5:
7212 {
7213 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
7214 hrtim_eecr1 |= (pEventCfg->Source << 24U);
7215 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR1_EE5POL));
7216 hrtim_eecr1 |= (pEventCfg->Sensitivity << 24U);
7217 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
7218 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7219 /* Update the HRTIM registers (EE5FAST bit) */
7220 hrtim_eecr1 |= (pEventCfg->FastMode << 24U);
7221 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
7222 }
7223 break;
7224 case HRTIM_EVENT_6:
7225 {
7226 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
7227 hrtim_eecr2 |= pEventCfg->Source;
7228 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
7229 hrtim_eecr2 |= pEventCfg->Sensitivity;
7230 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
7231 hrtim_eecr3 |= pEventCfg->Filter;
7232 /* Update the HRTIM registers */
7233 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7234 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7235 }
7236 break;
7237 case HRTIM_EVENT_7:
7238 {
7239 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
7240 hrtim_eecr2 |= (pEventCfg->Source << 6U);
7241 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & (HRTIM_EECR2_EE7POL));
7242 hrtim_eecr2 |= (pEventCfg->Sensitivity << 6U);
7243 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
7244 hrtim_eecr3 |= (pEventCfg->Filter << 6U);
7245 /* Update the HRTIM registers */
7246 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7247 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7248 }
7249 break;
7250 case HRTIM_EVENT_8:
7251 {
7252 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
7253 hrtim_eecr2 |= (pEventCfg->Source << 12U);
7254 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & (HRTIM_EECR2_EE8POL));
7255 hrtim_eecr2 |= (pEventCfg->Sensitivity << 12U);
7256 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
7257 hrtim_eecr3 |= (pEventCfg->Filter << 12U);
7258 /* Update the HRTIM registers */
7259 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7260 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7261 }
7262 break;
7263 case HRTIM_EVENT_9:
7264 {
7265 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
7266 hrtim_eecr2 |= (pEventCfg->Source << 18U);
7267 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & (HRTIM_EECR2_EE9POL));
7268 hrtim_eecr2 |= (pEventCfg->Sensitivity << 18U);
7269 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
7270 hrtim_eecr3 |= (pEventCfg->Filter << 18U);
7271 /* Update the HRTIM registers */
7272 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7273 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7274 }
7275 break;
7276 case HRTIM_EVENT_10:
7277 {
7278 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
7279 hrtim_eecr2 |= (pEventCfg->Source << 24U);
7280 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & (HRTIM_EECR2_EE10POL));
7281 hrtim_eecr2 |= (pEventCfg->Sensitivity << 24U);
7282 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
7283 hrtim_eecr3 |= (pEventCfg->Filter << 24U);
7284 /* Update the HRTIM registers */
7285 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
7286 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
7287 }
7288 break;
7289 default:
7290 break;
7291 }
7292 }
7293
7294 /**
7295 * @brief Configures the timer counter reset
7296 * @param hhrtim pointer to HAL HRTIM handle
7297 * @param TimerIdx Timer index
7298 * @param Event Event channel identifier
7299 * @retval None
7300 */
7301 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
7302 uint32_t TimerIdx,
7303 uint32_t Event)
7304 {
7305 switch (Event)
7306 {
7307 case HRTIM_EVENT_1:
7308 {
7309 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
7310 }
7311 break;
7312 case HRTIM_EVENT_2:
7313 {
7314 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
7315 }
7316 break;
7317 case HRTIM_EVENT_3:
7318 {
7319 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
7320 }
7321 break;
7322 case HRTIM_EVENT_4:
7323 {
7324 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
7325 }
7326 break;
7327 case HRTIM_EVENT_5:
7328 {
7329 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
7330 }
7331 break;
7332 case HRTIM_EVENT_6:
7333 {
7334 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
7335 }
7336 break;
7337 case HRTIM_EVENT_7:
7338 {
7339 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
7340 }
7341 break;
7342 case HRTIM_EVENT_8:
7343 {
7344 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
7345 }
7346 break;
7347 case HRTIM_EVENT_9:
7348 {
7349 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
7350 }
7351 break;
7352 case HRTIM_EVENT_10:
7353 {
7354 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
7355 }
7356 break;
7357 default:
7358 break;
7359 }
7360 }
7361
7362 /**
7363 * @brief Returns the interrupt to enable or disable according to the
7364 * OC mode.
7365 * @param hhrtim pointer to HAL HRTIM handle
7366 * @param TimerIdx Timer index
7367 * @param OCChannel Timer output
7368 * This parameter can be one of the following values:
7369 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7370 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7371 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7372 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7373 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7374 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7375 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7376 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7377 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7378 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7379 * @retval Interrupt to enable or disable
7380 */
7381 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
7382 uint32_t TimerIdx,
7383 uint32_t OCChannel)
7384 {
7385 uint32_t hrtim_set;
7386 uint32_t hrtim_reset;
7387 uint32_t interrupt = 0U;
7388
7389 switch (OCChannel)
7390 {
7391 case HRTIM_OUTPUT_TA1:
7392 case HRTIM_OUTPUT_TB1:
7393 case HRTIM_OUTPUT_TC1:
7394 case HRTIM_OUTPUT_TD1:
7395 case HRTIM_OUTPUT_TE1:
7396 {
7397 /* Retreives actual OC mode and set interrupt accordingly */
7398 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
7399 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
7400
7401 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7402 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7403 {
7404 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7405 interrupt = HRTIM_TIM_IT_CMP1;
7406 }
7407 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7408 (hrtim_reset == 0U))
7409 {
7410 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7411 interrupt = HRTIM_TIM_IT_SET1;
7412 }
7413 else if ((hrtim_set == 0U) &&
7414 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7415 {
7416 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7417 interrupt = HRTIM_TIM_IT_RST1;
7418 }
7419 }
7420 break;
7421 case HRTIM_OUTPUT_TA2:
7422 case HRTIM_OUTPUT_TB2:
7423 case HRTIM_OUTPUT_TC2:
7424 case HRTIM_OUTPUT_TD2:
7425 case HRTIM_OUTPUT_TE2:
7426 {
7427 /* Retreives actual OC mode and set interrupt accordingly */
7428 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
7429 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
7430
7431 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7432 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7433 {
7434 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7435 interrupt = HRTIM_TIM_IT_CMP2;
7436 }
7437 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7438 (hrtim_reset == 0U))
7439 {
7440 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7441 interrupt = HRTIM_TIM_IT_SET2;
7442 }
7443 else if ((hrtim_set == 0U) &&
7444 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7445 {
7446 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7447 interrupt = HRTIM_TIM_IT_RST2;
7448 }
7449 }
7450 break;
7451 default:
7452 break;
7453 }
7454
7455 return interrupt;
7456 }
7457
7458 /**
7459 * @brief Returns the DMA request to enable or disable according to the
7460 * OC mode.
7461 * @param hhrtim pointer to HAL HRTIM handle
7462 * @param TimerIdx Timer index
7463 * @param OCChannel Timer output
7464 * This parameter can be one of the following values:
7465 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7466 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7467 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7468 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7469 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7470 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7471 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7472 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7473 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7474 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7475 * @retval DMA request to enable or disable
7476 */
7477 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
7478 uint32_t TimerIdx,
7479 uint32_t OCChannel)
7480 {
7481 uint32_t hrtim_set;
7482 uint32_t hrtim_reset;
7483 uint32_t dma_request = 0U;
7484
7485 switch (OCChannel)
7486 {
7487 case HRTIM_OUTPUT_TA1:
7488 case HRTIM_OUTPUT_TB1:
7489 case HRTIM_OUTPUT_TC1:
7490 case HRTIM_OUTPUT_TD1:
7491 case HRTIM_OUTPUT_TE1:
7492 {
7493 /* Retreives actual OC mode and set dma_request accordingly */
7494 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
7495 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
7496
7497 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7498 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7499 {
7500 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7501 dma_request = HRTIM_TIM_DMA_CMP1;
7502 }
7503 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
7504 (hrtim_reset == 0U))
7505 {
7506 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7507 dma_request = HRTIM_TIM_DMA_SET1;
7508 }
7509 else if ((hrtim_set == 0U) &&
7510 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1))
7511 {
7512 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7513 dma_request = HRTIM_TIM_DMA_RST1;
7514 }
7515 }
7516 break;
7517 case HRTIM_OUTPUT_TA2:
7518 case HRTIM_OUTPUT_TB2:
7519 case HRTIM_OUTPUT_TC2:
7520 case HRTIM_OUTPUT_TD2:
7521 case HRTIM_OUTPUT_TE2:
7522 {
7523 /* Retreives actual OC mode and set dma_request accordingly */
7524 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
7525 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
7526
7527 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7528 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7529 {
7530 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
7531 dma_request = HRTIM_TIM_DMA_CMP2;
7532 }
7533 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
7534 (hrtim_reset == 0U))
7535 {
7536 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
7537 dma_request = HRTIM_TIM_DMA_SET2;
7538 }
7539 else if ((hrtim_set == 0U) &&
7540 ((hrtim_reset & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2))
7541 {
7542 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
7543 dma_request = HRTIM_TIM_DMA_RST2;
7544 }
7545 }
7546 break;
7547 default:
7548 break;
7549 }
7550
7551 return dma_request;
7552 }
7553
7554 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
7555 uint32_t TimerIdx)
7556 {
7557 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
7558
7559 switch (TimerIdx)
7560 {
7561 case HRTIM_TIMERINDEX_MASTER:
7562 {
7563 hdma = hhrtim->hdmaMaster;
7564 }
7565 break;
7566 case HRTIM_TIMERINDEX_TIMER_A:
7567 {
7568 hdma = hhrtim->hdmaTimerA;
7569 }
7570 break;
7571 case HRTIM_TIMERINDEX_TIMER_B:
7572 {
7573 hdma = hhrtim->hdmaTimerB;
7574 }
7575 break;
7576 case HRTIM_TIMERINDEX_TIMER_C:
7577 {
7578 hdma = hhrtim->hdmaTimerC;
7579 }
7580 break;
7581 case HRTIM_TIMERINDEX_TIMER_D:
7582 {
7583 hdma = hhrtim->hdmaTimerD;
7584 }
7585 break;
7586 case HRTIM_TIMERINDEX_TIMER_E:
7587 {
7588 hdma = hhrtim->hdmaTimerE;
7589 }
7590 break;
7591 default:
7592 break;
7593 }
7594
7595 return hdma;
7596 }
7597
7598 static uint32_t GetTimerIdxFromDMAHandle(DMA_HandleTypeDef *hdma)
7599 {
7600 uint32_t timed_idx = 0xFFFFFFFFU;
7601
7602 if (hdma->Instance == DMA1_Channel2)
7603 {
7604 timed_idx = HRTIM_TIMERINDEX_MASTER;
7605 }
7606 else if (hdma->Instance == DMA1_Channel3)
7607 {
7608 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
7609 }
7610 else if (hdma->Instance == DMA1_Channel4)
7611 {
7612 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
7613 }
7614 else if (hdma->Instance == DMA1_Channel5)
7615 {
7616 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
7617 }
7618 else if (hdma->Instance == DMA1_Channel6)
7619 {
7620 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
7621 }
7622 else if (hdma->Instance == DMA1_Channel7)
7623 {
7624 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
7625 }
7626
7627 return timed_idx;
7628 }
7629
7630 /**
7631 * @brief Forces an immediate transfer from the preload to the active
7632 * registers.
7633 * @param hhrtim pointer to HAL HRTIM handle
7634 * @param TimerIdx Timer index
7635 * @retval None
7636 */
7637 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
7638 uint32_t TimerIdx)
7639 {
7640 switch (TimerIdx)
7641 {
7642 case HRTIM_TIMERINDEX_MASTER:
7643 {
7644 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
7645 }
7646 break;
7647 case HRTIM_TIMERINDEX_TIMER_A:
7648 {
7649 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
7650 }
7651 break;
7652 case HRTIM_TIMERINDEX_TIMER_B:
7653 {
7654 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
7655 }
7656 break;
7657 case HRTIM_TIMERINDEX_TIMER_C:
7658 {
7659 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
7660 }
7661 break;
7662 case HRTIM_TIMERINDEX_TIMER_D:
7663 {
7664 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
7665 }
7666 break;
7667 case HRTIM_TIMERINDEX_TIMER_E:
7668 {
7669 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
7670 }
7671 break;
7672 default:
7673 break;
7674 }
7675 }
7676
7677
7678 /**
7679 * @brief HRTIM interrupts service routine
7680 * @param hhrtim pointer to HAL HRTIM handle
7681 * @retval None
7682 */
7683 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
7684 {
7685 /* Fault 1 event */
7686 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != RESET)
7687 {
7688 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
7689 {
7690 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
7691
7692 /* Invoke Fault 1 event callback */
7693 HAL_HRTIM_Fault1Callback(hhrtim);
7694 }
7695 }
7696
7697 /* Fault 2 event */
7698 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != RESET)
7699 {
7700 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
7701 {
7702 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
7703
7704 /* Invoke Fault 2 event callback */
7705 HAL_HRTIM_Fault2Callback(hhrtim);
7706 }
7707 }
7708
7709 /* Fault 3 event */
7710 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != RESET)
7711 {
7712 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
7713 {
7714 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
7715
7716 /* Invoke Fault 3 event callback */
7717 HAL_HRTIM_Fault3Callback(hhrtim);
7718 }
7719 }
7720
7721 /* Fault 4 event */
7722 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != RESET)
7723 {
7724 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
7725 {
7726 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
7727
7728 /* Invoke Fault 4 event callback */
7729 HAL_HRTIM_Fault4Callback(hhrtim);
7730 }
7731 }
7732
7733 /* Fault 5 event */
7734 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != RESET)
7735 {
7736 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
7737 {
7738 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
7739
7740 /* Invoke Fault 5 event callback */
7741 HAL_HRTIM_Fault5Callback(hhrtim);
7742 }
7743 }
7744
7745 /* System fault event */
7746 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != RESET)
7747 {
7748 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
7749 {
7750 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
7751
7752 /* Invoke System fault event callback */
7753 HAL_HRTIM_SystemFaultCallback(hhrtim);
7754 }
7755 }
7756 }
7757
7758 /**
7759 * @brief Master timer interrupts service routine
7760 * @param hhrtim pointer to HAL HRTIM handle
7761 * @retval None
7762 */
7763 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
7764 {
7765 /* DLL calibration ready event */
7766 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != RESET)
7767 {
7768 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
7769 {
7770 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
7771
7772 /* Set HRTIM State */
7773 hhrtim->State = HAL_HRTIM_STATE_READY;
7774
7775 /* Process unlocked */
7776 __HAL_UNLOCK(hhrtim);
7777
7778 /* Invoke System fault event callback */
7779 HAL_HRTIM_DLLCalbrationReadyCallback(hhrtim);
7780 }
7781 }
7782
7783 /* Burst mode period event */
7784 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != RESET)
7785 {
7786 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
7787 {
7788 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
7789
7790 /* Invoke Burst mode period event callback */
7791 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
7792 }
7793 }
7794
7795 /* Master timer compare 1 event */
7796 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != RESET)
7797 {
7798 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
7799 {
7800 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
7801
7802 /* Invoke compare 1 event callback */
7803 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7804 }
7805 }
7806
7807 /* Master timer compare 2 event */
7808 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != RESET)
7809 {
7810 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
7811 {
7812 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
7813
7814 /* Invoke compare 2 event callback */
7815 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7816 }
7817 }
7818
7819 /* Master timer compare 3 event */
7820 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != RESET)
7821 {
7822 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
7823 {
7824 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
7825
7826 /* Invoke compare 3 event callback */
7827 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7828 }
7829 }
7830
7831 /* Master timer compare 4 event */
7832 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != RESET)
7833 {
7834 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
7835 {
7836 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
7837
7838 /* Invoke compare 4 event callback */
7839 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7840 }
7841 }
7842
7843 /* Master timer repetition event */
7844 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != RESET)
7845 {
7846 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
7847 {
7848 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
7849
7850 /* Invoke repetition event callback */
7851 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7852 }
7853 }
7854
7855 /* Synchronization input event */
7856 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != RESET)
7857 {
7858 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
7859 {
7860 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
7861
7862 /* Invoke synchronization event callback */
7863 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
7864 }
7865 }
7866
7867 /* Master timer registers update event */
7868 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != RESET)
7869 {
7870 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
7871 {
7872 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
7873
7874 /* Invoke registers update event callback */
7875 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
7876 }
7877 }
7878 }
7879
7880 /**
7881 * @brief Timer interrupts service routine
7882 * @param hhrtim pointer to HAL HRTIM handle
7883 * @param TimerIdx Timer index
7884 * This parameter can be one of the following values:
7885 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7886 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7887 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7888 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7889 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7890 * @retval None
7891 */
7892 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
7893 uint32_t TimerIdx)
7894 {
7895 /* Timer compare 1 event */
7896 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != RESET)
7897 {
7898 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
7899 {
7900 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
7901
7902 /* Invoke compare 1 event callback */
7903 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
7904 }
7905 }
7906
7907 /* Timer compare 2 event */
7908 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != RESET)
7909 {
7910 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
7911 {
7912 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
7913
7914 /* Invoke compare 2 event callback */
7915 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
7916 }
7917 }
7918
7919 /* Timer compare 3 event */
7920 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != RESET)
7921 {
7922 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
7923 {
7924 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
7925
7926 /* Invoke compare 3 event callback */
7927 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
7928 }
7929 }
7930
7931 /* Timer compare 4 event */
7932 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != RESET)
7933 {
7934 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
7935 {
7936 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
7937
7938 /* Invoke compare 4 event callback */
7939 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
7940 }
7941 }
7942
7943 /* Timer repetition event */
7944 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != RESET)
7945 {
7946 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
7947 {
7948 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
7949
7950 /* Invoke repetition event callback */
7951 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
7952 }
7953 }
7954
7955 /* Timer registers update event */
7956 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != RESET)
7957 {
7958 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
7959 {
7960 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
7961
7962 /* Invoke registers update event callback */
7963 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
7964 }
7965 }
7966
7967 /* Timer capture 1 event */
7968 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != RESET)
7969 {
7970 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
7971 {
7972 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
7973
7974 /* Invoke capture 1 event callback */
7975 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
7976 }
7977 }
7978
7979 /* Timer capture 2 event */
7980 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != RESET)
7981 {
7982 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
7983 {
7984 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
7985
7986 /* Invoke capture 2 event callback */
7987 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
7988 }
7989 }
7990
7991 /* Timer ouput 1 set event */
7992 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != RESET)
7993 {
7994 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
7995 {
7996 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
7997
7998 /* Invoke ouput 1 set event callback */
7999 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
8000 }
8001 }
8002
8003 /* Timer ouput 1 reset event */
8004 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != RESET)
8005 {
8006 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
8007 {
8008 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
8009
8010 /* Invoke ouput 1 reset event callback */
8011 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
8012 }
8013 }
8014
8015 /* Timer ouput 2 set event */
8016 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != RESET)
8017 {
8018 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
8019 {
8020 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
8021
8022 /* Invoke ouput 2 set event callback */
8023 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
8024 }
8025 }
8026
8027 /* Timer ouput 2 reset event */
8028 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != RESET)
8029 {
8030 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
8031 {
8032 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
8033
8034 /* Invoke ouput 2 reset event callback */
8035 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
8036 }
8037 }
8038
8039 /* Timer reset event */
8040 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != RESET)
8041 {
8042 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
8043 {
8044 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
8045
8046 /* Invoke timer reset callback */
8047 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
8048 }
8049 }
8050
8051 /* Delayed protection event */
8052 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != RESET)
8053 {
8054 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
8055 {
8056 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
8057
8058 /* Invoke delayed protection callback */
8059 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
8060 }
8061 }
8062 }
8063
8064 /**
8065 * @brief DMA callback invoked upon master timer related DMA request completion
8066 * @param hdma pointer to DMA handle.
8067 * @retval None
8068 */
8069 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
8070 {
8071 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
8072
8073 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != RESET)
8074 {
8075 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8076 }
8077 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != RESET)
8078 {
8079 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8080 }
8081 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != RESET)
8082 {
8083 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8084 }
8085 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != RESET)
8086 {
8087 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8088 }
8089 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != RESET)
8090 {
8091 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8092 }
8093 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != RESET)
8094 {
8095 HAL_HRTIM_SynchronizationEventCallback(hrtim);
8096 }
8097 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != RESET)
8098 {
8099 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
8100 }
8101 }
8102
8103 /**
8104 * @brief DMA callback invoked upon timer A..E related DMA request completion
8105 * @param hdma pointer to DMA handle.
8106 * @retval None
8107 */
8108 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
8109 {
8110 uint8_t timer_idx;
8111
8112 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
8113
8114 timer_idx = GetTimerIdxFromDMAHandle(hdma);
8115
8116 if (IS_HRTIM_TIMING_UNIT( timer_idx))
8117 {
8118 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != RESET)
8119 {
8120 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
8121 }
8122 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != RESET)
8123 {
8124 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
8125 }
8126 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != RESET)
8127 {
8128 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
8129 }
8130 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != RESET)
8131 {
8132 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
8133 }
8134 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != RESET)
8135 {
8136 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
8137 }
8138 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != RESET)
8139 {
8140 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
8141 }
8142 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != RESET)
8143 {
8144 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
8145 }
8146 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != RESET)
8147 {
8148 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
8149 }
8150 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != RESET)
8151 {
8152 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
8153 }
8154 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != RESET)
8155 {
8156 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
8157 }
8158 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != RESET)
8159 {
8160 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
8161 }
8162 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != RESET)
8163 {
8164 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
8165 }
8166 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != RESET)
8167 {
8168 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
8169 }
8170 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != RESET)
8171 {
8172 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
8173 }
8174 }
8175 }
8176
8177 /**
8178 * @brief DMA error callback
8179 * @param hdma pointer to DMA handle.
8180 * @retval None
8181 */
8182 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
8183 {
8184 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
8185
8186 HAL_HRTIM_ErrorCallback(hrtim);
8187 }
8188
8189 /**
8190 * @brief DMA callback invoked upon burst DMA transfer completion
8191 * @param hdma pointer to DMA handle.
8192 * @retval None
8193 */
8194 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
8195 {
8196 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
8197
8198 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hdma));
8199 }
8200
8201 /**
8202 * @}
8203 */
8204
8205 /**
8206 * @}
8207 */
8208 #endif /* STM32F334x8 */
8209
8210 #endif /* HAL_HRTIM_MODULE_ENABLED */
8211
8212 /**
8213 * @}
8214 */
8215
8216 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8217
8218
8219