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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Src / stm32f3xx_hal_nand.c
blob23fb514fa272eb2c7de79e26ac3b4d0784364d5e
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_nand.c
4 * @author MCD Application Team
5 * @brief NAND HAL module driver.
6 * This file provides a generic firmware to drive NAND memories mounted
7 * as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control NAND flash memories. It uses the FMC layer functions to interface
16 with NAND devices. This driver is used as follows:
17
18 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
19 with control and timing parameters for both common and attribute spaces.
20
21 (+) Read NAND flash memory maker and device IDs using the function
22 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
23 structure declared by the function caller.
24
25 (+) Access NAND flash memory by read/write operations using the functions
26 HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
27 HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
28 HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
29 HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
30 to read/write page(s)/spare area(s). These functions use specific device
31 information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef
32 structure. The read/write address information is contained by the Nand_Address_Typedef
33 structure passed as parameter.
34
35 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
36
37 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
38 The erase block address information is contained in the Nand_Address_Typedef
39 structure passed as parameter.
40
41 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
42
43 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
44 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
45 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
46
47 (+) You can monitor the NAND device HAL state by calling the function
48 HAL_NAND_GetState()
49
50 [..]
51 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
52 If a NAND flash device contains different operations and/or implementations,
53 it should be implemented separately.
54
55 @endverbatim
56 ******************************************************************************
57 * @attention
58 *
59 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
60 *
61 * Redistribution and use in source and binary forms, with or without modification,
62 * are permitted provided that the following conditions are met:
63 * 1. Redistributions of source code must retain the above copyright notice,
64 * this list of conditions and the following disclaimer.
65 * 2. Redistributions in binary form must reproduce the above copyright notice,
66 * this list of conditions and the following disclaimer in the documentation
67 * and/or other materials provided with the distribution.
68 * 3. Neither the name of STMicroelectronics nor the names of its contributors
69 * may be used to endorse or promote products derived from this software
70 * without specific prior written permission.
71 *
72 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
73 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
75 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
78 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
79 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
80 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
81 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
82 *
83 ******************************************************************************
84 */
85
86 /* Includes ------------------------------------------------------------------*/
87 #include "stm32f3xx_hal.h"
88
89 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
90
91 /** @addtogroup STM32F3xx_HAL_Driver
92 * @{
93 */
94
95 #ifdef HAL_NAND_MODULE_ENABLED
96
97 /** @defgroup NAND NAND
98 * @brief NAND HAL module driver
99 * @{
100 */
101
102 /* Private typedef -----------------------------------------------------------*/
103 /* Private define ------------------------------------------------------------*/
104 /** @defgroup NAND_Private_Constants NAND Private Constants
105 * @{
106 */
107
108 /**
109 * @}
110 */
111
112 /* Private macro -------------------------------------------------------------*/
113 /** @defgroup NAND_Private_Macros NAND Private Macros
114 * @{
115 */
116
117 /**
118 * @}
119 */
120 /* Private variables ---------------------------------------------------------*/
121 /* Private function prototypes -----------------------------------------------*/
122 /* Exported functions --------------------------------------------------------*/
123 /** @defgroup NAND_Exported_Functions NAND Exported Functions
124 * @{
125 */
126
127 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
128 * @brief Initialization and Configuration functions
129 *
130 @verbatim
131 ==============================================================================
132 ##### NAND Initialization and de-initialization functions #####
133 ==============================================================================
134 [..]
135 This section provides functions allowing to initialize/de-initialize
136 the NAND memory
137
138 @endverbatim
139 * @{
140 */
141
142 /**
143 * @brief Perform NAND memory Initialization sequence
144 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
145 * the configuration information for NAND module.
146 * @param ComSpace_Timing pointer to Common space timing structure
147 * @param AttSpace_Timing pointer to Attribute space timing structure
148 * @retval HAL status
149 */
150 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
151 {
152 /* Check the NAND handle state */
153 if(hnand == NULL)
154 {
155 return HAL_ERROR;
156 }
157
158 if(hnand->State == HAL_NAND_STATE_RESET)
159 {
160 /* Allocate lock resource and initialize it */
161 hnand->Lock = HAL_UNLOCKED;
162 /* Initialize the low level hardware (MSP) */
163 HAL_NAND_MspInit(hnand);
164 }
165
166 /* Initialize NAND control Interface */
167 FMC_NAND_Init(hnand->Instance, &(hnand->Init));
168
169 /* Initialize NAND common space timing Interface */
170 FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
171
172 /* Initialize NAND attribute space timing Interface */
173 FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
174
175 /* Enable the NAND device */
176 __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank);
177
178 /* Update the NAND controller state */
179 hnand->State = HAL_NAND_STATE_READY;
180
181 return HAL_OK;
182 }
183
184 /**
185 * @brief Perform NAND memory De-Initialization sequence
186 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
187 * the configuration information for NAND module.
188 * @retval HAL status
189 */
190 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
191 {
192 /* Initialize the low level hardware (MSP) */
193 HAL_NAND_MspDeInit(hnand);
194
195 /* Configure the NAND registers with their reset values */
196 FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
197
198 /* Reset the NAND controller state */
199 hnand->State = HAL_NAND_STATE_RESET;
200
201 /* Release Lock */
202 __HAL_UNLOCK(hnand);
203
204 return HAL_OK;
205 }
206
207 /**
208 * @brief NAND MSP Init
209 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
210 * the configuration information for NAND module.
211 * @retval None
212 */
213 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
214 {
215 /* Prevent unused argument(s) compilation warning */
216 UNUSED(hnand);
217 /* NOTE : This function Should not be modified, when the callback is needed,
218 the HAL_NAND_MspInit could be implemented in the user file
219 */
220 }
221
222 /**
223 * @brief NAND MSP DeInit
224 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
225 * the configuration information for NAND module.
226 * @retval None
227 */
228 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
229 {
230 /* Prevent unused argument(s) compilation warning */
231 UNUSED(hnand);
232 /* NOTE : This function Should not be modified, when the callback is needed,
233 the HAL_NAND_MspDeInit could be implemented in the user file
234 */
235 }
236
237
238 /**
239 * @brief This function handles NAND device interrupt request.
240 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
241 * the configuration information for NAND module.
242 * @retval HAL status
243 */
244 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
245 {
246 /* Check NAND interrupt Rising edge flag */
247 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
248 {
249 /* NAND interrupt callback*/
250 HAL_NAND_ITCallback(hnand);
251
252 /* Clear NAND interrupt Rising edge pending bit */
253 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE);
254 }
255
256 /* Check NAND interrupt Level flag */
257 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
258 {
259 /* NAND interrupt callback*/
260 HAL_NAND_ITCallback(hnand);
261
262 /* Clear NAND interrupt Level pending bit */
263 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL);
264 }
265
266 /* Check NAND interrupt Falling edge flag */
267 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
268 {
269 /* NAND interrupt callback*/
270 HAL_NAND_ITCallback(hnand);
271
272 /* Clear NAND interrupt Falling edge pending bit */
273 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE);
274 }
275
276 /* Check NAND interrupt FIFO empty flag */
277 if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
278 {
279 /* NAND interrupt callback*/
280 HAL_NAND_ITCallback(hnand);
281
282 /* Clear NAND interrupt FIFO empty pending bit */
283 __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT);
284 }
285 }
286
287 /**
288 * @brief NAND interrupt feature callback
289 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
290 * the configuration information for NAND module.
291 * @retval None
292 */
293 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
294 {
295 /* Prevent unused argument(s) compilation warning */
296 UNUSED(hnand);
297 /* NOTE : This function Should not be modified, when the callback is needed,
298 the HAL_NAND_ITCallback could be implemented in the user file
299 */
300 }
301
302 /**
303 * @}
304 */
305
306 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
307 * @brief Input Output and memory control functions
308 *
309 @verbatim
310 ==============================================================================
311 ##### NAND Input and Output functions #####
312 ==============================================================================
313 [..]
314 This section provides functions allowing to use and control the NAND
315 memory
316
317 @endverbatim
318 * @{
319 */
320
321 /**
322 * @brief Read the NAND memory electronic signature
323 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
324 * the configuration information for NAND module.
325 * @param pNAND_ID NAND ID structure
326 * @retval HAL status
327 */
328 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
329 {
330 __IO uint32_t data = 0U;
331 __IO uint32_t data1 = 0U;
332 uint32_t deviceaddress = 0U;
333
334 /* Process Locked */
335 __HAL_LOCK(hnand);
336
337 /* Check the NAND controller state */
338 if(hnand->State == HAL_NAND_STATE_BUSY)
339 {
340 return HAL_BUSY;
341 }
342
343 /* Identify the device address */
344 if(hnand->Init.NandBank == FMC_NAND_BANK2)
345 {
346 deviceaddress = NAND_DEVICE1;
347 }
348 else
349 {
350 deviceaddress = NAND_DEVICE2;
351 }
352
353 /* Update the NAND controller state */
354 hnand->State = HAL_NAND_STATE_BUSY;
355
356 /* Send Read ID command sequence */
357 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID;
358 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
359
360 /* Read the electronic signature from NAND flash */
361 if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
362 {
363 data = *(__IO uint32_t *)deviceaddress;
364
365 /* Return the data read */
366 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
367 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
368 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
369 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
370 }
371 else
372 {
373 data = *(__IO uint32_t *)deviceaddress;
374 data1 = *((__IO uint32_t *)deviceaddress + 4U);
375
376 /* Return the data read */
377 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
378 pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
379 pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
380 pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
381 }
382
383 /* Update the NAND controller state */
384 hnand->State = HAL_NAND_STATE_READY;
385
386 /* Process unlocked */
387 __HAL_UNLOCK(hnand);
388
389 return HAL_OK;
390 }
391
392 /**
393 * @brief NAND memory reset
394 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
395 * the configuration information for NAND module.
396 * @retval HAL status
397 */
398 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
399 {
400 uint32_t deviceaddress = 0U;
401
402 /* Process Locked */
403 __HAL_LOCK(hnand);
404
405 /* Check the NAND controller state */
406 if(hnand->State == HAL_NAND_STATE_BUSY)
407 {
408 return HAL_BUSY;
409 }
410
411 /* Identify the device address */
412 if(hnand->Init.NandBank == FMC_NAND_BANK2)
413 {
414 deviceaddress = NAND_DEVICE1;
415 }
416 else
417 {
418 deviceaddress = NAND_DEVICE2;
419 }
420
421 /* Update the NAND controller state */
422 hnand->State = HAL_NAND_STATE_BUSY;
423
424 /* Send NAND reset command */
425 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF;
426
427
428 /* Update the NAND controller state */
429 hnand->State = HAL_NAND_STATE_READY;
430
431 /* Process unlocked */
432 __HAL_UNLOCK(hnand);
433
434 return HAL_OK;
435
436 }
437
438 /**
439 * @brief Configure the device: Enter the physical parameters of the device
440 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
441 * the configuration information for NAND module.
442 * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
443 * @retval HAL status
444 */
445 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
446 {
447 hnand->Config.PageSize = pDeviceConfig->PageSize;
448 hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
449 hnand->Config.BlockSize = pDeviceConfig->BlockSize;
450 hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
451 hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
452 hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
453 hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
454
455 return HAL_OK;
456 }
457
458 /**
459 * @brief Read Page(s) from NAND memory block (8-bits addressing)
460 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
461 * the configuration information for NAND module.
462 * @param pAddress pointer to NAND address structure
463 * @param pBuffer pointer to destination read buffer
464 * @param NumPageToRead number of pages to read from block
465 * @retval HAL status
466 */
467 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
468 {
469 __IO uint32_t index = 0U;
470 uint32_t tickstart = 0U;
471 uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
472
473 /* Process Locked */
474 __HAL_LOCK(hnand);
475
476 /* Check the NAND controller state */
477 if(hnand->State == HAL_NAND_STATE_BUSY)
478 {
479 return HAL_BUSY;
480 }
481
482 /* Identify the device address */
483 if(hnand->Init.NandBank == FMC_NAND_BANK2)
484 {
485 deviceaddress = NAND_DEVICE1;
486 }
487 else
488 {
489 deviceaddress = NAND_DEVICE2;
490 }
491
492 /* Update the NAND controller state */
493 hnand->State = HAL_NAND_STATE_BUSY;
494
495 /* NAND raw address calculation */
496 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
497
498 /* Page(s) read loop */
499 while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
500 {
501 /* update the buffer size */
502 size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
503
504 /* Send read page command sequence */
505 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
506
507 /* Cards with page size <= 512 bytes */
508 if((hnand->Config.PageSize) <= 512U)
509 {
510 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
511 {
512 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
513 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
514 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
515 }
516 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
517 {
518 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
519 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
520 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
521 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
522 }
523 }
524 else /* (hnand->Config.PageSize) > 512 */
525 {
526 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
527 {
528 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
529 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
530 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
531 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
532 }
533 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
534 {
535 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
536 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
537 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
538 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
539 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
540 }
541 }
542
543 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
544
545 /* Check if an extra command is needed for reading pages */
546 if(hnand->Config.ExtraCommandEnable == ENABLE)
547 {
548 /* Get tick */
549 tickstart = HAL_GetTick();
550
551 /* Read status until NAND is ready */
552 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
553 {
554 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
555 {
556 return HAL_TIMEOUT;
557 }
558 }
559
560 /* Go back to read mode */
561 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
562 __DSB();
563 }
564
565 /* Get Data into Buffer */
566 for(; index < size; index++)
567 {
568 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
569 }
570
571 /* Increment read pages number */
572 numPagesRead++;
573
574 /* Decrement pages to read */
575 NumPageToRead--;
576
577 /* Increment the NAND address */
578 nandaddress = (uint32_t)(nandaddress + 1U);
579 }
580
581 /* Update the NAND controller state */
582 hnand->State = HAL_NAND_STATE_READY;
583
584 /* Process unlocked */
585 __HAL_UNLOCK(hnand);
586
587 return HAL_OK;
588 }
589
590 /**
591 * @brief Read Page(s) from NAND memory block (16-bits addressing)
592 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
593 * the configuration information for NAND module.
594 * @param pAddress pointer to NAND address structure
595 * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
596 * @param NumPageToRead number of pages to read from block
597 * @retval HAL status
598 */
599 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
600 {
601 __IO uint32_t index = 0U;
602 uint32_t tickstart = 0U;
603 uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U;
604
605 /* Process Locked */
606 __HAL_LOCK(hnand);
607
608 /* Check the NAND controller state */
609 if(hnand->State == HAL_NAND_STATE_BUSY)
610 {
611 return HAL_BUSY;
612 }
613
614 /* Identify the device address */
615 if(hnand->Init.NandBank == FMC_NAND_BANK2)
616 {
617 deviceaddress = NAND_DEVICE1;
618 }
619 else
620 {
621 deviceaddress = NAND_DEVICE2;
622 }
623
624 /* Update the NAND controller state */
625 hnand->State = HAL_NAND_STATE_BUSY;
626
627 /* NAND raw address calculation */
628 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
629
630 /* Page(s) read loop */
631 while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
632 {
633 /* update the buffer size */
634 size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead);
635
636 /* Send read page command sequence */
637 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
638 __DSB();
639
640 /* Cards with page size <= 512 bytes */
641 if((hnand->Config.PageSize) <= 512U)
642 {
643 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
644 {
645 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
646 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
647 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
648 }
649 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
650 {
651 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
652 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
653 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
654 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
655 }
656 }
657 else /* (hnand->Config.PageSize) > 512 */
658 {
659 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
660 {
661 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
662 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
663 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
664 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
665 }
666 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
667 {
668 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
669 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
670 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
671 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
672 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
673 }
674 }
675
676 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
677
678 if(hnand->Config.ExtraCommandEnable == ENABLE)
679 {
680 /* Get tick */
681 tickstart = HAL_GetTick();
682
683 /* Read status until NAND is ready */
684 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
685 {
686 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
687 {
688 return HAL_TIMEOUT;
689 }
690 }
691
692 /* Go back to read mode */
693 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
694 }
695
696 /* Get Data into Buffer */
697 for(; index < size; index++)
698 {
699 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
700 }
701
702 /* Increment read pages number */
703 numPagesRead++;
704
705 /* Decrement pages to read */
706 NumPageToRead--;
707
708 /* Increment the NAND address */
709 nandaddress = (uint32_t)(nandaddress + 1U);
710 }
711
712 /* Update the NAND controller state */
713 hnand->State = HAL_NAND_STATE_READY;
714
715 /* Process unlocked */
716 __HAL_UNLOCK(hnand);
717
718 return HAL_OK;
719 }
720
721 /**
722 * @brief Write Page(s) to NAND memory block (8-bits addressing)
723 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
724 * the configuration information for NAND module.
725 * @param pAddress pointer to NAND address structure
726 * @param pBuffer pointer to source buffer to write
727 * @param NumPageToWrite : number of pages to write to block
728 * @retval HAL status
729 */
730 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
731 {
732 __IO uint32_t index = 0U;
733 uint32_t tickstart = 0U;
734 uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
735
736 /* Process Locked */
737 __HAL_LOCK(hnand);
738
739 /* Check the NAND controller state */
740 if(hnand->State == HAL_NAND_STATE_BUSY)
741 {
742 return HAL_BUSY;
743 }
744
745 /* Identify the device address */
746 if(hnand->Init.NandBank == FMC_NAND_BANK2)
747 {
748 deviceaddress = NAND_DEVICE1;
749 }
750 else
751 {
752 deviceaddress = NAND_DEVICE2;
753 }
754
755 /* Update the NAND controller state */
756 hnand->State = HAL_NAND_STATE_BUSY;
757
758 /* NAND raw address calculation */
759 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
760
761 /* Page(s) write loop */
762 while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
763 {
764 /* update the buffer size */
765 size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten);
766
767 /* Send write page command sequence */
768 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
769 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
770
771 /* Cards with page size <= 512 bytes */
772 if((hnand->Config.PageSize) <= 512U)
773 {
774 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
775 {
776 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
777 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
778 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
779 }
780 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
781 {
782 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
783 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
784 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
785 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
786 }
787 }
788 else /* (hnand->Config.PageSize) > 512 */
789 {
790 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
791 {
792 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
793 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
794 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
795 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
796 }
797 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
798 {
799 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
800 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
801 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
802 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
803 __DSB();
804 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
805 __DSB();
806 }
807 }
808
809
810 /* Write data to memory */
811 for(; index < size; index++)
812 {
813 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
814 }
815
816 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
817
818 /* Read status until NAND is ready */
819 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
820 {
821 /* Get tick */
822 tickstart = HAL_GetTick();
823
824 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
825 {
826 return HAL_TIMEOUT;
827 }
828 }
829
830 /* Increment written pages number */
831 numPagesWritten++;
832
833 /* Decrement pages to write */
834 NumPageToWrite--;
835
836 /* Increment the NAND address */
837 nandaddress = (uint32_t)(nandaddress + 1U);
838 }
839
840 /* Update the NAND controller state */
841 hnand->State = HAL_NAND_STATE_READY;
842
843 /* Process unlocked */
844 __HAL_UNLOCK(hnand);
845
846 return HAL_OK;
847 }
848
849 /**
850 * @brief Write Page(s) to NAND memory block (16-bits addressing)
851 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
852 * the configuration information for NAND module.
853 * @param pAddress pointer to NAND address structure
854 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
855 * @param NumPageToWrite : number of pages to write to block
856 * @retval HAL status
857 */
858 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
859 {
860 __IO uint32_t index = 0U;
861 uint32_t tickstart = 0U;
862 uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U;
863
864 /* Process Locked */
865 __HAL_LOCK(hnand);
866
867 /* Check the NAND controller state */
868 if(hnand->State == HAL_NAND_STATE_BUSY)
869 {
870 return HAL_BUSY;
871 }
872
873 /* Identify the device address */
874 if(hnand->Init.NandBank == FMC_NAND_BANK2)
875 {
876 deviceaddress = NAND_DEVICE1;
877 }
878 else
879 {
880 deviceaddress = NAND_DEVICE2;
881 }
882
883 /* Update the NAND controller state */
884 hnand->State = HAL_NAND_STATE_BUSY;
885
886 /* NAND raw address calculation */
887 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
888
889 /* Page(s) write loop */
890 while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
891 {
892 /* update the buffer size */
893 size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten);
894
895 /* Send write page command sequence */
896 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
897 __DSB();
898 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
899 __DSB();
900
901 /* Cards with page size <= 512 bytes */
902 if((hnand->Config.PageSize) <= 512U)
903 {
904 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
905 {
906 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
907 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
908 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
909 }
910 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
911 {
912 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
913 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
914 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
915 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
916 }
917 }
918 else /* (hnand->Config.PageSize) > 512 */
919 {
920 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
921 {
922 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
923 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
924 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
925 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
926 }
927 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
928 {
929 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
930 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
931 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
932 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
933 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
934 }
935 }
936
937 /* Write data to memory */
938 for(; index < size; index++)
939 {
940 *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
941 }
942
943 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
944
945 /* Read status until NAND is ready */
946 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
947 {
948 /* Get tick */
949 tickstart = HAL_GetTick();
950
951 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
952 {
953 return HAL_TIMEOUT;
954 }
955 }
956
957 /* Increment written pages number */
958 numPagesWritten++;
959
960 /* Decrement pages to write */
961 NumPageToWrite--;
962
963 /* Increment the NAND address */
964 nandaddress = (uint32_t)(nandaddress + 1U);
965 }
966
967 /* Update the NAND controller state */
968 hnand->State = HAL_NAND_STATE_READY;
969
970 /* Process unlocked */
971 __HAL_UNLOCK(hnand);
972
973 return HAL_OK;
974 }
975
976 /**
977 * @brief Read Spare area(s) from NAND memory
978 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
979 * the configuration information for NAND module.
980 * @param pAddress pointer to NAND address structure
981 * @param pBuffer pointer to source buffer to write
982 * @param NumSpareAreaToRead Number of spare area to read
983 * @retval HAL status
984 */
985 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
986 {
987 __IO uint32_t index = 0U;
988 uint32_t tickstart = 0U;
989 uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
990
991 /* Process Locked */
992 __HAL_LOCK(hnand);
993
994 /* Check the NAND controller state */
995 if(hnand->State == HAL_NAND_STATE_BUSY)
996 {
997 return HAL_BUSY;
998 }
999
1000 /* Identify the device address */
1001 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1002 {
1003 deviceaddress = NAND_DEVICE1;
1004 }
1005 else
1006 {
1007 deviceaddress = NAND_DEVICE2;
1008 }
1009
1010 /* Update the NAND controller state */
1011 hnand->State = HAL_NAND_STATE_BUSY;
1012
1013 /* NAND raw address calculation */
1014 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1015
1016 /* Column in page address */
1017 columnaddress = COLUMN_ADDRESS(hnand);
1018
1019 /* Spare area(s) read loop */
1020 while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1021 {
1022 /* update the buffer size */
1023 size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1024
1025 /* Cards with page size <= 512 bytes */
1026 if((hnand->Config.PageSize) <= 512U)
1027 {
1028 /* Send read spare area command sequence */
1029 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1030
1031 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1032 {
1033 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1034 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1035 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1036 }
1037 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1038 {
1039 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1040 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1041 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1042 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1043 }
1044 }
1045 else /* (hnand->Config.PageSize) > 512 */
1046 {
1047 /* Send read spare area command sequence */
1048 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1049
1050 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1051 {
1052 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1053 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1054 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1055 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1056 }
1057 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1058 {
1059 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1060 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1061 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1062 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1063 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1064 }
1065 }
1066
1067 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1068
1069 if(hnand->Config.ExtraCommandEnable == ENABLE)
1070 {
1071 /* Get tick */
1072 tickstart = HAL_GetTick();
1073
1074 /* Read status until NAND is ready */
1075 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1076 {
1077 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1078 {
1079 return HAL_TIMEOUT;
1080 }
1081 }
1082
1083 /* Go back to read mode */
1084 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
1085 }
1086
1087 /* Get Data into Buffer */
1088 for(; index < size; index++)
1089 {
1090 *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress;
1091 }
1092
1093 /* Increment read spare areas number */
1094 numSpareAreaRead++;
1095
1096 /* Decrement spare areas to read */
1097 NumSpareAreaToRead--;
1098
1099 /* Increment the NAND address */
1100 nandaddress = (uint32_t)(nandaddress + 1U);
1101 }
1102
1103 /* Update the NAND controller state */
1104 hnand->State = HAL_NAND_STATE_READY;
1105
1106 /* Process unlocked */
1107 __HAL_UNLOCK(hnand);
1108
1109 return HAL_OK;
1110 }
1111
1112 /**
1113 * @brief Read Spare area(s) from NAND memory (16-bits addressing)
1114 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1115 * the configuration information for NAND module.
1116 * @param pAddress pointer to NAND address structure
1117 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
1118 * @param NumSpareAreaToRead Number of spare area to read
1119 * @retval HAL status
1120 */
1121 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
1122 {
1123 __IO uint32_t index = 0U;
1124 uint32_t tickstart = 0U;
1125 uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U;
1126
1127 /* Process Locked */
1128 __HAL_LOCK(hnand);
1129
1130 /* Check the NAND controller state */
1131 if(hnand->State == HAL_NAND_STATE_BUSY)
1132 {
1133 return HAL_BUSY;
1134 }
1135
1136 /* Identify the device address */
1137 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1138 {
1139 deviceaddress = NAND_DEVICE1;
1140 }
1141 else
1142 {
1143 deviceaddress = NAND_DEVICE2;
1144 }
1145
1146 /* Update the NAND controller state */
1147 hnand->State = HAL_NAND_STATE_BUSY;
1148
1149 /* NAND raw address calculation */
1150 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1151
1152 /* Column in page address */
1153 columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1154
1155 /* Spare area(s) read loop */
1156 while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1157 {
1158 /* update the buffer size */
1159 size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead);
1160
1161 /* Cards with page size <= 512 bytes */
1162 if((hnand->Config.PageSize) <= 512U)
1163 {
1164 /* Send read spare area command sequence */
1165 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1166
1167 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1168 {
1169 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1170 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1171 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1172 }
1173 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1174 {
1175 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1176 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1177 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1178 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1179 }
1180 }
1181 else /* (hnand->Config.PageSize) > 512 */
1182 {
1183 /* Send read spare area command sequence */
1184 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1185
1186 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1187 {
1188 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1189 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1190 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1191 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1192 }
1193 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1194 {
1195 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1196 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1197 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1198 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1199 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1200 }
1201 }
1202
1203 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1204
1205 if(hnand->Config.ExtraCommandEnable == ENABLE)
1206 {
1207 /* Get tick */
1208 tickstart = HAL_GetTick();
1209
1210 /* Read status until NAND is ready */
1211 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1212 {
1213 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1214 {
1215 return HAL_TIMEOUT;
1216 }
1217 }
1218
1219 /* Go back to read mode */
1220 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00);
1221 }
1222
1223 /* Get Data into Buffer */
1224 for(; index < size; index++)
1225 {
1226 *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress;
1227 }
1228
1229 /* Increment read spare areas number */
1230 numSpareAreaRead++;
1231
1232 /* Decrement spare areas to read */
1233 NumSpareAreaToRead--;
1234
1235 /* Increment the NAND address */
1236 nandaddress = (uint32_t)(nandaddress + 1U);
1237 }
1238
1239 /* Update the NAND controller state */
1240 hnand->State = HAL_NAND_STATE_READY;
1241
1242 /* Process unlocked */
1243 __HAL_UNLOCK(hnand);
1244
1245 return HAL_OK;
1246 }
1247
1248 /**
1249 * @brief Write Spare area(s) to NAND memory
1250 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1251 * the configuration information for NAND module.
1252 * @param pAddress pointer to NAND address structure
1253 * @param pBuffer pointer to source buffer to write
1254 * @param NumSpareAreaTowrite : number of spare areas to write to block
1255 * @retval HAL status
1256 */
1257 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
1258 {
1259 __IO uint32_t index = 0U;
1260 uint32_t tickstart = 0U;
1261 uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
1262
1263 /* Process Locked */
1264 __HAL_LOCK(hnand);
1265
1266 /* Check the NAND controller state */
1267 if(hnand->State == HAL_NAND_STATE_BUSY)
1268 {
1269 return HAL_BUSY;
1270 }
1271
1272 /* Identify the device address */
1273 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1274 {
1275 deviceaddress = NAND_DEVICE1;
1276 }
1277 else
1278 {
1279 deviceaddress = NAND_DEVICE2;
1280 }
1281
1282 /* Update the FMC_NAND controller state */
1283 hnand->State = HAL_NAND_STATE_BUSY;
1284
1285 /* Page address calculation */
1286 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1287
1288 /* Column in page address */
1289 columnaddress = COLUMN_ADDRESS(hnand);
1290
1291 /* Spare area(s) write loop */
1292 while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1293 {
1294 /* update the buffer size */
1295 size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1296
1297 /* Cards with page size <= 512 bytes */
1298 if((hnand->Config.PageSize) <= 512U)
1299 {
1300 /* Send write Spare area command sequence */
1301 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1302 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1303
1304 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1305 {
1306 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1307 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1308 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1309 }
1310 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1311 {
1312 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1313 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1314 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1315 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1316 }
1317 }
1318 else /* (hnand->Config.PageSize) > 512 */
1319 {
1320 /* Send write Spare area command sequence */
1321 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1322 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1323
1324 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1325 {
1326 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1327 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1328 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1329 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1330 }
1331 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1332 {
1333 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1334 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1335 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1336 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1337 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1338 }
1339 }
1340
1341 /* Write data to memory */
1342 for(; index < size; index++)
1343 {
1344 *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++;
1345 }
1346
1347 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1348
1349 /* Get tick */
1350 tickstart = HAL_GetTick();
1351
1352 /* Read status until NAND is ready */
1353 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1354 {
1355 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1356 {
1357 return HAL_TIMEOUT;
1358 }
1359 }
1360
1361 /* Increment written spare areas number */
1362 numSpareAreaWritten++;
1363
1364 /* Decrement spare areas to write */
1365 NumSpareAreaTowrite--;
1366
1367 /* Increment the NAND address */
1368 nandaddress = (uint32_t)(nandaddress + 1U);
1369 }
1370
1371 /* Update the NAND controller state */
1372 hnand->State = HAL_NAND_STATE_READY;
1373
1374 /* Process unlocked */
1375 __HAL_UNLOCK(hnand);
1376
1377 return HAL_OK;
1378 }
1379
1380 /**
1381 * @brief Write Spare area(s) to NAND memory (16-bits addressing)
1382 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1383 * the configuration information for NAND module.
1384 * @param pAddress pointer to NAND address structure
1385 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
1386 * @param NumSpareAreaTowrite : number of spare areas to write to block
1387 * @retval HAL status
1388 */
1389 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
1390 {
1391 __IO uint32_t index = 0U;
1392 uint32_t tickstart = 0U;
1393 uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U;
1394
1395 /* Process Locked */
1396 __HAL_LOCK(hnand);
1397
1398 /* Check the NAND controller state */
1399 if(hnand->State == HAL_NAND_STATE_BUSY)
1400 {
1401 return HAL_BUSY;
1402 }
1403
1404 /* Identify the device address */
1405 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1406 {
1407 deviceaddress = NAND_DEVICE1;
1408 }
1409 else
1410 {
1411 deviceaddress = NAND_DEVICE2;
1412 }
1413
1414 /* Update the FMC_NAND controller state */
1415 hnand->State = HAL_NAND_STATE_BUSY;
1416
1417 /* NAND raw address calculation */
1418 nandaddress = ARRAY_ADDRESS(pAddress, hnand);
1419
1420 /* Column in page address */
1421 columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1422
1423 /* Spare area(s) write loop */
1424 while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1425 {
1426 /* update the buffer size */
1427 size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten);
1428
1429 /* Cards with page size <= 512 bytes */
1430 if((hnand->Config.PageSize) <= 512U)
1431 {
1432 /* Send write Spare area command sequence */
1433 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C;
1434 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1435
1436 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1437 {
1438 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1439 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1440 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1441 }
1442 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1443 {
1444 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00;
1445 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1446 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1447 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1448 }
1449 }
1450 else /* (hnand->Config.PageSize) > 512 */
1451 {
1452 /* Send write Spare area command sequence */
1453 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A;
1454 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0;
1455
1456 if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U)
1457 {
1458 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1459 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1460 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1461 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1462 }
1463 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1464 {
1465 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress);
1466 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress);
1467 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress);
1468 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress);
1469 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress);
1470 }
1471 }
1472
1473 /* Write data to memory */
1474 for(; index < size; index++)
1475 {
1476 *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++;
1477 }
1478
1479 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1480
1481 /* Read status until NAND is ready */
1482 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1483 {
1484 /* Get tick */
1485 tickstart = HAL_GetTick();
1486
1487 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1488 {
1489 return HAL_TIMEOUT;
1490 }
1491 }
1492
1493 /* Increment written spare areas number */
1494 numSpareAreaWritten++;
1495
1496 /* Decrement spare areas to write */
1497 NumSpareAreaTowrite--;
1498
1499 /* Increment the NAND address */
1500 nandaddress = (uint32_t)(nandaddress + 1U);
1501 }
1502
1503 /* Update the NAND controller state */
1504 hnand->State = HAL_NAND_STATE_READY;
1505
1506 /* Process unlocked */
1507 __HAL_UNLOCK(hnand);
1508
1509 return HAL_OK;
1510 }
1511
1512 /**
1513 * @brief NAND memory Block erase
1514 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1515 * the configuration information for NAND module.
1516 * @param pAddress pointer to NAND address structure
1517 * @retval HAL status
1518 */
1519 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1520 {
1521 uint32_t deviceaddress = 0U;
1522 uint32_t tickstart = 0U;
1523
1524 /* Process Locked */
1525 __HAL_LOCK(hnand);
1526
1527 /* Check the NAND controller state */
1528 if(hnand->State == HAL_NAND_STATE_BUSY)
1529 {
1530 return HAL_BUSY;
1531 }
1532
1533 /* Identify the device address */
1534 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1535 {
1536 deviceaddress = NAND_DEVICE1;
1537 }
1538 else
1539 {
1540 deviceaddress = NAND_DEVICE2;
1541 }
1542
1543 /* Update the NAND controller state */
1544 hnand->State = HAL_NAND_STATE_BUSY;
1545
1546 /* Send Erase block command sequence */
1547 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0;
1548
1549 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1550 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1551 *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1552
1553 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1;
1554
1555 /* Update the NAND controller state */
1556 hnand->State = HAL_NAND_STATE_READY;
1557
1558 /* Get tick */
1559 tickstart = HAL_GetTick();
1560
1561 /* Read status until NAND is ready */
1562 while(HAL_NAND_Read_Status(hnand) != NAND_READY)
1563 {
1564 if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
1565 {
1566 /* Process unlocked */
1567 __HAL_UNLOCK(hnand);
1568
1569 return HAL_TIMEOUT;
1570 }
1571 }
1572
1573 /* Process unlocked */
1574 __HAL_UNLOCK(hnand);
1575
1576 return HAL_OK;
1577 }
1578
1579 /**
1580 * @brief NAND memory read status
1581 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1582 * the configuration information for NAND module.
1583 * @retval NAND status
1584 */
1585 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
1586 {
1587 uint32_t data = 0U;
1588 uint32_t deviceaddress = 0U;
1589
1590 /* Identify the device address */
1591 if(hnand->Init.NandBank == FMC_NAND_BANK2)
1592 {
1593 deviceaddress = NAND_DEVICE1;
1594 }
1595 else
1596 {
1597 deviceaddress = NAND_DEVICE2;
1598 }
1599
1600 /* Send Read status operation command */
1601 *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS;
1602
1603 /* Read status register data */
1604 data = *(__IO uint8_t *)deviceaddress;
1605
1606 /* Return the status */
1607 if((data & NAND_ERROR) == NAND_ERROR)
1608 {
1609 return NAND_ERROR;
1610 }
1611 else if((data & NAND_READY) == NAND_READY)
1612 {
1613 return NAND_READY;
1614 }
1615
1616 return NAND_BUSY;
1617 }
1618
1619 /**
1620 * @brief Increment the NAND memory address
1621 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1622 * the configuration information for NAND module.
1623 * @param pAddress pointer to NAND address structure
1624 * @retval The new status of the increment address operation. It can be:
1625 * - NAND_VALID_ADDRESS: When the new address is valid address
1626 * - NAND_INVALID_ADDRESS: When the new address is invalid address
1627 */
1628 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1629 {
1630 uint32_t status = NAND_VALID_ADDRESS;
1631
1632 /* Increment page address */
1633 pAddress->Page++;
1634
1635 /* Check NAND address is valid */
1636 if(pAddress->Page == hnand->Config.BlockSize)
1637 {
1638 pAddress->Page = 0U;
1639 pAddress->Block++;
1640
1641 if(pAddress->Block == hnand->Config.PlaneSize)
1642 {
1643 pAddress->Block = 0U;
1644 pAddress->Plane++;
1645
1646 if(pAddress->Plane == (hnand->Config.PlaneNbr))
1647 {
1648 status = NAND_INVALID_ADDRESS;
1649 }
1650 }
1651 }
1652
1653 return (status);
1654 }
1655 /**
1656 * @}
1657 */
1658
1659 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
1660 * @brief management functions
1661 *
1662 @verbatim
1663 ==============================================================================
1664 ##### NAND Control functions #####
1665 ==============================================================================
1666 [..]
1667 This subsection provides a set of functions allowing to control dynamically
1668 the NAND interface.
1669
1670 @endverbatim
1671 * @{
1672 */
1673
1674
1675 /**
1676 * @brief Enables dynamically NAND ECC feature.
1677 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1678 * the configuration information for NAND module.
1679 * @retval HAL status
1680 */
1681 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
1682 {
1683 /* Check the NAND controller state */
1684 if(hnand->State == HAL_NAND_STATE_BUSY)
1685 {
1686 return HAL_BUSY;
1687 }
1688
1689 /* Update the NAND state */
1690 hnand->State = HAL_NAND_STATE_BUSY;
1691
1692 /* Enable ECC feature */
1693 FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
1694
1695 /* Update the NAND state */
1696 hnand->State = HAL_NAND_STATE_READY;
1697
1698 return HAL_OK;
1699 }
1700
1701 /**
1702 * @brief Disables dynamically FMC_NAND ECC feature.
1703 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1704 * the configuration information for NAND module.
1705 * @retval HAL status
1706 */
1707 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
1708 {
1709 /* Check the NAND controller state */
1710 if(hnand->State == HAL_NAND_STATE_BUSY)
1711 {
1712 return HAL_BUSY;
1713 }
1714
1715 /* Update the NAND state */
1716 hnand->State = HAL_NAND_STATE_BUSY;
1717
1718 /* Disable ECC feature */
1719 FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
1720
1721 /* Update the NAND state */
1722 hnand->State = HAL_NAND_STATE_READY;
1723
1724 return HAL_OK;
1725 }
1726
1727 /**
1728 * @brief Disables dynamically NAND ECC feature.
1729 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1730 * the configuration information for NAND module.
1731 * @param ECCval pointer to ECC value
1732 * @param Timeout maximum timeout to wait
1733 * @retval HAL status
1734 */
1735 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
1736 {
1737 HAL_StatusTypeDef status = HAL_OK;
1738
1739 /* Check the NAND controller state */
1740 if(hnand->State == HAL_NAND_STATE_BUSY)
1741 {
1742 return HAL_BUSY;
1743 }
1744
1745 /* Update the NAND state */
1746 hnand->State = HAL_NAND_STATE_BUSY;
1747
1748 /* Get NAND ECC value */
1749 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
1750
1751 /* Update the NAND state */
1752 hnand->State = HAL_NAND_STATE_READY;
1753
1754 return status;
1755 }
1756
1757 /**
1758 * @}
1759 */
1760
1761
1762 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
1763 * @brief Peripheral State functions
1764 *
1765 @verbatim
1766 ==============================================================================
1767 ##### NAND State functions #####
1768 ==============================================================================
1769 [..]
1770 This subsection permits to get in run-time the status of the NAND controller
1771 and the data flow.
1772
1773 @endverbatim
1774 * @{
1775 */
1776
1777 /**
1778 * @brief return the NAND state
1779 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1780 * the configuration information for NAND module.
1781 * @retval HAL state
1782 */
1783 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
1784 {
1785 return hnand->State;
1786 }
1787
1788 /**
1789 * @}
1790 */
1791
1792 /**
1793 * @}
1794 */
1795
1796 /**
1797 * @}
1798 */
1799
1800 #endif /* HAL_NAND_MODULE_ENABLED */
1801
1802 /**
1803 * @}
1804 */
1805 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
1806
1807 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/