lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_pwr.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_pwr.c
   4   * @author  MCD Application Team
   5   * @brief   PWR HAL module driver.
   6   *          This file provides firmware functions to manage the following
   7   *          functionalities of the Power Controller (PWR) peripheral:
   8   *           + Initialization/de-initialization functions
   9   *           + Peripheral Control functions
  10   *
  11   @verbatim
  12   ******************************************************************************
  13   * @attention
  14   *
  15   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  16   *
  17   * Redistribution and use in source and binary forms, with or without modification,
  18   * are permitted provided that the following conditions are met:
  19   *   1. Redistributions of source code must retain the above copyright notice,
  20   *      this list of conditions and the following disclaimer.
  21   *   2. Redistributions in binary form must reproduce the above copyright notice,
  22   *      this list of conditions and the following disclaimer in the documentation
  23   *      and/or other materials provided with the distribution.
  24   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  25   *      may be used to endorse or promote products derived from this software
  26   *      without specific prior written permission.
  27   *
  28   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  29   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  30   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  32   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  34   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  35   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  36   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  37   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38   *
  39   ******************************************************************************
  40   */
  41
  42 /* Includes ------------------------------------------------------------------*/
  43 #include "stm32f3xx_hal.h"
  44
  45 /** @addtogroup STM32F3xx_HAL_Driver
  46   * @{
  47   */
  48
  49 /** @defgroup PWR PWR
  50   * @brief PWR HAL module driver
  51   * @{
  52   */
  53
  54 #ifdef HAL_PWR_MODULE_ENABLED
  55
  56 /* Private typedef -----------------------------------------------------------*/
  57 /* Private define ------------------------------------------------------------*/
  58 /* Private macro -------------------------------------------------------------*/
  59 /* Private variables ---------------------------------------------------------*/
  60 /* Private function prototypes -----------------------------------------------*/
  61 /* Private functions ---------------------------------------------------------*/
  62
  63 /** @defgroup PWR_Exported_Functions PWR Exported Functions
  64   * @{
  65   */
  66
  67 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  68   *  @brief    Initialization and de-initialization functions
  69   *
  70 @verbatim
  71  ===============================================================================
  72               ##### Initialization and de-initialization functions #####
  73  ===============================================================================
  74     [..]
  75       After reset, the backup domain (RTC registers, RTC backup data
  76       registers and backup SRAM) is protected against possible unwanted
  77       write accesses.
  78       To enable access to the RTC Domain and RTC registers, proceed as follows:
  79         (+) Enable the Power Controller (PWR) APB1 interface clock using the
  80             __HAL_RCC_PWR_CLK_ENABLE() macro.
  81         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  82
  83 @endverbatim
  84   * @{
  85   */
  86
  87 /**
  88   * @brief Deinitializes the PWR peripheral registers to their default reset values.
  89   * @retval None
  90   */
  91 void HAL_PWR_DeInit(void)
  92 {
  93   __HAL_RCC_PWR_FORCE_RESET();
  94   __HAL_RCC_PWR_RELEASE_RESET();
  95 }
  96
  97 /**
  98   * @brief Enables access to the backup domain (RTC registers, RTC
  99   *         backup data registers and backup SRAM).
 100   * @note  If the HSE divided by 32 is used as the RTC clock, the
 101   *         Backup Domain Access should be kept enabled.
 102   * @retval None
 103   */
 104 void HAL_PWR_EnableBkUpAccess(void)
 105 {
 106   SET_BIT(PWR->CR, PWR_CR_DBP);
 107 }
 108
 109 /**
 110   * @brief Disables access to the backup domain (RTC registers, RTC
 111   *         backup data registers and backup SRAM).
 112   * @note  If the HSE divided by 32 is used as the RTC clock, the
 113   *         Backup Domain Access should be kept enabled.
 114   * @retval None
 115   */
 116 void HAL_PWR_DisableBkUpAccess(void)
 117 {
 118   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
 119 }
 120
 121 /**
 122   * @}
 123   */
 124
 125 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
 126   *  @brief Low Power modes configuration functions
 127   *
 128 @verbatim
 129
 130  ===============================================================================
 131                  ##### Peripheral Control functions #####
 132  ===============================================================================
 133
 134     *** WakeUp pin configuration ***
 135     ================================
 136     [..]
 137       (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
 138           forced in input pull down configuration and is active on rising edges.
 139       (+) There are up to three WakeUp pins:
 140           (++)WakeUp Pin 1 on PA.00.
 141           (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
 142           (++)WakeUp Pin 3 on PE.06.
 143
 144     *** Main and Backup Regulators configuration ***
 145     ================================================
 146     [..]
 147       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
 148           the backup SRAM is powered from VDD which replaces the VBAT power supply to
 149           save battery life.
 150
 151       (+) The backup SRAM is not mass erased by a tamper event. It is read
 152           protected to prevent confidential data, such as cryptographic private
 153           key, from being accessed. The backup SRAM can be erased only through
 154           the Flash interface when a protection level change from level 1 to
 155           level 0 is requested.
 156       -@- Refer to the description of Read protection (RDP) in the Flash
 157           programming manual.
 158
 159         Refer to the datasheets for more details.
 160
 161     *** Low Power modes configuration ***
 162     =====================================
 163     [..]
 164       The devices feature 3 low-power modes:
 165       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
 166       (+) Stop mode: all clocks are stopped, regulator running, regulator
 167           in low power mode
 168       (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
 169
 170    *** Sleep mode ***
 171    ==================
 172     [..]
 173       (+) Entry:
 174           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
 175               functions with
 176           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
 177           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
 178
 179       (+) Exit:
 180         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
 181               controller (NVIC) can wake up the device from Sleep mode.
 182
 183    *** Stop mode ***
 184    =================
 185     [..]
 186       In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
 187       and the HSE RC oscillators are disabled. Internal SRAM and register contents
 188       are preserved.
 189       The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
 190
 191       (+) Entry:
 192           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
 193              function with:
 194           (++) Main regulator ON or
 195           (++) Low Power regulator ON.
 196           (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
 197           (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
 198       (+) Exit:
 199           (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
 200           (++) Some specific communication peripherals (CEC, USART, I2C) interrupts,
 201                when programmed in wakeup mode (the peripheral must be
 202                programmed in wakeup mode and the corresponding interrupt vector
 203                must be enabled in the NVIC).
 204
 205    *** Standby mode ***
 206    ====================
 207      [..]
 208       The Standby mode allows to achieve the lowest power consumption. It is based
 209       on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
 210       The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
 211       the HSE oscillator are also switched off. SRAM and register contents are lost
 212       except for the RTC registers, RTC backup registers, backup SRAM and Standby
 213       circuitry.
 214       The voltage regulator is OFF.
 215
 216       (+) Entry:
 217           (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
 218       (+) Exit:
 219           (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
 220                tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
 221
 222    *** Auto-wakeup (AWU) from low-power mode ***
 223    =============================================
 224     [..]
 225       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
 226       Wakeup event, a tamper event, a time-stamp event, or a comparator event,
 227       without depending on an external interrupt (Auto-wakeup mode).
 228
 229     (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
 230
 231       (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
 232             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
 233
 234       (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
 235            is necessary to configure the RTC to detect the tamper or time stamp event using the
 236            HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
 237
 238       (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
 239            configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
 240
 241     (+) Comparator auto-wakeup (AWU) from the Stop mode
 242
 243       (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
 244            (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U)
 245                  to be sensitive to to the selected edges (falling, rising or falling
 246                  and rising) (Interrupt or Event modes) using the EXTI_Init() function.
 247            (+++) Configure the comparator to generate the event.
 248 @endverbatim
 249   * @{
 250   */
 251
 252 /**
 253   * @brief Enables the WakeUp PINx functionality.
 254   * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
 255   *         This parameter can be value of :
 256   *           @ref PWR_WakeUp_Pins
 257   * @retval None
 258   */
 259 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
 260 {
 261   /* Check the parameters */
 262   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 263   /* Enable the EWUPx pin */
 264   SET_BIT(PWR->CSR, WakeUpPinx);
 265 }
 266
 267 /**
 268   * @brief Disables the WakeUp PINx functionality.
 269   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
 270   *         This parameter can be values of :
 271   *           @ref PWR_WakeUp_Pins
 272   * @retval None
 273   */
 274 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
 275 {
 276   /* Check the parameters */
 277   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 278   /* Disable the EWUPx pin */
 279   CLEAR_BIT(PWR->CSR, WakeUpPinx);
 280 }
 281
 282 /**
 283   * @brief Enters Sleep mode.
 284   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
 285   * @param Regulator Specifies the regulator state in SLEEP mode.
 286   *          This parameter can be one of the following values:
 287   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
 288   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
 289   * @note This parameter has no effect in F3 family and is just maintained to
 290   *       offer full portability of other STM32 families softwares.
 291   * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
 292   *           When WFI entry is used, tick interrupt have to be disabled if not desired as
 293   *           the interrupt wake up source.
 294   *           This parameter can be one of the following values:
 295   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
 296   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
 297   * @retval None
 298   */
 299 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
 300 {
 301   /* Check the parameters */
 302   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
 303
 304   /* Clear SLEEPDEEP bit of Cortex System Control Register */
 305   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 306
 307   /* Select SLEEP mode entry -------------------------------------------------*/
 308   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
 309   {
 310     /* Request Wait For Interrupt */
 311     __WFI();
 312   }
 313   else
 314   {
 315     /* Request Wait For Event */
 316     __SEV();
 317     __WFE();
 318     __WFE();
 319   }
 320 }
 321
 322 /**
 323   * @brief Enters STOP mode.
 324   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
 325   * @note  When exiting Stop mode by issuing an interrupt or a wakeup event,
 326   *         the HSI RC oscillator is selected as system clock.
 327   * @note  When the voltage regulator operates in low power mode, an additional
 328   *         startup delay is incurred when waking up from Stop mode.
 329   *         By keeping the internal regulator ON during Stop mode, the consumption
 330   *         is higher although the startup time is reduced.
 331   * @param Regulator Specifies the regulator state in STOP mode.
 332   *          This parameter can be one of the following values:
 333   *            @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
 334   *            @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
 335   * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
 336   *          This parameter can be one of the following values:
 337   *            @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
 338   *            @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
 339   * @retval None
 340   */
 341 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 342 {
 343   uint32_t tmpreg = 0U;
 344
 345   /* Check the parameters */
 346   assert_param(IS_PWR_REGULATOR(Regulator));
 347   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
 348
 349   /* Select the regulator state in STOP mode ---------------------------------*/
 350   tmpreg = PWR->CR;
 351
 352   /* Clear PDDS and LPDS bits */
 353   tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
 354
 355   /* Set LPDS bit according to Regulator value */
 356   tmpreg |= Regulator;
 357
 358   /* Store the new value */
 359   PWR->CR = tmpreg;
 360
 361   /* Set SLEEPDEEP bit of Cortex System Control Register */
 362   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 363
 364   /* Select STOP mode entry --------------------------------------------------*/
 365   if(STOPEntry == PWR_STOPENTRY_WFI)
 366   {
 367     /* Request Wait For Interrupt */
 368     __WFI();
 369   }
 370   else
 371   {
 372     /* Request Wait For Event */
 373     __SEV();
 374     __WFE();
 375     __WFE();
 376   }
 377
 378   /* Reset SLEEPDEEP bit of Cortex System Control Register */
 379   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
 380 }
 381
 382 /**
 383   * @brief Enters STANDBY mode.
 384   * @note  In Standby mode, all I/O pins are high impedance except for:
 385   *          - Reset pad (still available),
 386   *          - RTC alternate function pins if configured for tamper, time-stamp, RTC
 387   *            Alarm out, or RTC clock calibration out,
 388   *          - WKUP pins if enabled.
 389   * @retval None
 390   */
 391 void HAL_PWR_EnterSTANDBYMode(void)
 392 {
 393   /* Select STANDBY mode */
 394   PWR->CR |= PWR_CR_PDDS;
 395
 396   /* Set SLEEPDEEP bit of Cortex System Control Register */
 397   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
 398
 399   /* This option is used to ensure that store operations are completed */
 400 #if defined ( __CC_ARM)
 401   __force_stores();
 402 #endif
 403   /* Request Wait For Interrupt */
 404   __WFI();
 405 }
 406
 407 /**
 408   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
 409   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
 410   *       re-enters SLEEP mode when an interruption handling is over.
 411   *       Setting this bit is useful when the processor is expected to run only on
 412   *       interruptions handling.
 413   * @retval None
 414   */
 415 void HAL_PWR_EnableSleepOnExit(void)
 416 {
 417   /* Set SLEEPONEXIT bit of Cortex System Control Register */
 418   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 419 }
 420
 421
 422 /**
 423   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
 424   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
 425   *       re-enters SLEEP mode when an interruption handling is over.
 426   * @retval None
 427   */
 428 void HAL_PWR_DisableSleepOnExit(void)
 429 {
 430   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
 431   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 432 }
 433
 434
 435
 436 /**
 437   * @brief Enables CORTEX M4 SEVONPEND bit.
 438   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
 439   *       WFE to wake up when an interrupt moves from inactive to pended.
 440   * @retval None
 441   */
 442 void HAL_PWR_EnableSEVOnPend(void)
 443 {
 444   /* Set SEVONPEND bit of Cortex System Control Register */
 445   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 446 }
 447
 448
 449 /**
 450   * @brief Disables CORTEX M4 SEVONPEND bit.
 451   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
 452   *       WFE to wake up when an interrupt moves from inactive to pended.
 453   * @retval None
 454   */
 455 void HAL_PWR_DisableSEVOnPend(void)
 456 {
 457   /* Clear SEVONPEND bit of Cortex System Control Register */
 458   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 459 }
 460 /**
 461   * @}
 462   */
 463
 464 /**
 465   * @}
 466   */
 467
 468 #endif /* HAL_PWR_MODULE_ENABLED */
 469 /**
 470   * @}
 471   */
 472
 473 /**
 474   * @}
 475   */
 476
 477 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/