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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Src / stm32f3xx_hal_tim.c
blob0c51e849216bdb8d602f3558490b6e49510a705f
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + Time Base Initialization
9 * + Time Base Start
10 * + Time Base Start Interruption
11 * + Time Base Start DMA
12 * + Time Output Compare/PWM Initialization
13 * + Time Output Compare/PWM Channel Configuration
14 * + Time Output Compare/PWM Start
15 * + Time Output Compare/PWM Start Interruption
16 * + Time Output Compare/PWM Start DMA
17 * + Time Input Capture Initialization
18 * + Time Input Capture Channel Configuration
19 * + Time Input Capture Start
20 * + Time Input Capture Start Interruption
21 * + Time Input Capture Start DMA
22 * + Time One Pulse Initialization
23 * + Time One Pulse Channel Configuration
24 * + Time One Pulse Start
25 * + Time Encoder Interface Initialization
26 * + Time Encoder Interface Start
27 * + Time Encoder Interface Start Interruption
28 * + Time Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + Time OCRef clear configuration
31 * + Time External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45
46 ##### How to use this driver #####
47 ==============================================================================
48 [..]
49 (#) Initialize the TIM low level resources by implementing the following functions
50 depending from feature used :
51 (++) Time Base : HAL_TIM_Base_MspInit()
52 (++) Input Capture : HAL_TIM_IC_MspInit()
53 (++) Output Compare : HAL_TIM_OC_MspInit()
54 (++) PWM generation : HAL_TIM_PWM_MspInit()
55 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
56 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
57
58 (#) Initialize the TIM low level resources :
59 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
60 (##) TIM pins configuration
61 (+++) Enable the clock for the TIM GPIOs using the following function:
62 __HAL_RCC_GPIOx_CLK_ENABLE();
63 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
64
65 (#) The external Clock can be configured, if needed (the default clock is the
66 internal clock from the APBx), using the following function:
67 HAL_TIM_ConfigClockSource, the clock configuration should be done before
68 any start function.
69
70 (#) Configure the TIM in the desired functioning mode using one of the
71 Initialization function of this driver:
72 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
73 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
74 Output Compare signal.
75 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
76 PWM signal.
77 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
78 external signal.
79 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
80 in One Pulse Mode.
81 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
82
83 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
84 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
85 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
86 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
87 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
88 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
89 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
90
91 (#) The DMA Burst is managed with the two following functions:
92 HAL_TIM_DMABurst_WriteStart()
93 HAL_TIM_DMABurst_ReadStart()
94
95 @endverbatim
96 ******************************************************************************
97 * @attention
98 *
99 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
100 *
101 * Redistribution and use in source and binary forms, with or without modification,
102 * are permitted provided that the following conditions are met:
103 * 1. Redistributions of source code must retain the above copyright notice,
104 * this list of conditions and the following disclaimer.
105 * 2. Redistributions in binary form must reproduce the above copyright notice,
106 * this list of conditions and the following disclaimer in the documentation
107 * and/or other materials provided with the distribution.
108 * 3. Neither the name of STMicroelectronics nor the names of its contributors
109 * may be used to endorse or promote products derived from this software
110 * without specific prior written permission.
111 *
112 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
113 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
114 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
115 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
116 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
117 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
118 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
119 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
120 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
121 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
122 *
123 ******************************************************************************
124 */
125
126 /* Includes ------------------------------------------------------------------*/
127 #include "stm32f3xx_hal.h"
128
129 /** @addtogroup STM32F3xx_HAL_Driver
130 * @{
131 */
132
133 /** @defgroup TIM TIM
134 * @brief TIM HAL module driver
135 * @{
136 */
137
138 #ifdef HAL_TIM_MODULE_ENABLED
139
140 /* Private typedef -----------------------------------------------------------*/
141 /* Private define ------------------------------------------------------------*/
142 /* Private macro -------------------------------------------------------------*/
143 /* Private variables ---------------------------------------------------------*/
144 /* Private function prototypes -----------------------------------------------*/
145
146 /** @defgroup TIM_Private_Functions TIM Private Functions
147 * @{
148 */
149 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
150 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
151 uint32_t TIM_ICFilter);
152 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
153 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
154 uint32_t TIM_ICFilter);
155 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
156 uint32_t TIM_ICFilter);
157 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
158 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
159 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
160 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
161 TIM_SlaveConfigTypeDef * sSlaveConfig);
162
163 /**
164 * @}
165 */
166
167 /* Exported functions ---------------------------------------------------------*/
168
169 /** @defgroup TIM_Exported_Functions TIM Exported Functions
170 * @{
171 */
172
173 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
174 * @brief Time Base functions
175 *
176 @verbatim
177 ==============================================================================
178 ##### Time Base functions #####
179 ==============================================================================
180 [..]
181 This section provides functions allowing to:
182 (+) Initialize and configure the TIM base.
183 (+) De-initialize the TIM base.
184 (+) Start the Time Base.
185 (+) Stop the Time Base.
186 (+) Start the Time Base and enable interrupt.
187 (+) Stop the Time Base and disable interrupt.
188 (+) Start the Time Base and enable DMA transfer.
189 (+) Stop the Time Base and disable DMA transfer.
190
191 @endverbatim
192 * @{
193 */
194 /**
195 * @brief Initializes the TIM Time base Unit according to the specified
196 * parameters in the TIM_HandleTypeDef and create the associated handle.
197 * @param htim TIM Base handle
198 * @retval HAL status
199 */
200 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
201 {
202 /* Check the TIM handle allocation */
203 if(htim == NULL)
204 {
205 return HAL_ERROR;
206 }
207
208 /* Check the parameters */
209 assert_param(IS_TIM_INSTANCE(htim->Instance));
210 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
211 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
212 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
213
214 if(htim->State == HAL_TIM_STATE_RESET)
215 {
216 /* Allocate lock resource and initialize it */
217 htim->Lock = HAL_UNLOCKED;
218
219 /* Init the low level hardware : GPIO, CLOCK, NVIC */
220 HAL_TIM_Base_MspInit(htim);
221 }
222
223 /* Set the TIM state */
224 htim->State= HAL_TIM_STATE_BUSY;
225
226 /* Set the Time Base configuration */
227 TIM_Base_SetConfig(htim->Instance, &htim->Init);
228
229 /* Initialize the TIM state*/
230 htim->State= HAL_TIM_STATE_READY;
231
232 return HAL_OK;
233 }
234
235 /**
236 * @brief DeInitializes the TIM Base peripheral
237 * @param htim TIM Base handle
238 * @retval HAL status
239 */
240 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
241 {
242 /* Check the parameters */
243 assert_param(IS_TIM_INSTANCE(htim->Instance));
244
245 htim->State = HAL_TIM_STATE_BUSY;
246
247 /* Disable the TIM Peripheral Clock */
248 __HAL_TIM_DISABLE(htim);
249
250 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
251 HAL_TIM_Base_MspDeInit(htim);
252
253 /* Change TIM state */
254 htim->State = HAL_TIM_STATE_RESET;
255
256 /* Release Lock */
257 __HAL_UNLOCK(htim);
258
259 return HAL_OK;
260 }
261
262 /**
263 * @brief Initializes the TIM Base MSP.
264 * @param htim TIM handle
265 * @retval None
266 */
267 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
268 {
269 /* Prevent unused argument(s) compilation warning */
270 UNUSED(htim);
271
272 /* NOTE : This function Should not be modified, when the callback is needed,
273 the HAL_TIM_Base_MspInit could be implemented in the user file
274 */
275 }
276
277 /**
278 * @brief DeInitializes TIM Base MSP.
279 * @param htim TIM handle
280 * @retval None
281 */
282 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
283 {
284 /* Prevent unused argument(s) compilation warning */
285 UNUSED(htim);
286
287 /* NOTE : This function Should not be modified, when the callback is needed,
288 the HAL_TIM_Base_MspDeInit could be implemented in the user file
289 */
290 }
291
292
293 /**
294 * @brief Starts the TIM Base generation.
295 * @param htim TIM handle
296 * @retval HAL status
297 */
298 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
299 {
300 /* Check the parameters */
301 assert_param(IS_TIM_INSTANCE(htim->Instance));
302
303 /* Set the TIM state */
304 htim->State= HAL_TIM_STATE_BUSY;
305
306 /* Enable the Peripheral */
307 __HAL_TIM_ENABLE(htim);
308
309 /* Change the TIM state*/
310 htim->State= HAL_TIM_STATE_READY;
311
312 /* Return function status */
313 return HAL_OK;
314 }
315
316 /**
317 * @brief Stops the TIM Base generation.
318 * @param htim TIM handle
319 * @retval HAL status
320 */
321 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
322 {
323 /* Check the parameters */
324 assert_param(IS_TIM_INSTANCE(htim->Instance));
325
326 /* Set the TIM state */
327 htim->State= HAL_TIM_STATE_BUSY;
328
329 /* Disable the Peripheral */
330 __HAL_TIM_DISABLE(htim);
331
332 /* Change the TIM state*/
333 htim->State= HAL_TIM_STATE_READY;
334
335 /* Return function status */
336 return HAL_OK;
337 }
338
339 /**
340 * @brief Starts the TIM Base generation in interrupt mode.
341 * @param htim TIM handle
342 * @retval HAL status
343 */
344 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
345 {
346 /* Check the parameters */
347 assert_param(IS_TIM_INSTANCE(htim->Instance));
348
349 /* Enable the TIM Update interrupt */
350 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
351
352 /* Enable the Peripheral */
353 __HAL_TIM_ENABLE(htim);
354
355 /* Return function status */
356 return HAL_OK;
357 }
358
359 /**
360 * @brief Stops the TIM Base generation in interrupt mode.
361 * @param htim TIM handle
362 * @retval HAL status
363 */
364 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
365 {
366 /* Check the parameters */
367 assert_param(IS_TIM_INSTANCE(htim->Instance));
368 /* Disable the TIM Update interrupt */
369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
370
371 /* Disable the Peripheral */
372 __HAL_TIM_DISABLE(htim);
373
374 /* Return function status */
375 return HAL_OK;
376 }
377
378 /**
379 * @brief Starts the TIM Base generation in DMA mode.
380 * @param htim TIM handle
381 * @param pData The source Buffer address.
382 * @param Length The length of data to be transferred from memory to peripheral.
383 * @retval HAL status
384 */
385 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
386 {
387 /* Check the parameters */
388 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
389
390 if((htim->State == HAL_TIM_STATE_BUSY))
391 {
392 return HAL_BUSY;
393 }
394 else if((htim->State == HAL_TIM_STATE_READY))
395 {
396 if((pData == 0U ) && (Length > 0U))
397 {
398 return HAL_ERROR;
399 }
400 else
401 {
402 htim->State = HAL_TIM_STATE_BUSY;
403 }
404 }
405 /* Set the DMA Period elapsed callback */
406 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
407
408 /* Set the DMA error callback */
409 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
410
411 /* Enable the DMA channel */
412 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
413
414 /* Enable the TIM Update DMA request */
415 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
416
417 /* Enable the Peripheral */
418 __HAL_TIM_ENABLE(htim);
419
420 /* Return function status */
421 return HAL_OK;
422 }
423
424 /**
425 * @brief Stops the TIM Base generation in DMA mode.
426 * @param htim TIM handle
427 * @retval HAL status
428 */
429 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
430 {
431 /* Check the parameters */
432 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
433
434 /* Disable the TIM Update DMA request */
435 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
436
437 /* Disable the Peripheral */
438 __HAL_TIM_DISABLE(htim);
439
440 /* Change the htim state */
441 htim->State = HAL_TIM_STATE_READY;
442
443 /* Return function status */
444 return HAL_OK;
445 }
446
447 /**
448 * @}
449 */
450
451 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
452 * @brief Time Output Compare functions
453 *
454 @verbatim
455 ==============================================================================
456 ##### Time Output Compare functions #####
457 ==============================================================================
458 [..]
459 This section provides functions allowing to:
460 (+) Initialize and configure the TIM Output Compare.
461 (+) De-initialize the TIM Output Compare.
462 (+) Start the Time Output Compare.
463 (+) Stop the Time Output Compare.
464 (+) Start the Time Output Compare and enable interrupt.
465 (+) Stop the Time Output Compare and disable interrupt.
466 (+) Start the Time Output Compare and enable DMA transfer.
467 (+) Stop the Time Output Compare and disable DMA transfer.
468
469 @endverbatim
470 * @{
471 */
472 /**
473 * @brief Initializes the TIM Output Compare according to the specified
474 * parameters in the TIM_HandleTypeDef and create the associated handle.
475 * @param htim TIM Output Compare handle
476 * @retval HAL status
477 */
478 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
479 {
480 /* Check the TIM handle allocation */
481 if(htim == NULL)
482 {
483 return HAL_ERROR;
484 }
485
486 /* Check the parameters */
487 assert_param(IS_TIM_INSTANCE(htim->Instance));
488 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
489 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
490 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
491
492 if(htim->State == HAL_TIM_STATE_RESET)
493 {
494 /* Allocate lock resource and initialize it */
495 htim->Lock = HAL_UNLOCKED;
496
497 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
498 HAL_TIM_OC_MspInit(htim);
499 }
500
501 /* Set the TIM state */
502 htim->State= HAL_TIM_STATE_BUSY;
503
504 /* Init the base time for the Output Compare */
505 TIM_Base_SetConfig(htim->Instance, &htim->Init);
506
507 /* Initialize the TIM state*/
508 htim->State= HAL_TIM_STATE_READY;
509
510 return HAL_OK;
511 }
512
513 /**
514 * @brief DeInitializes the TIM peripheral
515 * @param htim TIM Output Compare handle
516 * @retval HAL status
517 */
518 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
519 {
520 /* Check the parameters */
521 assert_param(IS_TIM_INSTANCE(htim->Instance));
522
523 htim->State = HAL_TIM_STATE_BUSY;
524
525 /* Disable the TIM Peripheral Clock */
526 __HAL_TIM_DISABLE(htim);
527
528 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
529 HAL_TIM_OC_MspDeInit(htim);
530
531 /* Change TIM state */
532 htim->State = HAL_TIM_STATE_RESET;
533
534 /* Release Lock */
535 __HAL_UNLOCK(htim);
536
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Initializes the TIM Output Compare MSP.
542 * @param htim TIM handle
543 * @retval None
544 */
545 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
546 {
547 /* Prevent unused argument(s) compilation warning */
548 UNUSED(htim);
549
550 /* NOTE : This function Should not be modified, when the callback is needed,
551 the HAL_TIM_OC_MspInit could be implemented in the user file
552 */
553 }
554
555 /**
556 * @brief DeInitializes TIM Output Compare MSP.
557 * @param htim TIM handle
558 * @retval None
559 */
560 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
561 {
562 /* Prevent unused argument(s) compilation warning */
563 UNUSED(htim);
564
565 /* NOTE : This function Should not be modified, when the callback is needed,
566 the HAL_TIM_OC_MspDeInit could be implemented in the user file
567 */
568 }
569
570 /**
571 * @brief Starts the TIM Output Compare signal generation.
572 * @param htim TIM Output Compare handle
573 * @param Channel TIM Channel to be enabled
574 * This parameter can be one of the following values:
575 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
576 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
577 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
578 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
579 * @retval HAL status
580 */
581 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
582 {
583 /* Check the parameters */
584 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
585
586 /* Enable the Output compare channel */
587 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
588
589 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
590 {
591 /* Enable the main output */
592 __HAL_TIM_MOE_ENABLE(htim);
593 }
594
595 /* Enable the Peripheral */
596 __HAL_TIM_ENABLE(htim);
597
598 /* Return function status */
599 return HAL_OK;
600 }
601
602 /**
603 * @brief Stops the TIM Output Compare signal generation.
604 * @param htim TIM handle
605 * @param Channel TIM Channel to be disabled
606 * This parameter can be one of the following values:
607 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
608 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
609 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
610 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
611 * @retval HAL status
612 */
613 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
614 {
615 /* Check the parameters */
616 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
617
618 /* Disable the Output compare channel */
619 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
620
621 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
622 {
623 /* Disable the Main Ouput */
624 __HAL_TIM_MOE_DISABLE(htim);
625 }
626
627 /* Disable the Peripheral */
628 __HAL_TIM_DISABLE(htim);
629
630 /* Return function status */
631 return HAL_OK;
632 }
633
634 /**
635 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
636 * @param htim TIM OC handle
637 * @param Channel TIM Channel to be enabled
638 * This parameter can be one of the following values:
639 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
640 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
641 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
642 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
643 * @retval HAL status
644 */
645 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
646 {
647 /* Check the parameters */
648 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
649
650 switch (Channel)
651 {
652 case TIM_CHANNEL_1:
653 {
654 /* Enable the TIM Capture/Compare 1 interrupt */
655 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
656 }
657 break;
658
659 case TIM_CHANNEL_2:
660 {
661 /* Enable the TIM Capture/Compare 2 interrupt */
662 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
663 }
664 break;
665
666 case TIM_CHANNEL_3:
667 {
668 /* Enable the TIM Capture/Compare 3 interrupt */
669 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
670 }
671 break;
672
673 case TIM_CHANNEL_4:
674 {
675 /* Enable the TIM Capture/Compare 4 interrupt */
676 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
677 }
678 break;
679
680 default:
681 break;
682 }
683
684 /* Enable the Output compare channel */
685 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
686
687 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
688 {
689 /* Enable the main output */
690 __HAL_TIM_MOE_ENABLE(htim);
691 }
692
693 /* Enable the Peripheral */
694 __HAL_TIM_ENABLE(htim);
695
696 /* Return function status */
697 return HAL_OK;
698 }
699
700 /**
701 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
702 * @param htim TIM Output Compare handle
703 * @param Channel TIM Channel to be disabled
704 * This parameter can be one of the following values:
705 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
706 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
707 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
708 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
709 * @retval HAL status
710 */
711 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
712 {
713 /* Check the parameters */
714 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
715
716 switch (Channel)
717 {
718 case TIM_CHANNEL_1:
719 {
720 /* Disable the TIM Capture/Compare 1 interrupt */
721 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
722 }
723 break;
724
725 case TIM_CHANNEL_2:
726 {
727 /* Disable the TIM Capture/Compare 2 interrupt */
728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
729 }
730 break;
731
732 case TIM_CHANNEL_3:
733 {
734 /* Disable the TIM Capture/Compare 3 interrupt */
735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
736 }
737 break;
738
739 case TIM_CHANNEL_4:
740 {
741 /* Disable the TIM Capture/Compare 4 interrupt */
742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
743 }
744 break;
745
746 default:
747 break;
748 }
749
750 /* Disable the Output compare channel */
751 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
752
753 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
754 {
755 /* Disable the Main Ouput */
756 __HAL_TIM_MOE_DISABLE(htim);
757 }
758
759 /* Disable the Peripheral */
760 __HAL_TIM_DISABLE(htim);
761
762 /* Return function status */
763 return HAL_OK;
764 }
765
766 /**
767 * @brief Starts the TIM Output Compare signal generation in DMA mode.
768 * @param htim TIM Output Compare handle
769 * @param Channel TIM Channel to be enabled
770 * This parameter can be one of the following values:
771 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
772 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
773 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
774 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
775 * @param pData The source Buffer address.
776 * @param Length The length of data to be transferred from memory to TIM peripheral
777 * @retval HAL status
778 */
779 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
780 {
781 /* Check the parameters */
782 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
783
784 if((htim->State == HAL_TIM_STATE_BUSY))
785 {
786 return HAL_BUSY;
787 }
788 else if((htim->State == HAL_TIM_STATE_READY))
789 {
790 if(((uint32_t)pData == 0U ) && (Length > 0U))
791 {
792 return HAL_ERROR;
793 }
794 else
795 {
796 htim->State = HAL_TIM_STATE_BUSY;
797 }
798 }
799 switch (Channel)
800 {
801 case TIM_CHANNEL_1:
802 {
803 /* Set the DMA Period elapsed callback */
804 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
805
806 /* Set the DMA error callback */
807 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
808
809 /* Enable the DMA channel */
810 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
811
812 /* Enable the TIM Capture/Compare 1 DMA request */
813 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
814 }
815 break;
816
817 case TIM_CHANNEL_2:
818 {
819 /* Set the DMA Period elapsed callback */
820 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
821
822 /* Set the DMA error callback */
823 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
824
825 /* Enable the DMA channel */
826 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
827
828 /* Enable the TIM Capture/Compare 2 DMA request */
829 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
830 }
831 break;
832
833 case TIM_CHANNEL_3:
834 {
835 /* Set the DMA Period elapsed callback */
836 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
837
838 /* Set the DMA error callback */
839 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
840
841 /* Enable the DMA channel */
842 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
843
844 /* Enable the TIM Capture/Compare 3 DMA request */
845 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
846 }
847 break;
848
849 case TIM_CHANNEL_4:
850 {
851 /* Set the DMA Period elapsed callback */
852 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
853
854 /* Set the DMA error callback */
855 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
856
857 /* Enable the DMA channel */
858 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
859
860 /* Enable the TIM Capture/Compare 4 DMA request */
861 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
862 }
863 break;
864
865 default:
866 break;
867 }
868
869 /* Enable the Output compare channel */
870 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
871
872 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
873 {
874 /* Enable the main output */
875 __HAL_TIM_MOE_ENABLE(htim);
876 }
877
878 /* Enable the Peripheral */
879 __HAL_TIM_ENABLE(htim);
880
881 /* Return function status */
882 return HAL_OK;
883 }
884
885 /**
886 * @brief Stops the TIM Output Compare signal generation in DMA mode.
887 * @param htim TIM Output Compare handle
888 * @param Channel TIM Channel to be disabled
889 * This parameter can be one of the following values:
890 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
891 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
892 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
893 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
894 * @retval HAL status
895 */
896 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
897 {
898 /* Check the parameters */
899 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
900
901 switch (Channel)
902 {
903 case TIM_CHANNEL_1:
904 {
905 /* Disable the TIM Capture/Compare 1 DMA request */
906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
907 }
908 break;
909
910 case TIM_CHANNEL_2:
911 {
912 /* Disable the TIM Capture/Compare 2 DMA request */
913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
914 }
915 break;
916
917 case TIM_CHANNEL_3:
918 {
919 /* Disable the TIM Capture/Compare 3 DMA request */
920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
921 }
922 break;
923
924 case TIM_CHANNEL_4:
925 {
926 /* Disable the TIM Capture/Compare 4 interrupt */
927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
928 }
929 break;
930
931 default:
932 break;
933 }
934
935 /* Disable the Output compare channel */
936 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
937
938 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
939 {
940 /* Disable the Main Ouput */
941 __HAL_TIM_MOE_DISABLE(htim);
942 }
943
944 /* Disable the Peripheral */
945 __HAL_TIM_DISABLE(htim);
946
947 /* Change the htim state */
948 htim->State = HAL_TIM_STATE_READY;
949
950 /* Return function status */
951 return HAL_OK;
952 }
953
954 /**
955 * @}
956 */
957
958 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
959 * @brief Time PWM functions
960 *
961 @verbatim
962 ==============================================================================
963 ##### Time PWM functions #####
964 ==============================================================================
965 [..]
966 This section provides functions allowing to:
967 (+) Initialize and configure the TIM OPWM.
968 (+) De-initialize the TIM PWM.
969 (+) Start the Time PWM.
970 (+) Stop the Time PWM.
971 (+) Start the Time PWM and enable interrupt.
972 (+) Stop the Time PWM and disable interrupt.
973 (+) Start the Time PWM and enable DMA transfer.
974 (+) Stop the Time PWM and disable DMA transfer.
975
976 @endverbatim
977 * @{
978 */
979 /**
980 * @brief Initializes the TIM PWM Time Base according to the specified
981 * parameters in the TIM_HandleTypeDef and create the associated handle.
982 * @param htim TIM handle
983 * @retval HAL status
984 */
985 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
986 {
987 /* Check the TIM handle allocation */
988 if(htim == NULL)
989 {
990 return HAL_ERROR;
991 }
992
993 /* Check the parameters */
994 assert_param(IS_TIM_INSTANCE(htim->Instance));
995 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
996 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
997 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
998
999 if(htim->State == HAL_TIM_STATE_RESET)
1000 {
1001 /* Allocate lock resource and initialize it */
1002 htim->Lock = HAL_UNLOCKED;
1003
1004 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1005 HAL_TIM_PWM_MspInit(htim);
1006 }
1007
1008 /* Set the TIM state */
1009 htim->State= HAL_TIM_STATE_BUSY;
1010
1011 /* Init the base time for the PWM */
1012 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1013
1014 /* Initialize the TIM state*/
1015 htim->State= HAL_TIM_STATE_READY;
1016
1017 return HAL_OK;
1018 }
1019
1020 /**
1021 * @brief DeInitializes the TIM peripheral
1022 * @param htim TIM handle
1023 * @retval HAL status
1024 */
1025 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1026 {
1027 /* Check the parameters */
1028 assert_param(IS_TIM_INSTANCE(htim->Instance));
1029
1030 htim->State = HAL_TIM_STATE_BUSY;
1031
1032 /* Disable the TIM Peripheral Clock */
1033 __HAL_TIM_DISABLE(htim);
1034
1035 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1036 HAL_TIM_PWM_MspDeInit(htim);
1037
1038 /* Change TIM state */
1039 htim->State = HAL_TIM_STATE_RESET;
1040
1041 /* Release Lock */
1042 __HAL_UNLOCK(htim);
1043
1044 return HAL_OK;
1045 }
1046
1047 /**
1048 * @brief Initializes the TIM PWM MSP.
1049 * @param htim TIM handle
1050 * @retval None
1051 */
1052 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1053 {
1054 /* Prevent unused argument(s) compilation warning */
1055 UNUSED(htim);
1056
1057 /* NOTE : This function Should not be modified, when the callback is needed,
1058 the HAL_TIM_PWM_MspInit could be implemented in the user file
1059 */
1060 }
1061
1062 /**
1063 * @brief DeInitializes TIM PWM MSP.
1064 * @param htim TIM handle
1065 * @retval None
1066 */
1067 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1068 {
1069 /* Prevent unused argument(s) compilation warning */
1070 UNUSED(htim);
1071
1072 /* NOTE : This function Should not be modified, when the callback is needed,
1073 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1074 */
1075 }
1076
1077 /**
1078 * @brief Starts the PWM signal generation.
1079 * @param htim TIM handle
1080 * @param Channel TIM Channels to be enabled
1081 * This parameter can be one of the following values:
1082 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1083 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1084 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1085 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1086 * @retval HAL status
1087 */
1088 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1089 {
1090 /* Check the parameters */
1091 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1092
1093 /* Enable the Capture compare channel */
1094 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1095
1096 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1097 {
1098 /* Enable the main output */
1099 __HAL_TIM_MOE_ENABLE(htim);
1100 }
1101
1102 /* Enable the Peripheral */
1103 __HAL_TIM_ENABLE(htim);
1104
1105 /* Return function status */
1106 return HAL_OK;
1107 }
1108
1109 /**
1110 * @brief Stops the PWM signal generation.
1111 * @param htim TIM handle
1112 * @param Channel TIM Channels to be disabled
1113 * This parameter can be one of the following values:
1114 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1115 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1116 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1117 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1118 * @retval HAL status
1119 */
1120 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1121 {
1122 /* Check the parameters */
1123 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1124
1125 /* Disable the Capture compare channel */
1126 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1127
1128 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1129 {
1130 /* Disable the Main Ouput */
1131 __HAL_TIM_MOE_DISABLE(htim);
1132 }
1133
1134 /* Disable the Peripheral */
1135 __HAL_TIM_DISABLE(htim);
1136
1137 /* Change the htim state */
1138 htim->State = HAL_TIM_STATE_READY;
1139
1140 /* Return function status */
1141 return HAL_OK;
1142 }
1143
1144 /**
1145 * @brief Starts the PWM signal generation in interrupt mode.
1146 * @param htim TIM handle
1147 * @param Channel TIM Channels to be enabled
1148 * This parameter can be one of the following values:
1149 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1150 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1151 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1152 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1153 * @retval HAL status
1154 */
1155 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1156 {
1157 /* Check the parameters */
1158 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1159
1160 switch (Channel)
1161 {
1162 case TIM_CHANNEL_1:
1163 {
1164 /* Enable the TIM Capture/Compare 1 interrupt */
1165 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1166 }
1167 break;
1168
1169 case TIM_CHANNEL_2:
1170 {
1171 /* Enable the TIM Capture/Compare 2 interrupt */
1172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1173 }
1174 break;
1175
1176 case TIM_CHANNEL_3:
1177 {
1178 /* Enable the TIM Capture/Compare 3 interrupt */
1179 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1180 }
1181 break;
1182
1183 case TIM_CHANNEL_4:
1184 {
1185 /* Enable the TIM Capture/Compare 4 interrupt */
1186 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1187 }
1188 break;
1189
1190 default:
1191 break;
1192 }
1193
1194 /* Enable the Capture compare channel */
1195 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1196
1197 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1198 {
1199 /* Enable the main output */
1200 __HAL_TIM_MOE_ENABLE(htim);
1201 }
1202
1203 /* Enable the Peripheral */
1204 __HAL_TIM_ENABLE(htim);
1205
1206 /* Return function status */
1207 return HAL_OK;
1208 }
1209
1210 /**
1211 * @brief Stops the PWM signal generation in interrupt mode.
1212 * @param htim TIM handle
1213 * @param Channel TIM Channels to be disabled
1214 * This parameter can be one of the following values:
1215 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1216 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1217 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1218 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1219 * @retval HAL status
1220 */
1221 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1222 {
1223 /* Check the parameters */
1224 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1225
1226 switch (Channel)
1227 {
1228 case TIM_CHANNEL_1:
1229 {
1230 /* Disable the TIM Capture/Compare 1 interrupt */
1231 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1232 }
1233 break;
1234
1235 case TIM_CHANNEL_2:
1236 {
1237 /* Disable the TIM Capture/Compare 2 interrupt */
1238 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1239 }
1240 break;
1241
1242 case TIM_CHANNEL_3:
1243 {
1244 /* Disable the TIM Capture/Compare 3 interrupt */
1245 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1246 }
1247 break;
1248
1249 case TIM_CHANNEL_4:
1250 {
1251 /* Disable the TIM Capture/Compare 4 interrupt */
1252 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1253 }
1254 break;
1255
1256 default:
1257 break;
1258 }
1259
1260 /* Disable the Capture compare channel */
1261 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1262
1263 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1264 {
1265 /* Disable the Main Ouput */
1266 __HAL_TIM_MOE_DISABLE(htim);
1267 }
1268
1269 /* Disable the Peripheral */
1270 __HAL_TIM_DISABLE(htim);
1271
1272 /* Return function status */
1273 return HAL_OK;
1274 }
1275
1276 /**
1277 * @brief Starts the TIM PWM signal generation in DMA mode.
1278 * @param htim TIM handle
1279 * @param Channel TIM Channels to be enabled
1280 * This parameter can be one of the following values:
1281 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1282 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1283 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1284 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1285 * @param pData The source Buffer address.
1286 * @param Length The length of data to be transferred from memory to TIM peripheral
1287 * @retval HAL status
1288 */
1289 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1290 {
1291 /* Check the parameters */
1292 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1293
1294 if((htim->State == HAL_TIM_STATE_BUSY))
1295 {
1296 return HAL_BUSY;
1297 }
1298 else if((htim->State == HAL_TIM_STATE_READY))
1299 {
1300 if(((uint32_t)pData == 0U ) && (Length > 0U))
1301 {
1302 return HAL_ERROR;
1303 }
1304 else
1305 {
1306 htim->State = HAL_TIM_STATE_BUSY;
1307 }
1308 }
1309 switch (Channel)
1310 {
1311 case TIM_CHANNEL_1:
1312 {
1313 /* Set the DMA Period elapsed callback */
1314 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1315
1316 /* Set the DMA error callback */
1317 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1318
1319 /* Enable the DMA channel */
1320 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
1321
1322 /* Enable the TIM Capture/Compare 1 DMA request */
1323 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1324 }
1325 break;
1326
1327 case TIM_CHANNEL_2:
1328 {
1329 /* Set the DMA Period elapsed callback */
1330 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1331
1332 /* Set the DMA error callback */
1333 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1334
1335 /* Enable the DMA channel */
1336 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
1337
1338 /* Enable the TIM Capture/Compare 2 DMA request */
1339 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1340 }
1341 break;
1342
1343 case TIM_CHANNEL_3:
1344 {
1345 /* Set the DMA Period elapsed callback */
1346 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1347
1348 /* Set the DMA error callback */
1349 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1350
1351 /* Enable the DMA channel */
1352 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
1353
1354 /* Enable the TIM Output Capture/Compare 3 request */
1355 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1356 }
1357 break;
1358
1359 case TIM_CHANNEL_4:
1360 {
1361 /* Set the DMA Period elapsed callback */
1362 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1363
1364 /* Set the DMA error callback */
1365 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1366
1367 /* Enable the DMA channel */
1368 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
1369
1370 /* Enable the TIM Capture/Compare 4 DMA request */
1371 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1372 }
1373 break;
1374
1375 default:
1376 break;
1377 }
1378
1379 /* Enable the Capture compare channel */
1380 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1381
1382 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1383 {
1384 /* Enable the main output */
1385 __HAL_TIM_MOE_ENABLE(htim);
1386 }
1387
1388 /* Enable the Peripheral */
1389 __HAL_TIM_ENABLE(htim);
1390
1391 /* Return function status */
1392 return HAL_OK;
1393 }
1394
1395 /**
1396 * @brief Stops the TIM PWM signal generation in DMA mode.
1397 * @param htim TIM handle
1398 * @param Channel TIM Channels to be disabled
1399 * This parameter can be one of the following values:
1400 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1401 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1402 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1403 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1404 * @retval HAL status
1405 */
1406 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1407 {
1408 /* Check the parameters */
1409 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1410
1411 switch (Channel)
1412 {
1413 case TIM_CHANNEL_1:
1414 {
1415 /* Disable the TIM Capture/Compare 1 DMA request */
1416 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1417 }
1418 break;
1419
1420 case TIM_CHANNEL_2:
1421 {
1422 /* Disable the TIM Capture/Compare 2 DMA request */
1423 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1424 }
1425 break;
1426
1427 case TIM_CHANNEL_3:
1428 {
1429 /* Disable the TIM Capture/Compare 3 DMA request */
1430 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1431 }
1432 break;
1433
1434 case TIM_CHANNEL_4:
1435 {
1436 /* Disable the TIM Capture/Compare 4 interrupt */
1437 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1438 }
1439 break;
1440
1441 default:
1442 break;
1443 }
1444
1445 /* Disable the Capture compare channel */
1446 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1447
1448 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1449 {
1450 /* Disable the Main Ouput */
1451 __HAL_TIM_MOE_DISABLE(htim);
1452 }
1453
1454 /* Disable the Peripheral */
1455 __HAL_TIM_DISABLE(htim);
1456
1457 /* Change the htim state */
1458 htim->State = HAL_TIM_STATE_READY;
1459
1460 /* Return function status */
1461 return HAL_OK;
1462 }
1463
1464 /**
1465 * @}
1466 */
1467
1468 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
1469 * @brief Time Input Capture functions
1470 *
1471 @verbatim
1472 ==============================================================================
1473 ##### Time Input Capture functions #####
1474 ==============================================================================
1475 [..]
1476 This section provides functions allowing to:
1477 (+) Initialize and configure the TIM Input Capture.
1478 (+) De-initialize the TIM Input Capture.
1479 (+) Start the Time Input Capture.
1480 (+) Stop the Time Input Capture.
1481 (+) Start the Time Input Capture and enable interrupt.
1482 (+) Stop the Time Input Capture and disable interrupt.
1483 (+) Start the Time Input Capture and enable DMA transfer.
1484 (+) Stop the Time Input Capture and disable DMA transfer.
1485
1486 @endverbatim
1487 * @{
1488 */
1489 /**
1490 * @brief Initializes the TIM Input Capture Time base according to the specified
1491 * parameters in the TIM_HandleTypeDef and create the associated handle.
1492 * @param htim TIM Input Capture handle
1493 * @retval HAL status
1494 */
1495 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1496 {
1497 /* Check the TIM handle allocation */
1498 if(htim == NULL)
1499 {
1500 return HAL_ERROR;
1501 }
1502
1503 /* Check the parameters */
1504 assert_param(IS_TIM_INSTANCE(htim->Instance));
1505 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1506 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1507 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1508
1509 if(htim->State == HAL_TIM_STATE_RESET)
1510 {
1511 /* Allocate lock resource and initialize it */
1512 htim->Lock = HAL_UNLOCKED;
1513
1514 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1515 HAL_TIM_IC_MspInit(htim);
1516 }
1517
1518 /* Set the TIM state */
1519 htim->State= HAL_TIM_STATE_BUSY;
1520
1521 /* Init the base time for the input capture */
1522 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1523
1524 /* Initialize the TIM state*/
1525 htim->State= HAL_TIM_STATE_READY;
1526
1527 return HAL_OK;
1528 }
1529
1530 /**
1531 * @brief DeInitializes the TIM peripheral
1532 * @param htim TIM Input Capture handle
1533 * @retval HAL status
1534 */
1535 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1536 {
1537 /* Check the parameters */
1538 assert_param(IS_TIM_INSTANCE(htim->Instance));
1539
1540 htim->State = HAL_TIM_STATE_BUSY;
1541
1542 /* Disable the TIM Peripheral Clock */
1543 __HAL_TIM_DISABLE(htim);
1544
1545 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1546 HAL_TIM_IC_MspDeInit(htim);
1547
1548 /* Change TIM state */
1549 htim->State = HAL_TIM_STATE_RESET;
1550
1551 /* Release Lock */
1552 __HAL_UNLOCK(htim);
1553
1554 return HAL_OK;
1555 }
1556
1557 /**
1558 * @brief Initializes the TIM Input Capture MSP.
1559 * @param htim TIM handle
1560 * @retval None
1561 */
1562 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1563 {
1564 /* Prevent unused argument(s) compilation warning */
1565 UNUSED(htim);
1566
1567 /* NOTE : This function Should not be modified, when the callback is needed,
1568 the HAL_TIM_IC_MspInit could be implemented in the user file
1569 */
1570 }
1571
1572 /**
1573 * @brief DeInitializes TIM Input Capture MSP.
1574 * @param htim TIM handle
1575 * @retval None
1576 */
1577 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1578 {
1579 /* Prevent unused argument(s) compilation warning */
1580 UNUSED(htim);
1581
1582 /* NOTE : This function Should not be modified, when the callback is needed,
1583 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1584 */
1585 }
1586
1587 /**
1588 * @brief Starts the TIM Input Capture measurement.
1589 * @param htim TIM Input Capture handle
1590 * @param Channel TIM Channels to be enabled
1591 * This parameter can be one of the following values:
1592 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1593 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1594 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1595 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1596 * @retval HAL status
1597 */
1598 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
1599 {
1600 /* Check the parameters */
1601 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1602
1603 /* Enable the Input Capture channel */
1604 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1605
1606 /* Enable the Peripheral */
1607 __HAL_TIM_ENABLE(htim);
1608
1609 /* Return function status */
1610 return HAL_OK;
1611 }
1612
1613 /**
1614 * @brief Stops the TIM Input Capture measurement.
1615 * @param htim TIM handle
1616 * @param Channel TIM Channels to be disabled
1617 * This parameter can be one of the following values:
1618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1622 * @retval HAL status
1623 */
1624 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1625 {
1626 /* Check the parameters */
1627 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1628
1629 /* Disable the Input Capture channel */
1630 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1631
1632 /* Disable the Peripheral */
1633 __HAL_TIM_DISABLE(htim);
1634
1635 /* Return function status */
1636 return HAL_OK;
1637 }
1638
1639 /**
1640 * @brief Starts the TIM Input Capture measurement in interrupt mode.
1641 * @param htim TIM Input Capture handle
1642 * @param Channel TIM Channels to be enabled
1643 * This parameter can be one of the following values:
1644 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1645 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1646 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1647 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1648 * @retval HAL status
1649 */
1650 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
1651 {
1652 /* Check the parameters */
1653 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1654
1655 switch (Channel)
1656 {
1657 case TIM_CHANNEL_1:
1658 {
1659 /* Enable the TIM Capture/Compare 1 interrupt */
1660 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1661 }
1662 break;
1663
1664 case TIM_CHANNEL_2:
1665 {
1666 /* Enable the TIM Capture/Compare 2 interrupt */
1667 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1668 }
1669 break;
1670
1671 case TIM_CHANNEL_3:
1672 {
1673 /* Enable the TIM Capture/Compare 3 interrupt */
1674 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1675 }
1676 break;
1677
1678 case TIM_CHANNEL_4:
1679 {
1680 /* Enable the TIM Capture/Compare 4 interrupt */
1681 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1682 }
1683 break;
1684
1685 default:
1686 break;
1687 }
1688 /* Enable the Input Capture channel */
1689 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1690
1691 /* Enable the Peripheral */
1692 __HAL_TIM_ENABLE(htim);
1693
1694 /* Return function status */
1695 return HAL_OK;
1696 }
1697
1698 /**
1699 * @brief Stops the TIM Input Capture measurement in interrupt mode.
1700 * @param htim TIM handle
1701 * @param Channel TIM Channels to be disabled
1702 * This parameter can be one of the following values:
1703 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1704 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1705 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1706 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1707 * @retval HAL status
1708 */
1709 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1710 {
1711 /* Check the parameters */
1712 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1713
1714 switch (Channel)
1715 {
1716 case TIM_CHANNEL_1:
1717 {
1718 /* Disable the TIM Capture/Compare 1 interrupt */
1719 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1720 }
1721 break;
1722
1723 case TIM_CHANNEL_2:
1724 {
1725 /* Disable the TIM Capture/Compare 2 interrupt */
1726 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1727 }
1728 break;
1729
1730 case TIM_CHANNEL_3:
1731 {
1732 /* Disable the TIM Capture/Compare 3 interrupt */
1733 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1734 }
1735 break;
1736
1737 case TIM_CHANNEL_4:
1738 {
1739 /* Disable the TIM Capture/Compare 4 interrupt */
1740 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1741 }
1742 break;
1743
1744 default:
1745 break;
1746 }
1747
1748 /* Disable the Input Capture channel */
1749 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1750
1751 /* Disable the Peripheral */
1752 __HAL_TIM_DISABLE(htim);
1753
1754 /* Return function status */
1755 return HAL_OK;
1756 }
1757
1758 /**
1759 * @brief Starts the TIM Input Capture measurement in DMA mode.
1760 * @param htim TIM Input Capture handle
1761 * @param Channel TIM Channels to be enabled
1762 * This parameter can be one of the following values:
1763 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1764 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1765 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1766 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1767 * @param pData The destination Buffer address.
1768 * @param Length The length of data to be transferred from TIM peripheral to memory.
1769 * @retval HAL status
1770 */
1771 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1772 {
1773 /* Check the parameters */
1774 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1775 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1776
1777 if((htim->State == HAL_TIM_STATE_BUSY))
1778 {
1779 return HAL_BUSY;
1780 }
1781 else if((htim->State == HAL_TIM_STATE_READY))
1782 {
1783 if((pData == 0U ) && (Length > 0U))
1784 {
1785 return HAL_ERROR;
1786 }
1787 else
1788 {
1789 htim->State = HAL_TIM_STATE_BUSY;
1790 }
1791 }
1792
1793 switch (Channel)
1794 {
1795 case TIM_CHANNEL_1:
1796 {
1797 /* Set the DMA Period elapsed callback */
1798 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
1799
1800 /* Set the DMA error callback */
1801 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1802
1803 /* Enable the DMA channel */
1804 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
1805
1806 /* Enable the TIM Capture/Compare 1 DMA request */
1807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1808 }
1809 break;
1810
1811 case TIM_CHANNEL_2:
1812 {
1813 /* Set the DMA Period elapsed callback */
1814 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
1815
1816 /* Set the DMA error callback */
1817 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1818
1819 /* Enable the DMA channel */
1820 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
1821
1822 /* Enable the TIM Capture/Compare 2 DMA request */
1823 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1824 }
1825 break;
1826
1827 case TIM_CHANNEL_3:
1828 {
1829 /* Set the DMA Period elapsed callback */
1830 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
1831
1832 /* Set the DMA error callback */
1833 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1834
1835 /* Enable the DMA channel */
1836 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
1837
1838 /* Enable the TIM Capture/Compare 3 DMA request */
1839 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1840 }
1841 break;
1842
1843 case TIM_CHANNEL_4:
1844 {
1845 /* Set the DMA Period elapsed callback */
1846 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
1847
1848 /* Set the DMA error callback */
1849 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1850
1851 /* Enable the DMA channel */
1852 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
1853
1854 /* Enable the TIM Capture/Compare 4 DMA request */
1855 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1856 }
1857 break;
1858
1859 default:
1860 break;
1861 }
1862
1863 /* Enable the Input Capture channel */
1864 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1865
1866 /* Enable the Peripheral */
1867 __HAL_TIM_ENABLE(htim);
1868
1869 /* Return function status */
1870 return HAL_OK;
1871 }
1872
1873 /**
1874 * @brief Stops the TIM Input Capture measurement in DMA mode.
1875 * @param htim TIM Input Capture handle
1876 * @param Channel TIM Channels to be disabled
1877 * This parameter can be one of the following values:
1878 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1879 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1880 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1881 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1882 * @retval HAL status
1883 */
1884 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1885 {
1886 /* Check the parameters */
1887 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1888 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
1889
1890 switch (Channel)
1891 {
1892 case TIM_CHANNEL_1:
1893 {
1894 /* Disable the TIM Capture/Compare 1 DMA request */
1895 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1896 }
1897 break;
1898
1899 case TIM_CHANNEL_2:
1900 {
1901 /* Disable the TIM Capture/Compare 2 DMA request */
1902 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1903 }
1904 break;
1905
1906 case TIM_CHANNEL_3:
1907 {
1908 /* Disable the TIM Capture/Compare 3 DMA request */
1909 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1910 }
1911 break;
1912
1913 case TIM_CHANNEL_4:
1914 {
1915 /* Disable the TIM Capture/Compare 4 DMA request */
1916 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1917 }
1918 break;
1919
1920 default:
1921 break;
1922 }
1923
1924 /* Disable the Input Capture channel */
1925 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1926
1927 /* Disable the Peripheral */
1928 __HAL_TIM_DISABLE(htim);
1929
1930 /* Change the htim state */
1931 htim->State = HAL_TIM_STATE_READY;
1932
1933 /* Return function status */
1934 return HAL_OK;
1935 }
1936 /**
1937 * @}
1938 */
1939
1940 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
1941 * @brief Time One Pulse functions
1942 *
1943 @verbatim
1944 ==============================================================================
1945 ##### Time One Pulse functions #####
1946 ==============================================================================
1947 [..]
1948 This section provides functions allowing to:
1949 (+) Initialize and configure the TIM One Pulse.
1950 (+) De-initialize the TIM One Pulse.
1951 (+) Start the Time One Pulse.
1952 (+) Stop the Time One Pulse.
1953 (+) Start the Time One Pulse and enable interrupt.
1954 (+) Stop the Time One Pulse and disable interrupt.
1955 (+) Start the Time One Pulse and enable DMA transfer.
1956 (+) Stop the Time One Pulse and disable DMA transfer.
1957
1958 @endverbatim
1959 * @{
1960 */
1961 /**
1962 * @brief Initializes the TIM One Pulse Time Base according to the specified
1963 * parameters in the TIM_HandleTypeDef and create the associated handle.
1964 * @param htim TIM OnePulse handle
1965 * @param OnePulseMode Select the One pulse mode.
1966 * This parameter can be one of the following values:
1967 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
1968 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
1969 * @retval HAL status
1970 */
1971 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
1972 {
1973 /* Check the TIM handle allocation */
1974 if(htim == NULL)
1975 {
1976 return HAL_ERROR;
1977 }
1978
1979 /* Check the parameters */
1980 assert_param(IS_TIM_INSTANCE(htim->Instance));
1981 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1982 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1983 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
1984 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1985
1986 if(htim->State == HAL_TIM_STATE_RESET)
1987 {
1988 /* Allocate lock resource and initialize it */
1989 htim->Lock = HAL_UNLOCKED;
1990
1991 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1992 HAL_TIM_OnePulse_MspInit(htim);
1993 }
1994
1995 /* Set the TIM state */
1996 htim->State= HAL_TIM_STATE_BUSY;
1997
1998 /* Configure the Time base in the One Pulse Mode */
1999 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2000
2001 /* Reset the OPM Bit */
2002 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2003
2004 /* Configure the OPM Mode */
2005 htim->Instance->CR1 |= OnePulseMode;
2006
2007 /* Initialize the TIM state*/
2008 htim->State= HAL_TIM_STATE_READY;
2009
2010 return HAL_OK;
2011 }
2012
2013 /**
2014 * @brief DeInitializes the TIM One Pulse
2015 * @param htim TIM One Pulse handle
2016 * @retval HAL status
2017 */
2018 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2019 {
2020 /* Check the parameters */
2021 assert_param(IS_TIM_INSTANCE(htim->Instance));
2022
2023 htim->State = HAL_TIM_STATE_BUSY;
2024
2025 /* Disable the TIM Peripheral Clock */
2026 __HAL_TIM_DISABLE(htim);
2027
2028 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2029 HAL_TIM_OnePulse_MspDeInit(htim);
2030
2031 /* Change TIM state */
2032 htim->State = HAL_TIM_STATE_RESET;
2033
2034 /* Release Lock */
2035 __HAL_UNLOCK(htim);
2036
2037 return HAL_OK;
2038 }
2039
2040 /**
2041 * @brief Initializes the TIM One Pulse MSP.
2042 * @param htim TIM handle
2043 * @retval None
2044 */
2045 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2046 {
2047 /* Prevent unused argument(s) compilation warning */
2048 UNUSED(htim);
2049
2050 /* NOTE : This function Should not be modified, when the callback is needed,
2051 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2052 */
2053 }
2054
2055 /**
2056 * @brief DeInitializes TIM One Pulse MSP.
2057 * @param htim TIM handle
2058 * @retval None
2059 */
2060 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2061 {
2062 /* Prevent unused argument(s) compilation warning */
2063 UNUSED(htim);
2064
2065 /* NOTE : This function Should not be modified, when the callback is needed,
2066 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2067 */
2068 }
2069
2070 /**
2071 * @brief Starts the TIM One Pulse signal generation.
2072 * @param htim TIM One Pulse handle
2073 * @param OutputChannel TIM Channels to be enabled
2074 * This parameter can be one of the following values:
2075 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2076 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2077 * @retval HAL status
2078 */
2079 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2080 {
2081 /* Enable the Capture compare and the Input Capture channels
2082 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2083 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2084 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2085 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2086
2087 No need to enable the counter, it's enabled automatically by hardware
2088 (the counter starts in response to a stimulus and generate a pulse */
2089
2090 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2091 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2092
2093 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2094 {
2095 /* Enable the main output */
2096 __HAL_TIM_MOE_ENABLE(htim);
2097 }
2098
2099 /* Return function status */
2100 return HAL_OK;
2101 }
2102
2103 /**
2104 * @brief Stops the TIM One Pulse signal generation.
2105 * @param htim TIM One Pulse handle
2106 * @param OutputChannel TIM Channels to be disable
2107 * This parameter can be one of the following values:
2108 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2109 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2110 * @retval HAL status
2111 */
2112 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2113 {
2114 /* Disable the Capture compare and the Input Capture channels
2115 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2116 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2117 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2118 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2119
2120 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2121 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2122
2123 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2124 {
2125 /* Disable the Main Ouput */
2126 __HAL_TIM_MOE_DISABLE(htim);
2127 }
2128
2129 /* Disable the Peripheral */
2130 __HAL_TIM_DISABLE(htim);
2131
2132 /* Return function status */
2133 return HAL_OK;
2134 }
2135
2136 /**
2137 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2138 * @param htim TIM One Pulse handle
2139 * @param OutputChannel TIM Channels to be enabled
2140 * This parameter can be one of the following values:
2141 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2142 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2143 * @retval HAL status
2144 */
2145 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2146 {
2147 /* Enable the Capture compare and the Input Capture channels
2148 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2149 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2150 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2151 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2152
2153 No need to enable the counter, it's enabled automatically by hardware
2154 (the counter starts in response to a stimulus and generate a pulse */
2155
2156 /* Enable the TIM Capture/Compare 1 interrupt */
2157 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2158
2159 /* Enable the TIM Capture/Compare 2 interrupt */
2160 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2161
2162 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2163 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2164
2165 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2166 {
2167 /* Enable the main output */
2168 __HAL_TIM_MOE_ENABLE(htim);
2169 }
2170
2171 /* Return function status */
2172 return HAL_OK;
2173 }
2174
2175 /**
2176 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2177 * @param htim TIM One Pulse handle
2178 * @param OutputChannel TIM Channels to be enabled
2179 * This parameter can be one of the following values:
2180 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2181 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2182 * @retval HAL status
2183 */
2184 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2185 {
2186 /* Disable the TIM Capture/Compare 1 interrupt */
2187 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2188
2189 /* Disable the TIM Capture/Compare 2 interrupt */
2190 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2191
2192 /* Disable the Capture compare and the Input Capture channels
2193 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2194 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2195 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2196 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2197 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2198 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2199
2200 if(IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2201 {
2202 /* Disable the Main Ouput */
2203 __HAL_TIM_MOE_DISABLE(htim);
2204 }
2205
2206 /* Disable the Peripheral */
2207 __HAL_TIM_DISABLE(htim);
2208
2209 /* Return function status */
2210 return HAL_OK;
2211 }
2212
2213 /**
2214 * @}
2215 */
2216
2217 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
2218 * @brief Time Encoder functions
2219 *
2220 @verbatim
2221 ==============================================================================
2222 ##### Time Encoder functions #####
2223 ==============================================================================
2224 [..]
2225 This section provides functions allowing to:
2226 (+) Initialize and configure the TIM Encoder.
2227 (+) De-initialize the TIM Encoder.
2228 (+) Start the Time Encoder.
2229 (+) Stop the Time Encoder.
2230 (+) Start the Time Encoder and enable interrupt.
2231 (+) Stop the Time Encoder and disable interrupt.
2232 (+) Start the Time Encoder and enable DMA transfer.
2233 (+) Stop the Time Encoder and disable DMA transfer.
2234
2235 @endverbatim
2236 * @{
2237 */
2238 /**
2239 * @brief Initializes the TIM Encoder Interface and create the associated handle.
2240 * @param htim TIM Encoder Interface handle
2241 * @param sConfig TIM Encoder Interface configuration structure
2242 * @retval HAL status
2243 */
2244 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
2245 {
2246 uint32_t tmpsmcr = 0U;
2247 uint32_t tmpccmr1 = 0U;
2248 uint32_t tmpccer = 0U;
2249
2250 /* Check the TIM handle allocation */
2251 if(htim == NULL)
2252 {
2253 return HAL_ERROR;
2254 }
2255
2256 /* Check the parameters */
2257 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2258 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2259 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2260 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2261 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2262 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2263 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2264 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
2265 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
2266 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2267 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2268 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2269 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2270
2271 if(htim->State == HAL_TIM_STATE_RESET)
2272 {
2273 /* Allocate lock resource and initialize it */
2274 htim->Lock = HAL_UNLOCKED;
2275
2276 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2277 HAL_TIM_Encoder_MspInit(htim);
2278 }
2279
2280 /* Set the TIM state */
2281 htim->State= HAL_TIM_STATE_BUSY;
2282
2283 /* Reset the SMS bits */
2284 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
2285
2286 /* Configure the Time base in the Encoder Mode */
2287 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2288
2289 /* Get the TIMx SMCR register value */
2290 tmpsmcr = htim->Instance->SMCR;
2291
2292 /* Get the TIMx CCMR1 register value */
2293 tmpccmr1 = htim->Instance->CCMR1;
2294
2295 /* Get the TIMx CCER register value */
2296 tmpccer = htim->Instance->CCER;
2297
2298 /* Set the encoder Mode */
2299 tmpsmcr |= sConfig->EncoderMode;
2300
2301 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2302 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2303 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2304
2305 /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2306 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2307 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2308 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2309 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2310
2311 /* Set the TI1 and the TI2 Polarities */
2312 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2313 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2314 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2315
2316 /* Write to TIMx SMCR */
2317 htim->Instance->SMCR = tmpsmcr;
2318
2319 /* Write to TIMx CCMR1 */
2320 htim->Instance->CCMR1 = tmpccmr1;
2321
2322 /* Write to TIMx CCER */
2323 htim->Instance->CCER = tmpccer;
2324
2325 /* Initialize the TIM state*/
2326 htim->State= HAL_TIM_STATE_READY;
2327
2328 return HAL_OK;
2329 }
2330
2331
2332 /**
2333 * @brief DeInitializes the TIM Encoder interface
2334 * @param htim TIM Encoder handle
2335 * @retval HAL status
2336 */
2337 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2338 {
2339 /* Check the parameters */
2340 assert_param(IS_TIM_INSTANCE(htim->Instance));
2341
2342 htim->State = HAL_TIM_STATE_BUSY;
2343
2344 /* Disable the TIM Peripheral Clock */
2345 __HAL_TIM_DISABLE(htim);
2346
2347 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2348 HAL_TIM_Encoder_MspDeInit(htim);
2349
2350 /* Change TIM state */
2351 htim->State = HAL_TIM_STATE_RESET;
2352
2353 /* Release Lock */
2354 __HAL_UNLOCK(htim);
2355
2356 return HAL_OK;
2357 }
2358
2359 /**
2360 * @brief Initializes the TIM Encoder Interface MSP.
2361 * @param htim TIM handle
2362 * @retval None
2363 */
2364 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
2365 {
2366 /* Prevent unused argument(s) compilation warning */
2367 UNUSED(htim);
2368
2369 /* NOTE : This function Should not be modified, when the callback is needed,
2370 the HAL_TIM_Encoder_MspInit could be implemented in the user file
2371 */
2372 }
2373
2374 /**
2375 * @brief DeInitializes TIM Encoder Interface MSP.
2376 * @param htim TIM handle
2377 * @retval None
2378 */
2379 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
2380 {
2381 /* Prevent unused argument(s) compilation warning */
2382 UNUSED(htim);
2383
2384 /* NOTE : This function Should not be modified, when the callback is needed,
2385 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
2386 */
2387 }
2388
2389 /**
2390 * @brief Starts the TIM Encoder Interface.
2391 * @param htim TIM Encoder Interface handle
2392 * @param Channel TIM Channels to be enabled
2393 * This parameter can be one of the following values:
2394 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2395 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2396 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2397 * @retval HAL status
2398 */
2399 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2400 {
2401 /* Check the parameters */
2402 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2403
2404 /* Enable the encoder interface channels */
2405 switch (Channel)
2406 {
2407 case TIM_CHANNEL_1:
2408 {
2409 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2410 break;
2411 }
2412 case TIM_CHANNEL_2:
2413 {
2414 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2415 break;
2416 }
2417 default :
2418 {
2419 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2420 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2421 break;
2422 }
2423 }
2424 /* Enable the Peripheral */
2425 __HAL_TIM_ENABLE(htim);
2426
2427 /* Return function status */
2428 return HAL_OK;
2429 }
2430
2431 /**
2432 * @brief Stops the TIM Encoder Interface.
2433 * @param htim TIM Encoder Interface handle
2434 * @param Channel TIM Channels to be disabled
2435 * This parameter can be one of the following values:
2436 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2437 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2438 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2439 * @retval HAL status
2440 */
2441 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2442 {
2443 /* Check the parameters */
2444 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2445
2446 /* Disable the Input Capture channels 1 and 2
2447 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2448 switch (Channel)
2449 {
2450 case TIM_CHANNEL_1:
2451 {
2452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2453 break;
2454 }
2455 case TIM_CHANNEL_2:
2456 {
2457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2458 break;
2459 }
2460 default :
2461 {
2462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2463 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2464 break;
2465 }
2466 }
2467
2468 /* Disable the Peripheral */
2469 __HAL_TIM_DISABLE(htim);
2470
2471 /* Return function status */
2472 return HAL_OK;
2473 }
2474
2475 /**
2476 * @brief Starts the TIM Encoder Interface in interrupt mode.
2477 * @param htim TIM Encoder Interface handle
2478 * @param Channel TIM Channels to be enabled
2479 * This parameter can be one of the following values:
2480 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2481 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2482 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2483 * @retval HAL status
2484 */
2485 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2486 {
2487 /* Check the parameters */
2488 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2489
2490 /* Enable the encoder interface channels */
2491 /* Enable the capture compare Interrupts 1 and/or 2U */
2492 switch (Channel)
2493 {
2494 case TIM_CHANNEL_1:
2495 {
2496 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2497 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2498 break;
2499 }
2500 case TIM_CHANNEL_2:
2501 {
2502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2503 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2504 break;
2505 }
2506 default :
2507 {
2508 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2509 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2510 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2511 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2512 break;
2513 }
2514 }
2515
2516 /* Enable the Peripheral */
2517 __HAL_TIM_ENABLE(htim);
2518
2519 /* Return function status */
2520 return HAL_OK;
2521 }
2522
2523 /**
2524 * @brief Stops the TIM Encoder Interface in interrupt mode.
2525 * @param htim TIM Encoder Interface handle
2526 * @param Channel TIM Channels to be disabled
2527 * This parameter can be one of the following values:
2528 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2529 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2530 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2531 * @retval HAL status
2532 */
2533 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2534 {
2535 /* Check the parameters */
2536 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2537
2538 /* Disable the Input Capture channels 1 and 2
2539 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2540 if(Channel == TIM_CHANNEL_1)
2541 {
2542 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2543
2544 /* Disable the capture compare Interrupts 1U */
2545 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2546 }
2547 else if(Channel == TIM_CHANNEL_2)
2548 {
2549 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2550
2551 /* Disable the capture compare Interrupts 2U */
2552 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2553 }
2554 else
2555 {
2556 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2557 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2558
2559 /* Disable the capture compare Interrupts 1 and 2U */
2560 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2561 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2562 }
2563
2564 /* Disable the Peripheral */
2565 __HAL_TIM_DISABLE(htim);
2566
2567 /* Change the htim state */
2568 htim->State = HAL_TIM_STATE_READY;
2569
2570 /* Return function status */
2571 return HAL_OK;
2572 }
2573
2574 /**
2575 * @brief Starts the TIM Encoder Interface in DMA mode.
2576 * @param htim TIM Encoder Interface handle
2577 * @param Channel TIM Channels to be enabled
2578 * This parameter can be one of the following values:
2579 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2580 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2581 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2582 * @param pData1: The destination Buffer address for IC1.
2583 * @param pData2: The destination Buffer address for IC2.
2584 * @param Length The length of data to be transferred from TIM peripheral to memory.
2585 * @retval HAL status
2586 */
2587 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
2588 {
2589 /* Check the parameters */
2590 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2591
2592 if((htim->State == HAL_TIM_STATE_BUSY))
2593 {
2594 return HAL_BUSY;
2595 }
2596 else if((htim->State == HAL_TIM_STATE_READY))
2597 {
2598 if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
2599 {
2600 return HAL_ERROR;
2601 }
2602 else
2603 {
2604 htim->State = HAL_TIM_STATE_BUSY;
2605 }
2606 }
2607
2608 switch (Channel)
2609 {
2610 case TIM_CHANNEL_1:
2611 {
2612 /* Set the DMA Period elapsed callback */
2613 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2614
2615 /* Set the DMA error callback */
2616 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2617
2618 /* Enable the DMA channel */
2619 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
2620
2621 /* Enable the TIM Input Capture DMA request */
2622 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2623
2624 /* Enable the Peripheral */
2625 __HAL_TIM_ENABLE(htim);
2626
2627 /* Enable the Capture compare channel */
2628 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2629 }
2630 break;
2631
2632 case TIM_CHANNEL_2:
2633 {
2634 /* Set the DMA Period elapsed callback */
2635 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2636
2637 /* Set the DMA error callback */
2638 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
2639 /* Enable the DMA channel */
2640 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2641
2642 /* Enable the TIM Input Capture DMA request */
2643 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2644
2645 /* Enable the Peripheral */
2646 __HAL_TIM_ENABLE(htim);
2647
2648 /* Enable the Capture compare channel */
2649 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2650 }
2651 break;
2652
2653 case TIM_CHANNEL_ALL:
2654 {
2655 /* Set the DMA Period elapsed callback */
2656 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2657
2658 /* Set the DMA error callback */
2659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2660
2661 /* Enable the DMA channel */
2662 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
2663
2664 /* Set the DMA Period elapsed callback */
2665 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2666
2667 /* Set the DMA error callback */
2668 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2669
2670 /* Enable the DMA channel */
2671 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
2672
2673 /* Enable the Peripheral */
2674 __HAL_TIM_ENABLE(htim);
2675
2676 /* Enable the Capture compare channel */
2677 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2678 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2679
2680 /* Enable the TIM Input Capture DMA request */
2681 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2682 /* Enable the TIM Input Capture DMA request */
2683 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2684 }
2685 break;
2686
2687 default:
2688 break;
2689 }
2690 /* Return function status */
2691 return HAL_OK;
2692 }
2693
2694 /**
2695 * @brief Stops the TIM Encoder Interface in DMA mode.
2696 * @param htim TIM Encoder Interface handle
2697 * @param Channel TIM Channels to be enabled
2698 * This parameter can be one of the following values:
2699 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2700 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2701 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
2702 * @retval HAL status
2703 */
2704 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2705 {
2706 /* Check the parameters */
2707 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2708
2709 /* Disable the Input Capture channels 1 and 2
2710 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
2711 if(Channel == TIM_CHANNEL_1)
2712 {
2713 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2714
2715 /* Disable the capture compare DMA Request 1U */
2716 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2717 }
2718 else if(Channel == TIM_CHANNEL_2)
2719 {
2720 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2721
2722 /* Disable the capture compare DMA Request 2U */
2723 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2724 }
2725 else
2726 {
2727 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2728 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2729
2730 /* Disable the capture compare DMA Request 1 and 2U */
2731 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2732 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2733 }
2734
2735 /* Disable the Peripheral */
2736 __HAL_TIM_DISABLE(htim);
2737
2738 /* Change the htim state */
2739 htim->State = HAL_TIM_STATE_READY;
2740
2741 /* Return function status */
2742 return HAL_OK;
2743 }
2744
2745 /**
2746 * @}
2747 */
2748 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2749 * @brief IRQ handler management
2750 *
2751 @verbatim
2752 ==============================================================================
2753 ##### IRQ handler management #####
2754 ==============================================================================
2755 [..]
2756 This section provides Timer IRQ handler function.
2757
2758 @endverbatim
2759 * @{
2760 */
2761 /**
2762 * @brief This function handles TIM interrupts requests.
2763 * @param htim TIM handle
2764 * @retval None
2765 */
2766 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
2767 {
2768 /* Capture compare 1 event */
2769 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
2770 {
2771 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
2772 {
2773 {
2774 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
2775 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
2776
2777 /* Input capture event */
2778 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
2779 {
2780 HAL_TIM_IC_CaptureCallback(htim);
2781 }
2782 /* Output compare event */
2783 else
2784 {
2785 HAL_TIM_OC_DelayElapsedCallback(htim);
2786 HAL_TIM_PWM_PulseFinishedCallback(htim);
2787 }
2788 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2789 }
2790 }
2791 }
2792 /* Capture compare 2 event */
2793 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
2794 {
2795 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
2796 {
2797 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
2798 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
2799 /* Input capture event */
2800 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
2801 {
2802 HAL_TIM_IC_CaptureCallback(htim);
2803 }
2804 /* Output compare event */
2805 else
2806 {
2807 HAL_TIM_OC_DelayElapsedCallback(htim);
2808 HAL_TIM_PWM_PulseFinishedCallback(htim);
2809 }
2810 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2811 }
2812 }
2813 /* Capture compare 3 event */
2814 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
2815 {
2816 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
2817 {
2818 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
2819 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
2820 /* Input capture event */
2821 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
2822 {
2823 HAL_TIM_IC_CaptureCallback(htim);
2824 }
2825 /* Output compare event */
2826 else
2827 {
2828 HAL_TIM_OC_DelayElapsedCallback(htim);
2829 HAL_TIM_PWM_PulseFinishedCallback(htim);
2830 }
2831 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2832 }
2833 }
2834 /* Capture compare 4 event */
2835 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
2836 {
2837 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
2838 {
2839 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
2840 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
2841 /* Input capture event */
2842 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
2843 {
2844 HAL_TIM_IC_CaptureCallback(htim);
2845 }
2846 /* Output compare event */
2847 else
2848 {
2849 HAL_TIM_OC_DelayElapsedCallback(htim);
2850 HAL_TIM_PWM_PulseFinishedCallback(htim);
2851 }
2852 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
2853 }
2854 }
2855 /* TIM Update event */
2856 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
2857 {
2858 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
2859 {
2860 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
2861 HAL_TIM_PeriodElapsedCallback(htim);
2862 }
2863 }
2864 /* TIM Break input event */
2865 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
2866 {
2867 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
2868 {
2869 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
2870 HAL_TIMEx_BreakCallback(htim);
2871 }
2872 }
2873
2874 #if defined(TIM_FLAG_BREAK2)
2875 /* TIM Break input 2 event */
2876 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
2877 {
2878 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
2879 {
2880 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
2881 HAL_TIMEx_Break2Callback(htim);
2882 }
2883 }
2884 #endif
2885
2886 /* TIM Trigger detection event */
2887 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
2888 {
2889 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
2890 {
2891 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
2892 HAL_TIM_TriggerCallback(htim);
2893 }
2894 }
2895 /* TIM commutation event */
2896 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
2897 {
2898 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
2899 {
2900 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
2901 HAL_TIMEx_CommutationCallback(htim);
2902 }
2903 }
2904 }
2905
2906 /**
2907 * @}
2908 */
2909
2910 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
2911 * @brief Peripheral Control functions
2912 *
2913 @verbatim
2914 ==============================================================================
2915 ##### Peripheral Control functions #####
2916 ==============================================================================
2917 [..]
2918 This section provides functions allowing to:
2919 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
2920 (+) Configure External Clock source.
2921 (+) Configure Complementary channels, break features and dead time.
2922 (+) Configure Master and the Slave synchronization.
2923 (+) Configure the DMA Burst Mode.
2924
2925 @endverbatim
2926 * @{
2927 */
2928
2929 /**
2930 * @brief Initializes the TIM Output Compare Channels according to the specified
2931 * parameters in the TIM_OC_InitTypeDef.
2932 * @param htim TIM Output Compare handle
2933 * @param sConfig TIM Output Compare configuration structure
2934 * @param Channel TIM Channels to be enabled
2935 * This parameter can be one of the following values:
2936 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2937 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2938 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2939 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2940 * @retval HAL status
2941 */
2942 __weak HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
2943 {
2944 /* Check the parameters */
2945 assert_param(IS_TIM_CHANNELS(Channel));
2946 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
2947 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
2948
2949 /* Check input state */
2950 __HAL_LOCK(htim);
2951
2952 htim->State = HAL_TIM_STATE_BUSY;
2953
2954 switch (Channel)
2955 {
2956 case TIM_CHANNEL_1:
2957 {
2958 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
2959 /* Configure the TIM Channel 1 in Output Compare */
2960 TIM_OC1_SetConfig(htim->Instance, sConfig);
2961 }
2962 break;
2963
2964 case TIM_CHANNEL_2:
2965 {
2966 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
2967 /* Configure the TIM Channel 2 in Output Compare */
2968 TIM_OC2_SetConfig(htim->Instance, sConfig);
2969 }
2970 break;
2971
2972 case TIM_CHANNEL_3:
2973 {
2974 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
2975 /* Configure the TIM Channel 3 in Output Compare */
2976 TIM_OC3_SetConfig(htim->Instance, sConfig);
2977 }
2978 break;
2979
2980 case TIM_CHANNEL_4:
2981 {
2982 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
2983 /* Configure the TIM Channel 4 in Output Compare */
2984 TIM_OC4_SetConfig(htim->Instance, sConfig);
2985 }
2986 break;
2987
2988 default:
2989 break;
2990 }
2991 htim->State = HAL_TIM_STATE_READY;
2992
2993 __HAL_UNLOCK(htim);
2994
2995 return HAL_OK;
2996 }
2997
2998 /**
2999 * @brief Initializes the TIM Input Capture Channels according to the specified
3000 * parameters in the TIM_IC_InitTypeDef.
3001 * @param htim TIM IC handle
3002 * @param sConfig TIM Input Capture configuration structure
3003 * @param Channel TIM Channels to be enabled
3004 * This parameter can be one of the following values:
3005 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3006 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3007 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3008 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3009 * @retval HAL status
3010 */
3011 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
3012 {
3013 /* Check the parameters */
3014 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3015 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
3016 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
3017 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
3018 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
3019
3020 __HAL_LOCK(htim);
3021
3022 htim->State = HAL_TIM_STATE_BUSY;
3023
3024 if (Channel == TIM_CHANNEL_1)
3025 {
3026 /* TI1 Configuration */
3027 TIM_TI1_SetConfig(htim->Instance,
3028 sConfig->ICPolarity,
3029 sConfig->ICSelection,
3030 sConfig->ICFilter);
3031
3032 /* Reset the IC1PSC Bits */
3033 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3034
3035 /* Set the IC1PSC value */
3036 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
3037 }
3038 else if (Channel == TIM_CHANNEL_2)
3039 {
3040 /* TI2 Configuration */
3041 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3042
3043 TIM_TI2_SetConfig(htim->Instance,
3044 sConfig->ICPolarity,
3045 sConfig->ICSelection,
3046 sConfig->ICFilter);
3047
3048 /* Reset the IC2PSC Bits */
3049 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3050
3051 /* Set the IC2PSC value */
3052 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
3053 }
3054 else if (Channel == TIM_CHANNEL_3)
3055 {
3056 /* TI3 Configuration */
3057 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3058
3059 TIM_TI3_SetConfig(htim->Instance,
3060 sConfig->ICPolarity,
3061 sConfig->ICSelection,
3062 sConfig->ICFilter);
3063
3064 /* Reset the IC3PSC Bits */
3065 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
3066
3067 /* Set the IC3PSC value */
3068 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
3069 }
3070 else
3071 {
3072 /* TI4 Configuration */
3073 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3074
3075 TIM_TI4_SetConfig(htim->Instance,
3076 sConfig->ICPolarity,
3077 sConfig->ICSelection,
3078 sConfig->ICFilter);
3079
3080 /* Reset the IC4PSC Bits */
3081 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
3082
3083 /* Set the IC4PSC value */
3084 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
3085 }
3086
3087 htim->State = HAL_TIM_STATE_READY;
3088
3089 __HAL_UNLOCK(htim);
3090
3091 return HAL_OK;
3092 }
3093
3094 /**
3095 * @brief Initializes the TIM PWM channels according to the specified
3096 * parameters in the TIM_OC_InitTypeDef.
3097 * @param htim TIM handle
3098 * @param sConfig TIM PWM configuration structure
3099 * @param Channel TIM Channels to be enabled
3100 * This parameter can be one of the following values:
3101 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3102 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3103 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3104 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3105 * @retval HAL status
3106 */
3107 __weak HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
3108 {
3109 __HAL_LOCK(htim);
3110
3111 /* Check the parameters */
3112 assert_param(IS_TIM_CHANNELS(Channel));
3113 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
3114 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3115 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
3116
3117 htim->State = HAL_TIM_STATE_BUSY;
3118
3119 switch (Channel)
3120 {
3121 case TIM_CHANNEL_1:
3122 {
3123 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3124 /* Configure the Channel 1 in PWM mode */
3125 TIM_OC1_SetConfig(htim->Instance, sConfig);
3126
3127 /* Set the Preload enable bit for channel1 */
3128 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
3129
3130 /* Configure the Output Fast mode */
3131 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
3132 htim->Instance->CCMR1 |= sConfig->OCFastMode;
3133 }
3134 break;
3135
3136 case TIM_CHANNEL_2:
3137 {
3138 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3139 /* Configure the Channel 2 in PWM mode */
3140 TIM_OC2_SetConfig(htim->Instance, sConfig);
3141
3142 /* Set the Preload enable bit for channel2 */
3143 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
3144
3145 /* Configure the Output Fast mode */
3146 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
3147 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
3148 }
3149 break;
3150
3151 case TIM_CHANNEL_3:
3152 {
3153 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3154 /* Configure the Channel 3 in PWM mode */
3155 TIM_OC3_SetConfig(htim->Instance, sConfig);
3156
3157 /* Set the Preload enable bit for channel3 */
3158 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
3159
3160 /* Configure the Output Fast mode */
3161 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
3162 htim->Instance->CCMR2 |= sConfig->OCFastMode;
3163 }
3164 break;
3165
3166 case TIM_CHANNEL_4:
3167 {
3168 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3169 /* Configure the Channel 4 in PWM mode */
3170 TIM_OC4_SetConfig(htim->Instance, sConfig);
3171
3172 /* Set the Preload enable bit for channel4 */
3173 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
3174
3175 /* Configure the Output Fast mode */
3176 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
3177 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
3178 }
3179 break;
3180
3181 default:
3182 break;
3183 }
3184
3185 htim->State = HAL_TIM_STATE_READY;
3186
3187 __HAL_UNLOCK(htim);
3188
3189 return HAL_OK;
3190 }
3191
3192 /**
3193 * @brief Initializes the TIM One Pulse Channels according to the specified
3194 * parameters in the TIM_OnePulse_InitTypeDef.
3195 * @param htim TIM One Pulse handle
3196 * @param sConfig TIM One Pulse configuration structure
3197 * @param OutputChannel TIM Channels to be enabled
3198 * This parameter can be one of the following values:
3199 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3200 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3201 * @param InputChannel TIM Channels to be enabled
3202 * This parameter can be one of the following values:
3203 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3204 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3205 * @retval HAL status
3206 */
3207 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
3208 {
3209 TIM_OC_InitTypeDef temp1;
3210
3211 /* Check the parameters */
3212 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
3213 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
3214
3215 if(OutputChannel != InputChannel)
3216 {
3217 __HAL_LOCK(htim);
3218
3219 htim->State = HAL_TIM_STATE_BUSY;
3220
3221 /* Extract the Ouput compare configuration from sConfig structure */
3222 temp1.OCMode = sConfig->OCMode;
3223 temp1.Pulse = sConfig->Pulse;
3224 temp1.OCPolarity = sConfig->OCPolarity;
3225 temp1.OCNPolarity = sConfig->OCNPolarity;
3226 temp1.OCIdleState = sConfig->OCIdleState;
3227 temp1.OCNIdleState = sConfig->OCNIdleState;
3228
3229 switch (OutputChannel)
3230 {
3231 case TIM_CHANNEL_1:
3232 {
3233 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3234
3235 TIM_OC1_SetConfig(htim->Instance, &temp1);
3236 }
3237 break;
3238 case TIM_CHANNEL_2:
3239 {
3240 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3241
3242 TIM_OC2_SetConfig(htim->Instance, &temp1);
3243 }
3244 break;
3245 default:
3246 break;
3247 }
3248 switch (InputChannel)
3249 {
3250 case TIM_CHANNEL_1:
3251 {
3252 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3253
3254 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
3255 sConfig->ICSelection, sConfig->ICFilter);
3256
3257 /* Reset the IC1PSC Bits */
3258 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
3259
3260 /* Select the Trigger source */
3261 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3262 htim->Instance->SMCR |= TIM_TS_TI1FP1;
3263
3264 /* Select the Slave Mode */
3265 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3266 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3267 }
3268 break;
3269 case TIM_CHANNEL_2:
3270 {
3271 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3272
3273 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
3274 sConfig->ICSelection, sConfig->ICFilter);
3275
3276 /* Reset the IC2PSC Bits */
3277 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
3278
3279 /* Select the Trigger source */
3280 htim->Instance->SMCR &= ~TIM_SMCR_TS;
3281 htim->Instance->SMCR |= TIM_TS_TI2FP2;
3282
3283 /* Select the Slave Mode */
3284 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
3285 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
3286 }
3287 break;
3288
3289 default:
3290 break;
3291 }
3292
3293 htim->State = HAL_TIM_STATE_READY;
3294
3295 __HAL_UNLOCK(htim);
3296
3297 return HAL_OK;
3298 }
3299 else
3300 {
3301 return HAL_ERROR;
3302 }
3303 }
3304
3305 /**
3306 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
3307 * @param htim TIM handle
3308 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3309 * This parameter can be one of the following values:
3310 * @arg TIM_DMABASE_CR1
3311 * @arg TIM_DMABASE_CR2
3312 * @arg TIM_DMABASE_SMCR
3313 * @arg TIM_DMABASE_DIER
3314 * @arg TIM_DMABASE_SR
3315 * @arg TIM_DMABASE_EGR
3316 * @arg TIM_DMABASE_CCMR1
3317 * @arg TIM_DMABASE_CCMR2
3318 * @arg TIM_DMABASE_CCER
3319 * @arg TIM_DMABASE_CNT
3320 * @arg TIM_DMABASE_PSC
3321 * @arg TIM_DMABASE_ARR
3322 * @arg TIM_DMABASE_RCR
3323 * @arg TIM_DMABASE_CCR1
3324 * @arg TIM_DMABASE_CCR2
3325 * @arg TIM_DMABASE_CCR3
3326 * @arg TIM_DMABASE_CCR4
3327 * @arg TIM_DMABASE_BDTR
3328 * @arg TIM_DMABASE_DCR
3329 * @param BurstRequestSrc TIM DMA Request sources
3330 * This parameter can be one of the following values:
3331 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3332 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3333 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3334 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3335 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3336 * @arg TIM_DMA_COM: TIM Commutation DMA source
3337 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3338 * @param BurstBuffer The Buffer address.
3339 * @param BurstLength DMA Burst length. This parameter can be one value
3340 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3341 * @retval HAL status
3342 */
3343 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3344 uint32_t *BurstBuffer, uint32_t BurstLength)
3345 {
3346 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
3347 }
3348
3349 /**
3350 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
3351 * @param htim TIM handle
3352 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
3353 * This parameter can be one of the following values:
3354 * @arg TIM_DMABASE_CR1
3355 * @arg TIM_DMABASE_CR2
3356 * @arg TIM_DMABASE_SMCR
3357 * @arg TIM_DMABASE_DIER
3358 * @arg TIM_DMABASE_SR
3359 * @arg TIM_DMABASE_EGR
3360 * @arg TIM_DMABASE_CCMR1
3361 * @arg TIM_DMABASE_CCMR2
3362 * @arg TIM_DMABASE_CCER
3363 * @arg TIM_DMABASE_CNT
3364 * @arg TIM_DMABASE_PSC
3365 * @arg TIM_DMABASE_ARR
3366 * @arg TIM_DMABASE_RCR
3367 * @arg TIM_DMABASE_CCR1
3368 * @arg TIM_DMABASE_CCR2
3369 * @arg TIM_DMABASE_CCR3
3370 * @arg TIM_DMABASE_CCR4
3371 * @arg TIM_DMABASE_BDTR
3372 * @arg TIM_DMABASE_DCR
3373 * @param BurstRequestSrc TIM DMA Request sources
3374 * This parameter can be one of the following values:
3375 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3376 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3377 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3378 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3379 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3380 * @arg TIM_DMA_COM: TIM Commutation DMA source
3381 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3382 * @param BurstBuffer The Buffer address.
3383 * @param BurstLength DMA Burst length. This parameter can be one value
3384 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3385 * @param DataLength Data length. This parameter can be one value
3386 * between 1 and 0xFFFF.
3387 * @retval HAL status
3388 */
3389 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3390 uint32_t* BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
3391 {
3392 /* Check the parameters */
3393 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3394 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3395 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3396 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3397 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
3398
3399 if((htim->State == HAL_TIM_STATE_BUSY))
3400 {
3401 return HAL_BUSY;
3402 }
3403 else if((htim->State == HAL_TIM_STATE_READY))
3404 {
3405 if((BurstBuffer == 0U ) && (BurstLength > 0U))
3406 {
3407 return HAL_ERROR;
3408 }
3409 else
3410 {
3411 htim->State = HAL_TIM_STATE_BUSY;
3412 }
3413 }
3414 switch(BurstRequestSrc)
3415 {
3416 case TIM_DMA_UPDATE:
3417 {
3418 /* Set the DMA Period elapsed callback */
3419 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3420
3421 /* Set the DMA error callback */
3422 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3423
3424 /* Enable the DMA channel */
3425 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3426 }
3427 break;
3428 case TIM_DMA_CC1:
3429 {
3430 /* Set the DMA Period elapsed callback */
3431 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
3432
3433 /* Set the DMA error callback */
3434 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3435
3436 /* Enable the DMA channel */
3437 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3438 }
3439 break;
3440 case TIM_DMA_CC2:
3441 {
3442 /* Set the DMA Period elapsed callback */
3443 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
3444
3445 /* Set the DMA error callback */
3446 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3447
3448 /* Enable the DMA channel */
3449 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3450 }
3451 break;
3452 case TIM_DMA_CC3:
3453 {
3454 /* Set the DMA Period elapsed callback */
3455 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
3456
3457 /* Set the DMA error callback */
3458 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3459
3460 /* Enable the DMA channel */
3461 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3462 }
3463 break;
3464 case TIM_DMA_CC4:
3465 {
3466 /* Set the DMA Period elapsed callback */
3467 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
3468
3469 /* Set the DMA error callback */
3470 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3471
3472 /* Enable the DMA channel */
3473 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3474 }
3475 break;
3476 case TIM_DMA_COM:
3477 {
3478 /* Set the DMA Period elapsed callback */
3479 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3480
3481 /* Set the DMA error callback */
3482 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3483
3484 /* Enable the DMA channel */
3485 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3486 }
3487 break;
3488 case TIM_DMA_TRIGGER:
3489 {
3490 /* Set the DMA Period elapsed callback */
3491 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3492
3493 /* Set the DMA error callback */
3494 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3495
3496 /* Enable the DMA channel */
3497 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, DataLength);
3498 }
3499 break;
3500 default:
3501 break;
3502 }
3503 /* configure the DMA Burst Mode */
3504 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3505
3506 /* Enable the TIM DMA Request */
3507 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3508
3509 htim->State = HAL_TIM_STATE_READY;
3510
3511 /* Return function status */
3512 return HAL_OK;
3513 }
3514
3515 /**
3516 * @brief Stops the TIM DMA Burst mode
3517 * @param htim TIM handle
3518 * @param BurstRequestSrc TIM DMA Request sources to disable
3519 * @retval HAL status
3520 */
3521 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3522 {
3523 /* Check the parameters */
3524 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3525
3526 /* Abort the DMA transfer (at least disable the DMA channel) */
3527 switch(BurstRequestSrc)
3528 {
3529 case TIM_DMA_UPDATE:
3530 {
3531 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3532 }
3533 break;
3534 case TIM_DMA_CC1:
3535 {
3536 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3537 }
3538 break;
3539 case TIM_DMA_CC2:
3540 {
3541 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3542 }
3543 break;
3544 case TIM_DMA_CC3:
3545 {
3546 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3547 }
3548 break;
3549 case TIM_DMA_CC4:
3550 {
3551 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3552 }
3553 break;
3554 case TIM_DMA_COM:
3555 {
3556 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3557 }
3558 break;
3559 case TIM_DMA_TRIGGER:
3560 {
3561 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3562 }
3563 break;
3564 default:
3565 break;
3566 }
3567
3568 /* Disable the TIM Update DMA request */
3569 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3570
3571 /* Return function status */
3572 return HAL_OK;
3573 }
3574
3575 /**
3576 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
3577 * @param htim TIM handle
3578 * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
3579 * This parameter can be one of the following values:
3580 * @arg TIM_DMABASE_CR1
3581 * @arg TIM_DMABASE_CR2
3582 * @arg TIM_DMABASE_SMCR
3583 * @arg TIM_DMABASE_DIER
3584 * @arg TIM_DMABASE_SR
3585 * @arg TIM_DMABASE_EGR
3586 * @arg TIM_DMABASE_CCMR1
3587 * @arg TIM_DMABASE_CCMR2
3588 * @arg TIM_DMABASE_CCER
3589 * @arg TIM_DMABASE_CNT
3590 * @arg TIM_DMABASE_PSC
3591 * @arg TIM_DMABASE_ARR
3592 * @arg TIM_DMABASE_RCR
3593 * @arg TIM_DMABASE_CCR1
3594 * @arg TIM_DMABASE_CCR2
3595 * @arg TIM_DMABASE_CCR3
3596 * @arg TIM_DMABASE_CCR4
3597 * @arg TIM_DMABASE_BDTR
3598 * @arg TIM_DMABASE_DCR
3599 * @param BurstRequestSrc TIM DMA Request sources
3600 * This parameter can be one of the following values:
3601 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3602 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3603 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3604 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3605 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3606 * @arg TIM_DMA_COM: TIM Commutation DMA source
3607 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3608 * @param BurstBuffer The Buffer address.
3609 * @param BurstLength DMA Burst length. This parameter can be one value
3610 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3611 * @retval HAL status
3612 */
3613 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3614 uint32_t *BurstBuffer, uint32_t BurstLength)
3615 {
3616 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, ((BurstLength) >> 8U) + 1U);
3617 }
3618
3619 /**
3620 * @brief Configure the DMA Burst to transfer multiple Data from the TIM peripheral to the memory
3621 * @param htim TIM handle
3622 * @param BurstBaseAddress TIM Base address from where the DMA will starts the Data read
3623 * This parameter can be one of the following values:
3624 * @arg TIM_DMABASE_CR1
3625 * @arg TIM_DMABASE_CR2
3626 * @arg TIM_DMABASE_SMCR
3627 * @arg TIM_DMABASE_DIER
3628 * @arg TIM_DMABASE_SR
3629 * @arg TIM_DMABASE_EGR
3630 * @arg TIM_DMABASE_CCMR1
3631 * @arg TIM_DMABASE_CCMR2
3632 * @arg TIM_DMABASE_CCER
3633 * @arg TIM_DMABASE_CNT
3634 * @arg TIM_DMABASE_PSC
3635 * @arg TIM_DMABASE_ARR
3636 * @arg TIM_DMABASE_RCR
3637 * @arg TIM_DMABASE_CCR1
3638 * @arg TIM_DMABASE_CCR2
3639 * @arg TIM_DMABASE_CCR3
3640 * @arg TIM_DMABASE_CCR4
3641 * @arg TIM_DMABASE_BDTR
3642 * @arg TIM_DMABASE_DCR
3643 * @param BurstRequestSrc TIM DMA Request sources
3644 * This parameter can be one of the following values:
3645 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
3646 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
3647 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
3648 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
3649 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
3650 * @arg TIM_DMA_COM: TIM Commutation DMA source
3651 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
3652 * @param BurstBuffer The Buffer address.
3653 * @param BurstLength DMA Burst length. This parameter can be one value
3654 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
3655 * @param DataLength Data length. This parameter can be one value
3656 * between 1 and 0xFFFF.
3657 * @retval HAL status
3658 */
3659 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
3660 uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength)
3661 {
3662 /* Check the parameters */
3663 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
3664 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
3665 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3666 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
3667 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
3668
3669 if((htim->State == HAL_TIM_STATE_BUSY))
3670 {
3671 return HAL_BUSY;
3672 }
3673 else if((htim->State == HAL_TIM_STATE_READY))
3674 {
3675 if((BurstBuffer == 0U ) && (BurstLength > 0U))
3676 {
3677 return HAL_ERROR;
3678 }
3679 else
3680 {
3681 htim->State = HAL_TIM_STATE_BUSY;
3682 }
3683 }
3684 switch(BurstRequestSrc)
3685 {
3686 case TIM_DMA_UPDATE:
3687 {
3688 /* Set the DMA Period elapsed callback */
3689 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
3690
3691 /* Set the DMA error callback */
3692 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
3693
3694 /* Enable the DMA channel */
3695 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3696 }
3697 break;
3698 case TIM_DMA_CC1:
3699 {
3700 /* Set the DMA Period elapsed callback */
3701 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3702
3703 /* Set the DMA error callback */
3704 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3705
3706 /* Enable the DMA channel */
3707 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3708 }
3709 break;
3710 case TIM_DMA_CC2:
3711 {
3712 /* Set the DMA Period elapsed callback */
3713 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3714
3715 /* Set the DMA error callback */
3716 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3717
3718 /* Enable the DMA channel */
3719 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3720 }
3721 break;
3722 case TIM_DMA_CC3:
3723 {
3724 /* Set the DMA Period elapsed callback */
3725 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
3726
3727 /* Set the DMA error callback */
3728 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
3729
3730 /* Enable the DMA channel */
3731 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3732 }
3733 break;
3734 case TIM_DMA_CC4:
3735 {
3736 /* Set the DMA Period elapsed callback */
3737 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
3738
3739 /* Set the DMA error callback */
3740 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
3741
3742 /* Enable the DMA channel */
3743 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3744 }
3745 break;
3746 case TIM_DMA_COM:
3747 {
3748 /* Set the DMA Period elapsed callback */
3749 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
3750
3751 /* Set the DMA error callback */
3752 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
3753
3754 /* Enable the DMA channel */
3755 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3756 }
3757 break;
3758 case TIM_DMA_TRIGGER:
3759 {
3760 /* Set the DMA Period elapsed callback */
3761 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
3762
3763 /* Set the DMA error callback */
3764 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
3765
3766 /* Enable the DMA channel */
3767 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, DataLength);
3768 }
3769 break;
3770 default:
3771 break;
3772 }
3773
3774 /* configure the DMA Burst Mode */
3775 htim->Instance->DCR = BurstBaseAddress | BurstLength;
3776
3777 /* Enable the TIM DMA Request */
3778 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
3779
3780 htim->State = HAL_TIM_STATE_READY;
3781
3782 /* Return function status */
3783 return HAL_OK;
3784 }
3785
3786 /**
3787 * @brief Stop the DMA burst reading
3788 * @param htim TIM handle
3789 * @param BurstRequestSrc TIM DMA Request sources to disable.
3790 * @retval HAL status
3791 */
3792 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
3793 {
3794 /* Check the parameters */
3795 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
3796
3797 /* Abort the DMA transfer (at least disable the DMA channel) */
3798 switch(BurstRequestSrc)
3799 {
3800 case TIM_DMA_UPDATE:
3801 {
3802 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
3803 }
3804 break;
3805 case TIM_DMA_CC1:
3806 {
3807 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
3808 }
3809 break;
3810 case TIM_DMA_CC2:
3811 {
3812 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
3813 }
3814 break;
3815 case TIM_DMA_CC3:
3816 {
3817 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
3818 }
3819 break;
3820 case TIM_DMA_CC4:
3821 {
3822 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
3823 }
3824 break;
3825 case TIM_DMA_COM:
3826 {
3827 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
3828 }
3829 break;
3830 case TIM_DMA_TRIGGER:
3831 {
3832 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
3833 }
3834 break;
3835 default:
3836 break;
3837 }
3838
3839 /* Disable the TIM Update DMA request */
3840 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
3841
3842 /* Return function status */
3843 return HAL_OK;
3844 }
3845
3846 /**
3847 * @brief Generate a software event
3848 * @param htim TIM handle
3849 * @param EventSource specifies the event source.
3850 * This parameter can be one of the following values:
3851 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
3852 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
3853 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
3854 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
3855 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
3856 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
3857 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
3858 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
3859 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
3860 * @retval HAL status
3861 * @note TIM_EVENTSOURCE_BREAK2 isn't relevant for STM32F37xx and STM32F38xx
3862 * devices
3863 */
3864
3865 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
3866 {
3867 /* Check the parameters */
3868 assert_param(IS_TIM_INSTANCE(htim->Instance));
3869 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
3870
3871 /* Process Locked */
3872 __HAL_LOCK(htim);
3873
3874 /* Change the TIM state */
3875 htim->State = HAL_TIM_STATE_BUSY;
3876
3877 /* Set the event sources */
3878 htim->Instance->EGR = EventSource;
3879
3880 /* Change the TIM state */
3881 htim->State = HAL_TIM_STATE_READY;
3882
3883 __HAL_UNLOCK(htim);
3884
3885 /* Return function status */
3886 return HAL_OK;
3887 }
3888
3889 /**
3890 * @brief Configures the OCRef clear feature
3891 * @param htim TIM handle
3892 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
3893 * contains the OCREF clear feature and parameters for the TIM peripheral.
3894 * @param Channel specifies the TIM Channel
3895 * This parameter can be one of the following values:
3896 * @arg TIM_CHANNEL_1: TIM Channel 1
3897 * @arg TIM_CHANNEL_2: TIM Channel 2
3898 * @arg TIM_CHANNEL_3: TIM Channel 3
3899 * @arg TIM_CHANNEL_4: TIM Channel 4
3900 * @retval HAL status
3901 */
3902 __weak HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
3903 {
3904 /* Check the parameters */
3905 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3906 assert_param(IS_TIM_CHANNELS(Channel));
3907 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
3908
3909 /* Process Locked */
3910 __HAL_LOCK(htim);
3911
3912 htim->State = HAL_TIM_STATE_BUSY;
3913
3914 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
3915 {
3916 /* Check the parameters */
3917 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
3918 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
3919 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
3920
3921 TIM_ETR_SetConfig(htim->Instance,
3922 sClearInputConfig->ClearInputPrescaler,
3923 sClearInputConfig->ClearInputPolarity,
3924 sClearInputConfig->ClearInputFilter);
3925 }
3926
3927 switch (Channel)
3928 {
3929 case TIM_CHANNEL_1:
3930 {
3931 if(sClearInputConfig->ClearInputState != RESET)
3932 {
3933 /* Enable the Ocref clear feature for Channel 1U */
3934 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
3935 }
3936 else
3937 {
3938 /* Disable the Ocref clear feature for Channel 1U */
3939 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
3940 }
3941 }
3942 break;
3943 case TIM_CHANNEL_2:
3944 {
3945 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3946 if(sClearInputConfig->ClearInputState != RESET)
3947 {
3948 /* Enable the Ocref clear feature for Channel 2U */
3949 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
3950 }
3951 else
3952 {
3953 /* Disable the Ocref clear feature for Channel 2U */
3954 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
3955 }
3956 }
3957 break;
3958 case TIM_CHANNEL_3:
3959 {
3960 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3961 if(sClearInputConfig->ClearInputState != RESET)
3962 {
3963 /* Enable the Ocref clear feature for Channel 3U */
3964 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
3965 }
3966 else
3967 {
3968 /* Disable the Ocref clear feature for Channel 3U */
3969 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
3970 }
3971 }
3972 break;
3973 case TIM_CHANNEL_4:
3974 {
3975 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3976 if(sClearInputConfig->ClearInputState != RESET)
3977 {
3978 /* Enable the Ocref clear feature for Channel 4U */
3979 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
3980 }
3981 else
3982 {
3983 /* Disable the Ocref clear feature for Channel 4U */
3984 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
3985 }
3986 }
3987 break;
3988 default:
3989 break;
3990 }
3991
3992 htim->State = HAL_TIM_STATE_READY;
3993
3994 __HAL_UNLOCK(htim);
3995
3996 return HAL_OK;
3997 }
3998
3999 /**
4000 * @brief Configures the clock source to be used
4001 * @param htim TIM handle
4002 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
4003 * contains the clock source information for the TIM peripheral.
4004 * @retval HAL status
4005 */
4006 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
4007 {
4008 uint32_t tmpsmcr = 0U;
4009
4010 /* Process Locked */
4011 __HAL_LOCK(htim);
4012
4013 htim->State = HAL_TIM_STATE_BUSY;
4014
4015 /* Check the parameters */
4016 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
4017
4018 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
4019 tmpsmcr = htim->Instance->SMCR;
4020 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4021 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
4022 htim->Instance->SMCR = tmpsmcr;
4023
4024 switch (sClockSourceConfig->ClockSource)
4025 {
4026 case TIM_CLOCKSOURCE_INTERNAL:
4027 {
4028 assert_param(IS_TIM_INSTANCE(htim->Instance));
4029 /* Disable slave mode to clock the prescaler directly with the internal clock */
4030 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4031 }
4032 break;
4033
4034 case TIM_CLOCKSOURCE_ETRMODE1:
4035 {
4036 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
4037 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
4038
4039 /* Check ETR input conditioning related parameters */
4040 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4041 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4042 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4043
4044 /* Configure the ETR Clock source */
4045 TIM_ETR_SetConfig(htim->Instance,
4046 sClockSourceConfig->ClockPrescaler,
4047 sClockSourceConfig->ClockPolarity,
4048 sClockSourceConfig->ClockFilter);
4049 /* Get the TIMx SMCR register value */
4050 tmpsmcr = htim->Instance->SMCR;
4051 /* Reset the SMS and TS Bits */
4052 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
4053 /* Select the External clock mode1 and the ETRF trigger */
4054 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
4055 /* Write to TIMx SMCR */
4056 htim->Instance->SMCR = tmpsmcr;
4057 }
4058 break;
4059
4060 case TIM_CLOCKSOURCE_ETRMODE2:
4061 {
4062 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
4063 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
4064
4065 /* Check ETR input conditioning related parameters */
4066 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
4067 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4068 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4069
4070 /* Configure the ETR Clock source */
4071 TIM_ETR_SetConfig(htim->Instance,
4072 sClockSourceConfig->ClockPrescaler,
4073 sClockSourceConfig->ClockPolarity,
4074 sClockSourceConfig->ClockFilter);
4075 /* Enable the External clock mode2 */
4076 htim->Instance->SMCR |= TIM_SMCR_ECE;
4077 }
4078 break;
4079
4080 case TIM_CLOCKSOURCE_TI1:
4081 {
4082 /* Check whether or not the timer instance supports external clock mode 1U */
4083 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4084
4085 /* Check TI1 input conditioning related parameters */
4086 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4087 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4088
4089 TIM_TI1_ConfigInputStage(htim->Instance,
4090 sClockSourceConfig->ClockPolarity,
4091 sClockSourceConfig->ClockFilter);
4092 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
4093 }
4094 break;
4095 case TIM_CLOCKSOURCE_TI2:
4096 {
4097 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
4098 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4099
4100 /* Check TI2 input conditioning related parameters */
4101 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4102 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4103
4104 TIM_TI2_ConfigInputStage(htim->Instance,
4105 sClockSourceConfig->ClockPolarity,
4106 sClockSourceConfig->ClockFilter);
4107 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
4108 }
4109 break;
4110 case TIM_CLOCKSOURCE_TI1ED:
4111 {
4112 /* Check whether or not the timer instance supports external clock mode 1U */
4113 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
4114
4115 /* Check TI1 input conditioning related parameters */
4116 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
4117 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
4118
4119 TIM_TI1_ConfigInputStage(htim->Instance,
4120 sClockSourceConfig->ClockPolarity,
4121 sClockSourceConfig->ClockFilter);
4122 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
4123 }
4124 break;
4125 case TIM_CLOCKSOURCE_ITR0:
4126 {
4127 /* Check whether or not the timer instance supports external clock mode 1U */
4128 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4129
4130 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
4131 }
4132 break;
4133 case TIM_CLOCKSOURCE_ITR1:
4134 {
4135 /* Check whether or not the timer instance supports external clock mode 1U */
4136 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4137
4138 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
4139 }
4140 break;
4141 case TIM_CLOCKSOURCE_ITR2:
4142 {
4143 /* Check whether or not the timer instance supports external clock mode 1U */
4144 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4145
4146 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
4147 }
4148 break;
4149 case TIM_CLOCKSOURCE_ITR3:
4150 {
4151 /* Check whether or not the timer instance supports external clock mode 1U */
4152 assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
4153
4154 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
4155 }
4156 break;
4157
4158 default:
4159 break;
4160 }
4161 htim->State = HAL_TIM_STATE_READY;
4162
4163 __HAL_UNLOCK(htim);
4164
4165 return HAL_OK;
4166 }
4167
4168 /**
4169 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
4170 * or a XOR combination between CH1_input, CH2_input & CH3_input
4171 * @param htim TIM handle.
4172 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
4173 * output of a XOR gate.
4174 * This parameter can be one of the following values:
4175 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
4176 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
4177 * pins are connected to the TI1 input (XOR combination)
4178 * @retval HAL status
4179 */
4180 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
4181 {
4182 uint32_t tmpcr2 = 0U;
4183
4184 /* Check the parameters */
4185 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
4186 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
4187
4188 /* Get the TIMx CR2 register value */
4189 tmpcr2 = htim->Instance->CR2;
4190
4191 /* Reset the TI1 selection */
4192 tmpcr2 &= ~TIM_CR2_TI1S;
4193
4194 /* Set the the TI1 selection */
4195 tmpcr2 |= TI1_Selection;
4196
4197 /* Write to TIMxCR2 */
4198 htim->Instance->CR2 = tmpcr2;
4199
4200 return HAL_OK;
4201 }
4202
4203 /**
4204 * @brief Configures the TIM in Slave mode
4205 * @param htim TIM handle.
4206 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4207 * contains the selected trigger (internal trigger input, filtered
4208 * timer input or external trigger input) and the ) and the Slave
4209 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4210 * @retval HAL status
4211 */
4212 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
4213 {
4214 /* Check the parameters */
4215 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4216 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4217 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4218
4219 __HAL_LOCK(htim);
4220
4221 htim->State = HAL_TIM_STATE_BUSY;
4222
4223 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4224
4225 /* Disable Trigger Interrupt */
4226 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
4227
4228 /* Disable Trigger DMA request */
4229 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4230
4231 htim->State = HAL_TIM_STATE_READY;
4232
4233 __HAL_UNLOCK(htim);
4234
4235 return HAL_OK;
4236 }
4237
4238 /**
4239 * @brief Configures the TIM in Slave mode in interrupt mode
4240 * @param htim TIM handle.
4241 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
4242 * contains the selected trigger (internal trigger input, filtered
4243 * timer input or external trigger input) and the ) and the Slave
4244 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
4245 * @retval HAL status
4246 */
4247 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
4248 TIM_SlaveConfigTypeDef * sSlaveConfig)
4249 {
4250 /* Check the parameters */
4251 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
4252 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
4253 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
4254
4255 __HAL_LOCK(htim);
4256
4257 htim->State = HAL_TIM_STATE_BUSY;
4258
4259 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
4260
4261 /* Enable Trigger Interrupt */
4262 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
4263
4264 /* Disable Trigger DMA request */
4265 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
4266
4267 htim->State = HAL_TIM_STATE_READY;
4268
4269 __HAL_UNLOCK(htim);
4270
4271 return HAL_OK;
4272 }
4273
4274 /**
4275 * @brief Read the captured value from Capture Compare unit
4276 * @param htim TIM handle.
4277 * @param Channel TIM Channels to be enabled
4278 * This parameter can be one of the following values:
4279 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4280 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4281 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4282 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4283 * @retval Captured value
4284 */
4285 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
4286 {
4287 uint32_t tmpreg = 0U;
4288
4289 __HAL_LOCK(htim);
4290
4291 switch (Channel)
4292 {
4293 case TIM_CHANNEL_1:
4294 {
4295 /* Check the parameters */
4296 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4297
4298 /* Return the capture 1 value */
4299 tmpreg = htim->Instance->CCR1;
4300
4301 break;
4302 }
4303 case TIM_CHANNEL_2:
4304 {
4305 /* Check the parameters */
4306 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4307
4308 /* Return the capture 2 value */
4309 tmpreg = htim->Instance->CCR2;
4310
4311 break;
4312 }
4313
4314 case TIM_CHANNEL_3:
4315 {
4316 /* Check the parameters */
4317 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4318
4319 /* Return the capture 3 value */
4320 tmpreg = htim->Instance->CCR3;
4321
4322 break;
4323 }
4324
4325 case TIM_CHANNEL_4:
4326 {
4327 /* Check the parameters */
4328 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4329
4330 /* Return the capture 4 value */
4331 tmpreg = htim->Instance->CCR4;
4332
4333 break;
4334 }
4335
4336 default:
4337 break;
4338 }
4339
4340 __HAL_UNLOCK(htim);
4341 return tmpreg;
4342 }
4343
4344 /**
4345 * @}
4346 */
4347
4348 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
4349 * @brief TIM Callbacks functions
4350 *
4351 @verbatim
4352 ==============================================================================
4353 ##### TIM Callbacks functions #####
4354 ==============================================================================
4355 [..]
4356 This section provides TIM callback functions:
4357 (+) Timer Period elapsed callback
4358 (+) Timer Output Compare callback
4359 (+) Timer Input capture callback
4360 (+) Timer Trigger callback
4361 (+) Timer Error callback
4362
4363 @endverbatim
4364 * @{
4365 */
4366
4367 /**
4368 * @brief Period elapsed callback in non blocking mode
4369 * @param htim TIM handle
4370 * @retval None
4371 */
4372 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
4373 {
4374 /* Prevent unused argument(s) compilation warning */
4375 UNUSED(htim);
4376
4377 /* NOTE : This function Should not be modified, when the callback is needed,
4378 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
4379 */
4380
4381 }
4382 /**
4383 * @brief Output Compare callback in non blocking mode
4384 * @param htim TIM OC handle
4385 * @retval None
4386 */
4387 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
4388 {
4389 /* Prevent unused argument(s) compilation warning */
4390 UNUSED(htim);
4391
4392 /* NOTE : This function Should not be modified, when the callback is needed,
4393 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
4394 */
4395 }
4396 /**
4397 * @brief Input Capture callback in non blocking mode
4398 * @param htim TIM IC handle
4399 * @retval None
4400 */
4401 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
4402 {
4403 /* Prevent unused argument(s) compilation warning */
4404 UNUSED(htim);
4405
4406 /* NOTE : This function Should not be modified, when the callback is needed,
4407 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
4408 */
4409 }
4410
4411 /**
4412 * @brief PWM Pulse finished callback in non blocking mode
4413 * @param htim TIM handle
4414 * @retval None
4415 */
4416 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
4417 {
4418 /* Prevent unused argument(s) compilation warning */
4419 UNUSED(htim);
4420
4421 /* NOTE : This function Should not be modified, when the callback is needed,
4422 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
4423 */
4424 }
4425
4426 /**
4427 * @brief Hall Trigger detection callback in non blocking mode
4428 * @param htim TIM handle
4429 * @retval None
4430 */
4431 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
4432 {
4433 /* Prevent unused argument(s) compilation warning */
4434 UNUSED(htim);
4435
4436 /* NOTE : This function Should not be modified, when the callback is needed,
4437 the HAL_TIM_TriggerCallback could be implemented in the user file
4438 */
4439 }
4440
4441 /**
4442 * @brief Timer error callback in non blocking mode
4443 * @param htim TIM handle
4444 * @retval None
4445 */
4446 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
4447 {
4448 /* Prevent unused argument(s) compilation warning */
4449 UNUSED(htim);
4450
4451 /* NOTE : This function Should not be modified, when the callback is needed,
4452 the HAL_TIM_ErrorCallback could be implemented in the user file
4453 */
4454 }
4455
4456 /**
4457 * @}
4458 */
4459
4460 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
4461 * @brief Peripheral State functions
4462 *
4463 @verbatim
4464 ==============================================================================
4465 ##### Peripheral State functions #####
4466 ==============================================================================
4467 [..]
4468 This subsection permit to get in run-time the status of the peripheral
4469 and the data flow.
4470
4471 @endverbatim
4472 * @{
4473 */
4474
4475 /**
4476 * @brief Return the TIM Base state
4477 * @param htim TIM Base handle
4478 * @retval HAL state
4479 */
4480 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
4481 {
4482 return htim->State;
4483 }
4484
4485 /**
4486 * @brief Return the TIM OC state
4487 * @param htim TIM Ouput Compare handle
4488 * @retval HAL state
4489 */
4490 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
4491 {
4492 return htim->State;
4493 }
4494
4495 /**
4496 * @brief Return the TIM PWM state
4497 * @param htim TIM handle
4498 * @retval HAL state
4499 */
4500 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
4501 {
4502 return htim->State;
4503 }
4504
4505 /**
4506 * @brief Return the TIM Input Capture state
4507 * @param htim TIM IC handle
4508 * @retval HAL state
4509 */
4510 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
4511 {
4512 return htim->State;
4513 }
4514
4515 /**
4516 * @brief Return the TIM One Pulse Mode state
4517 * @param htim TIM OPM handle
4518 * @retval HAL state
4519 */
4520 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
4521 {
4522 return htim->State;
4523 }
4524
4525 /**
4526 * @brief Return the TIM Encoder Mode state
4527 * @param htim TIM Encoder handle
4528 * @retval HAL state
4529 */
4530 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
4531 {
4532 return htim->State;
4533 }
4534
4535 /**
4536 * @}
4537 */
4538
4539 /**
4540 * @}
4541 */
4542
4543 /** @addtogroup TIM_Private_Functions TIM_Private_Functions
4544 * @{
4545 */
4546
4547 /**
4548 * @brief TIM DMA error callback
4549 * @param hdma pointer to DMA handle.
4550 * @retval None
4551 */
4552 void TIM_DMAError(DMA_HandleTypeDef *hdma)
4553 {
4554 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4555
4556 htim->State= HAL_TIM_STATE_READY;
4557
4558 HAL_TIM_ErrorCallback(htim);
4559 }
4560
4561 /**
4562 * @brief TIM DMA Delay Pulse complete callback.
4563 * @param hdma pointer to DMA handle.
4564 * @retval None
4565 */
4566 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
4567 {
4568 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4569
4570 htim->State= HAL_TIM_STATE_READY;
4571
4572 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4573 {
4574 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4575 }
4576 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4577 {
4578 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4579 }
4580 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4581 {
4582 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4583 }
4584 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4585 {
4586 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4587 }
4588
4589 HAL_TIM_PWM_PulseFinishedCallback(htim);
4590
4591 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4592 }
4593 /**
4594 * @brief TIM DMA Capture complete callback.
4595 * @param hdma pointer to DMA handle.
4596 * @retval None
4597 */
4598 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
4599 {
4600 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4601
4602 htim->State= HAL_TIM_STATE_READY;
4603
4604 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
4605 {
4606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
4607 }
4608 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
4609 {
4610 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
4611 }
4612 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
4613 {
4614 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
4615 }
4616 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
4617 {
4618 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
4619 }
4620
4621 HAL_TIM_IC_CaptureCallback(htim);
4622
4623 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
4624 }
4625
4626 /**
4627 * @brief TIM DMA Period Elapse complete callback.
4628 * @param hdma pointer to DMA handle.
4629 * @retval None
4630 */
4631 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
4632 {
4633 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4634
4635 htim->State= HAL_TIM_STATE_READY;
4636
4637 HAL_TIM_PeriodElapsedCallback(htim);
4638 }
4639
4640 /**
4641 * @brief TIM DMA Trigger callback.
4642 * @param hdma pointer to DMA handle.
4643 * @retval None
4644 */
4645 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
4646 {
4647 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4648
4649 htim->State= HAL_TIM_STATE_READY;
4650
4651 HAL_TIM_TriggerCallback(htim);
4652 }
4653
4654 /**
4655 * @brief Time Base configuration
4656 * @param TIMx TIM periheral
4657 * @param Structure TIM Base configuration structure
4658 * @retval None
4659 */
4660 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
4661 {
4662 uint32_t tmpcr1 = 0U;
4663 tmpcr1 = TIMx->CR1;
4664
4665 /* Set TIM Time Base Unit parameters ---------------------------------------*/
4666 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
4667 {
4668 /* Select the Counter Mode */
4669 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
4670 tmpcr1 |= Structure->CounterMode;
4671 }
4672
4673 if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
4674 {
4675 /* Set the clock division */
4676 tmpcr1 &= ~TIM_CR1_CKD;
4677 tmpcr1 |= (uint32_t)Structure->ClockDivision;
4678 }
4679
4680 /* Set the auto-reload preload */
4681 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
4682
4683 TIMx->CR1 = tmpcr1;
4684
4685 /* Set the Autoreload value */
4686 TIMx->ARR = (uint32_t)Structure->Period ;
4687
4688 /* Set the Prescaler value */
4689 TIMx->PSC = (uint32_t)Structure->Prescaler;
4690
4691 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
4692 {
4693 /* Set the Repetition Counter value */
4694 TIMx->RCR = Structure->RepetitionCounter;
4695 }
4696
4697 /* Generate an update event to reload the Prescaler
4698 and the repetition counter(only for TIM1 and TIM8) value immediatly */
4699 TIMx->EGR = TIM_EGR_UG;
4700 }
4701
4702 /**
4703 * @brief Time Ouput Compare 1 configuration
4704 * @param TIMx to select the TIM peripheral
4705 * @param OC_Config The ouput configuration structure
4706 * @retval None
4707 */
4708 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4709 {
4710 uint32_t tmpccmrx = 0U;
4711 uint32_t tmpccer = 0U;
4712 uint32_t tmpcr2 = 0U;
4713
4714 /* Disable the Channel 1: Reset the CC1E Bit */
4715 TIMx->CCER &= ~TIM_CCER_CC1E;
4716
4717 /* Get the TIMx CCER register value */
4718 tmpccer = TIMx->CCER;
4719 /* Get the TIMx CR2 register value */
4720 tmpcr2 = TIMx->CR2;
4721
4722 /* Get the TIMx CCMR1 register value */
4723 tmpccmrx = TIMx->CCMR1;
4724
4725 /* Reset the Output Compare Mode Bits */
4726 tmpccmrx &= ~TIM_CCMR1_OC1M;
4727 tmpccmrx &= ~TIM_CCMR1_CC1S;
4728 /* Select the Output Compare Mode */
4729 tmpccmrx |= OC_Config->OCMode;
4730
4731 /* Reset the Output Polarity level */
4732 tmpccer &= ~TIM_CCER_CC1P;
4733 /* Set the Output Compare Polarity */
4734 tmpccer |= OC_Config->OCPolarity;
4735
4736 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
4737 {
4738 /* Check parameters */
4739 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4740
4741 /* Reset the Output N Polarity level */
4742 tmpccer &= ~TIM_CCER_CC1NP;
4743 /* Set the Output N Polarity */
4744 tmpccer |= OC_Config->OCNPolarity;
4745 /* Reset the Output N State */
4746 tmpccer &= ~TIM_CCER_CC1NE;
4747 }
4748
4749 if(IS_TIM_BREAK_INSTANCE(TIMx))
4750 {
4751 /* Check parameters */
4752 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4753 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4754
4755 /* Reset the Output Compare and Output Compare N IDLE State */
4756 tmpcr2 &= ~TIM_CR2_OIS1;
4757 tmpcr2 &= ~TIM_CR2_OIS1N;
4758 /* Set the Output Idle state */
4759 tmpcr2 |= OC_Config->OCIdleState;
4760 /* Set the Output N Idle state */
4761 tmpcr2 |= OC_Config->OCNIdleState;
4762 }
4763 /* Write to TIMx CR2 */
4764 TIMx->CR2 = tmpcr2;
4765
4766 /* Write to TIMx CCMR1 */
4767 TIMx->CCMR1 = tmpccmrx;
4768
4769 /* Set the Capture Compare Register value */
4770 TIMx->CCR1 = OC_Config->Pulse;
4771
4772 /* Write to TIMx CCER */
4773 TIMx->CCER = tmpccer;
4774 }
4775
4776 /**
4777 * @brief Time Ouput Compare 2 configuration
4778 * @param TIMx to select the TIM peripheral
4779 * @param OC_Config The ouput configuration structure
4780 * @retval None
4781 */
4782 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4783 {
4784 uint32_t tmpccmrx = 0U;
4785 uint32_t tmpccer = 0U;
4786 uint32_t tmpcr2 = 0U;
4787
4788 /* Disable the Channel 2: Reset the CC2E Bit */
4789 TIMx->CCER &= ~TIM_CCER_CC2E;
4790
4791 /* Get the TIMx CCER register value */
4792 tmpccer = TIMx->CCER;
4793 /* Get the TIMx CR2 register value */
4794 tmpcr2 = TIMx->CR2;
4795
4796 /* Get the TIMx CCMR1 register value */
4797 tmpccmrx = TIMx->CCMR1;
4798
4799 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4800 tmpccmrx &= ~TIM_CCMR1_OC2M;
4801 tmpccmrx &= ~TIM_CCMR1_CC2S;
4802
4803 /* Select the Output Compare Mode */
4804 tmpccmrx |= (OC_Config->OCMode << 8U);
4805
4806 /* Reset the Output Polarity level */
4807 tmpccer &= ~TIM_CCER_CC2P;
4808 /* Set the Output Compare Polarity */
4809 tmpccer |= (OC_Config->OCPolarity << 4U);
4810
4811 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
4812 {
4813 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4814
4815 /* Reset the Output N Polarity level */
4816 tmpccer &= ~TIM_CCER_CC2NP;
4817 /* Set the Output N Polarity */
4818 tmpccer |= (OC_Config->OCNPolarity << 4U);
4819 /* Reset the Output N State */
4820 tmpccer &= ~TIM_CCER_CC2NE;
4821
4822 }
4823
4824 if(IS_TIM_BREAK_INSTANCE(TIMx))
4825 {
4826 /* Check parameters */
4827 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4828 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4829
4830 /* Reset the Output Compare IDLE State */
4831 tmpcr2 &= ~TIM_CR2_OIS2;
4832 #if defined(STM32F373xC) || defined(STM32F378xx)
4833 #else
4834 /* Reset the Output Compare N IDLE State */
4835 tmpcr2 &= ~TIM_CR2_OIS2N;
4836 #endif
4837 /* Set the Output Idle state */
4838 tmpcr2 |= (OC_Config->OCIdleState << 2U);
4839 /* Set the Output N Idle state */
4840 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
4841 }
4842
4843 /* Write to TIMx CR2 */
4844 TIMx->CR2 = tmpcr2;
4845
4846 /* Write to TIMx CCMR1 */
4847 TIMx->CCMR1 = tmpccmrx;
4848
4849 /* Set the Capture Compare Register value */
4850 TIMx->CCR2 = OC_Config->Pulse;
4851
4852 /* Write to TIMx CCER */
4853 TIMx->CCER = tmpccer;
4854 }
4855
4856 /**
4857 * @brief Time Ouput Compare 3 configuration
4858 * @param TIMx to select the TIM peripheral
4859 * @param OC_Config The ouput configuration structure
4860 * @retval None
4861 */
4862 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4863 {
4864 uint32_t tmpccmrx = 0U;
4865 uint32_t tmpccer = 0U;
4866 uint32_t tmpcr2 = 0U;
4867
4868 /* Disable the Channel 3: Reset the CC2E Bit */
4869 TIMx->CCER &= ~TIM_CCER_CC3E;
4870
4871 /* Get the TIMx CCER register value */
4872 tmpccer = TIMx->CCER;
4873 /* Get the TIMx CR2 register value */
4874 tmpcr2 = TIMx->CR2;
4875
4876 /* Get the TIMx CCMR2 register value */
4877 tmpccmrx = TIMx->CCMR2;
4878
4879 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4880 tmpccmrx &= ~TIM_CCMR2_OC3M;
4881 tmpccmrx &= ~TIM_CCMR2_CC3S;
4882 /* Select the Output Compare Mode */
4883 tmpccmrx |= OC_Config->OCMode;
4884
4885 /* Reset the Output Polarity level */
4886 tmpccer &= ~TIM_CCER_CC3P;
4887 /* Set the Output Compare Polarity */
4888 tmpccer |= (OC_Config->OCPolarity << 8U);
4889
4890 if(IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
4891 {
4892 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
4893
4894 /* Reset the Output N Polarity level */
4895 tmpccer &= ~TIM_CCER_CC3NP;
4896 /* Set the Output N Polarity */
4897 tmpccer |= (OC_Config->OCNPolarity << 8U);
4898 /* Reset the Output N State */
4899 tmpccer &= ~TIM_CCER_CC3NE;
4900 }
4901
4902 if(IS_TIM_BREAK_INSTANCE(TIMx))
4903 {
4904 /* Check parameters */
4905 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
4906 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4907
4908 #if defined(STM32F373xC) || defined(STM32F378xx)
4909 #else
4910 /* Reset the Output Compare and Output Compare N IDLE State */
4911 tmpcr2 &= ~TIM_CR2_OIS3;
4912 tmpcr2 &= ~TIM_CR2_OIS3N;
4913 #endif
4914 /* Set the Output Idle state */
4915 tmpcr2 |= (OC_Config->OCIdleState << 4U);
4916 /* Set the Output N Idle state */
4917 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
4918 }
4919
4920 /* Write to TIMx CR2 */
4921 TIMx->CR2 = tmpcr2;
4922
4923 /* Write to TIMx CCMR2 */
4924 TIMx->CCMR2 = tmpccmrx;
4925
4926 /* Set the Capture Compare Register value */
4927 TIMx->CCR3 = OC_Config->Pulse;
4928
4929 /* Write to TIMx CCER */
4930 TIMx->CCER = tmpccer;
4931 }
4932
4933 /**
4934 * @brief Time Ouput Compare 4 configuration
4935 * @param TIMx to select the TIM peripheral
4936 * @param OC_Config The ouput configuration structure
4937 * @retval None
4938 */
4939 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
4940 {
4941 uint32_t tmpccmrx = 0U;
4942 uint32_t tmpccer = 0U;
4943 uint32_t tmpcr2 = 0U;
4944
4945 /* Disable the Channel 4: Reset the CC4E Bit */
4946 TIMx->CCER &= ~TIM_CCER_CC4E;
4947
4948 /* Get the TIMx CCER register value */
4949 tmpccer = TIMx->CCER;
4950 /* Get the TIMx CR2 register value */
4951 tmpcr2 = TIMx->CR2;
4952
4953 /* Get the TIMx CCMR2 register value */
4954 tmpccmrx = TIMx->CCMR2;
4955
4956 /* Reset the Output Compare mode and Capture/Compare selection Bits */
4957 tmpccmrx &= ~TIM_CCMR2_OC4M;
4958 tmpccmrx &= ~TIM_CCMR2_CC4S;
4959
4960 /* Select the Output Compare Mode */
4961 tmpccmrx |= (OC_Config->OCMode << 8U);
4962
4963 /* Reset the Output Polarity level */
4964 tmpccer &= ~TIM_CCER_CC4P;
4965 /* Set the Output Compare Polarity */
4966 tmpccer |= (OC_Config->OCPolarity << 12U);
4967
4968 if(IS_TIM_BREAK_INSTANCE(TIMx))
4969 {
4970 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
4971
4972 #if defined(STM32F373xC) || defined(STM32F378xx)
4973 #else
4974 /* Reset the Output Compare IDLE State */
4975 tmpcr2 &= ~TIM_CR2_OIS4;
4976 #endif
4977 /* Set the Output Idle state */
4978 tmpcr2 |= (OC_Config->OCIdleState << 6U);
4979 }
4980
4981 /* Write to TIMx CR2 */
4982 TIMx->CR2 = tmpcr2;
4983
4984 /* Write to TIMx CCMR2 */
4985 TIMx->CCMR2 = tmpccmrx;
4986
4987 /* Set the Capture Compare Register value */
4988 TIMx->CCR4 = OC_Config->Pulse;
4989
4990 /* Write to TIMx CCER */
4991 TIMx->CCER = tmpccer;
4992 }
4993
4994 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
4995 TIM_SlaveConfigTypeDef * sSlaveConfig)
4996 {
4997 uint32_t tmpsmcr = 0U;
4998 uint32_t tmpccmr1 = 0U;
4999 uint32_t tmpccer = 0U;
5000
5001 /* Get the TIMx SMCR register value */
5002 tmpsmcr = htim->Instance->SMCR;
5003
5004 /* Reset the Trigger Selection Bits */
5005 tmpsmcr &= ~TIM_SMCR_TS;
5006 /* Set the Input Trigger source */
5007 tmpsmcr |= sSlaveConfig->InputTrigger;
5008
5009 /* Reset the slave mode Bits */
5010 tmpsmcr &= ~TIM_SMCR_SMS;
5011 /* Set the slave mode */
5012 tmpsmcr |= sSlaveConfig->SlaveMode;
5013
5014 /* Write to TIMx SMCR */
5015 htim->Instance->SMCR = tmpsmcr;
5016
5017 /* Configure the trigger prescaler, filter, and polarity */
5018 switch (sSlaveConfig->InputTrigger)
5019 {
5020 case TIM_TS_ETRF:
5021 {
5022 /* Check the parameters */
5023 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5024 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
5025 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5026 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5027 /* Configure the ETR Trigger source */
5028 TIM_ETR_SetConfig(htim->Instance,
5029 sSlaveConfig->TriggerPrescaler,
5030 sSlaveConfig->TriggerPolarity,
5031 sSlaveConfig->TriggerFilter);
5032 }
5033 break;
5034
5035 case TIM_TS_TI1F_ED:
5036 {
5037 /* Check the parameters */
5038 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5039 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5040
5041 /* Disable the Channel 1: Reset the CC1E Bit */
5042 tmpccer = htim->Instance->CCER;
5043 htim->Instance->CCER &= ~TIM_CCER_CC1E;
5044 tmpccmr1 = htim->Instance->CCMR1;
5045
5046 /* Set the filter */
5047 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5048 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
5049
5050 /* Write to TIMx CCMR1 and CCER registers */
5051 htim->Instance->CCMR1 = tmpccmr1;
5052 htim->Instance->CCER = tmpccer;
5053
5054 }
5055 break;
5056
5057 case TIM_TS_TI1FP1:
5058 {
5059 /* Check the parameters */
5060 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5061 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5062 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5063
5064 /* Configure TI1 Filter and Polarity */
5065 TIM_TI1_ConfigInputStage(htim->Instance,
5066 sSlaveConfig->TriggerPolarity,
5067 sSlaveConfig->TriggerFilter);
5068 }
5069 break;
5070
5071 case TIM_TS_TI2FP2:
5072 {
5073 /* Check the parameters */
5074 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5075 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
5076 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
5077
5078 /* Configure TI2 Filter and Polarity */
5079 TIM_TI2_ConfigInputStage(htim->Instance,
5080 sSlaveConfig->TriggerPolarity,
5081 sSlaveConfig->TriggerFilter);
5082 }
5083 break;
5084
5085 case TIM_TS_ITR0:
5086 {
5087 /* Check the parameter */
5088 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5089 }
5090 break;
5091
5092 case TIM_TS_ITR1:
5093 {
5094 /* Check the parameter */
5095 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5096 }
5097 break;
5098
5099 case TIM_TS_ITR2:
5100 {
5101 /* Check the parameter */
5102 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5103 }
5104 break;
5105
5106 case TIM_TS_ITR3:
5107 {
5108 /* Check the parameter */
5109 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5110 }
5111 break;
5112
5113 default:
5114 break;
5115 }
5116 }
5117
5118 /**
5119 * @brief Configure the TI1 as Input.
5120 * @param TIMx to select the TIM peripheral.
5121 * @param TIM_ICPolarity The Input Polarity.
5122 * This parameter can be one of the following values:
5123 * @arg TIM_ICPOLARITY_RISING
5124 * @arg TIM_ICPOLARITY_FALLING
5125 * @arg TIM_ICPOLARITY_BOTHEDGE
5126 * @param TIM_ICSelection specifies the input to be used.
5127 * This parameter can be one of the following values:
5128 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
5129 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
5130 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
5131 * @param TIM_ICFilter Specifies the Input Capture Filter.
5132 * This parameter must be a value between 0x00 and 0x0F.
5133 * @retval None
5134 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
5135 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
5136 * protected against un-initialized filter and polarity values.
5137 */
5138 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5139 uint32_t TIM_ICFilter)
5140 {
5141 uint32_t tmpccmr1 = 0U;
5142 uint32_t tmpccer = 0U;
5143
5144 /* Disable the Channel 1: Reset the CC1E Bit */
5145 TIMx->CCER &= ~TIM_CCER_CC1E;
5146 tmpccmr1 = TIMx->CCMR1;
5147 tmpccer = TIMx->CCER;
5148
5149 /* Select the Input */
5150 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
5151 {
5152 tmpccmr1 &= ~TIM_CCMR1_CC1S;
5153 tmpccmr1 |= TIM_ICSelection;
5154 }
5155 else
5156 {
5157 tmpccmr1 |= TIM_CCMR1_CC1S_0;
5158 }
5159
5160 /* Set the filter */
5161 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5162 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
5163
5164 /* Select the Polarity and set the CC1E Bit */
5165 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5166 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
5167
5168 /* Write to TIMx CCMR1 and CCER registers */
5169 TIMx->CCMR1 = tmpccmr1;
5170 TIMx->CCER = tmpccer;
5171 }
5172
5173 /**
5174 * @brief Configure the Polarity and Filter for TI1.
5175 * @param TIMx to select the TIM peripheral.
5176 * @param TIM_ICPolarity The Input Polarity.
5177 * This parameter can be one of the following values:
5178 * @arg TIM_ICPOLARITY_RISING
5179 * @arg TIM_ICPOLARITY_FALLING
5180 * @arg TIM_ICPOLARITY_BOTHEDGE
5181 * @param TIM_ICFilter Specifies the Input Capture Filter.
5182 * This parameter must be a value between 0x00 and 0x0F.
5183 * @retval None
5184 */
5185 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5186 {
5187 uint32_t tmpccmr1 = 0U;
5188 uint32_t tmpccer = 0U;
5189
5190 /* Disable the Channel 1: Reset the CC1E Bit */
5191 tmpccer = TIMx->CCER;
5192 TIMx->CCER &= ~TIM_CCER_CC1E;
5193 tmpccmr1 = TIMx->CCMR1;
5194
5195 /* Set the filter */
5196 tmpccmr1 &= ~TIM_CCMR1_IC1F;
5197 tmpccmr1 |= (TIM_ICFilter << 4U);
5198
5199 /* Select the Polarity and set the CC1E Bit */
5200 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
5201 tmpccer |= TIM_ICPolarity;
5202
5203 /* Write to TIMx CCMR1 and CCER registers */
5204 TIMx->CCMR1 = tmpccmr1;
5205 TIMx->CCER = tmpccer;
5206 }
5207
5208 /**
5209 * @brief Configure the TI2 as Input.
5210 * @param TIMx to select the TIM peripheral
5211 * @param TIM_ICPolarity The Input Polarity.
5212 * This parameter can be one of the following values:
5213 * @arg TIM_ICPOLARITY_RISING
5214 * @arg TIM_ICPOLARITY_FALLING
5215 * @arg TIM_ICPOLARITY_BOTHEDGE
5216 * @param TIM_ICSelection specifies the input to be used.
5217 * This parameter can be one of the following values:
5218 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
5219 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
5220 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
5221 * @param TIM_ICFilter Specifies the Input Capture Filter.
5222 * This parameter must be a value between 0x00 and 0x0F.
5223 * @retval None
5224 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
5225 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
5226 * protected against un-initialized filter and polarity values.
5227 */
5228 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5229 uint32_t TIM_ICFilter)
5230 {
5231 uint32_t tmpccmr1 = 0U;
5232 uint32_t tmpccer = 0U;
5233
5234 /* Disable the Channel 2: Reset the CC2E Bit */
5235 TIMx->CCER &= ~TIM_CCER_CC2E;
5236 tmpccmr1 = TIMx->CCMR1;
5237 tmpccer = TIMx->CCER;
5238
5239 /* Select the Input */
5240 tmpccmr1 &= ~TIM_CCMR1_CC2S;
5241 tmpccmr1 |= (TIM_ICSelection << 8U);
5242
5243 /* Set the filter */
5244 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5245 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
5246
5247 /* Select the Polarity and set the CC2E Bit */
5248 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5249 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
5250
5251 /* Write to TIMx CCMR1 and CCER registers */
5252 TIMx->CCMR1 = tmpccmr1 ;
5253 TIMx->CCER = tmpccer;
5254 }
5255
5256 /**
5257 * @brief Configure the Polarity and Filter for TI2.
5258 * @param TIMx to select the TIM peripheral.
5259 * @param TIM_ICPolarity The Input Polarity.
5260 * This parameter can be one of the following values:
5261 * @arg TIM_ICPOLARITY_RISING
5262 * @arg TIM_ICPOLARITY_FALLING
5263 * @arg TIM_ICPOLARITY_BOTHEDGE
5264 * @param TIM_ICFilter Specifies the Input Capture Filter.
5265 * This parameter must be a value between 0x00 and 0x0F.
5266 * @retval None
5267 */
5268 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
5269 {
5270 uint32_t tmpccmr1 = 0U;
5271 uint32_t tmpccer = 0U;
5272
5273 /* Disable the Channel 2: Reset the CC2E Bit */
5274 TIMx->CCER &= ~TIM_CCER_CC2E;
5275 tmpccmr1 = TIMx->CCMR1;
5276 tmpccer = TIMx->CCER;
5277
5278 /* Set the filter */
5279 tmpccmr1 &= ~TIM_CCMR1_IC2F;
5280 tmpccmr1 |= (TIM_ICFilter << 12U);
5281
5282 /* Select the Polarity and set the CC2E Bit */
5283 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
5284 tmpccer |= (TIM_ICPolarity << 4U);
5285
5286 /* Write to TIMx CCMR1 and CCER registers */
5287 TIMx->CCMR1 = tmpccmr1 ;
5288 TIMx->CCER = tmpccer;
5289 }
5290
5291 /**
5292 * @brief Configure the TI3 as Input.
5293 * @param TIMx to select the TIM peripheral
5294 * @param TIM_ICPolarity The Input Polarity.
5295 * This parameter can be one of the following values:
5296 * @arg TIM_ICPOLARITY_RISING
5297 * @arg TIM_ICPOLARITY_FALLING
5298 * @arg TIM_ICPOLARITY_BOTHEDGE
5299 * @param TIM_ICSelection specifies the input to be used.
5300 * This parameter can be one of the following values:
5301 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
5302 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
5303 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
5304 * @param TIM_ICFilter Specifies the Input Capture Filter.
5305 * This parameter must be a value between 0x00 and 0x0F.
5306 * @retval None
5307 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
5308 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5309 * protected against un-initialized filter and polarity values.
5310 */
5311 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5312 uint32_t TIM_ICFilter)
5313 {
5314 uint32_t tmpccmr2 = 0U;
5315 uint32_t tmpccer = 0U;
5316
5317 /* Disable the Channel 3: Reset the CC3E Bit */
5318 TIMx->CCER &= ~TIM_CCER_CC3E;
5319 tmpccmr2 = TIMx->CCMR2;
5320 tmpccer = TIMx->CCER;
5321
5322 /* Select the Input */
5323 tmpccmr2 &= ~TIM_CCMR2_CC3S;
5324 tmpccmr2 |= TIM_ICSelection;
5325
5326 /* Set the filter */
5327 tmpccmr2 &= ~TIM_CCMR2_IC3F;
5328 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
5329
5330 /* Select the Polarity and set the CC3E Bit */
5331 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
5332 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
5333
5334 /* Write to TIMx CCMR2 and CCER registers */
5335 TIMx->CCMR2 = tmpccmr2;
5336 TIMx->CCER = tmpccer;
5337 }
5338
5339 /**
5340 * @brief Configure the TI4 as Input.
5341 * @param TIMx to select the TIM peripheral
5342 * @param TIM_ICPolarity The Input Polarity.
5343 * This parameter can be one of the following values:
5344 * @arg TIM_ICPOLARITY_RISING
5345 * @arg TIM_ICPOLARITY_FALLING
5346 * @arg TIM_ICPOLARITY_BOTHEDGE
5347 * @param TIM_ICSelection specifies the input to be used.
5348 * This parameter can be one of the following values:
5349 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
5350 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
5351 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
5352 * @param TIM_ICFilter Specifies the Input Capture Filter.
5353 * This parameter must be a value between 0x00 and 0x0F.
5354 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
5355 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
5356 * protected against un-initialized filter and polarity values.
5357 * @retval None
5358 */
5359 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
5360 uint32_t TIM_ICFilter)
5361 {
5362 uint32_t tmpccmr2 = 0U;
5363 uint32_t tmpccer = 0U;
5364
5365 /* Disable the Channel 4: Reset the CC4E Bit */
5366 TIMx->CCER &= ~TIM_CCER_CC4E;
5367 tmpccmr2 = TIMx->CCMR2;
5368 tmpccer = TIMx->CCER;
5369
5370 /* Select the Input */
5371 tmpccmr2 &= ~TIM_CCMR2_CC4S;
5372 tmpccmr2 |= (TIM_ICSelection << 8U);
5373
5374 /* Set the filter */
5375 tmpccmr2 &= ~TIM_CCMR2_IC4F;
5376 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
5377
5378 /* Select the Polarity and set the CC4E Bit */
5379 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
5380 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
5381
5382 /* Write to TIMx CCMR2 and CCER registers */
5383 TIMx->CCMR2 = tmpccmr2;
5384 TIMx->CCER = tmpccer ;
5385 }
5386
5387 /**
5388 * @brief Selects the Input Trigger source
5389 * @param TIMx to select the TIM peripheral
5390 * @param InputTriggerSource The Input Trigger source.
5391 * This parameter can be one of the following values:
5392 * @arg TIM_TS_ITR0: Internal Trigger 0
5393 * @arg TIM_TS_ITR1: Internal Trigger 1
5394 * @arg TIM_TS_ITR2: Internal Trigger 2
5395 * @arg TIM_TS_ITR3: Internal Trigger 3
5396 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
5397 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
5398 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
5399 * @arg TIM_TS_ETRF: External Trigger input
5400 * @retval None
5401 */
5402 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
5403 {
5404 uint32_t tmpsmcr = 0U;
5405
5406 /* Get the TIMx SMCR register value */
5407 tmpsmcr = TIMx->SMCR;
5408 /* Reset the TS Bits */
5409 tmpsmcr &= ~TIM_SMCR_TS;
5410 /* Set the Input Trigger source and the slave mode*/
5411 tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
5412 /* Write to TIMx SMCR */
5413 TIMx->SMCR = tmpsmcr;
5414 }
5415 /**
5416 * @brief Configures the TIMx External Trigger (ETR).
5417 * @param TIMx to select the TIM peripheral
5418 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
5419 * This parameter can be one of the following values:
5420 * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF.
5421 * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2.
5422 * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4.
5423 * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8.
5424 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
5425 * This parameter can be one of the following values:
5426 * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active.
5427 * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active.
5428 * @param ExtTRGFilter External Trigger Filter.
5429 * This parameter must be a value between 0x00 and 0x0F
5430 * @retval None
5431 */
5432 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
5433 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
5434 {
5435 uint32_t tmpsmcr = 0U;
5436
5437 tmpsmcr = TIMx->SMCR;
5438
5439 /* Reset the ETR Bits */
5440 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5441
5442 /* Set the Prescaler, the Filter value and the Polarity */
5443 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
5444
5445 /* Write to TIMx SMCR */
5446 TIMx->SMCR = tmpsmcr;
5447 }
5448
5449 /**
5450 * @brief Enables or disables the TIM Capture Compare Channel x.
5451 * @param TIMx to select the TIM peripheral
5452 * @param Channel specifies the TIM Channel
5453 * This parameter can be one of the following values:
5454 * @arg TIM_CHANNEL_1: TIM Channel 1
5455 * @arg TIM_CHANNEL_2: TIM Channel 2
5456 * @arg TIM_CHANNEL_3: TIM Channel 3
5457 * @arg TIM_CHANNEL_4: TIM Channel 4
5458 * @param ChannelState specifies the TIM Channel CCxE bit new state.
5459 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
5460 * @retval None
5461 */
5462 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
5463 {
5464 uint32_t tmp = 0U;
5465
5466 /* Check the parameters */
5467 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
5468 assert_param(IS_TIM_CHANNELS(Channel));
5469
5470 tmp = TIM_CCER_CC1E << Channel;
5471
5472 /* Reset the CCxE Bit */
5473 TIMx->CCER &= ~tmp;
5474
5475 /* Set or reset the CCxE Bit */
5476 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
5477 }
5478
5479
5480 /**
5481 * @}
5482 */
5483
5484 #endif /* HAL_TIM_MODULE_ENABLED */
5485 /**
5486 * @}
5487 */
5488
5489 /**
5490 * @}
5491 */
5492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/