lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_dma.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_dma.c
   4   * @author  MCD Application Team
   5   * @brief   DMA LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35 #if defined(USE_FULL_LL_DRIVER)
  36
  37 /* Includes ------------------------------------------------------------------*/
  38 #include "stm32f3xx_ll_dma.h"
  39 #include "stm32f3xx_ll_bus.h"
  40 #ifdef  USE_FULL_ASSERT
  41 #include "stm32_assert.h"
  42 #else
  43 #define assert_param(expr) ((void)0U)
  44 #endif
  45
  46 /** @addtogroup STM32F3xx_LL_Driver
  47   * @{
  48   */
  49
  50 #if defined (DMA1) || defined (DMA2)
  51
  52 /** @defgroup DMA_LL DMA
  53   * @{
  54   */
  55
  56 /* Private types -------------------------------------------------------------*/
  57 /* Private variables ---------------------------------------------------------*/
  58 /* Private constants ---------------------------------------------------------*/
  59 /* Private macros ------------------------------------------------------------*/
  60 /** @addtogroup DMA_LL_Private_Macros
  61   * @{
  62   */
  63 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
  64                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
  65                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
  66
  67 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
  68                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
  69
  70 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
  71                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
  72
  73 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
  74                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
  75
  76 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
  77                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
  78                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
  79
  80 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
  81                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
  82                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
  83
  84 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
  85
  86
  87 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
  88                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
  89                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
  90                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
  91
  92 #if defined (DMA2)
  93 #if defined (DMA2_Channel6) && defined (DMA2_Channel7)
  94 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
  95                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
  96                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
  97                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
  98                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
  99                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 100                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 101                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
 102                                                          (((INSTANCE) == DMA2) && \
 103                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 104                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 105                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 106                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 107                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 108                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 109                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))))
 110 #else
 111 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
 112                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 113                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 114                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 115                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 116                                                           ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 117                                                           ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 118                                                           ((CHANNEL) == LL_DMA_CHANNEL_7))) || \
 119                                                          (((INSTANCE) == DMA2) && \
 120                                                          (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 121                                                           ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 122                                                           ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 123                                                           ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 124                                                           ((CHANNEL) == LL_DMA_CHANNEL_5))))
 125 #endif
 126 #else
 127 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
 128                                                             (((CHANNEL) == LL_DMA_CHANNEL_1)|| \
 129                                                             ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 130                                                             ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 131                                                             ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 132                                                             ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 133                                                             ((CHANNEL) == LL_DMA_CHANNEL_6) || \
 134                                                             ((CHANNEL) == LL_DMA_CHANNEL_7))))
 135 #endif
 136 /**
 137   * @}
 138   */
 139
 140 /* Private function prototypes -----------------------------------------------*/
 141
 142 /* Exported functions --------------------------------------------------------*/
 143 /** @addtogroup DMA_LL_Exported_Functions
 144   * @{
 145   */
 146
 147 /** @addtogroup DMA_LL_EF_Init
 148   * @{
 149   */
 150
 151 /**
 152   * @brief  De-initialize the DMA registers to their default reset values.
 153   * @param  DMAx DMAx Instance
 154   * @param  Channel This parameter can be one of the following values:
 155   *         @arg @ref LL_DMA_CHANNEL_1
 156   *         @arg @ref LL_DMA_CHANNEL_2
 157   *         @arg @ref LL_DMA_CHANNEL_3
 158   *         @arg @ref LL_DMA_CHANNEL_4
 159   *         @arg @ref LL_DMA_CHANNEL_5
 160   *         @arg @ref LL_DMA_CHANNEL_6
 161   *         @arg @ref LL_DMA_CHANNEL_7
 162   * @retval An ErrorStatus enumeration value:
 163   *          - SUCCESS: DMA registers are de-initialized
 164   *          - ERROR: DMA registers are not de-initialized
 165   */
 166 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
 167 {
 168   DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
 169   ErrorStatus status = SUCCESS;
 170
 171   /* Check the DMA Instance DMAx and Channel parameters*/
 172   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
 173
 174     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
 175
 176     /* Disable the selected DMAx_Channely */
 177     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
 178
 179     /* Reset DMAx_Channely control register */
 180     LL_DMA_WriteReg(tmp, CCR, 0U);
 181
 182     /* Reset DMAx_Channely remaining bytes register */
 183     LL_DMA_WriteReg(tmp, CNDTR, 0U);
 184
 185     /* Reset DMAx_Channely peripheral address register */
 186     LL_DMA_WriteReg(tmp, CPAR, 0U);
 187
 188     /* Reset DMAx_Channely memory address register */
 189     LL_DMA_WriteReg(tmp, CMAR, 0U);
 190
 191
 192     if (Channel == LL_DMA_CHANNEL_1)
 193     {
 194       /* Reset interrupt pending bits for DMAx Channel1 */
 195       LL_DMA_ClearFlag_GI1(DMAx);
 196     }
 197     else if (Channel == LL_DMA_CHANNEL_2)
 198     {
 199       /* Reset interrupt pending bits for DMAx Channel2 */
 200       LL_DMA_ClearFlag_GI2(DMAx);
 201     }
 202     else if (Channel == LL_DMA_CHANNEL_3)
 203     {
 204       /* Reset interrupt pending bits for DMAx Channel3 */
 205       LL_DMA_ClearFlag_GI3(DMAx);
 206     }
 207     else if (Channel == LL_DMA_CHANNEL_4)
 208     {
 209       /* Reset interrupt pending bits for DMAx Channel4 */
 210       LL_DMA_ClearFlag_GI4(DMAx);
 211     }
 212     else if (Channel == LL_DMA_CHANNEL_5)
 213     {
 214       /* Reset interrupt pending bits for DMAx Channel5 */
 215       LL_DMA_ClearFlag_GI5(DMAx);
 216     }
 217
 218     else if (Channel == LL_DMA_CHANNEL_6)
 219     {
 220       /* Reset interrupt pending bits for DMAx Channel6 */
 221       LL_DMA_ClearFlag_GI6(DMAx);
 222     }
 223     else if (Channel == LL_DMA_CHANNEL_7)
 224     {
 225       /* Reset interrupt pending bits for DMAx Channel7 */
 226       LL_DMA_ClearFlag_GI7(DMAx);
 227     }
 228     else
 229     {
 230       status = ERROR;
 231     }
 232
 233   return status;
 234 }
 235
 236 /**
 237   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
 238   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
 239   *         @arg @ref __LL_DMA_GET_INSTANCE
 240   *         @arg @ref __LL_DMA_GET_CHANNEL
 241   * @param  DMAx DMAx Instance
 242   * @param  Channel This parameter can be one of the following values:
 243   *         @arg @ref LL_DMA_CHANNEL_1
 244   *         @arg @ref LL_DMA_CHANNEL_2
 245   *         @arg @ref LL_DMA_CHANNEL_3
 246   *         @arg @ref LL_DMA_CHANNEL_4
 247   *         @arg @ref LL_DMA_CHANNEL_5
 248   *         @arg @ref LL_DMA_CHANNEL_6
 249   *         @arg @ref LL_DMA_CHANNEL_7
 250   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
 251   * @retval An ErrorStatus enumeration value:
 252   *          - SUCCESS: DMA registers are initialized
 253   *          - ERROR: Not applicable
 254   */
 255 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
 256 {
 257   /* Check the DMA Instance DMAx and Channel parameters*/
 258   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
 259
 260   /* Check the DMA parameters from DMA_InitStruct */
 261   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
 262   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
 263   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
 264   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
 265   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
 266   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
 267   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
 268   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
 269
 270   /*---------------------------- DMAx CCR Configuration ------------------------
 271    * Configure DMAx_Channely: data transfer direction, data transfer mode,
 272    *                          peripheral and memory increment mode,
 273    *                          data size alignment and  priority level with parameters :
 274    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
 275    * - Mode:           DMA_CCR_CIRC bit
 276    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
 277    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
 278    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
 279    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
 280    * - Priority:               DMA_CCR_PL[1:0] bits
 281    */
 282   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
 283                         DMA_InitStruct->Mode                   | \
 284                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
 285                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
 286                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
 287                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
 288                         DMA_InitStruct->Priority);
 289
 290   /*-------------------------- DMAx CMAR Configuration -------------------------
 291    * Configure the memory or destination base address with parameter :
 292    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
 293    */
 294   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
 295
 296   /*-------------------------- DMAx CPAR Configuration -------------------------
 297    * Configure the peripheral or source base address with parameter :
 298    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
 299    */
 300   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
 301
 302   /*--------------------------- DMAx CNDTR Configuration -----------------------
 303    * Configure the peripheral base address with parameter :
 304    * - NbData: DMA_CNDTR_NDT[15:0] bits
 305    */
 306   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
 307
 308
 309   return SUCCESS;
 310 }
 311
 312 /**
 313   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
 314   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
 315   * @retval None
 316   */
 317 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 318 {
 319   /* Set DMA_InitStruct fields to default values */
 320   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
 321   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
 322   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
 323   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
 324   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
 325   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
 326   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
 327   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
 328   DMA_InitStruct->NbData                 = 0x00000000U;
 329   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
 330 }
 331
 332 /**
 333   * @}
 334   */
 335
 336 /**
 337   * @}
 338   */
 339
 340 /**
 341   * @}
 342   */
 343
 344 #endif /* DMA1 || DMA2 */
 345
 346 /**
 347   * @}
 348   */
 349
 350 #endif /* USE_FULL_LL_DRIVER */
 351
 352 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/