lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_fmc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_fmc.c
   4   * @author  MCD Application Team
   5   * @brief   FMC Low Layer HAL module driver.
   6   *
   7   *          This file provides firmware functions to manage the following
   8   *          functionalities of the Flexible Memory Controller (FMC) peripheral memories:
   9   *           + Initialization/de-initialization functions
  10   *           + Peripheral Control functions
  11   *           + Peripheral State functions
  12   *
  13   @verbatim
  14   =============================================================================
  15                         ##### FMC peripheral features #####
  16   =============================================================================
  17     [..] The Flexible memory controller (FMC) includes following memory controllers:
  18          (+) The NOR/PSRAM memory controller
  19          (+) The PC Card memory controller
  20          (+) The NAND memory controller
  21
  22     [..] The FMC functional block makes the interface with synchronous and asynchronous static
  23          memories and 16-bit PC memory cards. Its main purposes are:
  24          (+) to translate AHB transactions into the appropriate external device protocol.
  25          (+) to meet the access time requirements of the external memory devices.
  26
  27     [..] All external memories share the addresses, data and control signals with the controller.
  28          Each external device is accessed by means of a unique Chip Select. The FMC performs
  29          only one access at a time to an external device.
  30          The main features of the FMC controller are the following:
  31           (+) Interface with static-memory mapped devices including:
  32              (++) Static random access memory (SRAM).
  33              (++) NOR Flash memory.
  34              (++) PSRAM (4 memory banks).
  35              (++) 16-bit PC Card compatible devices
  36              (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
  37                 data
  38           (+) Independent Chip Select control for each memory bank
  39           (+) Independent configuration for each memory bank
  40
  41   @endverbatim
  42   ******************************************************************************
  43   * @attention
  44   *
  45   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  46   *
  47   * Redistribution and use in source and binary forms, with or without modification,
  48   * are permitted provided that the following conditions are met:
  49   *   1. Redistributions of source code must retain the above copyright notice,
  50   *      this list of conditions and the following disclaimer.
  51   *   2. Redistributions in binary form must reproduce the above copyright notice,
  52   *      this list of conditions and the following disclaimer in the documentation
  53   *      and/or other materials provided with the distribution.
  54   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  55   *      may be used to endorse or promote products derived from this software
  56   *      without specific prior written permission.
  57   *
  58   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  59   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  60   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  61   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  62   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  63   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  64   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  65   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  66   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  67   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  68   *
  69   ******************************************************************************
  70   */
  71
  72 /* Includes ------------------------------------------------------------------*/
  73 #include "stm32f3xx_hal.h"
  74
  75 /** @addtogroup STM32F3xx_HAL_Driver
  76   * @{
  77   */
  78
  79 #if defined(FMC_BANK1)
  80
  81 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
  82
  83 /** @defgroup FMC_LL FMC Low Layer
  84   * @brief FMC driver modules
  85   * @{
  86   */
  87
  88 /* Private typedef -----------------------------------------------------------*/
  89 /* Private define ------------------------------------------------------------*/
  90 /** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants
  91   * @{
  92   */
  93
  94 /* ----------------------- FMC registers bit mask --------------------------- */
  95 /* --- PCR Register ---*/
  96 /* PCR register clear mask */
  97 #define PCR_CLEAR_MASK    ((uint32_t)(FMC_PCRx_PWAITEN | FMC_PCRx_PBKEN  | \
  98                                       FMC_PCRx_PTYP    | FMC_PCRx_PWID   | \
  99                                       FMC_PCRx_ECCEN   | FMC_PCRx_TCLR   | \
 100                                       FMC_PCRx_TAR     | FMC_PCRx_ECCPS))
 101
 102 /* --- PMEM Register ---*/
 103 /* PMEM register clear mask */
 104 #define PMEM_CLEAR_MASK   ((uint32_t)(FMC_PMEMx_MEMSETx  | FMC_PMEMx_MEMWAITx |\
 105                                       FMC_PMEMx_MEMHOLDx | FMC_PMEMx_MEMHIZx))
 106
 107 /* --- PATT Register ---*/
 108 /* PATT register clear mask */
 109 #define PATT_CLEAR_MASK   ((uint32_t)(FMC_PATTx_ATTSETx  | FMC_PATTx_ATTWAITx |\
 110                                       FMC_PATTx_ATTHOLDx | FMC_PATTx_ATTHIZx))
 111
 112 /* --- BCR Register ---*/
 113 /* BCR register clear mask */
 114 #define BCR_CLEAR_MASK                 ((uint32_t)(FMC_BCRx_MBKEN     | FMC_BCRx_MUXEN    |\
 115                                                    FMC_BCRx_MTYP      | FMC_BCRx_MWID     |\
 116                                                    FMC_BCRx_FACCEN    | FMC_BCRx_BURSTEN  |\
 117                                                    FMC_BCRx_WAITPOL   | FMC_BCRx_WRAPMOD  |\
 118                                                    FMC_BCRx_WAITCFG   | FMC_BCRx_WREN     |\
 119                                                    FMC_BCRx_WAITEN    | FMC_BCRx_EXTMOD   |\
 120                                                    FMC_BCRx_ASYNCWAIT | FMC_BCRx_CBURSTRW |\
 121                                                    FMC_BCR1_CCLKEN))
 122
 123 /* --- BTR Register ---*/
 124 /* BTR register clear mask */
 125 #define BTR_CLEAR_MASK                 ((uint32_t)(FMC_BTRx_ADDSET | FMC_BTRx_ADDHLD  |\
 126                                                    FMC_BTRx_DATAST | FMC_BTRx_BUSTURN |\
 127                                                    FMC_BTRx_CLKDIV | FMC_BTRx_DATLAT  |\
 128                                                    FMC_BTRx_ACCMOD))
 129
 130 /* --- BWTR Register ---*/
 131 /* BWTR register clear mask */
 132 #define BWTR_CLEAR_MASK                ((uint32_t)(FMC_BWTRx_ADDSET | FMC_BWTRx_ADDHLD |\
 133                                                    FMC_BWTRx_DATAST | FMC_BWTRx_ACCMOD))
 134
 135 /* --- PIO4 Register ---*/
 136 /* PIO4 register clear mask */
 137 #define PIO4_CLEAR_MASK   ((uint32_t)(FMC_PIO4_IOSET4    | FMC_PIO4_IOWAIT4   | \
 138                                       FMC_PIO4_IOHOLD4   | FMC_PIO4_IOHIZ4))
 139 /**
 140   * @}
 141   */
 142
 143 /* Private macro -------------------------------------------------------------*/
 144 /** @defgroup FMC_LL_Private_Macros FMC Low Layer Private Macros
 145   * @{
 146   */
 147
 148 /**
 149   * @}
 150   */
 151
 152 /* Private variables ---------------------------------------------------------*/
 153 /* Private function prototypes -----------------------------------------------*/
 154 /* Exported functions --------------------------------------------------------*/
 155
 156 /** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions
 157   * @{
 158   */
 159
 160 /** @defgroup FMC_NORSRAM FMC NORSRAM Controller functions
 161   * @brief    NORSRAM Controller functions
 162   *
 163   @verbatim
 164   ==============================================================================
 165                    ##### How to use NORSRAM device driver #####
 166   ==============================================================================
 167
 168   [..]
 169     This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
 170     to run the NORSRAM external devices.
 171
 172     (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
 173     (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
 174     (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
 175     (+) FMC NORSRAM bank extended timing configuration using the function
 176         FMC_NORSRAM_Extended_Timing_Init()
 177     (+) FMC NORSRAM bank enable/disable write operation using the functions
 178         FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
 179
 180
 181 @endverbatim
 182   * @{
 183   */
 184
 185 /** @defgroup FMC_NORSRAM_Group1 Initialization/de-initialization functions
 186   * @brief    Initialization and Configuration functions
 187   *
 188   @verbatim
 189   ==============================================================================
 190               ##### Initialization and de_initialization functions #####
 191   ==============================================================================
 192   [..]
 193     This section provides functions allowing to:
 194     (+) Initialize and configure the FMC NORSRAM interface
 195     (+) De-initialize the FMC NORSRAM interface
 196     (+) Configure the FMC clock and associated GPIOs
 197
 198 @endverbatim
 199   * @{
 200   */
 201
 202 /**
 203   * @brief  Initialize the FMC_NORSRAM device according to the specified
 204   *         control parameters in the FMC_NORSRAM_InitTypeDef
 205   * @param  Device Pointer to NORSRAM device instance
 206   * @param  Init Pointer to NORSRAM Initialization structure
 207   * @retval HAL status
 208   */
 209 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init)
 210 {
 211   /* Check the parameters */
 212   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 213   assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
 214   assert_param(IS_FMC_MUX(Init->DataAddressMux));
 215   assert_param(IS_FMC_MEMORY(Init->MemoryType));
 216   assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
 217   assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
 218   assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
 219   assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
 220   assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
 221   assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
 222   assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
 223   assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
 224   assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
 225   assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
 226   assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
 227
 228   /* Disable NORSRAM Device */
 229   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
 230
 231   /* Set NORSRAM device control parameters */
 232   if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
 233   {
 234     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_ENABLE
 235                | Init->DataAddressMux
 236                | Init->MemoryType
 237                | Init->MemoryDataWidth
 238                | Init->BurstAccessMode
 239                | Init->WaitSignalPolarity
 240                | Init->WrapMode
 241                | Init->WaitSignalActive
 242                | Init->WriteOperation
 243                | Init->WaitSignal
 244                | Init->ExtendedMode
 245                | Init->AsynchronousWait
 246                | Init->WriteBurst
 247                | Init->ContinuousClock
 248                                                                      )
 249               );
 250   }
 251   else
 252   {
 253     MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FMC_NORSRAM_FLASH_ACCESS_DISABLE
 254                | Init->DataAddressMux
 255                | Init->MemoryType
 256                | Init->MemoryDataWidth
 257                | Init->BurstAccessMode
 258                | Init->WaitSignalPolarity
 259                | Init->WrapMode
 260                | Init->WaitSignalActive
 261                | Init->WriteOperation
 262                | Init->WaitSignal
 263                | Init->ExtendedMode
 264                | Init->AsynchronousWait
 265                | Init->WriteBurst
 266                | Init->ContinuousClock
 267                                                                      )
 268               );
 269   }
 270
 271   /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
 272   if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
 273   {
 274     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
 275   }
 276
 277   return HAL_OK;
 278 }
 279
 280
 281 /**
 282   * @brief  DeInitialize the FMC_NORSRAM peripheral
 283   * @param  Device Pointer to NORSRAM device instance
 284   * @param  ExDevice Pointer to NORSRAM extended mode device instance
 285   * @param  Bank NORSRAM bank number
 286   * @retval HAL status
 287   */
 288 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
 289 {
 290   /* Check the parameters */
 291   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 292   assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
 293   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 294
 295   /* Disable the FMC_NORSRAM device */
 296   __FMC_NORSRAM_DISABLE(Device, Bank);
 297
 298   /* De-initialize the FMC_NORSRAM device */
 299   /* FMC_NORSRAM_BANK1 */
 300   if (Bank == FMC_NORSRAM_BANK1)
 301   {
 302     Device->BTCR[Bank] = 0x000030DB;
 303   }
 304   /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
 305   else
 306   {
 307     Device->BTCR[Bank] = 0x000030D2;
 308   }
 309
 310   Device->BTCR[Bank + 1] = 0x0FFFFFFF;
 311   ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
 312
 313   return HAL_OK;
 314 }
 315
 316
 317 /**
 318   * @brief  Initialize the FMC_NORSRAM Timing according to the specified
 319   *         parameters in the FMC_NORSRAM_TimingTypeDef
 320   * @param  Device Pointer to NORSRAM device instance
 321   * @param  Timing Pointer to NORSRAM Timing structure
 322   * @param  Bank NORSRAM bank number
 323   * @retval HAL status
 324   */
 325 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
 326 {
 327   uint32_t tmpr = 0;
 328
 329   /* Check the parameters */
 330   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 331   assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 332   assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 333   assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 334   assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
 335   assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
 336   assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
 337   assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 338   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 339
 340   /* Set FMC_NORSRAM device timing parameters */
 341   MODIFY_REG(Device->BTCR[Bank + 1],                                                    \
 342              BTR_CLEAR_MASK,                                                                     \
 343              (uint32_t)(Timing->AddressSetupTime                                               | \
 344                         ((Timing->AddressHoldTime)        << POSITION_VAL(FMC_BTRx_ADDHLD))        | \
 345                         ((Timing->DataSetupTime)          << POSITION_VAL(FMC_BTRx_DATAST))        | \
 346                         ((Timing->BusTurnAroundDuration)  << POSITION_VAL(FMC_BTRx_BUSTURN))       | \
 347                         (((Timing->CLKDivision) - 1)        << POSITION_VAL(FMC_BTRx_CLKDIV))        | \
 348                         (((Timing->DataLatency) - 2)        << POSITION_VAL(FMC_BTRx_DATLAT))        | \
 349                         (Timing->AccessMode)));
 350
 351   /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
 352   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
 353   {
 354     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << POSITION_VAL(FMC_BTRx_CLKDIV)));
 355     tmpr |= (uint32_t)(((Timing->CLKDivision) - 1) << POSITION_VAL(FMC_BTRx_CLKDIV));
 356     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1], FMC_BTRx_CLKDIV, tmpr);
 357   }
 358
 359   return HAL_OK;
 360 }
 361
 362 /**
 363   * @brief  Initialize the FMC_NORSRAM Extended mode Timing according to the specified
 364   *         parameters in the FMC_NORSRAM_TimingTypeDef
 365   * @param  Device Pointer to NORSRAM device instance
 366   * @param  Timing Pointer to NORSRAM Timing structure
 367   * @param  Bank NORSRAM bank number
 368   * @param  ExtendedMode FMC Extended Mode
 369   *          This parameter can be one of the following values:
 370   *            @arg FMC_EXTENDED_MODE_DISABLE
 371   *            @arg FMC_EXTENDED_MODE_ENABLE
 372   * @retval HAL status
 373   */
 374 HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
 375 {
 376   /* Check the parameters */
 377   assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
 378
 379   /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 380   if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
 381   {
 382     /* Check the parameters */
 383     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
 384     assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
 385     assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
 386     assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
 387     assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
 388     assert_param(IS_FMC_NORSRAM_BANK(Bank));
 389
 390     /* Set NORSRAM device timing register for write configuration, if extended mode is used */
 391     MODIFY_REG(Device->BWTR[Bank],                                                  \
 392                BWTR_CLEAR_MASK,                                                              \
 393                (uint32_t)(Timing->AddressSetupTime                                         | \
 394                           ((Timing->AddressHoldTime)        << POSITION_VAL(FMC_BWTRx_ADDHLD)) | \
 395                           ((Timing->DataSetupTime)          << POSITION_VAL(FMC_BWTRx_DATAST)) | \
 396                           (Timing->AccessMode)));
 397   }
 398   else
 399   {
 400     Device->BWTR[Bank] = 0x0FFFFFFF;
 401   }
 402
 403   return HAL_OK;
 404 }
 405
 406
 407 /**
 408   * @}
 409   */
 410
 411
 412 /** @defgroup FMC_NORSRAM_Group2 Control functions
 413  *  @brief   management functions
 414  *
 415 @verbatim
 416   ==============================================================================
 417                       ##### FMC_NORSRAM Control functions #####
 418   ==============================================================================
 419   [..]
 420     This subsection provides a set of functions allowing to control dynamically
 421     the FMC NORSRAM interface.
 422
 423 @endverbatim
 424   * @{
 425   */
 426
 427 /**
 428   * @brief  Enables dynamically FMC_NORSRAM write operation.
 429   * @param  Device Pointer to NORSRAM device instance
 430   * @param  Bank NORSRAM bank number
 431   * @retval HAL status
 432   */
 433 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 434 {
 435   /* Check the parameters */
 436   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 437   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 438
 439   /* Enable write operation */
 440   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
 441
 442   return HAL_OK;
 443 }
 444
 445 /**
 446   * @brief  Disables dynamically FMC_NORSRAM write operation.
 447   * @param  Device Pointer to NORSRAM device instance
 448   * @param  Bank NORSRAM bank number
 449   * @retval HAL status
 450   */
 451 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
 452 {
 453   /* Check the parameters */
 454   assert_param(IS_FMC_NORSRAM_DEVICE(Device));
 455   assert_param(IS_FMC_NORSRAM_BANK(Bank));
 456
 457   /* Disable write operation */
 458   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
 459
 460   return HAL_OK;
 461 }
 462
 463 /**
 464   * @}
 465   */
 466
 467 /**
 468   * @}
 469   */
 470 /** @defgroup FMC_NAND FMC NAND Controller functions
 471   * @brief    NAND Controller functions
 472   *
 473   @verbatim
 474   ==============================================================================
 475                     ##### How to use NAND device driver #####
 476   ==============================================================================
 477   [..]
 478     This driver contains a set of APIs to interface with the FMC NAND banks in order
 479     to run the NAND external devices.
 480
 481     (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
 482     (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
 483     (+) FMC NAND bank common space timing configuration using the function
 484         FMC_NAND_CommonSpace_Timing_Init()
 485     (+) FMC NAND bank attribute space timing configuration using the function
 486         FMC_NAND_AttributeSpace_Timing_Init()
 487     (+) FMC NAND bank enable/disable ECC correction feature using the functions
 488         FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
 489     (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
 490
 491 @endverbatim
 492   * @{
 493   */
 494
 495 /** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 496  *  @brief    Initialization and Configuration functions
 497  *
 498 @verbatim
 499   ==============================================================================
 500               ##### Initialization and de_initialization functions #####
 501   ==============================================================================
 502   [..]
 503     This section provides functions allowing to:
 504     (+) Initialize and configure the FMC NAND interface
 505     (+) De-initialize the FMC NAND interface
 506     (+) Configure the FMC clock and associated GPIOs
 507
 508 @endverbatim
 509   * @{
 510   */
 511
 512 /**
 513   * @brief  Initializes the FMC_NAND device according to the specified
 514   *         control parameters in the FMC_NAND_HandleTypeDef
 515   * @param  Device Pointer to NAND device instance
 516   * @param  Init Pointer to NAND Initialization structure
 517   * @retval HAL status
 518   */
 519 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
 520 {
 521   /* Check the parameters */
 522   assert_param(IS_FMC_NAND_DEVICE(Device));
 523   assert_param(IS_FMC_NAND_BANK(Init->NandBank));
 524   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 525   assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
 526   assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
 527   assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
 528   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 529   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 530
 531   /* Set NAND device control parameters */
 532   if (Init->NandBank == FMC_NAND_BANK2)
 533   {
 534     /* NAND bank 2 registers configuration */
 535     MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature                                                       |
 536                                               FMC_PCR_MEMORY_TYPE_NAND                                         |
 537                                               Init->MemoryDataWidth                                                   |
 538                                               Init->EccComputation                                                    |
 539                                               Init->ECCPageSize                                                       |
 540                                               ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
 541                                               ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
 542   }
 543   else
 544   {
 545     /* NAND bank 3 registers configuration */
 546     MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature                                                       |
 547                                               FMC_PCR_MEMORY_TYPE_NAND                                         |
 548                                               Init->MemoryDataWidth                                                   |
 549                                               Init->EccComputation                                                    |
 550                                               Init->ECCPageSize                                                       |
 551                                               ((Init->TCLRSetupTime) << POSITION_VAL(FMC_PCRx_TCLR)) |
 552                                               ((Init->TARSetupTime) << POSITION_VAL(FMC_PCRx_TAR))));
 553   }
 554
 555   return HAL_OK;
 556
 557 }
 558
 559 /**
 560   * @brief  Initializes the FMC_NAND Common space Timing according to the specified
 561   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 562   * @param  Device Pointer to NAND device instance
 563   * @param  Timing Pointer to NAND timing structure
 564   * @param  Bank NAND bank number
 565   * @retval HAL status
 566   */
 567 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 568 {
 569   /* Check the parameters */
 570   assert_param(IS_FMC_NAND_DEVICE(Device));
 571   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 572   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 573   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 574   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 575   assert_param(IS_FMC_NAND_BANK(Bank));
 576
 577   /* Set FMC_NAND device timing parameters */
 578   if (Bank == FMC_NAND_BANK2)
 579   {
 580     /* NAND bank 2 registers configuration */
 581     MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime                      | \
 582                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx))      | \
 583                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx))      | \
 584                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
 585   }
 586   else
 587   {
 588     /* NAND bank 3 registers configuration */
 589     MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime                      | \
 590                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx))      | \
 591                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx))      | \
 592                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
 593   }
 594
 595   return HAL_OK;
 596 }
 597
 598 /**
 599   * @brief  Initializes the FMC_NAND Attribute space Timing according to the specified
 600   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 601   * @param  Device Pointer to NAND device instance
 602   * @param  Timing Pointer to NAND timing structure
 603   * @param  Bank NAND bank number
 604   * @retval HAL status
 605   */
 606 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
 607 {
 608   /* Check the parameters */
 609   assert_param(IS_FMC_NAND_DEVICE(Device));
 610   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 611   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 612   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 613   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 614   assert_param(IS_FMC_NAND_BANK(Bank));
 615
 616   /* Set FMC_NAND device timing parameters */
 617   if (Bank == FMC_NAND_BANK2)
 618   {
 619     /* NAND bank 2 registers configuration */
 620     MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime                       | \
 621                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx))       | \
 622                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx))       | \
 623                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
 624   }
 625   else
 626   {
 627     /* NAND bank 3 registers configuration */
 628     MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime                       | \
 629                                                 ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx))       | \
 630                                                 ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx))       | \
 631                                                 ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
 632   }
 633
 634   return HAL_OK;
 635 }
 636
 637
 638 /**
 639   * @brief  DeInitialize the FMC_NAND device
 640   * @param  Device Pointer to NAND device instance
 641   * @param  Bank NAND bank number
 642   * @retval HAL status
 643   */
 644 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
 645 {
 646   /* Check the parameters */
 647   assert_param(IS_FMC_NAND_DEVICE(Device));
 648   assert_param(IS_FMC_NAND_BANK(Bank));
 649
 650   /* Disable the NAND Bank */
 651   __FMC_NAND_DISABLE(Device, Bank);
 652
 653   /* De-initialize the NAND Bank */
 654   if (Bank == FMC_NAND_BANK2)
 655   {
 656     /* Set the FMC_NAND_BANK2 registers to their reset values */
 657     WRITE_REG(Device->PCR2,  0x00000018);
 658     WRITE_REG(Device->SR2,   0x00000040);
 659     WRITE_REG(Device->PMEM2, 0xFCFCFCFC);
 660     WRITE_REG(Device->PATT2, 0xFCFCFCFC);
 661   }
 662   /* FMC_Bank3_NAND */
 663   else
 664   {
 665     /* Set the FMC_NAND_BANK3 registers to their reset values */
 666     WRITE_REG(Device->PCR3,  0x00000018);
 667     WRITE_REG(Device->SR3,   0x00000040);
 668     WRITE_REG(Device->PMEM3, 0xFCFCFCFC);
 669     WRITE_REG(Device->PATT3, 0xFCFCFCFC);
 670   }
 671
 672   return HAL_OK;
 673 }
 674
 675 /**
 676   * @}
 677   */
 678
 679
 680 /** @defgroup FMC_NAND_Exported_Functions_Group2 Peripheral Control functions
 681  *  @brief   management functions
 682  *
 683 @verbatim
 684   ==============================================================================
 685                        ##### FMC_NAND Control functions #####
 686   ==============================================================================
 687   [..]
 688     This subsection provides a set of functions allowing to control dynamically
 689     the FMC NAND interface.
 690
 691 @endverbatim
 692   * @{
 693   */
 694
 695
 696 /**
 697   * @brief  Enables dynamically FMC_NAND ECC feature.
 698   * @param  Device Pointer to NAND device instance
 699   * @param  Bank NAND bank number
 700   * @retval HAL status
 701   */
 702 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 703 {
 704   /* Check the parameters */
 705   assert_param(IS_FMC_NAND_DEVICE(Device));
 706   assert_param(IS_FMC_NAND_BANK(Bank));
 707
 708   /* Enable ECC feature */
 709   if (Bank == FMC_NAND_BANK2)
 710   {
 711     SET_BIT(Device->PCR2, FMC_PCRx_ECCEN);
 712   }
 713   else
 714   {
 715     SET_BIT(Device->PCR3, FMC_PCRx_ECCEN);
 716   }
 717
 718   return HAL_OK;
 719 }
 720
 721
 722 /**
 723   * @brief  Disables dynamically FMC_NAND ECC feature.
 724   * @param  Device Pointer to NAND device instance
 725   * @param  Bank NAND bank number
 726   * @retval HAL status
 727   */
 728 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
 729 {
 730   /* Check the parameters */
 731   assert_param(IS_FMC_NAND_DEVICE(Device));
 732   assert_param(IS_FMC_NAND_BANK(Bank));
 733
 734   /* Disable ECC feature */
 735   if (Bank == FMC_NAND_BANK2)
 736   {
 737     CLEAR_BIT(Device->PCR2, FMC_PCRx_ECCEN);
 738   }
 739   else
 740   {
 741     CLEAR_BIT(Device->PCR3, FMC_PCRx_ECCEN);
 742   }
 743
 744   return HAL_OK;
 745 }
 746
 747 /**
 748   * @brief  Disables dynamically FMC_NAND ECC feature.
 749   * @param  Device Pointer to NAND device instance
 750   * @param  ECCval Pointer to ECC value
 751   * @param  Bank NAND bank number
 752   * @param  Timeout Timeout wait value
 753   * @retval HAL status
 754   */
 755 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
 756 {
 757   uint32_t tickstart = 0;
 758
 759   /* Check the parameters */
 760   assert_param(IS_FMC_NAND_DEVICE(Device));
 761   assert_param(IS_FMC_NAND_BANK(Bank));
 762
 763   /* Get tick */
 764   tickstart = HAL_GetTick();
 765
 766   /* Wait until FIFO is empty */
 767   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
 768   {
 769     /* Check for the Timeout */
 770     if (Timeout != HAL_MAX_DELAY)
 771     {
 772       if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
 773       {
 774         return HAL_TIMEOUT;
 775       }
 776     }
 777   }
 778
 779   if (Bank == FMC_NAND_BANK2)
 780   {
 781     /* Get the ECCR2 register value */
 782     *ECCval = (uint32_t)Device->ECCR2;
 783   }
 784   else
 785   {
 786     /* Get the ECCR3 register value */
 787     *ECCval = (uint32_t)Device->ECCR3;
 788   }
 789
 790   return HAL_OK;
 791 }
 792
 793 /**
 794   * @}
 795   */
 796
 797 /**
 798   * @}
 799   */
 800
 801 /** @defgroup FMC_PCCARD FMC PCCARD Controller functions
 802   * @brief    PCCARD Controller functions
 803   *
 804   @verbatim
 805   ==============================================================================
 806                     ##### How to use PCCARD device driver #####
 807   ==============================================================================
 808   [..]
 809     This driver contains a set of APIs to interface with the FMC PCCARD bank in order
 810     to run the PCCARD/compact flash external devices.
 811
 812     (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
 813     (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
 814     (+) FMC PCCARD bank common space timing configuration using the function
 815         FMC_PCCARD_CommonSpace_Timing_Init()
 816     (+) FMC PCCARD bank attribute space timing configuration using the function
 817         FMC_PCCARD_AttributeSpace_Timing_Init()
 818     (+) FMC PCCARD bank IO space timing configuration using the function
 819         FMC_PCCARD_IOSpace_Timing_Init()
 820
 821
 822 @endverbatim
 823   * @{
 824   */
 825
 826 /** @defgroup FMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
 827  *  @brief    Initialization and Configuration functions
 828  *
 829 @verbatim
 830   ==============================================================================
 831               ##### Initialization and de_initialization functions #####
 832   ==============================================================================
 833   [..]
 834     This section provides functions allowing to:
 835     (+) Initialize and configure the FMC PCCARD interface
 836     (+) De-initialize the FMC PCCARD interface
 837     (+) Configure the FMC clock and associated GPIOs
 838
 839 @endverbatim
 840   * @{
 841   */
 842
 843 /**
 844   * @brief  Initializes the FMC_PCCARD device according to the specified
 845   *         control parameters in the FMC_PCCARD_HandleTypeDef
 846   * @param  Device Pointer to PCCARD device instance
 847   * @param  Init Pointer to PCCARD Initialization structure
 848   * @retval HAL status
 849   */
 850 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
 851 {
 852   /* Check the parameters */
 853   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 854   assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
 855   assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
 856   assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
 857
 858   /* Set FMC_PCCARD device control parameters */
 859   MODIFY_REG(Device->PCR4,
 860              (FMC_PCRx_PTYP | FMC_PCRx_PWAITEN |  FMC_PCRx_PWID  |
 861               FMC_PCRx_TCLR | FMC_PCRx_TAR),
 862              (FMC_PCR_MEMORY_TYPE_PCCARD                                                                     |
 863               Init->Waitfeature                                                                                     |
 864               FMC_NAND_PCC_MEM_BUS_WIDTH_16                                                                  |
 865               (Init->TCLRSetupTime << POSITION_VAL(FMC_PCRx_TCLR))                                 |
 866               (Init->TARSetupTime << POSITION_VAL(FMC_PCRx_TAR))));
 867
 868   return HAL_OK;
 869
 870 }
 871
 872 /**
 873   * @brief  Initializes the FMC_PCCARD Common space Timing according to the specified
 874   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 875   * @param  Device Pointer to PCCARD device instance
 876   * @param  Timing Pointer to PCCARD timing structure
 877   * @retval HAL status
 878   */
 879 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 880 {
 881   /* Check the parameters */
 882   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 883   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 884   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 885   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 886   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 887
 888   /* Set PCCARD timing parameters */
 889   MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
 890              (Timing->SetupTime                                                     |
 891               ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PMEMx_MEMWAITx))  |
 892               ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHOLDx))  |
 893               ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PMEMx_MEMHIZx))));
 894
 895   return HAL_OK;
 896 }
 897
 898 /**
 899   * @brief  Initializes the FMC_PCCARD Attribute space Timing according to the specified
 900   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 901   * @param  Device Pointer to PCCARD device instance
 902   * @param  Timing Pointer to PCCARD timing structure
 903   * @retval HAL status
 904   */
 905 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 906 {
 907   /* Check the parameters */
 908   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 909   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 910   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 911   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 912   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 913
 914   /* Set PCCARD timing parameters */
 915   MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK,                          \
 916              (Timing->SetupTime                                              | \
 917               ((Timing->WaitSetupTime) << POSITION_VAL(FMC_PATTx_ATTWAITx))  | \
 918               ((Timing->HoldSetupTime) << POSITION_VAL(FMC_PATTx_ATTHOLDx))   | \
 919               ((Timing->HiZSetupTime) << POSITION_VAL(FMC_PATTx_ATTHIZx))));
 920
 921   return HAL_OK;
 922 }
 923
 924 /**
 925   * @brief  Initializes the FMC_PCCARD IO space Timing according to the specified
 926   *         parameters in the FMC_NAND_PCC_TimingTypeDef
 927   * @param  Device Pointer to PCCARD device instance
 928   * @param  Timing Pointer to PCCARD timing structure
 929   * @retval HAL status
 930   */
 931 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
 932 {
 933   /* Check the parameters */
 934   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 935   assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
 936   assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
 937   assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
 938   assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
 939
 940   /* Set FMC_PCCARD device timing parameters */
 941   MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK,                         \
 942              (Timing->SetupTime                                            | \
 943               (Timing->WaitSetupTime   << POSITION_VAL(FMC_PIO4_IOWAIT4)) | \
 944               (Timing->HoldSetupTime   << POSITION_VAL(FMC_PIO4_IOHOLD4)) | \
 945               (Timing->HiZSetupTime    << POSITION_VAL(FMC_PIO4_IOHIZ4))));
 946
 947   return HAL_OK;
 948 }
 949
 950 /**
 951   * @brief  DeInitialize the FMC_PCCARD device
 952   * @param  Device Pointer to PCCARD device instance
 953   * @retval HAL status
 954   */
 955 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
 956 {
 957   /* Check the parameters */
 958   assert_param(IS_FMC_PCCARD_DEVICE(Device));
 959
 960   /* Disable the FMC_PCCARD device */
 961   __FMC_PCCARD_DISABLE(Device);
 962
 963   /* De-initialize the FMC_PCCARD device */
 964   WRITE_REG(Device->PCR4,  0x00000018);
 965   WRITE_REG(Device->SR4,   0x00000040);
 966   WRITE_REG(Device->PMEM4, 0xFCFCFCFC);
 967   WRITE_REG(Device->PATT4, 0xFCFCFCFC);
 968   WRITE_REG(Device->PIO4,  0xFCFCFCFC);
 969
 970   return HAL_OK;
 971 }
 972
 973 /**
 974   * @}
 975   */
 976
 977 /**
 978   * @}
 979   */
 980
 981 /**
 982   * @}
 983   */
 984
 985 /**
 986   * @}
 987   */
 988
 989 #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */
 990
 991 #endif /* FMC_BANK1 */
 992
 993 /**
 994   * @}
 995   */
 996
 997 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/