lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_spi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_spi.c
   4   * @author  MCD Application Team
   5   * @brief   SPI LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35 #if defined(USE_FULL_LL_DRIVER)
  36
  37 /* Includes ------------------------------------------------------------------*/
  38 #include "stm32f3xx_ll_spi.h"
  39 #include "stm32f3xx_ll_bus.h"
  40 #include "stm32f3xx_ll_rcc.h"
  41
  42 #ifdef  USE_FULL_ASSERT
  43 #include "stm32_assert.h"
  44 #else
  45 #define assert_param(expr) ((void)0U)
  46 #endif
  47
  48 /** @addtogroup STM32F3xx_LL_Driver
  49   * @{
  50   */
  51
  52 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
  53
  54 /** @addtogroup SPI_LL
  55   * @{
  56   */
  57
  58 /* Private types -------------------------------------------------------------*/
  59 /* Private variables ---------------------------------------------------------*/
  60
  61 /* Private constants ---------------------------------------------------------*/
  62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  63   * @{
  64   */
  65 /* SPI registers Masks */
  66 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
  67                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
  68                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
  69                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
  70                                             SPI_CR1_BIDIMODE)
  71 /**
  72   * @}
  73   */
  74
  75 /* Private macros ------------------------------------------------------------*/
  76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  77   * @{
  78   */
  79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)    \
  80                                               || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
  81                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  82                                               || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  83
  84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  85                                 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  86
  87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)  \
  88                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
  89                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
  90                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
  91                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
  92                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
  93                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
  94                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
  95                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
  96                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
  97                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
  98                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
  99                                      || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
 100
 101 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
 102                                     || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
 103
 104 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
 105                                  || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
 106
 107 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
 108                                || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
 109                                || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
 110
 111 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)   \
 112                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
 113                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
 114                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
 115                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
 116                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
 117                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
 118                                     || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
 119
 120 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
 121                                     || ((__VALUE__) == LL_SPI_MSB_FIRST))
 122
 123 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
 124                                           || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
 125
 126 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
 127
 128 /**
 129   * @}
 130   */
 131
 132 /* Private function prototypes -----------------------------------------------*/
 133
 134 /* Exported functions --------------------------------------------------------*/
 135 /** @addtogroup SPI_LL_Exported_Functions
 136   * @{
 137   */
 138
 139 /** @addtogroup SPI_LL_EF_Init
 140   * @{
 141   */
 142
 143 /**
 144   * @brief  De-initialize the SPI registers to their default reset values.
 145   * @param  SPIx SPI Instance
 146   * @retval An ErrorStatus enumeration value:
 147   *          - SUCCESS: SPI registers are de-initialized
 148   *          - ERROR: SPI registers are not de-initialized
 149   */
 150 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
 151 {
 152   ErrorStatus status = ERROR;
 153
 154   /* Check the parameters */
 155   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 156
 157 #if defined(SPI1)
 158   if (SPIx == SPI1)
 159   {
 160     /* Force reset of SPI clock */
 161     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
 162
 163     /* Release reset of SPI clock */
 164     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
 165
 166     status = SUCCESS;
 167   }
 168 #endif /* SPI1 */
 169 #if defined(SPI2)
 170   if (SPIx == SPI2)
 171   {
 172     /* Force reset of SPI clock */
 173     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
 174
 175     /* Release reset of SPI clock */
 176     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
 177
 178     status = SUCCESS;
 179   }
 180 #endif /* SPI2 */
 181 #if defined(SPI3)
 182   if (SPIx == SPI3)
 183   {
 184     /* Force reset of SPI clock */
 185     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
 186
 187     /* Release reset of SPI clock */
 188     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
 189
 190     status = SUCCESS;
 191   }
 192 #endif /* SPI3 */
 193 #if defined(SPI4)
 194   if (SPIx == SPI4)
 195   {
 196     /* Force reset of SPI clock */
 197     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
 198
 199     /* Release reset of SPI clock */
 200     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
 201
 202     status = SUCCESS;
 203   }
 204 #endif /* SPI4 */
 205
 206   return status;
 207 }
 208
 209 /**
 210   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
 211   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 212   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 213   * @param  SPIx SPI Instance
 214   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 215   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
 216   */
 217 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
 218 {
 219   ErrorStatus status = ERROR;
 220
 221   /* Check the SPI Instance SPIx*/
 222   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 223
 224   /* Check the SPI parameters from SPI_InitStruct*/
 225   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
 226   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
 227   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
 228   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
 229   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
 230   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
 231   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
 232   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
 233   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
 234
 235   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
 236   {
 237     /*---------------------------- SPIx CR1 Configuration ------------------------
 238      * Configure SPIx CR1 with parameters:
 239      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
 240      * - Master/Slave Mode:  SPI_CR1_MSTR bit
 241      * - ClockPolarity:      SPI_CR1_CPOL bit
 242      * - ClockPhase:         SPI_CR1_CPHA bit
 243      * - NSS management:     SPI_CR1_SSM bit
 244      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
 245      * - BitOrder:           SPI_CR1_LSBFIRST bit
 246      * - CRCCalculation:     SPI_CR1_CRCEN bit
 247      */
 248     MODIFY_REG(SPIx->CR1,
 249                SPI_CR1_CLEAR_MASK,
 250                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
 251                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
 252                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
 253                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
 254
 255     /*---------------------------- SPIx CR2 Configuration ------------------------
 256      * Configure SPIx CR2 with parameters:
 257      * - DataWidth:          DS[3:0] bits
 258      * - NSS management:     SSOE bit
 259      */
 260     MODIFY_REG(SPIx->CR2,
 261                SPI_CR2_DS | SPI_CR2_SSOE,
 262                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
 263
 264     /*---------------------------- SPIx CRCPR Configuration ----------------------
 265      * Configure SPIx CRCPR with parameters:
 266      * - CRCPoly:            CRCPOLY[15:0] bits
 267      */
 268     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
 269     {
 270       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
 271       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
 272     }
 273     status = SUCCESS;
 274   }
 275
 276 #if defined (SPI_I2S_SUPPORT)
 277   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
 278   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 279 #endif /* SPI_I2S_SUPPORT */
 280   return status;
 281 }
 282
 283 /**
 284   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
 285   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 286   * whose fields will be set to default values.
 287   * @retval None
 288   */
 289 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
 290 {
 291   /* Set SPI_InitStruct fields to default values */
 292   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
 293   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
 294   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
 295   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
 296   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
 297   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
 298   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
 299   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
 300   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
 301   SPI_InitStruct->CRCPoly           = 7U;
 302 }
 303
 304 /**
 305   * @}
 306   */
 307
 308 /**
 309   * @}
 310   */
 311
 312 /**
 313   * @}
 314   */
 315
 316 #if defined(SPI_I2S_SUPPORT)
 317 /** @addtogroup I2S_LL
 318   * @{
 319   */
 320
 321 /* Private types -------------------------------------------------------------*/
 322 /* Private variables ---------------------------------------------------------*/
 323 /* Private constants ---------------------------------------------------------*/
 324 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
 325   * @{
 326   */
 327 /* I2S registers Masks */
 328 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
 329                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
 330                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
 331
 332 #define I2S_I2SPR_CLEAR_MASK               0x0002U
 333 /**
 334   * @}
 335   */
 336 /* Private macros ------------------------------------------------------------*/
 337 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
 338   * @{
 339   */
 340
 341 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)          \
 342                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
 343                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
 344                                        || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
 345
 346 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
 347                                        || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
 348
 349 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)   \
 350                                        || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
 351                                        || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
 352                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
 353                                        || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
 354
 355 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)  \
 356                                        || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
 357                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
 358                                        || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
 359
 360 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
 361                                        || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
 362
 363 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)    \
 364                                        && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
 365                                        || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
 366
 367 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
 368
 369 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
 370                                            || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
 371 /**
 372   * @}
 373   */
 374
 375 /* Private function prototypes -----------------------------------------------*/
 376
 377 /* Exported functions --------------------------------------------------------*/
 378 /** @addtogroup I2S_LL_Exported_Functions
 379   * @{
 380   */
 381
 382 /** @addtogroup I2S_LL_EF_Init
 383   * @{
 384   */
 385
 386 /**
 387   * @brief  De-initialize the SPI/I2S registers to their default reset values.
 388   * @param  SPIx SPI Instance
 389   * @retval An ErrorStatus enumeration value:
 390   *          - SUCCESS: SPI registers are de-initialized
 391   *          - ERROR: SPI registers are not de-initialized
 392   */
 393 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
 394 {
 395   return LL_SPI_DeInit(SPIx);
 396 }
 397
 398 /**
 399   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
 400   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 401   *         SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 402   * @param  SPIx SPI Instance
 403   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 404   * @retval An ErrorStatus enumeration value:
 405   *          - SUCCESS: SPI registers are Initialized
 406   *          - ERROR: SPI registers are not Initialized
 407   */
 408 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
 409 {
 410   uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
 411   uint32_t tmp = 0U;
 412   LL_RCC_ClocksTypeDef rcc_clocks;
 413   uint32_t sourceclock = 0U;
 414   ErrorStatus status = ERROR;
 415
 416   /* Check the I2S parameters */
 417   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 418   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 419   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 420   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 421   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
 422   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
 423   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 424
 425   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
 426   {
 427     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 428      * Configure SPIx I2SCFGR with parameters:
 429      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 430      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 431      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 432      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 433      */
 434
 435     /* Write to SPIx I2SCFGR */
 436     MODIFY_REG(SPIx->I2SCFGR,
 437                I2S_I2SCFGR_CLEAR_MASK,
 438                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
 439                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 440                SPI_I2SCFGR_I2SMOD);
 441
 442     /*---------------------------- SPIx I2SPR Configuration ----------------------
 443      * Configure SPIx I2SPR with parameters:
 444      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
 445      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
 446      */
 447
 448     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
 449      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
 450      */
 451     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
 452     {
 453       /* Check the frame length (For the Prescaler computing)
 454        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
 455        */
 456       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
 457       {
 458         /* Packet length is 32 bits */
 459         packetlength = 2U;
 460       }
 461
 462       /* I2S Clock source is System clock: Get System Clock frequency */
 463       LL_RCC_GetSystemClocksFreq(&rcc_clocks);
 464
 465       /* Get the source clock value: based on System Clock value */
 466       sourceclock = rcc_clocks.SYSCLK_Frequency;
 467
 468       /* Compute the Real divider depending on the MCLK output state with a floating point */
 469       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
 470       {
 471         /* MCLK output is enabled */
 472         tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 473       }
 474       else
 475       {
 476         /* MCLK output is disabled */
 477         tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 478       }
 479
 480       /* Remove the floating point */
 481       tmp = tmp / 10U;
 482
 483       /* Check the parity of the divider */
 484       i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
 485
 486       /* Compute the i2sdiv prescaler */
 487       i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
 488
 489       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 490       i2sodd = (uint16_t)(i2sodd << 8U);
 491     }
 492
 493     /* Test if the divider is 1 or 0 or greater than 0xFF */
 494     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
 495     {
 496       /* Set the default values */
 497       i2sdiv = 2U;
 498       i2sodd = 0U;
 499     }
 500
 501     /* Write to SPIx I2SPR register the computed value */
 502     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
 503
 504     status = SUCCESS;
 505   }
 506   return status;
 507 }
 508
 509 /**
 510   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
 511   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 512   *         whose fields will be set to default values.
 513   * @retval None
 514   */
 515 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
 516 {
 517   /*--------------- Reset I2S init structure parameters values -----------------*/
 518   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
 519   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
 520   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
 521   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
 522   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
 523   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
 524 }
 525
 526 /**
 527   * @brief  Set linear and parity prescaler.
 528   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
 529   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
 530   * @param  SPIx SPI Instance
 531   * @param  PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
 532   * @param  PrescalerParity This parameter can be one of the following values:
 533   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
 534   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
 535   * @retval None
 536   */
 537 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
 538 {
 539   /* Check the I2S parameters */
 540   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 541   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
 542   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
 543
 544   /* Write to SPIx I2SPR */
 545   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
 546 }
 547
 548 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
 549 /**
 550   * @brief  Configures the full duplex mode for the I2Sx peripheral using its extension
 551   *         I2Sxext according to the specified parameters in the I2S_InitStruct.
 552   * @note   The structure pointed by I2S_InitStruct parameter should be the same
 553   *         used for the master I2S peripheral. In this case, if the master is
 554   *         configured as transmitter, the slave will be receiver and vice versa.
 555   *         Or you can force a different mode by modifying the field I2S_Mode to the
 556   *         value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
 557   * @param  I2Sxext SPI Instance
 558   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 559   * @retval An ErrorStatus enumeration value:
 560   *          - SUCCESS: I2Sxext registers are Initialized
 561   *          - ERROR: I2Sxext registers are not Initialized
 562   */
 563 ErrorStatus  LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
 564 {
 565   uint16_t mode = 0U;
 566   ErrorStatus status = ERROR;
 567
 568   /* Check the I2S parameters */
 569   assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
 570   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 571   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 572   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 573   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 574
 575   if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
 576   {
 577     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 578      * Configure SPIx I2SCFGR with parameters:
 579      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 580      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 581      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 582      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 583      */
 584
 585     /* Reset I2SPR registers */
 586     WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
 587
 588     /* Get the mode to be configured for the extended I2S */
 589     if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
 590     {
 591       mode = LL_I2S_MODE_SLAVE_RX;
 592     }
 593     else
 594     {
 595       if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
 596       {
 597         mode = LL_I2S_MODE_SLAVE_TX;
 598       }
 599     }
 600
 601     /* Write to SPIx I2SCFGR */
 602     MODIFY_REG(I2Sxext->I2SCFGR,
 603                I2S_I2SCFGR_CLEAR_MASK,
 604                I2S_InitStruct->Standard |
 605                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 606                SPI_I2SCFGR_I2SMOD | mode);
 607
 608     status = SUCCESS;
 609   }
 610   return status;
 611 }
 612 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
 613
 614 /**
 615   * @}
 616   */
 617
 618 /**
 619   * @}
 620   */
 621
 622 /**
 623   * @}
 624   */
 625 #endif /* SPI_I2S_SUPPORT */
 626
 627 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
 628
 629 /**
 630   * @}
 631   */
 632
 633 #endif /* USE_FULL_LL_DRIVER */
 634
 635 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/