lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @brief   TIM LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35 #if defined(USE_FULL_LL_DRIVER)
  36
  37 /* Includes ------------------------------------------------------------------*/
  38 #include "stm32f3xx_ll_tim.h"
  39 #include "stm32f3xx_ll_bus.h"
  40
  41 #ifdef  USE_FULL_ASSERT
  42 #include "stm32_assert.h"
  43 #else
  44 #define assert_param(expr) ((void)0U)
  45 #endif
  46
  47 /** @addtogroup STM32F3xx_LL_Driver
  48   * @{
  49   */
  50
  51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM18) || defined (TIM19) || defined (TIM20)
  52
  53 /** @addtogroup TIM_LL
  54   * @{
  55   */
  56
  57 /* Private types -------------------------------------------------------------*/
  58 /* Private variables ---------------------------------------------------------*/
  59 /* Private constants ---------------------------------------------------------*/
  60 /* Private macros ------------------------------------------------------------*/
  61 /** @addtogroup TIM_LL_Private_Macros
  62   * @{
  63   */
  64 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  65                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  66                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  67                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  68                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  69
  70 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  71                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  72                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  73
  74 #if defined(TIM_CCMR1_OC1M_3)
  75 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  76                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  77                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  78                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  79                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  80                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  81                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  82                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  83                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  84                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  85                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  86                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  87                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  88                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
  89 #else
  90 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  91                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  92                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  93                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  94                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  95                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  96                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  97                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
  98 #endif
  99
 100 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
 101                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
 102
 103 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
 104                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
 105
 106 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
 107                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
 108
 109 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
 110                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
 111                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
 112
 113 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
 114                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
 115                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
 116                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
 117
 118 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
 119                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
 120                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
 121                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
 122                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
 123                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
 124                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
 125                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
 126                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 127                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 128                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 129                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 130                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 131                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 132                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 133                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 134
 135 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 136                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 137                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 138
 139 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 140                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 141                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 142
 143 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 144                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 145
 146 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 147                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 148
 149 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 150                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 151
 152 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 153                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 154                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 155                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 156
 157 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 158                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 159
 160 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 161                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 162 #if defined(TIM_BDTR_BKF)
 163
 164 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
 165                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
 166                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
 167                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
 168                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
 169                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
 170                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
 171                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
 172                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
 173                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
 174                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
 175                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
 176                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
 177                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
 178                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
 179                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
 180 #endif /* TIM_BDTR_BKF */
 181 #if defined(TIM_BDTR_BK2E)
 182
 183 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
 184                                         || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
 185
 186 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
 187                                            || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
 188
 189 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
 190                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
 191                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
 192                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
 193                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
 194                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
 195                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
 196                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
 197                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
 198                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
 199                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
 200                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
 201                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
 202                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
 203                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
 204                                          || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
 205 #endif /* TIM_BDTR_BK2E */
 206
 207 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 208                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 209 /**
 210   * @}
 211   */
 212
 213
 214 /* Private function prototypes -----------------------------------------------*/
 215 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 216   * @{
 217   */
 218 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 219 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 220 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 221 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 222 #if defined(TIM_CCER_CC5E)
 223 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 224 #endif /* TIM_CCER_CC5E */
 225 #if defined(TIM_CCER_CC6E)
 226 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 227 #endif /* TIM_CCER_CC6E */
 228 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 229 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 230 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 231 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 232 /**
 233   * @}
 234   */
 235
 236 /* Exported functions --------------------------------------------------------*/
 237 /** @addtogroup TIM_LL_Exported_Functions
 238   * @{
 239   */
 240
 241 /** @addtogroup TIM_LL_EF_Init
 242   * @{
 243   */
 244
 245 /**
 246   * @brief  Set TIMx registers to their reset values.
 247   * @param  TIMx Timer instance
 248   * @retval An ErrorStatus enumeration value:
 249   *          - SUCCESS: TIMx registers are de-initialized
 250   *          - ERROR: invalid TIMx instance
 251   */
 252 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 253 {
 254   ErrorStatus result = SUCCESS;
 255
 256   /* Check the parameters */
 257   assert_param(IS_TIM_INSTANCE(TIMx));
 258
 259
 260   if (TIMx == TIM2)
 261   {
 262     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 263     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 264   }
 265
 266 #if defined(TIM1)
 267   else if (TIMx == TIM1)
 268   {
 269     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 270     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 271   }
 272 #endif
 273 #if defined(TIM3)
 274   else if (TIMx == TIM3)
 275   {
 276     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 277     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 278   }
 279 #endif
 280 #if defined(TIM4)
 281   else if (TIMx == TIM4)
 282   {
 283     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 284     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 285   }
 286 #endif
 287 #if defined(TIM5)
 288   else if (TIMx == TIM5)
 289   {
 290     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 291     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 292   }
 293 #endif
 294 #if defined(TIM6)
 295   else if (TIMx == TIM6)
 296   {
 297     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 298     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 299   }
 300 #endif
 301 #if defined(TIM7)
 302   else if (TIMx == TIM7)
 303   {
 304     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 305     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 306   }
 307 #endif
 308 #if defined(TIM8)
 309   else if (TIMx == TIM8)
 310   {
 311     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 312     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 313   }
 314 #endif
 315 #if defined(TIM12)
 316   else if (TIMx == TIM12)
 317   {
 318     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 319     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 320   }
 321 #endif
 322 #if defined(TIM13)
 323   else if (TIMx == TIM13)
 324   {
 325     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 326     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 327   }
 328 #endif
 329 #if defined(TIM14)
 330   else if (TIMx == TIM14)
 331   {
 332     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 333     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 334   }
 335 #endif
 336 #if defined(TIM15)
 337   else if (TIMx == TIM15)
 338   {
 339     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
 340     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
 341   }
 342 #endif
 343 #if defined(TIM16)
 344   else if (TIMx == TIM16)
 345   {
 346     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
 347     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
 348   }
 349 #endif
 350 #if defined(TIM17)
 351   else if (TIMx == TIM17)
 352   {
 353     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
 354     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
 355   }
 356 #endif
 357 #if defined(TIM18)
 358   else if (TIMx == TIM18)
 359   {
 360     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM18);
 361     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM18);
 362   }
 363 #endif
 364 #if defined(TIM19)
 365   else if (TIMx == TIM19)
 366   {
 367     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM19);
 368     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM19);
 369   }
 370 #endif
 371 #if defined(TIM20)
 372   else if (TIMx == TIM20)
 373   {
 374     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
 375     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
 376   }
 377 #endif
 378   else
 379   {
 380     result = ERROR;
 381   }
 382
 383
 384   return result;
 385 }
 386
 387 /**
 388   * @brief  Set the fields of the time base unit configuration data structure
 389   *         to their default values.
 390   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 391   * @retval None
 392   */
 393 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 394 {
 395   /* Set the default configuration */
 396   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
 397   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 398   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 399   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 400   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
 401 }
 402
 403 /**
 404   * @brief  Configure the TIMx time base unit.
 405   * @param  TIMx Timer Instance
 406   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 407   * @retval An ErrorStatus enumeration value:
 408   *          - SUCCESS: TIMx registers are de-initialized
 409   *          - ERROR: not applicable
 410   */
 411 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 412 {
 413   uint32_t tmpcr1 = 0U;
 414
 415   /* Check the parameters */
 416   assert_param(IS_TIM_INSTANCE(TIMx));
 417   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 418   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 419
 420   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 421
 422   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 423   {
 424     /* Select the Counter Mode */
 425     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 426   }
 427
 428   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 429   {
 430     /* Set the clock division */
 431     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 432   }
 433
 434   /* Write to TIMx CR1 */
 435   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 436
 437   /* Set the Autoreload value */
 438   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 439
 440   /* Set the Prescaler value */
 441   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 442
 443   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 444   {
 445     /* Set the Repetition Counter value */
 446     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 447   }
 448
 449   /* Generate an update event to reload the Prescaler
 450      and the repetition counter value (if applicable) immediately */
 451   LL_TIM_GenerateEvent_UPDATE(TIMx);
 452
 453   return SUCCESS;
 454 }
 455
 456 /**
 457   * @brief  Set the fields of the TIMx output channel configuration data
 458   *         structure to their default values.
 459   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 460   * @retval None
 461   */
 462 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 463 {
 464   /* Set the default configuration */
 465   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 466   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 467   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 468   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 469   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 470   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 471   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 472   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 473 }
 474
 475 /**
 476   * @brief  Configure the TIMx output channel.
 477   * @param  TIMx Timer Instance
 478   * @param  Channel This parameter can be one of the following values:
 479   *         @arg @ref LL_TIM_CHANNEL_CH1
 480   *         @arg @ref LL_TIM_CHANNEL_CH2
 481   *         @arg @ref LL_TIM_CHANNEL_CH3
 482   *         @arg @ref LL_TIM_CHANNEL_CH4
 483   *         @arg @ref LL_TIM_CHANNEL_CH5
 484   *         @arg @ref LL_TIM_CHANNEL_CH6
 485   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 486   * @note   OC5 and OC6 are not available for all F3 devices
 487   * @retval An ErrorStatus enumeration value:
 488   *          - SUCCESS: TIMx output channel is initialized
 489   *          - ERROR: TIMx output channel is not initialized
 490   */
 491 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 492 {
 493   ErrorStatus result = ERROR;
 494
 495   switch (Channel)
 496   {
 497     case LL_TIM_CHANNEL_CH1:
 498       result = OC1Config(TIMx, TIM_OC_InitStruct);
 499       break;
 500     case LL_TIM_CHANNEL_CH2:
 501       result = OC2Config(TIMx, TIM_OC_InitStruct);
 502       break;
 503     case LL_TIM_CHANNEL_CH3:
 504       result = OC3Config(TIMx, TIM_OC_InitStruct);
 505       break;
 506     case LL_TIM_CHANNEL_CH4:
 507       result = OC4Config(TIMx, TIM_OC_InitStruct);
 508       break;
 509 #if defined(TIM_CCER_CC5E)
 510     case LL_TIM_CHANNEL_CH5:
 511       result = OC5Config(TIMx, TIM_OC_InitStruct);
 512       break;
 513     case LL_TIM_CHANNEL_CH6:
 514       result = OC6Config(TIMx, TIM_OC_InitStruct);
 515       break;
 516 #endif /* TIM_CCER_CC5E */
 517     default:
 518       break;
 519   }
 520
 521   return result;
 522 }
 523
 524 /**
 525   * @brief  Set the fields of the TIMx input channel configuration data
 526   *         structure to their default values.
 527   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 528   * @retval None
 529   */
 530 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 531 {
 532   /* Set the default configuration */
 533   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 534   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 535   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 536   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 537 }
 538
 539 /**
 540   * @brief  Configure the TIMx input channel.
 541   * @param  TIMx Timer Instance
 542   * @param  Channel This parameter can be one of the following values:
 543   *         @arg @ref LL_TIM_CHANNEL_CH1
 544   *         @arg @ref LL_TIM_CHANNEL_CH2
 545   *         @arg @ref LL_TIM_CHANNEL_CH3
 546   *         @arg @ref LL_TIM_CHANNEL_CH4
 547   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 548   * @retval An ErrorStatus enumeration value:
 549   *          - SUCCESS: TIMx output channel is initialized
 550   *          - ERROR: TIMx output channel is not initialized
 551   */
 552 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 553 {
 554   ErrorStatus result = ERROR;
 555
 556   switch (Channel)
 557   {
 558     case LL_TIM_CHANNEL_CH1:
 559       result = IC1Config(TIMx, TIM_IC_InitStruct);
 560       break;
 561     case LL_TIM_CHANNEL_CH2:
 562       result = IC2Config(TIMx, TIM_IC_InitStruct);
 563       break;
 564     case LL_TIM_CHANNEL_CH3:
 565       result = IC3Config(TIMx, TIM_IC_InitStruct);
 566       break;
 567     case LL_TIM_CHANNEL_CH4:
 568       result = IC4Config(TIMx, TIM_IC_InitStruct);
 569       break;
 570     default:
 571       break;
 572   }
 573
 574   return result;
 575 }
 576
 577 /**
 578   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 579   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 580   * @retval None
 581   */
 582 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 583 {
 584   /* Set the default configuration */
 585   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 586   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 587   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 588   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 589   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 590   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 591   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 592   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 593   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 594 }
 595
 596 /**
 597   * @brief  Configure the encoder interface of the timer instance.
 598   * @param  TIMx Timer Instance
 599   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 600   * @retval An ErrorStatus enumeration value:
 601   *          - SUCCESS: TIMx registers are de-initialized
 602   *          - ERROR: not applicable
 603   */
 604 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 605 {
 606   uint32_t tmpccmr1 = 0U;
 607   uint32_t tmpccer = 0U;
 608
 609   /* Check the parameters */
 610   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 611   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 612   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 613   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 614   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 615   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 616   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 617   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 618   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 619   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 620
 621   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 622   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 623
 624   /* Get the TIMx CCMR1 register value */
 625   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 626
 627   /* Get the TIMx CCER register value */
 628   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 629
 630   /* Configure TI1 */
 631   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 632   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 633   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 634   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 635
 636   /* Configure TI2 */
 637   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 638   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 639   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 640   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 641
 642   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 643   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 644   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 645   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 646   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 647
 648   /* Set encoder mode */
 649   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 650
 651   /* Write to TIMx CCMR1 */
 652   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 653
 654   /* Write to TIMx CCER */
 655   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 656
 657   return SUCCESS;
 658 }
 659
 660 #if defined TIM_CR2_MMS2
 661 /**
 662   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 663   *         structure to their default values.
 664   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 665   * @retval None
 666   */
 667 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 668 {
 669   /* Set the default configuration */
 670   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 671   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 672   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 673   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 674 }
 675
 676 /**
 677   * @brief  Configure the Hall sensor interface of the timer instance.
 678   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 679   *       to the TI1 input channel
 680   * @note TIMx slave mode controller is configured in reset mode.
 681           Selected internal trigger is TI1F_ED.
 682   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 683   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 684   *       between 2 changes on the inputs. It gives information about motor speed.
 685   * @note Channel 2 is configured in output PWM 2 mode.
 686   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 687   * @note OC2REF is selected as trigger output on TRGO.
 688   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 689   *       when TIMx operates in Hall sensor interface mode.
 690   * @param  TIMx Timer Instance
 691   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 692   * @retval An ErrorStatus enumeration value:
 693   *          - SUCCESS: TIMx registers are de-initialized
 694   *          - ERROR: not applicable
 695   */
 696 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 697 {
 698   uint32_t tmpcr2 = 0U;
 699   uint32_t tmpccmr1 = 0U;
 700   uint32_t tmpccer = 0U;
 701   uint32_t tmpsmcr = 0U;
 702
 703   /* Check the parameters */
 704   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 705   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 706   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 707   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 708
 709   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 710   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 711
 712   /* Get the TIMx CR2 register value */
 713   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 714
 715   /* Get the TIMx CCMR1 register value */
 716   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 717
 718   /* Get the TIMx CCER register value */
 719   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 720
 721   /* Get the TIMx SMCR register value */
 722   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 723
 724   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 725   tmpcr2 |= TIM_CR2_TI1S;
 726
 727   /* OC2REF signal is used as trigger output (TRGO) */
 728   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 729
 730   /* Configure the slave mode controller */
 731   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 732   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 733   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 734
 735   /* Configure input channel 1 */
 736   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 737   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 738   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 739   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 740
 741   /* Configure input channel 2 */
 742   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 743   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 744
 745   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 746   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 747   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 748   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 749
 750   /* Write to TIMx CR2 */
 751   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 752
 753   /* Write to TIMx SMCR */
 754   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 755
 756   /* Write to TIMx CCMR1 */
 757   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 758
 759   /* Write to TIMx CCER */
 760   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 761
 762   /* Write to TIMx CCR2 */
 763   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 764
 765   return SUCCESS;
 766 }
 767 #endif /* TIM_CR2_MMS2 */
 768
 769 /**
 770   * @brief  Set the fields of the Break and Dead Time configuration data structure
 771   *         to their default values.
 772   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 773   * @retval None
 774   */
 775 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 776 {
 777   /* Set the default configuration */
 778   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 779   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 780   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 781   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
 782   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 783   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 784 #if defined(TIM_BDTR_BKF)
 785   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
 786 #endif /* TIM_BDTR_BKF */
 787 #if defined(TIM_BDTR_BK2E)
 788   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
 789   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
 790   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
 791 #endif /* TIM_BDTR_BK2E */
 792   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 793 }
 794
 795 /**
 796   * @brief  Configure the Break and Dead Time feature of the timer instance.
 797   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
 798   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
 799   *  can be necessary to configure all of them during the first write access to
 800   *  the TIMx_BDTR register.
 801   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 802   *       a timer instance provides a break input.
 803   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
 804   *       a timer instance provides a second break input.
 805   * @param  TIMx Timer Instance
 806   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
 807   * @retval An ErrorStatus enumeration value:
 808   *          - SUCCESS: Break and Dead Time is initialized
 809   *          - ERROR: not applicable
 810   */
 811 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 812 {
 813   uint32_t tmpbdtr = 0;
 814
 815   /* Check the parameters */
 816   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 817   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 818   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 819   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 820   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 821   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 822   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 823
 824   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 825   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 826
 827   /* Set the BDTR bits */
 828   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 829   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 830   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 831   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 832   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 833   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 834   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 835   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 836 #if defined(TIM_BDTR_BKF)
 837   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
 838   {
 839     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
 840     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
 841   }
 842 #endif /* TIM_BDTR_BKF */
 843 #if defined(TIM_BDTR_BK2E)
 844
 845   if (IS_TIM_BKIN2_INSTANCE(TIMx))
 846   {
 847     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
 848     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
 849     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
 850
 851     /* Set the BREAK2 input related BDTR bit-fields */
 852     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
 853     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
 854     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
 855   }
 856 #endif /* TIM_BDTR_BK2E */
 857
 858   /* Set TIMx_BDTR */
 859   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 860
 861   return SUCCESS;
 862 }
 863 /**
 864   * @}
 865   */
 866
 867 /**
 868   * @}
 869   */
 870
 871 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 872  *  @brief   Private functions
 873   * @{
 874   */
 875 /**
 876   * @brief  Configure the TIMx output channel 1.
 877   * @param  TIMx Timer Instance
 878   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 879   * @retval An ErrorStatus enumeration value:
 880   *          - SUCCESS: TIMx registers are de-initialized
 881   *          - ERROR: not applicable
 882   */
 883 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 884 {
 885   uint32_t tmpccmr1 = 0U;
 886   uint32_t tmpccer = 0U;
 887   uint32_t tmpcr2 = 0U;
 888
 889   /* Check the parameters */
 890   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 891   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 892   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 893   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 894   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 895   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 896
 897   /* Disable the Channel 1: Reset the CC1E Bit */
 898   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 899
 900   /* Get the TIMx CCER register value */
 901   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 902
 903   /* Get the TIMx CR2 register value */
 904   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 905
 906   /* Get the TIMx CCMR1 register value */
 907   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 908
 909   /* Reset Capture/Compare selection Bits */
 910   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 911
 912   /* Set the Output Compare Mode */
 913   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 914
 915   /* Set the Output Compare Polarity */
 916   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 917
 918   /* Set the Output State */
 919   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 920
 921   if (IS_TIM_BREAK_INSTANCE(TIMx))
 922   {
 923     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 924     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 925
 926     /* Set the complementary output Polarity */
 927     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 928
 929     /* Set the complementary output State */
 930     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 931
 932     /* Set the Output Idle state */
 933     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 934
 935     /* Set the complementary output Idle state */
 936     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 937   }
 938
 939   /* Write to TIMx CR2 */
 940   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 941
 942   /* Write to TIMx CCMR1 */
 943   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 944
 945   /* Set the Capture Compare Register value */
 946   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 947
 948   /* Write to TIMx CCER */
 949   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 950
 951   return SUCCESS;
 952 }
 953
 954 /**
 955   * @brief  Configure the TIMx output channel 2.
 956   * @param  TIMx Timer Instance
 957   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 958   * @retval An ErrorStatus enumeration value:
 959   *          - SUCCESS: TIMx registers are de-initialized
 960   *          - ERROR: not applicable
 961   */
 962 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 963 {
 964   uint32_t tmpccmr1 = 0U;
 965   uint32_t tmpccer = 0U;
 966   uint32_t tmpcr2 = 0U;
 967
 968   /* Check the parameters */
 969   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 970   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 971   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 972   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 973   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 974   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 975
 976   /* Disable the Channel 2: Reset the CC2E Bit */
 977   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 978
 979   /* Get the TIMx CCER register value */
 980   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 981
 982   /* Get the TIMx CR2 register value */
 983   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 984
 985   /* Get the TIMx CCMR1 register value */
 986   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 987
 988   /* Reset Capture/Compare selection Bits */
 989   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 990
 991   /* Select the Output Compare Mode */
 992   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 993
 994   /* Set the Output Compare Polarity */
 995   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 996
 997   /* Set the Output State */
 998   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 999
1000   if (IS_TIM_BREAK_INSTANCE(TIMx))
1001   {
1002     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1003     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1004
1005     /* Set the complementary output Polarity */
1006     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
1007
1008     /* Set the complementary output State */
1009     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
1010
1011     /* Set the Output Idle state */
1012     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
1013
1014 #if defined(STM32F373xC) || defined(STM32F378xx)
1015 #else
1016     /* Set the complementary output Idle state */
1017     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
1018 #endif
1019   }
1020
1021   /* Write to TIMx CR2 */
1022   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1023
1024   /* Write to TIMx CCMR1 */
1025   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
1026
1027   /* Set the Capture Compare Register value */
1028   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
1029
1030   /* Write to TIMx CCER */
1031   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1032
1033   return SUCCESS;
1034 }
1035
1036 /**
1037   * @brief  Configure the TIMx output channel 3.
1038   * @param  TIMx Timer Instance
1039   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
1040   * @retval An ErrorStatus enumeration value:
1041   *          - SUCCESS: TIMx registers are de-initialized
1042   *          - ERROR: not applicable
1043   */
1044 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1045 {
1046   uint32_t tmpccmr2 = 0U;
1047   uint32_t tmpccer = 0U;
1048   uint32_t tmpcr2 = 0U;
1049
1050   /* Check the parameters */
1051   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1052   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1053   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1054   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1055   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1056   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1057
1058   /* Disable the Channel 3: Reset the CC3E Bit */
1059   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1060
1061   /* Get the TIMx CCER register value */
1062   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
1063
1064   /* Get the TIMx CR2 register value */
1065   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1066
1067   /* Get the TIMx CCMR2 register value */
1068   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1069
1070   /* Reset Capture/Compare selection Bits */
1071   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1072
1073   /* Select the Output Compare Mode */
1074   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1075
1076   /* Set the Output Compare Polarity */
1077   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1078
1079   /* Set the Output State */
1080   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1081
1082   if (IS_TIM_BREAK_INSTANCE(TIMx))
1083   {
1084     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1085     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1086
1087     /* Set the complementary output Polarity */
1088     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1089
1090     /* Set the complementary output State */
1091     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1092
1093 #if defined(STM32F373xC) || defined(STM32F378xx)
1094 #else
1095     /* Set the Output Idle state */
1096     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1097
1098     /* Set the complementary output Idle state */
1099     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1100 #endif
1101   }
1102
1103   /* Write to TIMx CR2 */
1104   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1105
1106   /* Write to TIMx CCMR2 */
1107   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1108
1109   /* Set the Capture Compare Register value */
1110   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1111
1112   /* Write to TIMx CCER */
1113   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1114
1115   return SUCCESS;
1116 }
1117
1118 /**
1119   * @brief  Configure the TIMx output channel 4.
1120   * @param  TIMx Timer Instance
1121   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1122   * @retval An ErrorStatus enumeration value:
1123   *          - SUCCESS: TIMx registers are de-initialized
1124   *          - ERROR: not applicable
1125   */
1126 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1127 {
1128   uint32_t tmpccmr2 = 0U;
1129   uint32_t tmpccer = 0U;
1130   uint32_t tmpcr2 = 0U;
1131
1132   /* Check the parameters */
1133   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1134   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1135   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1136   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1137   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1138   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1139
1140   /* Disable the Channel 4: Reset the CC4E Bit */
1141   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1142
1143   /* Get the TIMx CCER register value */
1144   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1145
1146   /* Get the TIMx CR2 register value */
1147   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1148
1149   /* Get the TIMx CCMR2 register value */
1150   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1151
1152   /* Reset Capture/Compare selection Bits */
1153   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1154
1155   /* Select the Output Compare Mode */
1156   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1157
1158   /* Set the Output Compare Polarity */
1159   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1160
1161   /* Set the Output State */
1162   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1163
1164   if (IS_TIM_BREAK_INSTANCE(TIMx))
1165   {
1166     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1167     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1168
1169 #if defined(STM32F373xC) || defined(STM32F378xx)
1170 #else
1171     /* Set the Output Idle state */
1172     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1173 #endif
1174   }
1175
1176   /* Write to TIMx CR2 */
1177   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1178
1179   /* Write to TIMx CCMR2 */
1180   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1181
1182   /* Set the Capture Compare Register value */
1183   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1184
1185   /* Write to TIMx CCER */
1186   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1187
1188   return SUCCESS;
1189 }
1190
1191 #if defined(TIM_CCER_CC5E)
1192 /**
1193   * @brief  Configure the TIMx output channel 5.
1194   * @param  TIMx Timer Instance
1195   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1196   * @note   OC5 is not available for all F3 devices
1197   * @retval An ErrorStatus enumeration value:
1198   *          - SUCCESS: TIMx registers are de-initialized
1199   *          - ERROR: not applicable
1200   */
1201 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1202 {
1203   uint32_t tmpccmr3 = 0U;
1204   uint32_t tmpccer = 0U;
1205
1206   /* Check the parameters */
1207   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1208   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1209   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1210   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1211   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1212   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1213
1214   /* Disable the Channel 5: Reset the CC5E Bit */
1215   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1216
1217   /* Get the TIMx CCER register value */
1218   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1219
1220   /* Get the TIMx CCMR3 register value */
1221   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1222
1223   /* Select the Output Compare Mode */
1224   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1225
1226   /* Set the Output Compare Polarity */
1227   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1228
1229   /* Set the Output State */
1230   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1231
1232   if (IS_TIM_BREAK_INSTANCE(TIMx))
1233   {
1234     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1235     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1236
1237     /* Set the Output Idle state */
1238     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1239
1240   }
1241
1242   /* Write to TIMx CCMR3 */
1243   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1244
1245   /* Set the Capture Compare Register value */
1246   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1247
1248   /* Write to TIMx CCER */
1249   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1250
1251   return SUCCESS;
1252 }
1253
1254 /**
1255   * @brief  Configure the TIMx output channel 6.
1256   * @param  TIMx Timer Instance
1257   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1258   * @note   OC6 is not available for all F3 devices
1259   * @retval An ErrorStatus enumeration value:
1260   *          - SUCCESS: TIMx registers are de-initialized
1261   *          - ERROR: not applicable
1262   */
1263 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1264 {
1265   uint32_t tmpccmr3 = 0U;
1266   uint32_t tmpccer = 0U;
1267
1268   /* Check the parameters */
1269   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1270   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1271   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1272   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1273   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1274   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1275
1276   /* Disable the Channel 5: Reset the CC6E Bit */
1277   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1278
1279   /* Get the TIMx CCER register value */
1280   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1281
1282   /* Get the TIMx CCMR3 register value */
1283   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1284
1285   /* Select the Output Compare Mode */
1286   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1287
1288   /* Set the Output Compare Polarity */
1289   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1290
1291   /* Set the Output State */
1292   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1293
1294   if (IS_TIM_BREAK_INSTANCE(TIMx))
1295   {
1296     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1297     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1298
1299     /* Set the Output Idle state */
1300     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1301   }
1302
1303   /* Write to TIMx CCMR3 */
1304   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1305
1306   /* Set the Capture Compare Register value */
1307   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1308
1309   /* Write to TIMx CCER */
1310   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1311
1312   return SUCCESS;
1313 }
1314 #endif /* TIM_CCER_CC5E */
1315
1316 /**
1317   * @brief  Configure the TIMx input channel 1.
1318   * @param  TIMx Timer Instance
1319   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1320   * @retval An ErrorStatus enumeration value:
1321   *          - SUCCESS: TIMx registers are de-initialized
1322   *          - ERROR: not applicable
1323   */
1324 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1325 {
1326   /* Check the parameters */
1327   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1328   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1329   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1330   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1331   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1332
1333   /* Disable the Channel 1: Reset the CC1E Bit */
1334   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1335
1336   /* Select the Input and set the filter and the prescaler value */
1337   MODIFY_REG(TIMx->CCMR1,
1338              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1339              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1340
1341   /* Select the Polarity and set the CC1E Bit */
1342   MODIFY_REG(TIMx->CCER,
1343              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1344              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1345
1346   return SUCCESS;
1347 }
1348
1349 /**
1350   * @brief  Configure the TIMx input channel 2.
1351   * @param  TIMx Timer Instance
1352   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1353   * @retval An ErrorStatus enumeration value:
1354   *          - SUCCESS: TIMx registers are de-initialized
1355   *          - ERROR: not applicable
1356   */
1357 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1358 {
1359   /* Check the parameters */
1360   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1361   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1362   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1363   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1364   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1365
1366   /* Disable the Channel 2: Reset the CC2E Bit */
1367   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1368
1369   /* Select the Input and set the filter and the prescaler value */
1370   MODIFY_REG(TIMx->CCMR1,
1371              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1372              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1373
1374   /* Select the Polarity and set the CC2E Bit */
1375   MODIFY_REG(TIMx->CCER,
1376              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1377              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1378
1379   return SUCCESS;
1380 }
1381
1382 /**
1383   * @brief  Configure the TIMx input channel 3.
1384   * @param  TIMx Timer Instance
1385   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1386   * @retval An ErrorStatus enumeration value:
1387   *          - SUCCESS: TIMx registers are de-initialized
1388   *          - ERROR: not applicable
1389   */
1390 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1391 {
1392   /* Check the parameters */
1393   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1394   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1395   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1396   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1397   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1398
1399   /* Disable the Channel 3: Reset the CC3E Bit */
1400   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1401
1402   /* Select the Input and set the filter and the prescaler value */
1403   MODIFY_REG(TIMx->CCMR2,
1404              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1405              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1406
1407   /* Select the Polarity and set the CC3E Bit */
1408   MODIFY_REG(TIMx->CCER,
1409              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1410              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1411
1412   return SUCCESS;
1413 }
1414
1415 /**
1416   * @brief  Configure the TIMx input channel 4.
1417   * @param  TIMx Timer Instance
1418   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1419   * @retval An ErrorStatus enumeration value:
1420   *          - SUCCESS: TIMx registers are de-initialized
1421   *          - ERROR: not applicable
1422   */
1423 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1424 {
1425   /* Check the parameters */
1426   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1427   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1428   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1429   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1430   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1431
1432   /* Disable the Channel 4: Reset the CC4E Bit */
1433   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1434
1435   /* Select the Input and set the filter and the prescaler value */
1436   MODIFY_REG(TIMx->CCMR2,
1437              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1438              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1439
1440   /* Select the Polarity and set the CC2E Bit */
1441   MODIFY_REG(TIMx->CCER,
1442              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1443              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1444
1445   return SUCCESS;
1446 }
1447
1448
1449 /**
1450   * @}
1451   */
1452
1453 /**
1454   * @}
1455   */
1456
1457 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 || TIM18 || TIM19 || TIM20 */
1458
1459 /**
1460   * @}
1461   */
1462
1463 #endif /* USE_FULL_LL_DRIVER */
1464
1465 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/