lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_hal.h
   4   * @author  MCD Application Team
   5   * @brief   This file contains all the functions prototypes for the HAL
   6   *          module driver.
   7   ******************************************************************************
   8   * @attention
   9   *
  10   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
  11   * All rights reserved.</center></h2>
  12   *
  13   * This software component is licensed by ST under BSD 3-Clause license,
  14   * the "License"; You may not use this file except in compliance with the
  15   * License. You may obtain a copy of the License at:
  16   *                        opensource.org/licenses/BSD-3-Clause
  17   *
  18   ******************************************************************************
  19   */
  20
  21 /* Define to prevent recursive inclusion -------------------------------------*/
  22 #ifndef STM32G4xx_HAL_H
  23 #define STM32G4xx_HAL_H
  24
  25 #ifdef __cplusplus
  26 extern "C" {
  27 #endif
  28
  29 /* Includes ------------------------------------------------------------------*/
  30 #include "stm32g4xx_hal_conf.h"
  31
  32 /** @addtogroup STM32G4xx_HAL_Driver
  33   * @{
  34   */
  35
  36 /** @addtogroup HAL HAL
  37   * @{
  38   */
  39
  40 /* Exported types ------------------------------------------------------------*/
  41 /* Exported constants --------------------------------------------------------*/
  42
  43 /** @defgroup HAL_Exported_Constants HAL Exported Constants
  44   * @{
  45   */
  46
  47 /** @defgroup HAL_TICK_FREQ Tick Frequency
  48   * @{
  49   */
  50 #define HAL_TICK_FREQ_10HZ         100U
  51 #define HAL_TICK_FREQ_100HZ        10U
  52 #define HAL_TICK_FREQ_1KHZ         1U
  53 #define HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ
  54
  55 /**
  56   * @}
  57   */
  58
  59 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
  60   * @{
  61   */
  62
  63 /** @defgroup SYSCFG_BootMode Boot Mode
  64   * @{
  65   */
  66 #define SYSCFG_BOOT_MAINFLASH          0x00000000U
  67 #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMMEMRMP_MODE_0
  68
  69 #if defined (FMC_BANK1)
  70 #define SYSCFG_BOOT_FMC                SYSCFG_MEMMEMRMP_MODE_1
  71 #endif /* FMC_BANK1 */
  72
  73 #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
  74
  75 #if defined (QUADSPI)
  76 #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
  77 #endif /* QUADSPI */
  78
  79 /**
  80   * @}
  81   */
  82
  83 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
  84   * @{
  85   */
  86 #define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
  87 #define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
  88 #define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
  89 #define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
  90 #define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
  91 #define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
  92
  93 /**
  94   * @}
  95   */
  96
  97 /** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
  98   * @{
  99   */
 100 #define SYSCFG_CCMSRAMWRP_PAGE0          SYSCFG_SWPR_PAGE0  /*!< CCMSRAM Write protection page 0 */
 101 #define SYSCFG_CCMSRAMWRP_PAGE1          SYSCFG_SWPR_PAGE1  /*!< CCMSRAM Write protection page 1 */
 102 #define SYSCFG_CCMSRAMWRP_PAGE2          SYSCFG_SWPR_PAGE2  /*!< CCMSRAM Write protection page 2 */
 103 #define SYSCFG_CCMSRAMWRP_PAGE3          SYSCFG_SWPR_PAGE3  /*!< CCMSRAM Write protection page 3 */
 104 #define SYSCFG_CCMSRAMWRP_PAGE4          SYSCFG_SWPR_PAGE4  /*!< CCMSRAM Write protection page 4 */
 105 #define SYSCFG_CCMSRAMWRP_PAGE5          SYSCFG_SWPR_PAGE5  /*!< CCMSRAM Write protection page 5 */
 106 #define SYSCFG_CCMSRAMWRP_PAGE6          SYSCFG_SWPR_PAGE6  /*!< CCMSRAM Write protection page 6 */
 107 #define SYSCFG_CCMSRAMWRP_PAGE7          SYSCFG_SWPR_PAGE7  /*!< CCMSRAM Write protection page 7 */
 108 #define SYSCFG_CCMSRAMWRP_PAGE8          SYSCFG_SWPR_PAGE8  /*!< CCMSRAM Write protection page 8 */
 109 #define SYSCFG_CCMSRAMWRP_PAGE9          SYSCFG_SWPR_PAGE9  /*!< CCMSRAM Write protection page 9 */
 110 #define SYSCFG_CCMSRAMWRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
 111 #define SYSCFG_CCMSRAMWRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
 112 #define SYSCFG_CCMSRAMWRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
 113 #define SYSCFG_CCMSRAMWRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
 114 #define SYSCFG_CCMSRAMWRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
 115 #define SYSCFG_CCMSRAMWRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
 116 #define SYSCFG_CCMSRAMWRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
 117 #define SYSCFG_CCMSRAMWRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
 118 #define SYSCFG_CCMSRAMWRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
 119 #define SYSCFG_CCMSRAMWRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
 120 #define SYSCFG_CCMSRAMWRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
 121 #define SYSCFG_CCMSRAMWRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
 122 #define SYSCFG_CCMSRAMWRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
 123 #define SYSCFG_CCMSRAMWRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
 124 #define SYSCFG_CCMSRAMWRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
 125 #define SYSCFG_CCMSRAMWRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
 126 #define SYSCFG_CCMSRAMWRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
 127 #define SYSCFG_CCMSRAMWRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
 128 #define SYSCFG_CCMSRAMWRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
 129 #define SYSCFG_CCMSRAMWRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
 130 #define SYSCFG_CCMSRAMWRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
 131 #define SYSCFG_CCMSRAMWRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
 132
 133 /**
 134   * @}
 135   */
 136
 137 #if defined(VREFBUF)
 138 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
 139   * @{
 140   */
 141 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
 142 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS_0      /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V)   */
 143 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2  VREFBUF_CSR_VRS_1      /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V)   */
 144
 145 /**
 146   * @}
 147   */
 148
 149 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
 150   * @{
 151   */
 152 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  0x00000000U       /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
 153 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ       /*!< VREF_plus pin is high impedance */
 154
 155 /**
 156   * @}
 157   */
 158 #endif /* VREFBUF */
 159
 160 /** @defgroup SYSCFG_flags_definition Flags
 161   * @{
 162   */
 163
 164 #define SYSCFG_FLAG_SRAM_PE             SYSCFG_CFGR2_SPF       /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
 165 #define SYSCFG_FLAG_CCMSRAM_BUSY        SYSCFG_SCSR_CCMBSY     /*!< CCMSRAM busy by erase operation */
 166
 167 /**
 168   * @}
 169   */
 170
 171 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
 172   * @{
 173   */
 174
 175 /** @brief  Fast-mode Plus driving capability on a specific GPIO
 176   */
 177 #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
 178 #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
 179 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
 180 #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
 181 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
 182 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
 183 #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
 184 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
 185
 186 /**
 187   * @}
 188   */
 189
 190 /**
 191   * @}
 192   */
 193
 194 /**
 195   * @}
 196   */
 197
 198 /* Exported macros -----------------------------------------------------------*/
 199
 200 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
 201   * @{
 202   */
 203
 204 /** @brief  Freeze/Unfreeze Peripherals in Debug mode
 205   */
 206 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
 207 #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
 208 #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
 209 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
 210
 211 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
 212 #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
 213 #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
 214 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
 215
 216 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
 217 #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
 218 #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
 219 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
 220
 221 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
 222 #define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
 223 #define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
 224 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
 225
 226 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
 227 #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
 228 #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
 229 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
 230
 231 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
 232 #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
 233 #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
 234 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
 235
 236 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
 237 #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
 238 #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
 239 #endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
 240
 241 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
 242 #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
 243 #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
 244 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
 245
 246 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
 247 #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
 248 #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
 249 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
 250
 251 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
 252 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
 253 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
 254 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
 255
 256 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
 257 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
 258 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
 259 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
 260
 261 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
 262 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
 263 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
 264 #endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
 265
 266 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
 267 #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
 268 #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
 269 #endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
 270
 271 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
 272 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
 273 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
 274 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
 275
 276 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
 277 #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
 278 #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
 279 #endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
 280
 281 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
 282 #define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
 283 #define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
 284 #endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
 285
 286 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
 287 #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
 288 #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
 289 #endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
 290
 291 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
 292 #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
 293 #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
 294 #endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
 295
 296 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
 297 #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
 298 #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
 299 #endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
 300
 301 #if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
 302 #define __HAL_DBGMCU_FREEZE_TIM20()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
 303 #define __HAL_DBGMCU_UNFREEZE_TIM20()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
 304 #endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
 305
 306 #if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
 307 #define __HAL_DBGMCU_FREEZE_HRTIM1()         SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
 308 #define __HAL_DBGMCU_UNFREEZE_HRTIM1()       CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
 309 #endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
 310
 311 /**
 312   * @}
 313   */
 314
 315 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
 316   * @{
 317   */
 318
 319 /** @brief  Main Flash memory mapped at 0x00000000.
 320   */
 321 #define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
 322
 323 /** @brief  System Flash memory mapped at 0x00000000.
 324   */
 325 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
 326
 327 /** @brief  Embedded SRAM mapped at 0x00000000.
 328   */
 329 #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
 330
 331 #if defined (FMC_BANK1)
 332 /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
 333   */
 334 #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
 335 #endif /* FMC_BANK1 */
 336
 337 #if defined (QUADSPI)
 338 /** @brief  QUADSPI mapped at 0x00000000.
 339   */
 340 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
 341 #endif /* QUADSPI */
 342
 343 /**
 344   * @brief  Return the boot mode as configured by user.
 345   * @retval The boot mode as configured by user. The returned value can be one
 346   *         of the following values:
 347   *           @arg @ref SYSCFG_BOOT_MAINFLASH
 348   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
 349   *           @arg @ref SYSCFG_BOOT_FMC (*)
 350   *           @arg @ref SYSCFG_BOOT_QUADSPI (*)
 351   *           @arg @ref SYSCFG_BOOT_SRAM
 352   * @note   (*) availability depends on devices
 353   */
 354 #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
 355
 356 /** @brief  CCMSRAM page write protection enable macro
 357   * @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
 358   * @note   write protection can only be disabled by a system reset
 359   * @retval None
 360   */
 361 /* Legacy define */
 362 #define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE   __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
 363 #define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__)    do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
 364                                                                      SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
 365                                                                    }while(0)
 366
 367 /** @brief  CCMSRAM page write protection unlock prior to erase
 368   * @note   Writing a wrong key reactivates the write protection
 369   */
 370 #define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK()    do {SYSCFG->SKR = 0xCA;\
 371                                                   SYSCFG->SKR = 0x53;\
 372                                                 }while(0)
 373
 374 /** @brief  CCMSRAM erase
 375   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
 376   */
 377 #define __HAL_SYSCFG_CCMSRAM_ERASE()         SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
 378
 379 /** @brief  Floating Point Unit interrupt enable/disable macros
 380   * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
 381   */
 382 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
 383                                                                  SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
 384                                                                }while(0)
 385
 386 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
 387                                                                  CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
 388                                                                }while(0)
 389
 390 /** @brief  SYSCFG Break ECC lock.
 391   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
 392   * @note   The selected configuration is locked and can be unlocked only by system reset.
 393   */
 394 #define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
 395
 396 /** @brief  SYSCFG Break Cortex-M4 Lockup lock.
 397   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
 398   * @note   The selected configuration is locked and can be unlocked only by system reset.
 399   */
 400 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
 401
 402 /** @brief  SYSCFG Break PVD lock.
 403   *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
 404   * @note   The selected configuration is locked and can be unlocked only by system reset.
 405   */
 406 #define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
 407
 408 /** @brief  SYSCFG Break SRAM parity lock.
 409   *         Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
 410   * @note   The selected configuration is locked and can be unlocked by system reset.
 411   */
 412 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
 413
 414 /** @brief  Check SYSCFG flag is set or not.
 415   * @param  __FLAG__: specifies the flag to check.
 416   *         This parameter can be one of the following values:
 417   *            @arg @ref SYSCFG_FLAG_SRAM_PE   SRAM Parity Error Flag
 418   *            @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
 419   * @retval The new state of __FLAG__ (TRUE or FALSE).
 420   */
 421 #define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
 422                                                 & (__FLAG__))!= 0U) ? 1U : 0U)
 423
 424 /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
 425   */
 426 #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
 427
 428 /** @brief  Fast-mode Plus driving capability enable/disable macros
 429   * @param __FASTMODEPLUS__: This parameter can be a value of :
 430   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
 431   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
 432   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
 433   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
 434   */
 435 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
 436                                                                  SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
 437                                                                }while(0)
 438
 439 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
 440                                                                  CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
 441                                                                }while(0)
 442
 443 /**
 444   * @}
 445   */
 446
 447 /* Private macros ------------------------------------------------------------*/
 448 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
 449   * @{
 450   */
 451
 452 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
 453                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
 454                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
 455                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
 456                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
 457                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
 458
 459 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
 460                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
 461                                             ((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY)    || \
 462                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
 463
 464 #if (CCMSRAM_SIZE == 0x00008000UL)
 465 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  ((__PAGE__) > 0U)
 466 #elif (CCMSRAM_SIZE == 0x00002800UL)
 467 #define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__)  (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
 468 #endif /* CCMSRAM_SIZE */
 469
 470 #if defined(VREFBUF)
 471 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
 472                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
 473                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
 474
 475 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
 476                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
 477
 478 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
 479 #endif /* VREFBUF */
 480
 481 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
 482 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
 483                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
 484                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
 485                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
 486 #elif defined(SYSCFG_FASTMODEPLUS_PB8)
 487 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
 488                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
 489                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
 490 #elif defined(SYSCFG_FASTMODEPLUS_PB9)
 491 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
 492                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
 493                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
 494 #else
 495 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
 496                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
 497 #endif /* SYSCFG_FASTMODEPLUS_PB */
 498 /**
 499   * @}
 500   */
 501
 502 /** @defgroup HAL_Private_Macros HAL Private Macros
 503   * @{
 504   */
 505 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
 506                            ((FREQ) == HAL_TICK_FREQ_100HZ) || \
 507                            ((FREQ) == HAL_TICK_FREQ_1KHZ))
 508 /**
 509   * @}
 510   */
 511
 512 /* Exported functions --------------------------------------------------------*/
 513
 514 /** @addtogroup HAL_Exported_Functions
 515   * @{
 516   */
 517
 518 /** @addtogroup HAL_Exported_Functions_Group1
 519   * @{
 520   */
 521 /* Initialization and Configuration functions  ******************************/
 522 HAL_StatusTypeDef HAL_Init(void);
 523 HAL_StatusTypeDef HAL_DeInit(void);
 524 void HAL_MspInit(void);
 525 void HAL_MspDeInit(void);
 526 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
 527
 528 /**
 529   * @}
 530   */
 531
 532 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
 533   * @{
 534   */
 535
 536 /* Peripheral Control functions  ************************************************/
 537 void HAL_IncTick(void);
 538 void HAL_Delay(uint32_t Delay);
 539 uint32_t HAL_GetTick(void);
 540 uint32_t HAL_GetTickPrio(void);
 541 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
 542 uint32_t HAL_GetTickFreq(void);
 543 void HAL_SuspendTick(void);
 544 void HAL_ResumeTick(void);
 545 uint32_t HAL_GetHalVersion(void);
 546 uint32_t HAL_GetREVID(void);
 547 uint32_t HAL_GetDEVID(void);
 548
 549 /**
 550   * @}
 551   */
 552
 553 /** @addtogroup HAL_Exported_Functions_Group3
 554   * @{
 555   */
 556
 557 /* DBGMCU Peripheral Control functions  *****************************************/
 558 void HAL_DBGMCU_EnableDBGSleepMode(void);
 559 void HAL_DBGMCU_DisableDBGSleepMode(void);
 560 void HAL_DBGMCU_EnableDBGStopMode(void);
 561 void HAL_DBGMCU_DisableDBGStopMode(void);
 562 void HAL_DBGMCU_EnableDBGStandbyMode(void);
 563 void HAL_DBGMCU_DisableDBGStandbyMode(void);
 564
 565 /**
 566   * @}
 567   */
 568
 569 /* Exported variables ---------------------------------------------------------*/
 570 /** @addtogroup HAL_Exported_Variables
 571   * @{
 572   */
 573 extern __IO uint32_t uwTick;
 574 extern uint32_t uwTickPrio;
 575 extern uint32_t uwTickFreq;
 576 /**
 577   * @}
 578   */
 579
 580 /** @addtogroup HAL_Exported_Functions_Group4
 581   * @{
 582   */
 583
 584 /* SYSCFG Control functions  ****************************************************/
 585 void HAL_SYSCFG_CCMSRAMErase(void);
 586 void HAL_SYSCFG_EnableMemorySwappingBank(void);
 587 void HAL_SYSCFG_DisableMemorySwappingBank(void);
 588
 589 #if defined(VREFBUF)
 590 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
 591 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
 592 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
 593 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
 594 void HAL_SYSCFG_DisableVREFBUF(void);
 595 #endif /* VREFBUF */
 596
 597 void HAL_SYSCFG_EnableIOSwitchBooster(void);
 598 void HAL_SYSCFG_DisableIOSwitchBooster(void);
 599 void HAL_SYSCFG_EnableIOSwitchVDD(void);
 600 void HAL_SYSCFG_DisableIOSwitchVDD(void);
 601
 602 void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
 603
 604 /**
 605   * @}
 606   */
 607
 608 /**
 609   * @}
 610   */
 611
 612 /**
 613   * @}
 614   */
 615
 616 /**
 617   * @}
 618   */
 619
 620 #ifdef __cplusplus
 621 }
 622 #endif
 623
 624 #endif /* STM32G4xx_HAL_H */
 625
 626 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/