?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_hal_adc.h
blobf301d01885ce85d22477e079d34ac324ef24b2cd
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_HAL_ADC_H
22 #define STM32G4xx_HAL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx_hal_def.h"
30
31 /* Include low level driver */
32 #include "stm32g4xx_ll_adc.h"
33
34 /** @addtogroup STM32G4xx_HAL_Driver
35 * @{
36 */
37
38 /** @addtogroup ADC
39 * @{
40 */
41
42 /* Exported types ------------------------------------------------------------*/
43 /** @defgroup ADC_Exported_Types ADC Exported Types
44 * @{
45 */
46
47 /**
48 * @brief ADC group regular oversampling structure definition
49 */
50 typedef struct
51 {
52 uint32_t Ratio; /*!< Configures the oversampling ratio.
53 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
54
55 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
56 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
57
58 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
59 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
60
61 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
62 The oversampling is either temporary stopped or reset upon an injected
63 sequence interruption.
64 If oversampling is enabled on both regular and injected groups, this parameter
65 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
66 (the oversampling buffer is zeroed during injection sequence).
67 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
68
69 } ADC_OversamplingTypeDef;
70
71 /**
72 * @brief Structure definition of ADC instance and ADC group regular.
73 * @note Parameters of this structure are shared within 2 scopes:
74 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
75 * GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
76 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
77 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode.
78 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
79 * ADC state can be either:
80 * - For all parameters: ADC disabled
81 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
82 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
83 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
84 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter
85 * (which fulfills the ADC state condition) on the fly).
86 */
87 typedef struct
88 {
89 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
90 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
91 Note: The ADC clock configuration is common to all ADC instances.
92 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
93 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
94 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
95 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
96 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
97 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
98 Note: This parameter can be modified only if all ADC instances are disabled. */
99
100 uint32_t Resolution; /*!< Configure the ADC resolution.
101 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
102
103 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
104 Refer to reference manual for alignments formats versus resolutions.
105 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
106
107 uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula:
108 DATA = DATA(raw) * (gain compensation coef) / 4096
109 2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa
110 Gain step is 1/4096 = 0.000244
111 Gain range is 0.0000 to 3.999756
112 This parameter value can be
113 0 Gain compensation will be disabled and coefficient set to 0
114 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value
115
116 Note: Gain compensation when enabled is appied to all channels. */
117
118 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
119 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
120 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
121 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
122 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
123 Scan direction is upward: from rank 1 to rank 'n'.
124 This parameter can be a value of @ref ADC_Scan_mode */
125
126 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
127 This parameter can be a value of @ref ADC_EOCSelection. */
128
129 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
130 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
131 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
132 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
133 for low frequency applications.
134 This parameter can be set to ENABLE or DISABLE.
135 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
136 to free the IRQ vector sequencer.
137 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
138 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
139 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
140
141 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
142 after the first ADC conversion start trigger occurred (software start or external trigger).
143 This parameter can be set to ENABLE or DISABLE. */
144
145 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
146 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
147 This parameter must be a number between Min_Data = 1 and Max_Data = 16.
148 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
149 continuous mode or external trigger that could launch a conversion). */
150
151 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
152 (main sequence subdivided in successive parts).
153 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
154 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
155 This parameter can be set to ENABLE or DISABLE. */
156
157 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
158 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
159 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
160
161 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
162 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
163 This parameter can be a value of @ref ADC_regular_external_trigger_source.
164 Caution: external trigger source is common to all ADC instances. */
165
166 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
167 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
168 This parameter can be a value of @ref ADC_regular_external_trigger_edge */
169
170 uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
171 This parameter can be a value of @ref ADC_regular_sampling_mode */
172
173 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
174 or in continuous mode (DMA transfer unlimited, whatever number of conversions).
175 This parameter can be set to ENABLE or DISABLE.
176 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
177
178 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
179 This parameter applies to ADC group regular only.
180 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
181 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
182 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
183 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
184 Note: Error reporting with respect to the conversion mode:
185 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
186 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
187 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
188
189 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
190 This parameter can be set to ENABLE or DISABLE.
191 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
192
193 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
194 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
195
196 } ADC_InitTypeDef;
197
198 /**
199 * @brief Structure definition of ADC channel for regular group
200 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
201 * ADC state can be either:
202 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
203 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
204 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
205 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
206 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
207 * on the fly).
208 */
209 typedef struct
210 {
211 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
212 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
213 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
214
215 uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
216 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
217 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
218 the new channel setting (or parameter number of conversions adjusted) */
219
220 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
221 Unit: ADC clock cycles
222 Conversion time is the addition of sampling time and processing time
223 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
224 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
225 Caution: This parameter applies to a channel that can be used into regular and/or injected group.
226 It overwrites the last setting.
227 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
228 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
229 Refer to device datasheet for timings values. */
230
231 uint32_t SingleDiff; /*!< Select single-ended or differential input.
232 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
233 Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
234 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
235 Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
236 It overwrites the last setting.
237 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
238 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
239 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
240 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
241 of another parameter update on the fly) */
242
243 uint32_t OffsetNumber; /*!< Select the offset number
244 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
245 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
246
247 uint32_t Offset; /*!< Define the offset to be applied on the raw converted data.
248 Offset value must be a positive number.
249 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
250 0x3FF, 0xFF or 0x3F respectively.
251 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
252 without continuous mode or external trigger that could launch a conversion). */
253
254 uint32_t OffsetSign; /*!< Define if the offset should be substracted (negative sign) or added (positive sign) from or to the raw converted data.
255 This parameter can be a value of @ref ADCEx_OffsetSign.
256 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
257 without continuous mode or external trigger that could launch a conversion). */
258 FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
259 This parameter value can be ENABLE or DISABLE.
260 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
261 without continuous mode or external trigger that could launch a conversion). */
262
263 } ADC_ChannelConfTypeDef;
264
265 /**
266 * @brief Structure definition of ADC analog watchdog
267 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
268 * ADC state can be either:
269 * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
270 * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups.
271 */
272 typedef struct
273 {
274 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
275 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
276 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
277 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
278
279 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
280 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
281 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
282 This parameter can be a value of @ref ADC_analog_watchdog_mode. */
283
284 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
285 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
286 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
287 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
288
289 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
290 This parameter can be set to ENABLE or DISABLE */
291
292 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
293 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
294 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
295 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
296 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
297 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
298 impacted: the comparison of analog watchdog thresholds is done on
299 oversampling final computation (after ratio and shift application):
300 ADC data register bitfield [15:4] (12 most significant bits). */
301
302 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
303 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
304 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
305 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
306 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
307 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
308 impacted: the comparison of analog watchdog thresholds is done on
309 oversampling final computation (after ratio and shift application):
310 ADC data register bitfield [15:4] (12 most significant bits). */
311
312 uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
313 Before setting flag or raising interrupt, analog watchdog can wait to have several
314 consecutive out-of-window samples. This parameter allows to configure this number.
315 This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE.
316 This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
317 } ADC_AnalogWDGConfTypeDef;
318
319 /**
320 * @brief ADC group injected contexts queue configuration
321 * @note Structure intended to be used only through structure "ADC_HandleTypeDef"
322 */
323 typedef struct
324 {
325 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
326 HAL_ADCEx_InjectedConfigChannel() call to finally initialize
327 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
328
329 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
330 } ADC_InjectionConfigTypeDef;
331
332 /** @defgroup ADC_States ADC States
333 * @{
334 */
335
336 /**
337 * @brief HAL ADC state machine: ADC states definition (bitfields)
338 * @note ADC state machine is managed by bitfields, state must be compared
339 * with bit by bit.
340 * For example:
341 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
342 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
343 */
344 /* States of ADC global scope */
345 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
346 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
347 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
348 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
349
350 /* States of ADC errors */
351 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
352 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
353 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
354
355 /* States of ADC group regular */
356 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
357 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
358 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
359 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
360 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
361
362 /* States of ADC group injected */
363 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
364 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
365 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
366 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
367
368 /* States of ADC analog watchdogs */
369 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
370 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
371 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
372
373 /* States of ADC multi-mode */
374 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
375
376 /**
377 * @}
378 */
379
380 /**
381 * @brief ADC handle Structure definition
382 */
383 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
384 typedef struct __ADC_HandleTypeDef
385 #else
386 typedef struct
387 #endif
388 {
389 ADC_TypeDef *Instance; /*!< Register base address */
390 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
391 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
392 HAL_LockTypeDef Lock; /*!< ADC locking object */
393 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
394 __IO uint32_t ErrorCode; /*!< ADC Error code */
395 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
396 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
397 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
398 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
399 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
400 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
401 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
402 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
403 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
404 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
405 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
406 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
407 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
408 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
409 } ADC_HandleTypeDef;
410
411 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
412 /**
413 * @brief HAL ADC Callback ID enumeration definition
414 */
415 typedef enum
416 {
417 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
418 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
419 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
420 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
421 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
422 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
423 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
424 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
425 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
426 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
427 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
428 } HAL_ADC_CallbackIDTypeDef;
429
430 /**
431 * @brief HAL ADC Callback pointer definition
432 */
433 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
434
435 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
436
437 /**
438 * @}
439 */
440
441
442 /* Exported constants --------------------------------------------------------*/
443
444 /** @defgroup ADC_Exported_Constants ADC Exported Constants
445 * @{
446 */
447
448 /** @defgroup ADC_Error_Code ADC Error Code
449 * @{
450 */
451 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
452 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
453 enable/disable, erroneous state, ...) */
454 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
455 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
456 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
457 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
458 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
459 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
460 /**
461 * @}
462 */
463
464 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
465 * @{
466 */
467 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
468 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
469 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
470
471 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
472 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
473 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
474 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
475 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
476 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
477 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
478 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
479 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
480 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
481 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
482 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
483 /**
484 * @}
485 */
486
487 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
488 * @{
489 */
490 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
491 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
492 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
493 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
494 /**
495 * @}
496 */
497
498 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
499 * @{
500 */
501 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
502 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
503 /**
504 * @}
505 */
506
507 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
508 * @{
509 */
510 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
511 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
512 /**
513 * @}
514 */
515
516 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
517 * @{
518 */
519 /* ADC group regular trigger sources for all ADC instances */
520 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
521 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
522 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
523 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
524 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
525 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
526 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
527 #define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
528 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
529 #define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
530 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
531 #define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
532 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
533 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
534 #define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
535 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
536 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
537 #define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
538 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
539 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
540 #define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
541 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
542 #define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
543 #define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
544 #define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
545 #define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
546 #define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
547 #define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */
548 #define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */
549 #define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */
550 #define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */
551 #define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */
552 #define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */
553 #define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */
554 #define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */
555 #define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */
556 #define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */
557 #define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */
558 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
559 #define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
560 /**
561 * @}
562 */
563
564 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
565 * @{
566 */
567 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
568 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
569 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
570 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
571 /**
572 * @}
573 */
574
575 /** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
576 * @{
577 */
578 #define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
579 #define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
580 Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
581 #define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
582 Trigger rising edge = start sampling
583 Trigger falling edge = stop sampling and start conversion */
584 /**
585 * @}
586 */
587
588 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
589 * @{
590 */
591 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
592 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
593 /**
594 * @}
595 */
596
597 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
598 * @{
599 */
600 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
601 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
602 /**
603 * @}
604 */
605
606 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
607 * @{
608 */
609 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
610 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
611 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
612 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
613 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
614 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
615 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
616 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
617 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
618 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
619 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
620 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
621 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
622 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
623 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
624 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
625 /**
626 * @}
627 */
628
629 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
630 * @{
631 */
632 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
633 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
634 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
635 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
636 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
637 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
638 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
639 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
640 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
641 /**
642 * @}
643 */
644
645 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
646 * @{
647 */
648 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
649 /* all ADC instances (refer to Reference Manual). */
650 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
651 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
652 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
653 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
654 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
655 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
656 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
657 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
658 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
659 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
660 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
661 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
662 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
663 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
664 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
665 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
666 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
667 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
668 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
669 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */
670 #define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */
671 #define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
672 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
673 #define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */
674 #define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */
675 #define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */
676 #define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
677 #define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
678 #define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
679 #define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */
680 /**
681 * @}
682 */
683
684 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
685 * @{
686 */
687 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
688 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
689 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
690 /**
691 * @}
692 */
693
694 /** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
695 * @{
696 */
697 #define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
698 #define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
699 #define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
700 #define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
701 #define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
702 #define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
703 #define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
704 #define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
705 /**
706 * @}
707 */
708
709 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
710 * @{
711 */
712 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
713 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
714 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
715 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
716 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
717 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
718 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
719 /**
720 * @}
721 */
722
723 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
724 * @{
725 */
726 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
727 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
728 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
729 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
730 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
731 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
732 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
733 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
734 /**
735 * @}
736 */
737
738 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
739 * @{
740 */
741 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
742 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
743 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
744 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
745 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
746 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
747 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
748 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
749 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
750 /**
751 * @}
752 */
753
754 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
755 * @{
756 */
757 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
758 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
759 /**
760 * @}
761 */
762
763 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
764 * @{
765 */
766 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
767 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
768 /**
769 * @}
770 */
771
772
773 /** @defgroup ADC_Event_type ADC Event type
774 * @{
775 */
776 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
777 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
778 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
779 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
780 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
781 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
782 /**
783 * @}
784 */
785 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
786
787 /** @defgroup ADC_interrupts_definition ADC interrupts definition
788 * @{
789 */
790 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
791 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
792 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
793 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
794 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
795 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
796 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
797 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
798 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
799 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
800 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
801
802 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
803
804 /**
805 * @}
806 */
807
808 /** @defgroup ADC_flags_definition ADC flags definition
809 * @{
810 */
811 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
812 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
813 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
814 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
815 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
816 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
817 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
818 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
819 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
820 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
821 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
822
823 /**
824 * @}
825 */
826
827 /**
828 * @}
829 */
830
831 /* Private macro -------------------------------------------------------------*/
832
833 /** @defgroup ADC_Private_Macros ADC Private Macros
834 * @{
835 */
836 /* Macro reserved for internal HAL driver usage, not intended to be used in */
837 /* code of final user. */
838
839 /**
840 * @brief Return resolution bits in CFGR register RES[1:0] field.
841 * @param __HANDLE__ ADC handle
842 * @retval Value of bitfield RES in CFGR register.
843 */
844 #define ADC_GET_RESOLUTION(__HANDLE__) \
845 (LL_ADC_GetResolution((__HANDLE__)->Instance))
846
847 /**
848 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
849 * @param __HANDLE__ ADC handle
850 * @retval None
851 */
852 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
853
854 /**
855 * @brief Simultaneously clear and set specific bits of the handle State.
856 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
857 * the first parameter is the ADC handle State, the second parameter is the
858 * bit field to clear, the third and last parameter is the bit field to set.
859 * @retval None
860 */
861 #define ADC_STATE_CLR_SET MODIFY_REG
862
863 /**
864 * @brief Verify that a given value is aligned with the ADC resolution range.
865 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
866 * @param __ADC_VALUE__ value checked against the resolution.
867 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
868 */
869 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
870 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
871
872 /**
873 * @brief Verify the length of the scheduled regular conversions group.
874 * @param __LENGTH__ number of programmed conversions.
875 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
876 */
877 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
878
879
880 /**
881 * @brief Verify the number of scheduled regular conversions in discontinuous mode.
882 * @param NUMBER number of scheduled regular conversions in discontinuous mode.
883 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
884 */
885 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
886
887
888 /**
889 * @brief Verify the ADC clock setting.
890 * @param __ADC_CLOCK__ programmed ADC clock.
891 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
892 */
893 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
894 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
895 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
896 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
897 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
898 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
899 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
900 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
901 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
902 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
903 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
904 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
905 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
906 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
907 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
908
909 /**
910 * @brief Verify the ADC resolution setting.
911 * @param __RESOLUTION__ programmed ADC resolution.
912 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
913 */
914 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
915 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
916 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
917 ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
918
919 /**
920 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
921 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
922 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
923 */
924 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
925 ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
926
927 /**
928 * @brief Verify the ADC converted data alignment.
929 * @param __ALIGN__ programmed ADC converted data alignment.
930 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
931 */
932 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
933 ((__ALIGN__) == ADC_DATAALIGN_LEFT) )
934
935 /**
936 * @brief Verify the ADC gain compensation.
937 * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
938 * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
939 */
940 #define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
941
942 /**
943 * @brief Verify the ADC scan mode.
944 * @param __SCAN_MODE__ programmed ADC scan mode.
945 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
946 */
947 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
948 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
949
950 /**
951 * @brief Verify the ADC edge trigger setting for regular group.
952 * @param __EDGE__ programmed ADC edge trigger setting.
953 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
954 */
955 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
956 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
957 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
958 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
959
960 /**
961 * @brief Verify the ADC regular conversions external trigger.
962 * @param __HANDLE__ ADC handle
963 * @param __REGTRIG__ programmed ADC regular conversions external trigger.
964 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
965 */
966 #if defined(STM32G474xx) || defined(STM32G484xx)
967 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
968 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
969 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
970 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
971 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
972 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
973 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
974 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
975 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
976 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
977 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
978 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
979 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
980 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
981 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \
982 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \
983 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \
984 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \
985 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \
986 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \
987 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \
988 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \
989 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
990 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
991 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
992 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
993 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
994 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
995 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
996 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
997 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
998 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
999 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
1000 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
1001 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
1002 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
1003 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
1004 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
1005 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \
1006 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
1007 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
1008 ((__REGTRIG__) == ADC_SOFTWARE_START) )
1009 #elif defined(STM32G473xx)
1010 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
1011 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
1012 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
1013 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
1014 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
1015 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
1016 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
1017 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
1018 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
1019 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
1020 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
1021 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
1022 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
1023 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
1024 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
1025 ((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
1026 (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
1027 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
1028 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
1029 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
1030 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
1031 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
1032 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
1033 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
1034 ((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
1035 (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
1036 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
1037 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
1038 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
1039 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
1040 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
1041 ((__REGTRIG__) == ADC_SOFTWARE_START) )
1042 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
1043 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
1044 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
1045 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
1046 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
1047 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
1048 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
1049 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
1050 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
1051 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
1052 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
1053 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
1054 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
1055 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
1056 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
1057 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
1058 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
1059 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
1060 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
1061 ((__REGTRIG__) == ADC_SOFTWARE_START) )
1062 #endif
1063
1064 /**
1065 * @brief Verify the ADC regular conversions external trigger.
1066 * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
1067 * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
1068 */
1069 #define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
1070 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
1071 ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
1072
1073 /**
1074 * @brief Verify the ADC regular conversions check for converted data availability.
1075 * @param __EOC_SELECTION__ converted data availability check.
1076 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
1077 */
1078 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
1079 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
1080
1081 /**
1082 * @brief Verify the ADC regular conversions overrun handling.
1083 * @param __OVR__ ADC regular conversions overrun handling.
1084 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
1085 */
1086 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
1087 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
1088
1089 /**
1090 * @brief Verify the ADC conversions sampling time.
1091 * @param __TIME__ ADC conversions sampling time.
1092 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
1093 */
1094 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
1095 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
1096 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
1097 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
1098 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
1099 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
1100 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
1101 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
1102 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
1103
1104 /**
1105 * @brief Verify the ADC regular channel setting.
1106 * @param __CHANNEL__ programmed ADC regular channel.
1107 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
1108 */
1109 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
1110 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
1111 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
1112 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
1113 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
1114 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
1115 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
1116 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
1117 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
1118 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
1119 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
1120 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
1121 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
1122 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
1123 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
1124 ((__CHANNEL__) == ADC_REGULAR_RANK_16) )
1125
1126 /**
1127 * @}
1128 */
1129
1130
1131 /* Private constants ---------------------------------------------------------*/
1132
1133 /** @defgroup ADC_Private_Constants ADC Private Constants
1134 * @{
1135 */
1136
1137 /* Fixed timeout values for ADC conversion (including sampling time) */
1138 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
1139 /* Maximum conversion time is 12.5 + Maximum sampling time */
1140 /* or 12.5 + 640.5 = 653 ADC clock cycles */
1141 /* Minimum ADC Clock frequency is 0.14 MHz */
1142 /* Maximum conversion time is */
1143 /* 653 / 0.14 MHz = 4.66 ms */
1144 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
1145
1146 /* Delay for temperature sensor stabilization time. */
1147 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
1148 /* Unit: us */
1149 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
1150
1151 /**
1152 * @}
1153 */
1154
1155 /* Exported macro ------------------------------------------------------------*/
1156
1157 /** @defgroup ADC_Exported_Macros ADC Exported Macros
1158 * @{
1159 */
1160 /* Macro for internal HAL driver usage, and possibly can be used into code of */
1161 /* final user. */
1162
1163 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
1164 * @{
1165 */
1166
1167 /** @brief Reset ADC handle state.
1168 * @param __HANDLE__ ADC handle
1169 * @retval None
1170 */
1171 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1172 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1173 do{ \
1174 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
1175 (__HANDLE__)->MspInitCallback = NULL; \
1176 (__HANDLE__)->MspDeInitCallback = NULL; \
1177 } while(0)
1178 #else
1179 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
1180 ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
1181 #endif
1182
1183 /**
1184 * @brief Enable ADC interrupt.
1185 * @param __HANDLE__ ADC handle
1186 * @param __INTERRUPT__ ADC Interrupt
1187 * This parameter can be one of the following values:
1188 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1189 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1190 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1191 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1192 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1193 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1194 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1195 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1196 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1197 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1198 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1199 * @retval None
1200 */
1201 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1202 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
1203
1204 /**
1205 * @brief Disable ADC interrupt.
1206 * @param __HANDLE__ ADC handle
1207 * @param __INTERRUPT__ ADC Interrupt
1208 * This parameter can be one of the following values:
1209 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1210 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1211 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1212 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1213 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1214 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1215 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1216 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1217 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1218 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1219 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1220 * @retval None
1221 */
1222 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1223 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
1224
1225 /** @brief Checks if the specified ADC interrupt source is enabled or disabled.
1226 * @param __HANDLE__ ADC handle
1227 * @param __INTERRUPT__ ADC interrupt source to check
1228 * This parameter can be one of the following values:
1229 * @arg @ref ADC_IT_RDY ADC Ready interrupt source
1230 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
1231 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
1232 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
1233 * @arg @ref ADC_IT_OVR ADC overrun interrupt source
1234 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
1235 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
1236 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
1237 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
1238 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
1239 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
1240 * @retval State of interruption (SET or RESET)
1241 */
1242 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
1243 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
1244
1245 /**
1246 * @brief Check whether the specified ADC flag is set or not.
1247 * @param __HANDLE__ ADC handle
1248 * @param __FLAG__ ADC flag
1249 * This parameter can be one of the following values:
1250 * @arg @ref ADC_FLAG_RDY ADC Ready flag
1251 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1252 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1253 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1254 * @arg @ref ADC_FLAG_OVR ADC overrun flag
1255 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
1256 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
1257 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1258 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1259 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1260 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
1261 * @retval State of flag (TRUE or FALSE).
1262 */
1263 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
1264 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
1265
1266 /**
1267 * @brief Clear the specified ADC flag.
1268 * @param __HANDLE__ ADC handle
1269 * @param __FLAG__ ADC flag
1270 * This parameter can be one of the following values:
1271 * @arg @ref ADC_FLAG_RDY ADC Ready flag
1272 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
1273 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
1274 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
1275 * @arg @ref ADC_FLAG_OVR ADC overrun flag
1276 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
1277 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
1278 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
1279 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
1280 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
1281 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
1282 * @retval None
1283 */
1284 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
1285 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1286 (((__HANDLE__)->Instance->ISR) = (__FLAG__))
1287
1288 /**
1289 * @}
1290 */
1291
1292 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
1293 * @{
1294 */
1295
1296 /**
1297 * @brief Helper macro to get ADC channel number in decimal format
1298 * from literals ADC_CHANNEL_x.
1299 * @note Example:
1300 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
1301 * will return decimal number "4".
1302 * @note The input can be a value from functions where a channel
1303 * number is returned, either defined with number
1304 * or with bitfield (only one bit must be set).
1305 * @param __CHANNEL__ This parameter can be one of the following values:
1306 * @arg @ref ADC_CHANNEL_0
1307 * @arg @ref ADC_CHANNEL_1 (8)
1308 * @arg @ref ADC_CHANNEL_2 (8)
1309 * @arg @ref ADC_CHANNEL_3 (8)
1310 * @arg @ref ADC_CHANNEL_4 (8)
1311 * @arg @ref ADC_CHANNEL_5 (8)
1312 * @arg @ref ADC_CHANNEL_6
1313 * @arg @ref ADC_CHANNEL_7
1314 * @arg @ref ADC_CHANNEL_8
1315 * @arg @ref ADC_CHANNEL_9
1316 * @arg @ref ADC_CHANNEL_10
1317 * @arg @ref ADC_CHANNEL_11
1318 * @arg @ref ADC_CHANNEL_12
1319 * @arg @ref ADC_CHANNEL_13
1320 * @arg @ref ADC_CHANNEL_14
1321 * @arg @ref ADC_CHANNEL_15
1322 * @arg @ref ADC_CHANNEL_16
1323 * @arg @ref ADC_CHANNEL_17
1324 * @arg @ref ADC_CHANNEL_18
1325 * @arg @ref ADC_CHANNEL_VREFINT (7)
1326 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1327 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1328 * @arg @ref ADC_CHANNEL_VBAT (6)
1329 * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
1330 * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
1331 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
1332 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
1333 * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
1334 * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
1335 * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
1336 *
1337 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1338 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1339 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1340 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1341 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1342 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1343 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1344 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1345 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1346 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1347 * @retval Value between Min_Data=0 and Max_Data=18
1348 */
1349 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1350 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
1351
1352 /**
1353 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
1354 * from number in decimal format.
1355 * @note Example:
1356 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1357 * will return a data equivalent to "ADC_CHANNEL_4".
1358 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1359 * @retval Returned value can be one of the following values:
1360 * @arg @ref ADC_CHANNEL_0
1361 * @arg @ref ADC_CHANNEL_1 (8)
1362 * @arg @ref ADC_CHANNEL_2 (8)
1363 * @arg @ref ADC_CHANNEL_3 (8)
1364 * @arg @ref ADC_CHANNEL_4 (8)
1365 * @arg @ref ADC_CHANNEL_5 (8)
1366 * @arg @ref ADC_CHANNEL_6
1367 * @arg @ref ADC_CHANNEL_7
1368 * @arg @ref ADC_CHANNEL_8
1369 * @arg @ref ADC_CHANNEL_9
1370 * @arg @ref ADC_CHANNEL_10
1371 * @arg @ref ADC_CHANNEL_11
1372 * @arg @ref ADC_CHANNEL_12
1373 * @arg @ref ADC_CHANNEL_13
1374 * @arg @ref ADC_CHANNEL_14
1375 * @arg @ref ADC_CHANNEL_15
1376 * @arg @ref ADC_CHANNEL_16
1377 * @arg @ref ADC_CHANNEL_17
1378 * @arg @ref ADC_CHANNEL_18
1379 * @arg @ref ADC_CHANNEL_VREFINT (7)
1380 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1381 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1382 * @arg @ref ADC_CHANNEL_VBAT (6)
1383 * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
1384 * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
1385 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
1386 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
1387 * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
1388 * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
1389 * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
1390 *
1391 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1392 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1393 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1394 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1395 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1396 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1397 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1398 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1399 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1400 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1401 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
1402 * comparison with internal channel parameter to be done
1403 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1404 */
1405 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1406 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
1407
1408 /**
1409 * @brief Helper macro to determine whether the selected channel
1410 * corresponds to literal definitions of driver.
1411 * @note The different literal definitions of ADC channels are:
1412 * - ADC internal channel:
1413 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
1414 * - ADC external channel (channel connected to a GPIO pin):
1415 * ADC_CHANNEL_1, ADC_CHANNEL_2, ...
1416 * @note The channel parameter must be a value defined from literal
1417 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1418 * ADC_CHANNEL_TEMPSENSOR, ...),
1419 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
1420 * must not be a value from functions where a channel number is
1421 * returned from ADC registers,
1422 * because internal and external channels share the same channel
1423 * number in ADC registers. The differentiation is made only with
1424 * parameters definitions of driver.
1425 * @param __CHANNEL__ This parameter can be one of the following values:
1426 * @arg @ref ADC_CHANNEL_0
1427 * @arg @ref ADC_CHANNEL_1 (8)
1428 * @arg @ref ADC_CHANNEL_2 (8)
1429 * @arg @ref ADC_CHANNEL_3 (8)
1430 * @arg @ref ADC_CHANNEL_4 (8)
1431 * @arg @ref ADC_CHANNEL_5 (8)
1432 * @arg @ref ADC_CHANNEL_6
1433 * @arg @ref ADC_CHANNEL_7
1434 * @arg @ref ADC_CHANNEL_8
1435 * @arg @ref ADC_CHANNEL_9
1436 * @arg @ref ADC_CHANNEL_10
1437 * @arg @ref ADC_CHANNEL_11
1438 * @arg @ref ADC_CHANNEL_12
1439 * @arg @ref ADC_CHANNEL_13
1440 * @arg @ref ADC_CHANNEL_14
1441 * @arg @ref ADC_CHANNEL_15
1442 * @arg @ref ADC_CHANNEL_16
1443 * @arg @ref ADC_CHANNEL_17
1444 * @arg @ref ADC_CHANNEL_18
1445 * @arg @ref ADC_CHANNEL_VREFINT (7)
1446 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1447 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1448 * @arg @ref ADC_CHANNEL_VBAT (6)
1449 * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
1450 * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
1451 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
1452 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
1453 * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
1454 * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
1455 * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
1456 *
1457 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1458 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1459 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1460 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1461 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1462 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1463 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1464 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1465 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1466 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1467 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1468 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1469 */
1470 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1471 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
1472
1473 /**
1474 * @brief Helper macro to convert a channel defined from parameter
1475 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1476 * ADC_CHANNEL_TEMPSENSOR, ...),
1477 * to its equivalent parameter definition of a ADC external channel
1478 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
1479 * @note The channel parameter can be, additionally to a value
1480 * defined from parameter definition of a ADC internal channel
1481 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
1482 * a value defined from parameter definition of
1483 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1484 * or a value from functions where a channel number is returned
1485 * from ADC registers.
1486 * @param __CHANNEL__ This parameter can be one of the following values:
1487 * @arg @ref ADC_CHANNEL_0
1488 * @arg @ref ADC_CHANNEL_1 (8)
1489 * @arg @ref ADC_CHANNEL_2 (8)
1490 * @arg @ref ADC_CHANNEL_3 (8)
1491 * @arg @ref ADC_CHANNEL_4 (8)
1492 * @arg @ref ADC_CHANNEL_5 (8)
1493 * @arg @ref ADC_CHANNEL_6
1494 * @arg @ref ADC_CHANNEL_7
1495 * @arg @ref ADC_CHANNEL_8
1496 * @arg @ref ADC_CHANNEL_9
1497 * @arg @ref ADC_CHANNEL_10
1498 * @arg @ref ADC_CHANNEL_11
1499 * @arg @ref ADC_CHANNEL_12
1500 * @arg @ref ADC_CHANNEL_13
1501 * @arg @ref ADC_CHANNEL_14
1502 * @arg @ref ADC_CHANNEL_15
1503 * @arg @ref ADC_CHANNEL_16
1504 * @arg @ref ADC_CHANNEL_17
1505 * @arg @ref ADC_CHANNEL_18
1506 * @arg @ref ADC_CHANNEL_VREFINT (7)
1507 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1508 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1509 * @arg @ref ADC_CHANNEL_VBAT (6)
1510 * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
1511 * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
1512 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
1513 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
1514 * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
1515 * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
1516 * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
1517 *
1518 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1519 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1520 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1521 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1522 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1523 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1524 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1525 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1526 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1527 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1528 * @retval Returned value can be one of the following values:
1529 * @arg @ref ADC_CHANNEL_0
1530 * @arg @ref ADC_CHANNEL_1
1531 * @arg @ref ADC_CHANNEL_2
1532 * @arg @ref ADC_CHANNEL_3
1533 * @arg @ref ADC_CHANNEL_4
1534 * @arg @ref ADC_CHANNEL_5
1535 * @arg @ref ADC_CHANNEL_6
1536 * @arg @ref ADC_CHANNEL_7
1537 * @arg @ref ADC_CHANNEL_8
1538 * @arg @ref ADC_CHANNEL_9
1539 * @arg @ref ADC_CHANNEL_10
1540 * @arg @ref ADC_CHANNEL_11
1541 * @arg @ref ADC_CHANNEL_12
1542 * @arg @ref ADC_CHANNEL_13
1543 * @arg @ref ADC_CHANNEL_14
1544 * @arg @ref ADC_CHANNEL_15
1545 * @arg @ref ADC_CHANNEL_16
1546 * @arg @ref ADC_CHANNEL_17
1547 * @arg @ref ADC_CHANNEL_18
1548 */
1549 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1550 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
1551
1552 /**
1553 * @brief Helper macro to determine whether the internal channel
1554 * selected is available on the ADC instance selected.
1555 * @note The channel parameter must be a value defined from parameter
1556 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
1557 * ADC_CHANNEL_TEMPSENSOR, ...),
1558 * must not be a value defined from parameter definition of
1559 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
1560 * or a value from functions where a channel number is
1561 * returned from ADC registers,
1562 * because internal and external channels share the same channel
1563 * number in ADC registers. The differentiation is made only with
1564 * parameters definitions of driver.
1565 * @param __ADC_INSTANCE__ ADC instance
1566 * @param __CHANNEL__ This parameter can be one of the following values:
1567 * @arg @ref ADC_CHANNEL_VREFINT (7)
1568 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1569 * @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1570 * @arg @ref ADC_CHANNEL_VBAT (6)
1571 * @arg @ref ADC_CHANNEL_VOPAMP1 (1)
1572 * @arg @ref ADC_CHANNEL_VOPAMP2 (2)
1573 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
1574 * @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
1575 * @arg @ref ADC_CHANNEL_VOPAMP4 (5)
1576 * @arg @ref ADC_CHANNEL_VOPAMP5 (5)
1577 * @arg @ref ADC_CHANNEL_VOPAMP6 (4)
1578 *
1579 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1580 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1581 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1582 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1583 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1584 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1585 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1586 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1587 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1588 * Value "1" if the internal channel selected is available on the ADC instance selected.
1589 */
1590 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1591 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
1592
1593 #if defined(ADC_MULTIMODE_SUPPORT)
1594 /**
1595 * @brief Helper macro to get the ADC multimode conversion data of ADC master
1596 * or ADC slave from raw value with both ADC conversion data concatenated.
1597 * @note This macro is intended to be used when multimode transfer by DMA
1598 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
1599 * In this case the transferred data need to processed with this macro
1600 * to separate the conversion data of ADC master and ADC slave.
1601 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1602 * @arg @ref LL_ADC_MULTI_MASTER
1603 * @arg @ref LL_ADC_MULTI_SLAVE
1604 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1605 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1606 */
1607 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1608 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
1609 #endif
1610
1611 /**
1612 * @brief Helper macro to select the ADC common instance
1613 * to which is belonging the selected ADC instance.
1614 * @note ADC common register instance can be used for:
1615 * - Set parameters common to several ADC instances
1616 * - Multimode (for devices with several ADC instances)
1617 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1618 * @param __ADCx__ ADC instance
1619 * @retval ADC common register instance
1620 */
1621 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
1622 __LL_ADC_COMMON_INSTANCE((__ADCx__))
1623
1624 /**
1625 * @brief Helper macro to check if all ADC instances sharing the same
1626 * ADC common instance are disabled.
1627 * @note This check is required by functions with setting conditioned to
1628 * ADC state:
1629 * All ADC instances of the ADC common group must be disabled.
1630 * Refer to functions having argument "ADCxy_COMMON" as parameter.
1631 * @note On devices with only 1 ADC common instance, parameter of this macro
1632 * is useless and can be ignored (parameter kept for compatibility
1633 * with devices featuring several ADC common instances).
1634 * @param __ADCXY_COMMON__ ADC common instance
1635 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1636 * @retval Value "0" if all ADC instances sharing the same ADC common instance
1637 * are disabled.
1638 * Value "1" if at least one ADC instance sharing the same ADC common instance
1639 * is enabled.
1640 */
1641 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1642 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
1643
1644 /**
1645 * @brief Helper macro to define the ADC conversion data full-scale digital
1646 * value corresponding to the selected ADC resolution.
1647 * @note ADC conversion data full-scale corresponds to voltage range
1648 * determined by analog voltage references Vref+ and Vref-
1649 * (refer to reference manual).
1650 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1651 * @arg @ref ADC_RESOLUTION_12B
1652 * @arg @ref ADC_RESOLUTION_10B
1653 * @arg @ref ADC_RESOLUTION_8B
1654 * @arg @ref ADC_RESOLUTION_6B
1655 * @retval ADC conversion data full-scale digital value
1656 */
1657 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1658 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
1659
1660 /**
1661 * @brief Helper macro to convert the ADC conversion data from
1662 * a resolution to another resolution.
1663 * @param __DATA__ ADC conversion data to be converted
1664 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
1665 * This parameter can be one of the following values:
1666 * @arg @ref ADC_RESOLUTION_12B
1667 * @arg @ref ADC_RESOLUTION_10B
1668 * @arg @ref ADC_RESOLUTION_8B
1669 * @arg @ref ADC_RESOLUTION_6B
1670 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
1671 * This parameter can be one of the following values:
1672 * @arg @ref ADC_RESOLUTION_12B
1673 * @arg @ref ADC_RESOLUTION_10B
1674 * @arg @ref ADC_RESOLUTION_8B
1675 * @arg @ref ADC_RESOLUTION_6B
1676 * @retval ADC conversion data to the requested resolution
1677 */
1678 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
1679 __ADC_RESOLUTION_CURRENT__,\
1680 __ADC_RESOLUTION_TARGET__) \
1681 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
1682 (__ADC_RESOLUTION_CURRENT__), \
1683 (__ADC_RESOLUTION_TARGET__))
1684
1685 /**
1686 * @brief Helper macro to calculate the voltage (unit: mVolt)
1687 * corresponding to a ADC conversion data (unit: digital value).
1688 * @note Analog reference voltage (Vref+) must be either known from
1689 * user board environment or can be calculated using ADC measurement
1690 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1691 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1692 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1693 * (unit: digital value).
1694 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1695 * @arg @ref ADC_RESOLUTION_12B
1696 * @arg @ref ADC_RESOLUTION_10B
1697 * @arg @ref ADC_RESOLUTION_8B
1698 * @arg @ref ADC_RESOLUTION_6B
1699 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1700 */
1701 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1702 __ADC_DATA__,\
1703 __ADC_RESOLUTION__) \
1704 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
1705 (__ADC_DATA__), \
1706 (__ADC_RESOLUTION__))
1707
1708 /**
1709 * @brief Helper macro to calculate analog reference voltage (Vref+)
1710 * (unit: mVolt) from ADC conversion data of internal voltage
1711 * reference VrefInt.
1712 * @note Computation is using VrefInt calibration value
1713 * stored in system memory for each device during production.
1714 * @note This voltage depends on user board environment: voltage level
1715 * connected to pin Vref+.
1716 * On devices with small package, the pin Vref+ is not present
1717 * and internally bonded to pin Vdda.
1718 * @note On this STM32 serie, calibration data of internal voltage reference
1719 * VrefInt corresponds to a resolution of 12 bits,
1720 * this is the recommended ADC resolution to convert voltage of
1721 * internal voltage reference VrefInt.
1722 * Otherwise, this macro performs the processing to scale
1723 * ADC conversion data to 12 bits.
1724 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
1725 * of internal voltage reference VrefInt (unit: digital value).
1726 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1727 * @arg @ref ADC_RESOLUTION_12B
1728 * @arg @ref ADC_RESOLUTION_10B
1729 * @arg @ref ADC_RESOLUTION_8B
1730 * @arg @ref ADC_RESOLUTION_6B
1731 * @retval Analog reference voltage (unit: mV)
1732 */
1733 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1734 __ADC_RESOLUTION__) \
1735 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
1736 (__ADC_RESOLUTION__))
1737
1738 /**
1739 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1740 * from ADC conversion data of internal temperature sensor.
1741 * @note Computation is using temperature sensor calibration values
1742 * stored in system memory for each device during production.
1743 * @note Calculation formula:
1744 * Temperature = ((TS_ADC_DATA - TS_CAL1)
1745 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
1746 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
1747 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1748 * Avg_Slope = (TS_CAL2 - TS_CAL1)
1749 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
1750 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
1751 * TEMP_DEGC_CAL1 (calibrated in factory)
1752 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
1753 * TEMP_DEGC_CAL2 (calibrated in factory)
1754 * Caution: Calculation relevancy under reserve that calibration
1755 * parameters are correct (address and data).
1756 * To calculate temperature using temperature sensor
1757 * datasheet typical values (generic values less, therefore
1758 * less accurate than calibrated values),
1759 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
1760 * @note As calculation input, the analog reference voltage (Vref+) must be
1761 * defined as it impacts the ADC LSB equivalent voltage.
1762 * @note Analog reference voltage (Vref+) must be either known from
1763 * user board environment or can be calculated using ADC measurement
1764 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1765 * @note On this STM32 serie, calibration data of temperature sensor
1766 * corresponds to a resolution of 12 bits,
1767 * this is the recommended ADC resolution to convert voltage of
1768 * temperature sensor.
1769 * Otherwise, this macro performs the processing to scale
1770 * ADC conversion data to 12 bits.
1771 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1772 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
1773 * temperature sensor (unit: digital value).
1774 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
1775 * sensor voltage has been measured.
1776 * This parameter can be one of the following values:
1777 * @arg @ref ADC_RESOLUTION_12B
1778 * @arg @ref ADC_RESOLUTION_10B
1779 * @arg @ref ADC_RESOLUTION_8B
1780 * @arg @ref ADC_RESOLUTION_6B
1781 * @retval Temperature (unit: degree Celsius)
1782 */
1783 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1784 __TEMPSENSOR_ADC_DATA__,\
1785 __ADC_RESOLUTION__) \
1786 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
1787 (__TEMPSENSOR_ADC_DATA__), \
1788 (__ADC_RESOLUTION__))
1789
1790 /**
1791 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1792 * from ADC conversion data of internal temperature sensor.
1793 * @note Computation is using temperature sensor typical values
1794 * (refer to device datasheet).
1795 * @note Calculation formula:
1796 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1797 * / Avg_Slope + CALx_TEMP
1798 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1799 * (unit: digital value)
1800 * Avg_Slope = temperature sensor slope
1801 * (unit: uV/Degree Celsius)
1802 * TS_TYP_CALx_VOLT = temperature sensor digital value at
1803 * temperature CALx_TEMP (unit: mV)
1804 * Caution: Calculation relevancy under reserve the temperature sensor
1805 * of the current device has characteristics in line with
1806 * datasheet typical values.
1807 * If temperature sensor calibration values are available on
1808 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1809 * temperature calculation will be more accurate using
1810 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1811 * @note As calculation input, the analog reference voltage (Vref+) must be
1812 * defined as it impacts the ADC LSB equivalent voltage.
1813 * @note Analog reference voltage (Vref+) must be either known from
1814 * user board environment or can be calculated using ADC measurement
1815 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
1816 * @note ADC measurement data must correspond to a resolution of 12bits
1817 * (full scale digital value 4095). If not the case, the data must be
1818 * preliminarily rescaled to an equivalent resolution of 12 bits.
1819 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1820 * On STM32G4, refer to device datasheet parameter "Avg_Slope".
1821 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1822 * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
1823 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1824 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1825 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1826 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1827 * This parameter can be one of the following values:
1828 * @arg @ref ADC_RESOLUTION_12B
1829 * @arg @ref ADC_RESOLUTION_10B
1830 * @arg @ref ADC_RESOLUTION_8B
1831 * @arg @ref ADC_RESOLUTION_6B
1832 * @retval Temperature (unit: degree Celsius)
1833 */
1834 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1835 __TEMPSENSOR_TYP_CALX_V__,\
1836 __TEMPSENSOR_CALX_TEMP__,\
1837 __VREFANALOG_VOLTAGE__,\
1838 __TEMPSENSOR_ADC_DATA__,\
1839 __ADC_RESOLUTION__) \
1840 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
1841 (__TEMPSENSOR_TYP_CALX_V__), \
1842 (__TEMPSENSOR_CALX_TEMP__), \
1843 (__VREFANALOG_VOLTAGE__), \
1844 (__TEMPSENSOR_ADC_DATA__), \
1845 (__ADC_RESOLUTION__))
1846
1847 /**
1848 * @}
1849 */
1850
1851 /**
1852 * @}
1853 */
1854
1855 /* Include ADC HAL Extended module */
1856 #include "stm32g4xx_hal_adc_ex.h"
1857
1858 /* Exported functions --------------------------------------------------------*/
1859 /** @addtogroup ADC_Exported_Functions
1860 * @{
1861 */
1862
1863 /** @addtogroup ADC_Exported_Functions_Group1
1864 * @brief Initialization and Configuration functions
1865 * @{
1866 */
1867 /* Initialization and de-initialization functions ****************************/
1868 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
1869 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
1870 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
1871 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
1872
1873 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
1874 /* Callbacks Register/UnRegister functions ***********************************/
1875 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
1876 pADC_CallbackTypeDef pCallback);
1877 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
1878 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1879 /**
1880 * @}
1881 */
1882
1883 /** @addtogroup ADC_Exported_Functions_Group2
1884 * @brief IO operation functions
1885 * @{
1886 */
1887 /* IO operation functions *****************************************************/
1888
1889 /* Blocking mode: Polling */
1890 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
1891 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
1892 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
1893 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
1894
1895 /* Non-blocking mode: Interruption */
1896 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
1897 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
1898
1899 /* Non-blocking mode: DMA */
1900 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
1901 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
1902
1903 /* ADC retrieve conversion value intended to be used with polling or interruption */
1904 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
1905
1906 /* ADC sampling control */
1907 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
1908 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
1909
1910 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
1911 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
1912 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
1913 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
1914 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
1915 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
1916 /**
1917 * @}
1918 */
1919
1920 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
1921 * @brief Peripheral Control functions
1922 * @{
1923 */
1924 /* Peripheral Control functions ***********************************************/
1925 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
1926 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
1927
1928 /**
1929 * @}
1930 */
1931
1932 /* Peripheral State functions *************************************************/
1933 /** @addtogroup ADC_Exported_Functions_Group4
1934 * @{
1935 */
1936 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
1937 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
1938
1939 /**
1940 * @}
1941 */
1942
1943 /**
1944 * @}
1945 */
1946
1947 /* Private functions -----------------------------------------------------------*/
1948 /** @addtogroup ADC_Private_Functions ADC Private Functions
1949 * @{
1950 */
1951 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
1952 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
1953 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
1954 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
1955 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
1956 void ADC_DMAError(DMA_HandleTypeDef *hdma);
1957
1958 /**
1959 * @}
1960 */
1961
1962 /**
1963 * @}
1964 */
1965
1966 /**
1967 * @}
1968 */
1969
1970 #ifdef __cplusplus
1971 }
1972 #endif
1973
1974
1975 #endif /* STM32G4xx_HAL_ADC_H */
1976
1977 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/