lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_hal_dma.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of DMA HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32G4xx_HAL_DMA_H
  22 #define __STM32G4xx_HAL_DMA_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32g4xx_hal_def.h"
  30
  31 /** @addtogroup STM32G4xx_HAL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup DMA
  36   * @{
  37   */
  38
  39 /* Exported types ------------------------------------------------------------*/
  40 /** @defgroup DMA_Exported_Types DMA Exported Types
  41   * @{
  42   */
  43
  44 /**
  45   * @brief  DMA Configuration Structure definition
  46   */
  47 typedef struct
  48 {
  49   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
  50                                            This parameter can be a value of @ref DMA_request */
  51
  52   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
  53                                            from memory to memory or from peripheral to memory.
  54                                            This parameter can be a value of @ref DMA_Data_transfer_direction */
  55
  56   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
  57                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
  58
  59   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
  60                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */
  61
  62   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
  63                                            This parameter can be a value of @ref DMA_Peripheral_data_size */
  64
  65   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
  66                                            This parameter can be a value of @ref DMA_Memory_data_size */
  67
  68   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
  69                                            This parameter can be a value of @ref DMA_mode
  70                                            @note The circular buffer mode cannot be used if the memory-to-memory
  71                                                  data transfer is configured on the selected Channel */
  72
  73   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
  74                                            This parameter can be a value of @ref DMA_Priority_level */
  75 } DMA_InitTypeDef;
  76
  77 /**
  78   * @brief  HAL DMA State structures definition
  79   */
  80 typedef enum
  81 {
  82   HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
  83   HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
  84   HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
  85   HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                     */
  86 } HAL_DMA_StateTypeDef;
  87
  88 /**
  89   * @brief  HAL DMA Error Code structure definition
  90   */
  91 typedef enum
  92 {
  93   HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */
  94   HAL_DMA_HALF_TRANSFER      = 0x01U     /*!< Half Transfer     */
  95 } HAL_DMA_LevelCompleteTypeDef;
  96
  97
  98 /**
  99   * @brief  HAL DMA Callback ID structure definition
 100   */
 101 typedef enum
 102 {
 103   HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */
 104   HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half transfer     */
 105   HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,    /*!< Error             */
 106   HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,    /*!< Abort             */
 107   HAL_DMA_XFER_ALL_CB_ID           = 0x04U     /*!< All               */
 108
 109 } HAL_DMA_CallbackIDTypeDef;
 110
 111 /**
 112   * @brief  DMA handle Structure definition
 113   */
 114 typedef struct __DMA_HandleTypeDef
 115 {
 116   DMA_Channel_TypeDef    *Instance;                                                  /*!< Register base address                */
 117
 118   DMA_InitTypeDef       Init;                                                        /*!< DMA communication parameters         */
 119
 120   HAL_LockTypeDef       Lock;                                                        /*!< DMA locking object                   */
 121
 122   __IO HAL_DMA_StateTypeDef  State;                                                  /*!< DMA transfer state                   */
 123
 124   void                  *Parent;                                                     /*!< Parent object state                  */
 125
 126   void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);                       /*!< DMA transfer complete callback       */
 127
 128   void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);                   /*!< DMA Half transfer complete callback  */
 129
 130   void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer error callback          */
 131
 132   void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);                      /*!< DMA transfer abort callback          */
 133
 134   __IO uint32_t          ErrorCode;                                                  /*!< DMA Error code                       */
 135
 136   DMA_TypeDef            *DmaBaseAddress;                                            /*!< DMA Channel Base Address             */
 137
 138   uint32_t               ChannelIndex;                                               /*!< DMA Channel Index                    */
 139
 140   DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                   /*!< Register base address                */
 141
 142   DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                             /*!< DMAMUX Channels Status Base Address  */
 143
 144   uint32_t                         DMAmuxChannelStatusMask;                          /*!< DMAMUX Channel Status Mask           */
 145
 146   DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                /*!< DMAMUX request generator Base Address */
 147
 148   DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                          /*!< DMAMUX request generator Address     */
 149
 150   uint32_t                         DMAmuxRequestGenStatusMask;                       /*!< DMAMUX request generator Status mask */
 151
 152 } DMA_HandleTypeDef;
 153 /**
 154   * @}
 155   */
 156
 157 /* Exported constants --------------------------------------------------------*/
 158
 159 /** @defgroup DMA_Exported_Constants DMA Exported Constants
 160   * @{
 161   */
 162
 163 /** @defgroup DMA_Error_Code DMA Error Code
 164   * @{
 165   */
 166 #define HAL_DMA_ERROR_NONE             0x00000000U    /*!< No error                              */
 167 #define HAL_DMA_ERROR_TE               0x00000001U    /*!< Transfer error                        */
 168 #define HAL_DMA_ERROR_NO_XFER          0x00000004U    /*!< Abort requested with no Xfer ongoing  */
 169 #define HAL_DMA_ERROR_TIMEOUT          0x00000020U    /*!< Timeout error                         */
 170 #define HAL_DMA_ERROR_NOT_SUPPORTED    0x00000100U    /*!< Not supported mode                    */
 171 #define HAL_DMA_ERROR_SYNC             0x00000200U    /*!< DMAMUX sync overrun  error              */
 172 #define HAL_DMA_ERROR_REQGEN           0x00000400U    /*!< DMAMUX request generator overrun  error */
 173 /**
 174   * @}
 175   */
 176
 177 /** @defgroup DMA_request DMA request
 178   * @{
 179   */
 180 #define DMA_REQUEST_MEM2MEM            0U  /*!< memory to memory transfer   */
 181
 182 #define DMA_REQUEST_GENERATOR0         1U
 183 #define DMA_REQUEST_GENERATOR1         2U
 184 #define DMA_REQUEST_GENERATOR2         3U
 185 #define DMA_REQUEST_GENERATOR3         4U
 186
 187 #define DMA_REQUEST_ADC1               5U
 188
 189 #define DMA_REQUEST_DAC1_CHANNEL1      6U
 190 #define DMA_REQUEST_DAC1_CHANNEL2      7U
 191
 192 #define DMA_REQUEST_TIM6_UP            8U
 193 #define DMA_REQUEST_TIM7_UP            9U
 194
 195 #define DMA_REQUEST_SPI1_RX           10U
 196 #define DMA_REQUEST_SPI1_TX           11U
 197 #define DMA_REQUEST_SPI2_RX           12U
 198 #define DMA_REQUEST_SPI2_TX           13U
 199 #define DMA_REQUEST_SPI3_RX           14U
 200 #define DMA_REQUEST_SPI3_TX           15U
 201
 202 #define DMA_REQUEST_I2C1_RX           16U
 203 #define DMA_REQUEST_I2C1_TX           17U
 204 #define DMA_REQUEST_I2C2_RX           18U
 205 #define DMA_REQUEST_I2C2_TX           19U
 206 #define DMA_REQUEST_I2C3_RX           20U
 207 #define DMA_REQUEST_I2C3_TX           21U
 208 #if defined (I2C4)
 209 #define DMA_REQUEST_I2C4_RX           22U
 210 #define DMA_REQUEST_I2C4_TX           23U
 211 #endif /* I2C4 */
 212
 213 #define DMA_REQUEST_USART1_RX         24U
 214 #define DMA_REQUEST_USART1_TX         25U
 215 #define DMA_REQUEST_USART2_RX         26U
 216 #define DMA_REQUEST_USART2_TX         27U
 217 #define DMA_REQUEST_USART3_RX         28U
 218 #define DMA_REQUEST_USART3_TX         29U
 219
 220 #define DMA_REQUEST_UART4_RX          30U
 221 #define DMA_REQUEST_UART4_TX          31U
 222 #if defined (UART5)
 223 #define DMA_REQUEST_UART5_RX          32U
 224 #define DMA_REQUEST_UART5_TX          33U
 225 #endif /* UART5 */
 226
 227 #define DMA_REQUEST_LPUART1_RX        34U
 228 #define DMA_REQUEST_LPUART1_TX        35U
 229
 230 #define DMA_REQUEST_ADC2              36U
 231 #if defined (ADC3)
 232 #define DMA_REQUEST_ADC3              37U
 233 #endif /* ADC3 */
 234 #if defined (ADC4)
 235 #define DMA_REQUEST_ADC4              38U
 236 #endif /* ADC4 */
 237 #if defined (ADC5)
 238 #define DMA_REQUEST_ADC5              39U
 239 #endif /* ADC5 */
 240
 241 #if defined (QUADSPI)
 242 #define DMA_REQUEST_QUADSPI           40U
 243 #endif /* QUADSPI */
 244
 245 #if defined (DAC2)
 246 #define DMA_REQUEST_DAC2_CHANNEL1     41U
 247 #endif /* DAC2 */
 248
 249 #define DMA_REQUEST_TIM1_CH1          42U
 250 #define DMA_REQUEST_TIM1_CH2          43U
 251 #define DMA_REQUEST_TIM1_CH3          44U
 252 #define DMA_REQUEST_TIM1_CH4          45U
 253 #define DMA_REQUEST_TIM1_UP           46U
 254 #define DMA_REQUEST_TIM1_TRIG         47U
 255 #define DMA_REQUEST_TIM1_COM          48U
 256
 257 #define DMA_REQUEST_TIM8_CH1          49U
 258 #define DMA_REQUEST_TIM8_CH2          50U
 259 #define DMA_REQUEST_TIM8_CH3          51U
 260 #define DMA_REQUEST_TIM8_CH4          52U
 261 #define DMA_REQUEST_TIM8_UP           53U
 262 #define DMA_REQUEST_TIM8_TRIG         54U
 263 #define DMA_REQUEST_TIM8_COM          55U
 264
 265 #define DMA_REQUEST_TIM2_CH1          56U
 266 #define DMA_REQUEST_TIM2_CH2          57U
 267 #define DMA_REQUEST_TIM2_CH3          58U
 268 #define DMA_REQUEST_TIM2_CH4          59U
 269 #define DMA_REQUEST_TIM2_UP           60U
 270
 271 #define DMA_REQUEST_TIM3_CH1          61U
 272 #define DMA_REQUEST_TIM3_CH2          62U
 273 #define DMA_REQUEST_TIM3_CH3          63U
 274 #define DMA_REQUEST_TIM3_CH4          64U
 275 #define DMA_REQUEST_TIM3_UP           65U
 276 #define DMA_REQUEST_TIM3_TRIG         66U
 277
 278 #define DMA_REQUEST_TIM4_CH1          67U
 279 #define DMA_REQUEST_TIM4_CH2          68U
 280 #define DMA_REQUEST_TIM4_CH3          69U
 281 #define DMA_REQUEST_TIM4_CH4          70U
 282 #define DMA_REQUEST_TIM4_UP           71U
 283
 284 #if defined (TIM5)
 285 #define DMA_REQUEST_TIM5_CH1          72U
 286 #define DMA_REQUEST_TIM5_CH2          73U
 287 #define DMA_REQUEST_TIM5_CH3          74U
 288 #define DMA_REQUEST_TIM5_CH4          75U
 289 #define DMA_REQUEST_TIM5_UP           76U
 290 #define DMA_REQUEST_TIM5_TRIG         77U
 291 #endif /* TIM5 */
 292
 293 #define DMA_REQUEST_TIM15_CH1         78U
 294 #define DMA_REQUEST_TIM15_UP          79U
 295 #define DMA_REQUEST_TIM15_TRIG        80U
 296 #define DMA_REQUEST_TIM15_COM         81U
 297
 298 #define DMA_REQUEST_TIM16_CH1         82U
 299 #define DMA_REQUEST_TIM16_UP          83U
 300 #define DMA_REQUEST_TIM17_CH1         84U
 301 #define DMA_REQUEST_TIM17_UP          85U
 302
 303 #if defined (TIM20)
 304 #define DMA_REQUEST_TIM20_CH1         86U
 305 #define DMA_REQUEST_TIM20_CH2         87U
 306 #define DMA_REQUEST_TIM20_CH3         88U
 307 #define DMA_REQUEST_TIM20_CH4         89U
 308 #define DMA_REQUEST_TIM20_UP          90U
 309 #endif /* TIM20 */
 310
 311 #define DMA_REQUEST_AES_IN            91U
 312 #define DMA_REQUEST_AES_OUT           92U
 313
 314 #if defined (TIM20)
 315 #define DMA_REQUEST_TIM20_TRIG        93U
 316 #define DMA_REQUEST_TIM20_COM         94U
 317 #endif /* TIM20 */
 318
 319 #if defined (HRTIM1)
 320 #define DMA_REQUEST_HRTIM1_M          95U
 321 #define DMA_REQUEST_HRTIM1_A          96U
 322 #define DMA_REQUEST_HRTIM1_B          97U
 323 #define DMA_REQUEST_HRTIM1_C          98U
 324 #define DMA_REQUEST_HRTIM1_D          99U
 325 #define DMA_REQUEST_HRTIM1_E          100U
 326 #define DMA_REQUEST_HRTIM1_F          101U
 327 #endif /* HRTIM1 */
 328
 329 #define DMA_REQUEST_DAC3_CHANNEL1     102U
 330 #define DMA_REQUEST_DAC3_CHANNEL2     103U
 331 #if defined (DAC4)
 332 #define DMA_REQUEST_DAC4_CHANNEL1     104U
 333 #define DMA_REQUEST_DAC4_CHANNEL2     105U
 334 #endif /* DAC4 */
 335
 336 #if defined (SPI4)
 337 #define DMA_REQUEST_SPI4_RX           106U
 338 #define DMA_REQUEST_SPI4_TX           107U
 339 #endif /* SPI4 */
 340
 341 #define DMA_REQUEST_SAI1_A            108U
 342 #define DMA_REQUEST_SAI1_B            109U
 343
 344 #define DMA_REQUEST_FMAC_READ         110U
 345 #define DMA_REQUEST_FMAC_WRITE        111U
 346
 347 #define DMA_REQUEST_CORDIC_READ       112U
 348 #define DMA_REQUEST_CORDIC_WRITE      113U
 349
 350 #define DMA_REQUEST_UCPD1_RX         114U
 351 #define DMA_REQUEST_UCPD1_TX         115U
 352
 353 /**
 354   * @}
 355   */
 356
 357 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
 358   * @{
 359   */
 360 #define DMA_PERIPH_TO_MEMORY         0x00000000U                   /*!< Peripheral to memory direction */
 361 #define DMA_MEMORY_TO_PERIPH         DMA_CCR_DIR                   /*!< Memory to peripheral direction */
 362 #define DMA_MEMORY_TO_MEMORY         DMA_CCR_MEM2MEM               /*!< Memory to memory direction     */
 363 /**
 364   * @}
 365   */
 366
 367 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
 368   * @{
 369   */
 370 #define DMA_PINC_ENABLE        DMA_CCR_PINC              /*!< Peripheral increment mode Enable */
 371 #define DMA_PINC_DISABLE       0x00000000U               /*!< Peripheral increment mode Disable */
 372 /**
 373   * @}
 374   */
 375
 376 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
 377   * @{
 378   */
 379 #define DMA_MINC_ENABLE         DMA_CCR_MINC              /*!< Memory increment mode Enable  */
 380 #define DMA_MINC_DISABLE        0x00000000U               /*!< Memory increment mode Disable */
 381 /**
 382   * @}
 383   */
 384
 385 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
 386   * @{
 387   */
 388 #define DMA_PDATAALIGN_BYTE          0x00000000U                  /*!< Peripheral data alignment : Byte     */
 389 #define DMA_PDATAALIGN_HALFWORD      DMA_CCR_PSIZE_0              /*!< Peripheral data alignment : HalfWord */
 390 #define DMA_PDATAALIGN_WORD          DMA_CCR_PSIZE_1              /*!< Peripheral data alignment : Word     */
 391 /**
 392   * @}
 393   */
 394
 395 /** @defgroup DMA_Memory_data_size DMA Memory data size
 396   * @{
 397   */
 398 #define DMA_MDATAALIGN_BYTE          0x00000000U                  /*!< Memory data alignment : Byte     */
 399 #define DMA_MDATAALIGN_HALFWORD      DMA_CCR_MSIZE_0              /*!< Memory data alignment : HalfWord */
 400 #define DMA_MDATAALIGN_WORD          DMA_CCR_MSIZE_1              /*!< Memory data alignment : Word     */
 401 /**
 402   * @}
 403   */
 404
 405 /** @defgroup DMA_mode DMA mode
 406   * @{
 407   */
 408 #define DMA_NORMAL         0x00000000U       /*!< Normal mode                  */
 409 #define DMA_CIRCULAR       DMA_CCR_CIRC      /*!< Circular mode                */
 410 /**
 411   * @}
 412   */
 413
 414 /** @defgroup DMA_Priority_level DMA Priority level
 415   * @{
 416   */
 417 #define DMA_PRIORITY_LOW              0x00000000U              /*!< Priority level : Low       */
 418 #define DMA_PRIORITY_MEDIUM           DMA_CCR_PL_0             /*!< Priority level : Medium    */
 419 #define DMA_PRIORITY_HIGH             DMA_CCR_PL_1             /*!< Priority level : High      */
 420 #define DMA_PRIORITY_VERY_HIGH        DMA_CCR_PL               /*!< Priority level : Very_High */
 421 /**
 422   * @}
 423   */
 424
 425
 426 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
 427   * @{
 428   */
 429 #define DMA_IT_TC                     DMA_CCR_TCIE
 430 #define DMA_IT_HT                     DMA_CCR_HTIE
 431 #define DMA_IT_TE                     DMA_CCR_TEIE
 432 /**
 433   * @}
 434   */
 435
 436 /** @defgroup DMA_flag_definitions DMA flag definitions
 437   * @{
 438   */
 439 #define DMA_FLAG_GL1                      0x00000001U
 440 #define DMA_FLAG_TC1                      0x00000002U
 441 #define DMA_FLAG_HT1                      0x00000004U
 442 #define DMA_FLAG_TE1                      0x00000008U
 443 #define DMA_FLAG_GL2                      0x00000010U
 444 #define DMA_FLAG_TC2                      0x00000020U
 445 #define DMA_FLAG_HT2                      0x00000040U
 446 #define DMA_FLAG_TE2                      0x00000080U
 447 #define DMA_FLAG_GL3                      0x00000100U
 448 #define DMA_FLAG_TC3                      0x00000200U
 449 #define DMA_FLAG_HT3                      0x00000400U
 450 #define DMA_FLAG_TE3                      0x00000800U
 451 #define DMA_FLAG_GL4                      0x00001000U
 452 #define DMA_FLAG_TC4                      0x00002000U
 453 #define DMA_FLAG_HT4                      0x00004000U
 454 #define DMA_FLAG_TE4                      0x00008000U
 455 #define DMA_FLAG_GL5                      0x00010000U
 456 #define DMA_FLAG_TC5                      0x00020000U
 457 #define DMA_FLAG_HT5                      0x00040000U
 458 #define DMA_FLAG_TE5                      0x00080000U
 459 #define DMA_FLAG_GL6                      0x00100000U
 460 #define DMA_FLAG_TC6                      0x00200000U
 461 #define DMA_FLAG_HT6                      0x00400000U
 462 #define DMA_FLAG_TE6                      0x00800000U
 463 #if defined (DMA1_Channel7)
 464 #define DMA_FLAG_GL7                      0x01000000U
 465 #define DMA_FLAG_TC7                      0x02000000U
 466 #define DMA_FLAG_HT7                      0x04000000U
 467 #define DMA_FLAG_TE7                      0x08000000U
 468 #endif /* DMA1_Channel7 */
 469 #if defined (DMA1_Channel8)
 470 #define DMA_FLAG_GL8                      0x10000000U
 471 #define DMA_FLAG_TC8                      0x20000000U
 472 #define DMA_FLAG_HT8                      0x40000000U
 473 #define DMA_FLAG_TE8                      0x80000000U
 474 #endif /* DMA1_Channel8 */
 475 /**
 476   * @}
 477   */
 478
 479 /**
 480   * @}
 481   */
 482
 483 /* Exported macros -----------------------------------------------------------*/
 484 /** @defgroup DMA_Exported_Macros DMA Exported Macros
 485   * @{
 486   */
 487
 488 /** @brief  Reset DMA handle state.
 489   * @param  __HANDLE__ DMA handle
 490   * @retval None
 491   */
 492 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 493
 494 /**
 495   * @brief  Enable the specified DMA Channel.
 496   * @param  __HANDLE__ DMA handle
 497   * @retval None
 498   */
 499 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
 500
 501 /**
 502   * @brief  Disable the specified DMA Channel.
 503   * @param  __HANDLE__ DMA handle
 504   * @retval None
 505   */
 506 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
 507
 508
 509 /* Interrupt & Flag management */
 510
 511 /**
 512   * @brief  Return the current DMA Channel transfer complete flag.
 513   * @param  __HANDLE__ DMA handle
 514   * @retval The specified transfer complete flag index.
 515   */
 516
 517 #if defined (DMA1_Channel8)
 518 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 519   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 520    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 521    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 522    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 523    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 524    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 525    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 526    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
 527    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 528    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
 529    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
 530    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
 531    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
 532    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
 533    DMA_FLAG_TC8)
 534 #elif defined (DMA1_Channel6)
 535 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 536   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
 537    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
 538    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
 539    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
 540    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
 541    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
 542    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
 543    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
 544    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
 545    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
 546    DMA_FLAG_TC6)
 547 #endif /* DMA1_Channel8 */
 548
 549 /**
 550   * @brief  Return the current DMA Channel half transfer complete flag.
 551   * @param  __HANDLE__ DMA handle
 552   * @retval The specified half transfer complete flag index.
 553   */
 554 #if defined (DMA1_Channel8)
 555 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 556   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 557    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 558    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 559    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 560    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 561    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 562    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 563    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
 564    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 565    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
 566    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
 567    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
 568    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
 569    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
 570    DMA_FLAG_HT8)
 571 #elif defined (DMA1_Channel6)
 572 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 573   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
 574    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
 575    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
 576    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
 577    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
 578    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
 579    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
 580    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
 581    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
 582    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
 583    DMA_FLAG_HT6)
 584 #endif /* DMA1_Channel8 */
 585
 586 /**
 587   * @brief  Return the current DMA Channel transfer error flag.
 588   * @param  __HANDLE__ DMA handle
 589   * @retval The specified transfer error flag index.
 590   */
 591 #if defined (DMA1_Channel8)
 592 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 593   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 594    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 595    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 596    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 597    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 598    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 599    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 600    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
 601    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 602    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
 603    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
 604    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
 605    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
 606    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
 607    DMA_FLAG_TE8)
 608 #elif defined (DMA1_Channel6)
 609 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 610   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
 611    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
 612    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
 613    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
 614    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
 615    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
 616    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
 617    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
 618    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
 619    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
 620    DMA_FLAG_TE6)
 621 #endif /* DMA1_Channel8 */
 622
 623 /**
 624   * @brief  Return the current DMA Channel Global interrupt flag.
 625   * @param  __HANDLE__ DMA handle
 626   * @retval The specified transfer error flag index.
 627   */
 628 #if defined (DMA1_Channel8)
 629 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 630   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
 631    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
 632    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
 633    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
 634    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
 635    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
 636    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
 637    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
 638    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
 639    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
 640    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
 641    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
 642    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
 643    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
 644    DMA_ISR_GIF8)
 645 #elif defined (DMA1_Channel6)
 646 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 647   (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
 648    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
 649    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
 650    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
 651    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
 652    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
 653    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
 654    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
 655    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
 656    ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
 657    DMA_ISR_GIF6)
 658 #endif /* DMA1_Channel8 */
 659
 660 /**
 661   * @brief  Get the DMA Channel pending flags.
 662   * @param  __HANDLE__ DMA handle
 663   * @param  __FLAG__ Get the specified flag.
 664   *          This parameter can be any combination of the following values:
 665   *            @arg DMA_FLAG_TCx  Transfer complete flag
 666   *            @arg DMA_FLAG_HTx  Half transfer complete flag
 667   *            @arg DMA_FLAG_TEx  Transfer error flag
 668   *            @arg DMA_FLAG_GLx  Global interrupt flag
 669   *         Where x can be from 1 to 8 to select the DMA Channel x flag.
 670   * @retval The state of FLAG (SET or RESET).
 671   */
 672 #if defined (DMA1_Channel8)
 673 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
 674                                                   (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
 675 #elif defined (DMA1_Channel6)
 676 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
 677                                                   (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
 678 #endif /* DMA1_Channel8 */
 679
 680 /**
 681   * @brief  Clear the DMA Channel pending flags.
 682   * @param  __HANDLE__ DMA handle
 683   * @param  __FLAG__ specifies the flag to clear.
 684   *          This parameter can be any combination of the following values:
 685   *            @arg DMA_FLAG_TCx  Transfer complete flag
 686   *            @arg DMA_FLAG_HTx  Half transfer complete flag
 687   *            @arg DMA_FLAG_TEx  Transfer error flag
 688   *            @arg DMA_FLAG_GLx  Global interrupt flag
 689   *         Where x can be from 1 to 8 to select the DMA Channel x flag.
 690   * @retval None
 691   */
 692 #if defined (DMA1_Channel8)
 693 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
 694                                                     (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
 695 #else
 696 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
 697                                                     (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
 698 #endif /* DMA1_Channel8 */
 699
 700 /**
 701   * @brief  Enable the specified DMA Channel interrupts.
 702   * @param  __HANDLE__ DMA handle
 703   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 704   *          This parameter can be any combination of the following values:
 705   *            @arg DMA_IT_TC  Transfer complete interrupt mask
 706   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
 707   *            @arg DMA_IT_TE  Transfer error interrupt mask
 708   * @retval None
 709   */
 710 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
 711
 712 /**
 713   * @brief  Disable the specified DMA Channel interrupts.
 714   * @param  __HANDLE__ DMA handle
 715   * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
 716   *          This parameter can be any combination of the following values:
 717   *            @arg DMA_IT_TC  Transfer complete interrupt mask
 718   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
 719   *            @arg DMA_IT_TE  Transfer error interrupt mask
 720   * @retval None
 721   */
 722 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
 723
 724 /**
 725   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
 726   * @param  __HANDLE__ DMA handle
 727   * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
 728   *          This parameter can be one of the following values:
 729   *            @arg DMA_IT_TC  Transfer complete interrupt mask
 730   *            @arg DMA_IT_HT  Half transfer complete interrupt mask
 731   *            @arg DMA_IT_TE  Transfer error interrupt mask
 732   * @retval The state of DMA_IT (SET or RESET).
 733   */
 734 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
 735
 736 /**
 737   * @brief  Return the number of remaining data units in the current DMA Channel transfer.
 738   * @param  __HANDLE__ DMA handle
 739   * @retval The number of remaining data units in the current DMA Channel transfer.
 740   */
 741 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
 742
 743 /**
 744   * @}
 745   */
 746
 747 /* Include DMA HAL Extension module */
 748 #include "stm32g4xx_hal_dma_ex.h"
 749
 750 /* Exported functions --------------------------------------------------------*/
 751
 752 /** @addtogroup DMA_Exported_Functions
 753   * @{
 754   */
 755
 756 /** @addtogroup DMA_Exported_Functions_Group1
 757   * @{
 758   */
 759 /* Initialization and de-initialization functions *****************************/
 760 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
 761 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
 762 /**
 763   * @}
 764   */
 765
 766 /** @addtogroup DMA_Exported_Functions_Group2
 767   * @{
 768   */
 769 /* IO operation functions *****************************************************/
 770 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 771 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
 772                                    uint32_t DataLength);
 773 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 774 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
 775 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
 776                                           uint32_t Timeout);
 777 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 778 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
 779 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
 780
 781 /**
 782   * @}
 783   */
 784
 785 /** @addtogroup DMA_Exported_Functions_Group3
 786   * @{
 787   */
 788 /* Peripheral State and Error functions ***************************************/
 789 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
 790 uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
 791 /**
 792   * @}
 793   */
 794
 795 /**
 796   * @}
 797   */
 798
 799 /* Private macros ------------------------------------------------------------*/
 800 /** @defgroup DMA_Private_Macros DMA Private Macros
 801   * @{
 802   */
 803
 804 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
 805                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
 806                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
 807
 808 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
 809
 810 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
 811                                             ((STATE) == DMA_PINC_DISABLE))
 812
 813 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
 814                                         ((STATE) == DMA_MINC_DISABLE))
 815
 816 #define IS_DMA_ALL_REQUEST(REQUEST)    ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
 817
 818 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
 819                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
 820                                            ((SIZE) == DMA_PDATAALIGN_WORD))
 821
 822 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
 823                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
 824                                        ((SIZE) == DMA_MDATAALIGN_WORD ))
 825
 826 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
 827                            ((MODE) == DMA_CIRCULAR))
 828
 829 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
 830                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
 831                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
 832                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
 833
 834 /**
 835   * @}
 836   */
 837
 838 /* Private functions ---------------------------------------------------------*/
 839
 840 /**
 841   * @}
 842   */
 843
 844 /**
 845   * @}
 846   */
 847
 848 #ifdef __cplusplus
 849 }
 850 #endif
 851
 852 #endif /* __STM32G4xx_HAL_DMA_H */
 853
 854 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/