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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_hal_fdcan.h
blob589c06de494d2d1dd408808ec362cb1040cc24f0
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_fdcan.h
4 * @author MCD Application Team
5 * @brief Header file of FDCAN HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_HAL_FDCAN_H
22 #define STM32G4xx_HAL_FDCAN_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx_hal_def.h"
30
31 #if defined(FDCAN1)
32
33 /** @addtogroup STM32G4xx_HAL_Driver
34 * @{
35 */
36
37 /** @addtogroup FDCAN
38 * @{
39 */
40
41 /* Exported types ------------------------------------------------------------*/
42 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
43 * @{
44 */
45
46 /**
47 * @brief HAL State structures definition
48 */
49 typedef enum
50 {
51 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
52 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
53 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
54 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
55 } HAL_FDCAN_StateTypeDef;
56
57 /**
58 * @brief FDCAN Init structure definition
59 */
60 typedef struct
61 {
62 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider.
63 The clock is common to all FDCAN instances.
64 This parameter is applied only at initialisation of
65 first FDCAN instance.
66 This parameter can be a value of @ref FDCAN_clock_divider. */
67
68 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
69 This parameter can be a value of @ref FDCAN_frame_format */
70
71 uint32_t Mode; /*!< Specifies the FDCAN mode.
72 This parameter can be a value of @ref FDCAN_operating_mode */
73
74 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
75 This parameter can be set to ENABLE or DISABLE */
76
77 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
78 This parameter can be set to ENABLE or DISABLE */
79
80 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
81 This parameter can be set to ENABLE or DISABLE */
82
83 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
84 divided for generating the nominal bit time quanta.
85 This parameter must be a number between 1 and 512 */
86
87 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
88 hardware is allowed to lengthen or shorten a bit to perform
89 resynchronization.
90 This parameter must be a number between 1 and 128 */
91
92 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
93 This parameter must be a number between 2 and 256 */
94
95 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
96 This parameter must be a number between 2 and 128 */
97
98 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
99 divided for generating the data bit time quanta.
100 This parameter must be a number between 1 and 32 */
101
102 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
103 hardware is allowed to lengthen or shorten a data bit to
104 perform resynchronization.
105 This parameter must be a number between 1 and 16 */
106
107 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
108 This parameter must be a number between 1 and 32 */
109
110 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
111 This parameter must be a number between 1 and 16 */
112
113 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
114 This parameter must be a number between 0 and 28 */
115
116 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
117 This parameter must be a number between 0 and 8 */
118
119 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
120 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
121
122 } FDCAN_InitTypeDef;
123
124 /**
125 * @brief FDCAN filter structure definition
126 */
127 typedef struct
128 {
129 uint32_t IdType; /*!< Specifies the identifier type.
130 This parameter can be a value of @ref FDCAN_id_type */
131
132 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
133 This parameter must be a number between:
134 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
135 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
136
137 uint32_t FilterType; /*!< Specifies the filter type.
138 This parameter can be a value of @ref FDCAN_filter_type.
139 The value FDCAN_FILTER_RANGE_NO_EIDM is permitted
140 only when IdType is FDCAN_EXTENDED_ID. */
141
142 uint32_t FilterConfig; /*!< Specifies the filter configuration.
143 This parameter can be a value of @ref FDCAN_filter_config */
144
145 uint32_t FilterID1; /*!< Specifies the filter identification 1.
146 This parameter must be a number between:
147 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
148 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
149
150 uint32_t FilterID2; /*!< Specifies the filter identification 2.
151 This parameter must be a number between:
152 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
153 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
154
155 } FDCAN_FilterTypeDef;
156
157 /**
158 * @brief FDCAN Tx header structure definition
159 */
160 typedef struct
161 {
162 uint32_t Identifier; /*!< Specifies the identifier.
163 This parameter must be a number between:
164 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
165 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
166
167 uint32_t IdType; /*!< Specifies the identifier type for the message that will be
168 transmitted.
169 This parameter can be a value of @ref FDCAN_id_type */
170
171 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
172 This parameter can be a value of @ref FDCAN_frame_type */
173
174 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
175 This parameter can be a value of @ref FDCAN_data_length_code */
176
177 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
178 This parameter can be a value of @ref FDCAN_error_state_indicator */
179
180 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
181 bit rate switching.
182 This parameter can be a value of @ref FDCAN_bit_rate_switching */
183
184 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
185 FD format.
186 This parameter can be a value of @ref FDCAN_format */
187
188 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
189 This parameter can be a value of @ref FDCAN_EFC */
190
191 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
192 element for identification of Tx message status.
193 This parameter must be a number between 0 and 0xFF */
194
195 } FDCAN_TxHeaderTypeDef;
196
197 /**
198 * @brief FDCAN Rx header structure definition
199 */
200 typedef struct
201 {
202 uint32_t Identifier; /*!< Specifies the identifier.
203 This parameter must be a number between:
204 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
205 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
206
207 uint32_t IdType; /*!< Specifies the identifier type of the received message.
208 This parameter can be a value of @ref FDCAN_id_type */
209
210 uint32_t RxFrameType; /*!< Specifies the the received message frame type.
211 This parameter can be a value of @ref FDCAN_frame_type */
212
213 uint32_t DataLength; /*!< Specifies the received frame length.
214 This parameter can be a value of @ref FDCAN_data_length_code */
215
216 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
217 This parameter can be a value of @ref FDCAN_error_state_indicator */
218
219 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
220 rate switching.
221 This parameter can be a value of @ref FDCAN_bit_rate_switching */
222
223 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
224 format.
225 This parameter can be a value of @ref FDCAN_format */
226
227 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
228 reception.
229 This parameter must be a number between 0 and 0xFFFF */
230
231 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
232 This parameter must be a number between:
233 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID
234 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */
235
236 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
237 Acceptance of non-matching frames may be enabled via
238 HAL_FDCAN_ConfigGlobalFilter().
239 This parameter can be 0 or 1 */
240
241 } FDCAN_RxHeaderTypeDef;
242
243 /**
244 * @brief FDCAN Tx event FIFO structure definition
245 */
246 typedef struct
247 {
248 uint32_t Identifier; /*!< Specifies the identifier.
249 This parameter must be a number between:
250 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
251 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
252
253 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
254 This parameter can be a value of @ref FDCAN_id_type */
255
256 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
257 This parameter can be a value of @ref FDCAN_frame_type */
258
259 uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
260 This parameter can be a value of @ref FDCAN_data_length_code */
261
262 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
263 This parameter can be a value of @ref FDCAN_error_state_indicator */
264
265 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
266 rate switching.
267 This parameter can be a value of @ref FDCAN_bit_rate_switching */
268
269 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
270 format.
271 This parameter can be a value of @ref FDCAN_format */
272
273 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
274 transmission.
275 This parameter must be a number between 0 and 0xFFFF */
276
277 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
278 for identification of Tx message status.
279 This parameter must be a number between 0 and 0xFF */
280
281 uint32_t EventType; /*!< Specifies the event type.
282 This parameter can be a value of @ref FDCAN_event_type */
283
284 } FDCAN_TxEventFifoTypeDef;
285
286 /**
287 * @brief FDCAN High Priority Message Status structure definition
288 */
289 typedef struct
290 {
291 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
292 This parameter can be:
293 - 0 : Standard Filter List
294 - 1 : Extended Filter List */
295
296 uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
297 This parameter can be a number between:
298 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard)
299 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */
300
301 uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
302 This parameter can be a value of @ref FDCAN_hp_msg_storage */
303
304 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
305 message was stored.
306 This parameter is valid only when MessageStorage is:
307 FDCAN_HP_STORAGE_RXFIFO0
308 or
309 FDCAN_HP_STORAGE_RXFIFO1 */
310
311 } FDCAN_HpMsgStatusTypeDef;
312
313 /**
314 * @brief FDCAN Protocol Status structure definition
315 */
316 typedef struct
317 {
318 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
319 This parameter can be a value of @ref FDCAN_protocol_error_code */
320
321 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
322 frame with its BRS flag set.
323 This parameter can be a value of @ref FDCAN_protocol_error_code */
324
325 uint32_t Activity; /*!< Specifies the FDCAN module communication state.
326 This parameter can be a value of @ref FDCAN_communication_state */
327
328 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
329 This parameter can be:
330 - 0 : The FDCAN is in Error_Active state
331 - 1 : The FDCAN is in Error_Passive state */
332
333 uint32_t Warning; /*!< Specifies the FDCAN module warning status.
334 This parameter can be:
335 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
336 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
337
338 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
339 This parameter can be:
340 - 0 : The FDCAN is not in Bus_Off state
341 - 1 : The FDCAN is in Bus_Off state */
342
343 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
344 This parameter can be:
345 - 0 : Last received CAN FD message did not have its ESI flag set
346 - 1 : Last received CAN FD message had its ESI flag set */
347
348 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
349 This parameter can be:
350 - 0 : Last received CAN FD message did not have its BRS flag set
351 - 1 : Last received CAN FD message had its BRS flag set */
352
353 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status
354 This parameter can be:
355 - 0 : No CAN FD message received
356 - 1 : CAN FD message received */
357
358 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
359 This parameter can be:
360 - 0 : No protocol exception event occurred since last read access
361 - 1 : Protocol exception event occurred */
362
363 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
364 This parameter can be a number between 0 and 127 */
365
366 } FDCAN_ProtocolStatusTypeDef;
367
368 /**
369 * @brief FDCAN Error Counters structure definition
370 */
371 typedef struct
372 {
373 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
374 This parameter can be a number between 0 and 255 */
375
376 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
377 This parameter can be a number between 0 and 127 */
378
379 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
380 This parameter can be:
381 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
382 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
383
384 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
385 This parameter can be a number between 0 and 255.
386 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
387 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
388 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
389
390 } FDCAN_ErrorCountersTypeDef;
391
392 /**
393 * @brief FDCAN Message RAM blocks
394 */
395 typedef struct
396 {
397 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
398 This parameter must be a 32-bit word address */
399
400 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
401 This parameter must be a 32-bit word address */
402
403 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
404 This parameter must be a 32-bit word address */
405
406 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
407 This parameter must be a 32-bit word address */
408
409 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
410 This parameter must be a 32-bit word address */
411
412 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
413 This parameter must be a 32-bit word address */
414
415 } FDCAN_MsgRamAddressTypeDef;
416
417 /**
418 * @brief FDCAN handle structure definition
419 */
420 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
421 typedef struct __FDCAN_HandleTypeDef
422 #else
423 typedef struct
424 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
425 {
426 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
427
428 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
429
430 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
431
432 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
433 of latest Tx FIFO/Queue request */
434
435 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
436
437 HAL_LockTypeDef Lock; /*!< FDCAN locking object */
438
439 __IO uint32_t ErrorCode; /*!< FDCAN Error code */
440
441 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
442 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
443 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
444 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
445 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
446 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
447 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
448 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */
449 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */
450 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */
451 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
452 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
453
454 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
455 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
456
457 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
458
459 } FDCAN_HandleTypeDef;
460
461 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
462 /**
463 * @brief HAL FDCAN common Callback ID enumeration definition
464 */
465 typedef enum
466 {
467 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
468 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */
469 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */
470 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */
471 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */
472
473 HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */
474 HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */
475
476 } HAL_FDCAN_CallbackIDTypeDef;
477
478 /**
479 * @brief HAL FDCAN Callback pointer definition
480 */
481 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */
482 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */
483 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
484 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
485 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
486 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */
487 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
488
489 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
490
491 /**
492 * @}
493 */
494
495 /* Exported constants --------------------------------------------------------*/
496 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
497 * @{
498 */
499
500 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
501 * @{
502 */
503 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
504 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
505 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
506 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
507 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
508 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
509 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
510 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
511 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
512 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
513 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
514 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
515 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
516 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
517 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
518 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
519
520 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
521 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */
522 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
523 /**
524 * @}
525 */
526
527 /** @defgroup FDCAN_frame_format FDCAN Frame Format
528 * @{
529 */
530 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
531 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
532 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
533 /**
534 * @}
535 */
536
537 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
538 * @{
539 */
540 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
541 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
542 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
543 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
544 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
545 /**
546 * @}
547 */
548
549 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
550 * @{
551 */
552 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
553 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */
554 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */
555 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */
556 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */
557 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */
558 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */
559 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */
560 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */
561 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */
562 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */
563 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */
564 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */
565 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */
566 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */
567 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */
568 /**
569 * @}
570 */
571
572 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
573 * @{
574 */
575 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
576 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
577 /**
578 * @}
579 */
580
581 /** @defgroup FDCAN_id_type FDCAN ID Type
582 * @{
583 */
584 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
585 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
586 /**
587 * @}
588 */
589
590 /** @defgroup FDCAN_frame_type FDCAN Frame Type
591 * @{
592 */
593 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
594 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
595 /**
596 * @}
597 */
598
599 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
600 * @{
601 */
602 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
603 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
604 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
605 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
606 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
607 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
608 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
609 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
610 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
611 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
612 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
613 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
614 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
615 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
616 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
617 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
618 /**
619 * @}
620 */
621
622 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
623 * @{
624 */
625 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
626 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
627 /**
628 * @}
629 */
630
631 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
632 * @{
633 */
634 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
635 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
636 /**
637 * @}
638 */
639
640 /** @defgroup FDCAN_format FDCAN format
641 * @{
642 */
643 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
644 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
645 /**
646 * @}
647 */
648
649 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
650 * @{
651 */
652 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
653 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
654 /**
655 * @}
656 */
657
658 /** @defgroup FDCAN_filter_type FDCAN Filter Type
659 * @{
660 */
661 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
662 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
663 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
664 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
665 /**
666 * @}
667 */
668
669 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
670 * @{
671 */
672 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
673 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
674 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
675 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
676 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
677 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
678 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
679 /**
680 * @}
681 */
682
683 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
684 * @{
685 */
686 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
687 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
688 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
689 /**
690 * @}
691 */
692
693 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
694 * @{
695 */
696 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
697 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
698 /**
699 * @}
700 */
701
702 /** @defgroup FDCAN_event_type FDCAN Event Type
703 * @{
704 */
705 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
706 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
707 /**
708 * @}
709 */
710
711 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
712 * @{
713 */
714 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
715 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
716 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
717 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
718 /**
719 * @}
720 */
721
722 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
723 * @{
724 */
725 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
726 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
727 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
728 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
729 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
730 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
731 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
732 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
733 /**
734 * @}
735 */
736
737 /** @defgroup FDCAN_communication_state FDCAN communication state
738 * @{
739 */
740 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
741 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
742 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
743 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
744 /**
745 * @}
746 */
747
748 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
749 * @{
750 */
751 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
752 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */
753 /**
754 * @}
755 */
756
757 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
758 * @{
759 */
760 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
761 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
762 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
763 /**
764 * @}
765 */
766
767 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
768 * @{
769 */
770 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
771 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
772 /**
773 * @}
774 */
775
776 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
777 * @{
778 */
779 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
780 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
781 /**
782 * @}
783 */
784
785 /** @defgroup FDCAN_Timestamp FDCAN timestamp
786 * @{
787 */
788 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
789 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
790 /**
791 * @}
792 */
793
794 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
795 * @{
796 */
797 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
798 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
799 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
800 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
801 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
802 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
803 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
804 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
805 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
806 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
807 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
808 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
809 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
810 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
811 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
812 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
813 /**
814 * @}
815 */
816
817 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
818 * @{
819 */
820 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
821 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
822 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
823 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
824 /**
825 * @}
826 */
827
828 /** @defgroup Interrupt_Masks Interrupt masks
829 * @{
830 */
831 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */
832 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */
833 /**
834 * @}
835 */
836
837 /** @defgroup FDCAN_flags FDCAN Flags
838 * @{
839 */
840 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
841 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
842 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
843 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
844 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
845 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
846 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
847 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
848 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
849 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
850 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
851 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
852 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
853 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
854 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
855 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
856 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
857 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
858 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
859 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
860 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
861 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
862 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
863 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
864 /**
865 * @}
866 */
867
868 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
869 * @{
870 */
871
872 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
873 * @{
874 */
875 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
876 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
877 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
878 /**
879 * @}
880 */
881
882 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
883 * @{
884 */
885 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
886 /**
887 * @}
888 */
889
890 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
891 * @{
892 */
893 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
894 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
895 /**
896 * @}
897 */
898
899 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
900 * @{
901 */
902 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
903 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
904 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
905 /**
906 * @}
907 */
908
909 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
910 * @{
911 */
912 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
913 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
914 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
915 /**
916 * @}
917 */
918
919 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
920 * @{
921 */
922 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
923 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
924 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
925 /**
926 * @}
927 */
928
929 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
930 * @{
931 */
932 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
933 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
934 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
935 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
936 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
937 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
938 /**
939 * @}
940 */
941
942 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
943 * @{
944 */
945 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
946 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
947 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
948 /**
949 * @}
950 */
951
952 /**
953 * @}
954 */
955
956 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List
957 * @{
958 */
959 #define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \
960 FDCAN_IT_RX_FIFO0_FULL | \
961 FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */
962 #define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \
963 FDCAN_IT_RX_FIFO1_FULL | \
964 FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */
965 #define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \
966 FDCAN_IT_TX_COMPLETE | \
967 FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */
968 #define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \
969 FDCAN_IT_TX_EVT_FIFO_FULL | \
970 FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \
971 FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */
972 #define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \
973 FDCAN_IT_RAM_ACCESS_FAILURE | \
974 FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */
975 #define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \
976 FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */
977 #define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \
978 FDCAN_IT_DATA_PROTOCOL_ERROR | \
979 FDCAN_IT_ARB_PROTOCOL_ERROR | \
980 FDCAN_IT_RAM_WATCHDOG | \
981 FDCAN_IT_BUS_OFF | \
982 FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */
983 /**
984 * @}
985 */
986
987 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group
988 * @{
989 */
990 #define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group:
991 RF0LL: Rx FIFO 0 Message Lost
992 RF0FL: Rx FIFO 0 is Full
993 RF0NL: Rx FIFO 0 Has New Message */
994 #define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group:
995 RF1LL: Rx FIFO 1 Message Lost
996 RF1FL: Rx FIFO 1 is Full
997 RF1NL: Rx FIFO 1 Has New Message */
998 #define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group:
999 TCFL: Transmission Cancellation Finished
1000 TCL: Transmission Completed
1001 HPML: High Priority Message */
1002 #define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group:
1003 TEFLL: Tx Event FIFO Element Lost
1004 TEFFL: Tx Event FIFO Full
1005 TEFNL: Tx Event FIFO New Entry
1006 TFEL: Tx FIFO Empty Interrupt Line */
1007 #define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group:
1008 TOOL: Timeout Occurred
1009 MRAFL: Message RAM Access Failure
1010 TSWL: Timestamp Wraparound */
1011 #define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group:
1012 EPL: Error Passive
1013 ELOL: Error Logging Overflow */
1014 #define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group:
1015 ARAL: Access to Reserved Address Line
1016 PEDL: Protocol Error in Data Phase Line
1017 PEAL: Protocol Error in Arbitration Phase Line
1018 WDIL: Watchdog Interrupt Line
1019 BOL: Bus_Off Status
1020 EWL: Warning Status */
1021 /**
1022 * @}
1023 */
1024
1025 /**
1026 * @}
1027 */
1028
1029 /* Exported macro ------------------------------------------------------------*/
1030 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
1031 * @{
1032 */
1033
1034 /** @brief Reset FDCAN handle state.
1035 * @param __HANDLE__ FDCAN handle.
1036 * @retval None
1037 */
1038 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
1039 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
1040 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
1041 (__HANDLE__)->MspInitCallback = NULL; \
1042 (__HANDLE__)->MspDeInitCallback = NULL; \
1043 } while(0)
1044 #else
1045 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
1046 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
1047
1048 /**
1049 * @brief Enable the specified FDCAN interrupts.
1050 * @param __HANDLE__ FDCAN handle.
1051 * @param __INTERRUPT__ FDCAN interrupt.
1052 * This parameter can be any combination of @arg FDCAN_Interrupts
1053 * @retval None
1054 */
1055 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1056 (__HANDLE__)->Instance->IE |= (__INTERRUPT__)
1057
1058 /**
1059 * @brief Disable the specified FDCAN interrupts.
1060 * @param __HANDLE__ FDCAN handle.
1061 * @param __INTERRUPT__ FDCAN interrupt.
1062 * This parameter can be any combination of @arg FDCAN_Interrupts
1063 * @retval None
1064 */
1065 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1066 ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__)
1067
1068 /**
1069 * @brief Check whether the specified FDCAN interrupt is set or not.
1070 * @param __HANDLE__ FDCAN handle.
1071 * @param __INTERRUPT__ FDCAN interrupt.
1072 * This parameter can be one of @arg FDCAN_Interrupts
1073 * @retval ITStatus
1074 */
1075 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__))
1076
1077 /**
1078 * @brief Clear the specified FDCAN interrupts.
1079 * @param __HANDLE__ FDCAN handle.
1080 * @param __INTERRUPT__ specifies the interrupts to clear.
1081 * This parameter can be any combination of @arg FDCAN_Interrupts
1082 * @retval None
1083 */
1084 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
1085 ((__HANDLE__)->Instance->IR) = (__INTERRUPT__)
1086
1087 /**
1088 * @brief Check whether the specified FDCAN flag is set or not.
1089 * @param __HANDLE__ FDCAN handle.
1090 * @param __FLAG__ FDCAN flag.
1091 * This parameter can be one of @arg FDCAN_flags
1092 * @retval FlagStatus
1093 */
1094 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__))
1095
1096 /**
1097 * @brief Clear the specified FDCAN flags.
1098 * @param __HANDLE__ FDCAN handle.
1099 * @param __FLAG__ specifies the flags to clear.
1100 * This parameter can be any combination of @arg FDCAN_flags
1101 * @retval None
1102 */
1103 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1104 ((__HANDLE__)->Instance->IR) = (__FLAG__)
1105
1106 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
1107 * @param __HANDLE__ FDCAN handle.
1108 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
1109 * This parameter can be a value of @arg FDCAN_Interrupts
1110 * @retval ITStatus
1111 */
1112 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__))
1113
1114 /**
1115 * @}
1116 */
1117
1118 /* Exported functions --------------------------------------------------------*/
1119 /** @addtogroup FDCAN_Exported_Functions
1120 * @{
1121 */
1122
1123 /** @addtogroup FDCAN_Exported_Functions_Group1
1124 * @{
1125 */
1126 /* Initialization and de-initialization functions *****************************/
1127 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
1128 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
1129 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
1130 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
1131 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
1132 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
1133
1134 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
1135 /* Callbacks Register/UnRegister functions ***********************************/
1136 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
1137 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
1138 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
1139 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
1140 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
1141 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
1142 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
1143 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
1144 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
1145 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
1146 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
1147 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
1148 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
1149 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
1150 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
1151 /**
1152 * @}
1153 */
1154
1155 /** @addtogroup FDCAN_Exported_Functions_Group2
1156 * @{
1157 */
1158 /* Configuration functions ****************************************************/
1159 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
1160 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
1161 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
1162 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
1163 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
1164 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
1165 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
1166 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1167 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1168 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1169 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
1170 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
1171 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
1172 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
1173 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
1174 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
1175 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
1176 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
1177 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
1178 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
1179 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
1180 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
1181 /**
1182 * @}
1183 */
1184
1185 /** @addtogroup FDCAN_Exported_Functions_Group3
1186 * @{
1187 */
1188 /* Control functions **********************************************************/
1189 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
1190 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
1191 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
1192 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
1193 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
1194 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
1195 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
1196 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
1197 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
1198 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
1199 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
1200 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
1201 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
1202 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
1203 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
1204 /**
1205 * @}
1206 */
1207
1208 /** @addtogroup FDCAN_Exported_Functions_Group4
1209 * @{
1210 */
1211 /* Interrupts management ******************************************************/
1212 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
1213 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
1214 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
1215 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
1216 /**
1217 * @}
1218 */
1219
1220 /** @addtogroup FDCAN_Exported_Functions_Group5
1221 * @{
1222 */
1223 /* Callback functions *********************************************************/
1224 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
1225 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
1226 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
1227 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
1228 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
1229 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
1230 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
1231 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
1232 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
1233 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
1234 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
1235 /**
1236 * @}
1237 */
1238
1239 /** @addtogroup FDCAN_Exported_Functions_Group6
1240 * @{
1241 */
1242 /* Peripheral State functions *************************************************/
1243 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
1244 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
1245 /**
1246 * @}
1247 */
1248
1249 /**
1250 * @}
1251 */
1252
1253 /* Private types -------------------------------------------------------------*/
1254 /** @defgroup FDCAN_Private_Types FDCAN Private Types
1255 * @{
1256 */
1257
1258 /**
1259 * @}
1260 */
1261
1262 /* Private variables ---------------------------------------------------------*/
1263 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
1264 * @{
1265 */
1266
1267 /**
1268 * @}
1269 */
1270
1271 /* Private constants ---------------------------------------------------------*/
1272 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
1273 * @{
1274 */
1275
1276 /**
1277 * @}
1278 */
1279
1280 /* Private macros ------------------------------------------------------------*/
1281 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
1282 * @{
1283 */
1284 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
1285 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
1286 ((FORMAT) == FDCAN_FRAME_FD_BRS ))
1287 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
1288 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
1289 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
1290 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
1291 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
1292 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
1293 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
1294 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
1295 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
1296 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
1297 ((CKDIV) == FDCAN_CLOCK_DIV10) || \
1298 ((CKDIV) == FDCAN_CLOCK_DIV12) || \
1299 ((CKDIV) == FDCAN_CLOCK_DIV14) || \
1300 ((CKDIV) == FDCAN_CLOCK_DIV16) || \
1301 ((CKDIV) == FDCAN_CLOCK_DIV18) || \
1302 ((CKDIV) == FDCAN_CLOCK_DIV20) || \
1303 ((CKDIV) == FDCAN_CLOCK_DIV22) || \
1304 ((CKDIV) == FDCAN_CLOCK_DIV24) || \
1305 ((CKDIV) == FDCAN_CLOCK_DIV26) || \
1306 ((CKDIV) == FDCAN_CLOCK_DIV28) || \
1307 ((CKDIV) == FDCAN_CLOCK_DIV30))
1308 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
1309 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
1310 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
1311 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
1312 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
1313 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
1314 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
1315 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
1316 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
1317 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
1318 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
1319 ((MODE) == FDCAN_TX_QUEUE_OPERATION))
1320 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
1321 ((ID_TYPE) == FDCAN_EXTENDED_ID))
1322 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
1323 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
1324 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
1325 ((CONFIG) == FDCAN_FILTER_REJECT ) || \
1326 ((CONFIG) == FDCAN_FILTER_HP ) || \
1327 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
1328 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP))
1329 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
1330 ((LOCATION) == FDCAN_TX_BUFFER2 ))
1331 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \
1332 ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2)))
1333 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
1334 ((FIFO) == FDCAN_RX_FIFO1))
1335 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
1336 ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
1337 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
1338 ((TYPE) == FDCAN_FILTER_DUAL ) || \
1339 ((TYPE) == FDCAN_FILTER_MASK ))
1340 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
1341 ((TYPE) == FDCAN_FILTER_DUAL ) || \
1342 ((TYPE) == FDCAN_FILTER_MASK ) || \
1343 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
1344 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
1345 ((TYPE) == FDCAN_REMOTE_FRAME))
1346 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
1347 ((DLC) == FDCAN_DLC_BYTES_1 ) || \
1348 ((DLC) == FDCAN_DLC_BYTES_2 ) || \
1349 ((DLC) == FDCAN_DLC_BYTES_3 ) || \
1350 ((DLC) == FDCAN_DLC_BYTES_4 ) || \
1351 ((DLC) == FDCAN_DLC_BYTES_5 ) || \
1352 ((DLC) == FDCAN_DLC_BYTES_6 ) || \
1353 ((DLC) == FDCAN_DLC_BYTES_7 ) || \
1354 ((DLC) == FDCAN_DLC_BYTES_8 ) || \
1355 ((DLC) == FDCAN_DLC_BYTES_12) || \
1356 ((DLC) == FDCAN_DLC_BYTES_16) || \
1357 ((DLC) == FDCAN_DLC_BYTES_20) || \
1358 ((DLC) == FDCAN_DLC_BYTES_24) || \
1359 ((DLC) == FDCAN_DLC_BYTES_32) || \
1360 ((DLC) == FDCAN_DLC_BYTES_48) || \
1361 ((DLC) == FDCAN_DLC_BYTES_64))
1362 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
1363 ((ESI) == FDCAN_ESI_PASSIVE))
1364 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
1365 ((BRS) == FDCAN_BRS_ON ))
1366 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
1367 ((FDF) == FDCAN_FD_CAN ))
1368 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
1369 ((EFC) == FDCAN_STORE_TX_EVENTS))
1370 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U)
1371 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U)
1372 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
1373 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
1374 ((DESTINATION) == FDCAN_REJECT ))
1375 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
1376 ((DESTINATION) == FDCAN_REJECT_REMOTE))
1377 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
1378 ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
1379 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
1380 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
1381 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
1382 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
1383 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
1384 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
1385 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
1386 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
1387 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
1388 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
1389 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
1390 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
1391 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
1392 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
1393 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
1394 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
1395 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
1396 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
1397 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
1398 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
1399 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
1400 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
1401 /**
1402 * @}
1403 */
1404
1405 /* Private functions prototypes ----------------------------------------------*/
1406 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
1407 * @{
1408 */
1409
1410 /**
1411 * @}
1412 */
1413
1414 /* Private functions ---------------------------------------------------------*/
1415 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
1416 * @{
1417 */
1418
1419 /**
1420 * @}
1421 */
1422 /**
1423 * @}
1424 */
1425
1426 /**
1427 * @}
1428 */
1429 #endif /* FDCAN1 */
1430
1431 #ifdef __cplusplus
1432 }
1433 #endif
1434
1435 #endif /* STM32G4xx_HAL_FDCAN_H */
1436
1437
1438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/