?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_hal_flash.h
blob476c6378b99e9ff6b85350a8d0d21d529f98605a
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_flash.h
4 * @author MCD Application Team
5 * @brief Header file of FLASH HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * This software component is licensed by ST under BSD 3-Clause license,
12 * the "License"; You may not use this file except in compliance with the
13 * License. You may obtain a copy of the License at:
14 * opensource.org/licenses/BSD-3-Clause
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32G4xx_HAL_FLASH_H
21 #define STM32G4xx_HAL_FLASH_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32g4xx_hal_def.h"
29
30 /** @addtogroup STM32G4xx_HAL_Driver
31 * @{
32 */
33
34 /** @addtogroup FLASH
35 * @{
36 */
37
38 /* Exported types ------------------------------------------------------------*/
39 /** @defgroup FLASH_Exported_Types FLASH Exported Types
40 * @{
41 */
42
43 /**
44 * @brief FLASH Erase structure definition
45 */
46 typedef struct
47 {
48 uint32_t TypeErase; /*!< Mass erase or page erase.
49 This parameter can be a value of @ref FLASH_Type_Erase */
50 uint32_t Banks; /*!< Select bank to erase.
51 This parameter must be a value of @ref FLASH_Banks
52 (FLASH_BANK_BOTH should be used only for mass erase) */
53 uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled.
54 This parameter must be a value between 0 and (max number of pages in the bank - 1)
55 (eg : 127 for 512KB dual bank) */
56 uint32_t NbPages; /*!< Number of pages to be erased.
57 This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
58 } FLASH_EraseInitTypeDef;
59
60 /**
61 * @brief FLASH Option Bytes Program structure definition
62 */
63 typedef struct
64 {
65 uint32_t OptionType; /*!< Option byte to be configured.
66 This parameter can be a combination of the values of @ref FLASH_OB_Type */
67 uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
68 Only one WRP area could be programmed at the same time.
69 This parameter can be value of @ref FLASH_OB_WRP_Area */
70 uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
71 This parameter must be a value between 0 and (max number of pages in the bank - 1) */
72 uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
73 This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
74 uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
75 This parameter can be a value of @ref FLASH_OB_Read_Protection */
76 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
77 This parameter can be a combination of @ref FLASH_OB_USER_Type */
78 uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
79 This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
80 @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
81 @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
82 @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
83 @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
84 @ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
85 @ref FLASH_OB_USER_CCMSRAM_RST
86 @note (*) availability depends on devices */
87 uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
88 This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
89 and @ref FLASH_OB_PCROP_RDP */
90 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
91 This parameter must be a value between begin and end of bank
92 => Be careful of the bank swapping for the address */
93 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
94 This parameter must be a value between PCROP Start address and end of bank */
95 uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK).
96 This parameter can be a value of @ref FLASH_OB_Boot_Lock */
97 uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC).
98 Only one securable memory area could be programmed at the same time.
99 This parameter can be one of the following values:
100 FLASH_BANK_1: Securable memory area to be programmed in bank 1
101 FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)
102 @note (*) availability depends on devices */
103 uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC),
104 in number of pages. Securable memory area is starting from first page of the bank.
105 Only one securable memory could be programmed at the same time.
106 This parameter must be a value between 0 and (max number of pages in the bank - 1) */
107 } FLASH_OBProgramInitTypeDef;
108
109 /**
110 * @brief FLASH Procedure structure definition
111 */
112 typedef enum
113 {
114 FLASH_PROC_NONE = 0,
115 FLASH_PROC_PAGE_ERASE,
116 FLASH_PROC_MASS_ERASE,
117 FLASH_PROC_PROGRAM,
118 FLASH_PROC_PROGRAM_LAST
119 } FLASH_ProcedureTypeDef;
120
121 /**
122 * @brief FLASH Cache structure definition
123 */
124 typedef enum
125 {
126 FLASH_CACHE_DISABLED = 0,
127 FLASH_CACHE_ICACHE_ENABLED,
128 FLASH_CACHE_DCACHE_ENABLED,
129 FLASH_CACHE_ICACHE_DCACHE_ENABLED
130 } FLASH_CacheTypeDef;
131
132 /**
133 * @brief FLASH handle Structure definition
134 */
135 typedef struct
136 {
137 HAL_LockTypeDef Lock; /* FLASH locking object */
138 __IO uint32_t ErrorCode; /* FLASH error code */
139 __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
140 __IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
141 __IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
142 __IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
143 __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
144 __IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
145 } FLASH_ProcessTypeDef;
146
147 /**
148 * @}
149 */
150
151 /* Exported constants --------------------------------------------------------*/
152 /** @defgroup FLASH_Exported_Constants FLASH Exported Constants
153 * @{
154 */
155
156 /** @defgroup FLASH_Error FLASH Error
157 * @{
158 */
159 #define HAL_FLASH_ERROR_NONE 0x00000000U
160 #define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
161 #define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
162 #define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
163 #define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
164 #define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
165 #define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
166 #define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
167 #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
168 #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
169 #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
170 #define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
171 #define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
172 #if defined (FLASH_OPTR_DBANK)
173 #define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2
174 #define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2
175 #endif
176 /**
177 * @}
178 */
179
180 /** @defgroup FLASH_Type_Erase FLASH Erase Type
181 * @{
182 */
183 #define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
184 #define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/
185 /**
186 * @}
187 */
188
189 /** @defgroup FLASH_Banks FLASH Banks
190 * @{
191 */
192 #define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
193 #if defined (FLASH_OPTR_DBANK)
194 #define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
195 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
196 #else
197 #define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */
198 #endif
199 /**
200 * @}
201 */
202
203
204 /** @defgroup FLASH_Type_Program FLASH Program Type
205 * @{
206 */
207 #define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U /*!< Program a double-word (64-bit) at a specified address.*/
208 #define FLASH_TYPEPROGRAM_FAST 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
209 And another 32 row double-word (64-bit) will be programmed */
210 #define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
211 And this is the last 32 row double-word (64-bit) programmed */
212 /**
213 * @}
214 */
215
216 /** @defgroup FLASH_OB_Type FLASH Option Bytes Type
217 * @{
218 */
219 #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
220 #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
221 #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
222 #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
223 #define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */
224 #define OPTIONBYTE_SEC 0x20U /*!< Securable memory option byte configuration */
225 /**
226 * @}
227 */
228
229 /** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
230 * @{
231 */
232 #define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */
233 #define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */
234 #if defined (FLASH_OPTR_DBANK)
235 #define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */
236 #define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */
237 #endif
238 /**
239 * @}
240 */
241
242 /** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
243 * @{
244 */
245 #define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */
246 #define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */
247 /**
248 * @}
249 */
250
251 /** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
252 * @{
253 */
254 #define OB_RDP_LEVEL_0 0xAAU
255 #define OB_RDP_LEVEL_1 0xBBU
256 #define OB_RDP_LEVEL_2 0xCCU /*!< Warning: When enabling read protection level 2
257 it's no more possible to go back to level 1 or 0 */
258 /**
259 * @}
260 */
261
262 /** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
263 * @{
264 */
265 #define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
266 #define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */
267 #define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */
268 #define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */
269 #define OB_USER_IWDG_STOP 0x00000010U /*!< Independent watchdog counter freeze in stop mode */
270 #define OB_USER_IWDG_STDBY 0x00000020U /*!< Independent watchdog counter freeze in standby mode */
271 #define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */
272 #if defined (FLASH_OPTR_DBANK)
273 #define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
274 #define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */
275 #endif
276 #define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
277 #define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
278 #define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */
279 #define OB_USER_nRST_SHDW 0x00001000U /*!< Reset generated when entering the shutdown mode */
280 #define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */
281 #define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */
282 #define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */
283 #define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */
284 /**
285 * @}
286 */
287
288 /** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
289 * @{
290 */
291 #define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */
292 #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */
293 #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */
294 #define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */
295 #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */
296 /**
297 * @}
298 */
299
300 /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
301 * @{
302 */
303 #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
304 #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
305 /**
306 * @}
307 */
308
309 /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
310 * @{
311 */
312 #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
313 #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
314 /**
315 * @}
316 */
317
318 /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
319 * @{
320 */
321 #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
322 #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */
323 /**
324 * @}
325 */
326
327 /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
328 * @{
329 */
330 #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
331 #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
332 /**
333 * @}
334 */
335
336 /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
337 * @{
338 */
339 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
340 #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */
341 /**
342 * @}
343 */
344
345 /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
346 * @{
347 */
348 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
349 #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
350 /**
351 * @}
352 */
353
354 /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
355 * @{
356 */
357 #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
358 #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
359 /**
360 * @}
361 */
362
363 #if defined (FLASH_OPTR_DBANK)
364 /** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
365 * @{
366 */
367 #define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */
368 #define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */
369 /**
370 * @}
371 */
372
373 /** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
374 * @{
375 */
376 #define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */
377 #define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */
378 /**
379 * @}
380 */
381 #endif
382
383 /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
384 * @{
385 */
386 #define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
387 #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */
388 /**
389 * @}
390 */
391
392 /** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type
393 * @{
394 */
395 #define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
396 #define OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */
397 /**
398 * @}
399 */
400
401 /** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type
402 * @{
403 */
404 #define OB_CCMSRAM_RST_ERASE 0x00000000U /*!< CCMSRAM erased when a system reset occurs */
405 #define OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs */
406 /**
407 * @}
408 */
409
410 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
411 * @{
412 */
413 #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
414 #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */
415 /**
416 * @}
417 */
418
419 /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
420 * @{
421 */
422 #define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
423 #define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
424 /**
425 * @}
426 */
427
428 /** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
429 * @{
430 */
431 #define OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */
432 #define OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */
433 #define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */
434 /**
435 * @}
436 */
437
438 /** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit
439 * @{
440 */
441 #define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */
442 #define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */
443 /**
444 * @}
445 */
446
447 /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
448 * @{
449 */
450 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
451 is decreased from Level 1 to Level 0 */
452 #define OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
453 decreased from Level 1 to Level 0 (full mass erase) */
454 /**
455 * @}
456 */
457
458 /** @defgroup FLASH_Latency FLASH Latency
459 * @{
460 */
461 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
462 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
463 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
464 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
465 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
466 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */
467 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */
468 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
469 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
470 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */
471 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */
472 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */
473 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */
474 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */
475 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */
476 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */
477 /**
478 * @}
479 */
480
481 /** @defgroup FLASH_Keys FLASH Keys
482 * @{
483 */
484 #define FLASH_KEY1 0x45670123U /*!< Flash key1 */
485 #define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
486 to unlock the FLASH registers access */
487
488 #define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
489 #define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
490 to unlock the RUN_PD bit in FLASH_ACR */
491
492 #define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
493 #define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
494 to allow option bytes operations */
495 /**
496 * @}
497 */
498
499 /** @defgroup FLASH_Flags FLASH Flags Definition
500 * @{
501 */
502 #define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
503 #define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
504 #define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
505 #define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
506 #define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
507 #define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
508 #define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
509 #define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
510 #define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
511 #define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
512 #define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
513 #define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
514 #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */
515 #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */
516 #if defined (FLASH_OPTR_DBANK)
517 #define FLASH_FLAG_ECCC2 FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */
518 #define FLASH_FLAG_ECCD2 FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */
519 #endif
520
521 #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
522 FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
523 FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
524 FLASH_FLAG_OPTVERR)
525 #if defined (FLASH_OPTR_DBANK)
526 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2)
527 #else
528 #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
529 #endif
530 #define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
531 /**
532 * @}
533 */
534
535 /** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
536 * @brief FLASH Interrupt definition
537 * @{
538 */
539 #define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
540 #define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
541 #define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
542 #define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
543 /**
544 * @}
545 */
546
547 /**
548 * @}
549 */
550
551 /* Exported macros -----------------------------------------------------------*/
552 /** @defgroup FLASH_Exported_Macros FLASH Exported Macros
553 * @brief macros to control FLASH features
554 * @{
555 */
556
557 /**
558 * @brief Set the FLASH Latency.
559 * @param __LATENCY__ FLASH Latency.
560 * This parameter can be one of the following values :
561 * @arg FLASH_LATENCY_0: FLASH Zero wait state
562 * @arg FLASH_LATENCY_1: FLASH One wait state
563 * @arg FLASH_LATENCY_2: FLASH Two wait states
564 * @arg FLASH_LATENCY_3: FLASH Three wait states
565 * @arg FLASH_LATENCY_4: FLASH Four wait states
566 * @arg FLASH_LATENCY_5: FLASH Five wait states
567 * @arg FLASH_LATENCY_6: FLASH Six wait states
568 * @arg FLASH_LATENCY_7: FLASH Seven wait states
569 * @retval None
570 */
571 #define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
572
573 /**
574 * @brief Get the FLASH Latency.
575 * @retval FLASH_Latency.
576 * This parameter can be one of the following values :
577 * @arg FLASH_LATENCY_0: FLASH Zero wait state
578 * @arg FLASH_LATENCY_1: FLASH One wait state
579 * @arg FLASH_LATENCY_2: FLASH Two wait states
580 * @arg FLASH_LATENCY_3: FLASH Three wait states
581 * @arg FLASH_LATENCY_4: FLASH Four wait states
582 * @arg FLASH_LATENCY_5: FLASH Five wait states
583 * @arg FLASH_LATENCY_6: FLASH Six wait states
584 * @arg FLASH_LATENCY_7: FLASH Seven wait states
585 */
586 #define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
587
588 /**
589 * @brief Enable the FLASH prefetch buffer.
590 * @retval None
591 */
592 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
593
594 /**
595 * @brief Disable the FLASH prefetch buffer.
596 * @retval None
597 */
598 #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
599
600 /**
601 * @brief Enable the FLASH instruction cache.
602 * @retval none
603 */
604 #define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
605
606 /**
607 * @brief Disable the FLASH instruction cache.
608 * @retval none
609 */
610 #define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
611
612 /**
613 * @brief Enable the FLASH data cache.
614 * @retval none
615 */
616 #define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
617
618 /**
619 * @brief Disable the FLASH data cache.
620 * @retval none
621 */
622 #define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
623
624 /**
625 * @brief Reset the FLASH instruction Cache.
626 * @note This function must be used only when the Instruction Cache is disabled.
627 * @retval None
628 */
629 #define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
630 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
631 } while (0)
632
633 /**
634 * @brief Reset the FLASH data Cache.
635 * @note This function must be used only when the data Cache is disabled.
636 * @retval None
637 */
638 #define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
639 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
640 } while (0)
641
642 /**
643 * @brief Enable the FLASH power down during Low-power run mode.
644 * @note Writing this bit to 1, automatically the keys are
645 * lost and a new unlock sequence is necessary to re-write it to 0.
646 */
647 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
648 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
649 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
650 } while (0)
651
652 /**
653 * @brief Disable the FLASH power down during Low-power run mode.
654 * @note Writing this bit to 0, automatically the keys are
655 * lost and a new unlock sequence is necessary to re-write it to 1.
656 */
657 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
658 WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
659 CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
660 } while (0)
661
662 /**
663 * @brief Enable the FLASH power down during Low-Power sleep mode
664 * @retval none
665 */
666 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
667
668 /**
669 * @brief Disable the FLASH power down during Low-Power sleep mode
670 * @retval none
671 */
672 #define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
673
674 /**
675 * @}
676 */
677
678 /** @defgroup FLASH_Interrupt FLASH Interrupts Macros
679 * @brief macros to handle FLASH interrupts
680 * @{
681 */
682
683 /**
684 * @brief Enable the specified FLASH interrupt.
685 * @param __INTERRUPT__ FLASH interrupt
686 * This parameter can be any combination of the following values:
687 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
688 * @arg FLASH_IT_OPERR: Error Interrupt
689 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
690 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
691 * @retval none
692 */
693 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
694 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
695 } while (0)
696
697 /**
698 * @brief Disable the specified FLASH interrupt.
699 * @param __INTERRUPT__ FLASH interrupt
700 * This parameter can be any combination of the following values:
701 * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
702 * @arg FLASH_IT_OPERR: Error Interrupt
703 * @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
704 * @arg FLASH_IT_ECCC: ECC Correction Interrupt
705 * @retval none
706 */
707 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
708 if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
709 } while (0)
710
711 /**
712 * @brief Check whether the specified FLASH flag is set or not.
713 * @param __FLAG__ specifies the FLASH flag to check.
714 * This parameter can be one of the following values:
715 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
716 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
717 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
718 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
719 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
720 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
721 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
722 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
723 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
724 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
725 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
726 * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
727 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
728 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
729 * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
730 * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
731 * @note (*) availability depends on devices
732 * @retval The new state of FLASH_FLAG (SET or RESET).
733 */
734 #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
735 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
736 (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
737
738 /**
739 * @brief Clear the FLASH's pending flags.
740 * @param __FLAG__ specifies the FLASH flags to clear.
741 * This parameter can be any combination of the following values:
742 * @arg FLASH_FLAG_EOP: FLASH End of Operation flag
743 * @arg FLASH_FLAG_OPERR: FLASH Operation error flag
744 * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
745 * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
746 * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
747 * @arg FLASH_FLAG_SIZERR: FLASH Size error flag
748 * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
749 * @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
750 * @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
751 * @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
752 * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
753 * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
754 * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
755 * @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
756 * @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
757 * @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
758 * @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
759 * @note (*) availability depends on devices
760 * @retval None
761 */
762 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
763 if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
764 } while (0)
765 /**
766 * @}
767 */
768
769 /* Include FLASH HAL Extended module */
770 #include "stm32g4xx_hal_flash_ex.h"
771 #include "stm32g4xx_hal_flash_ramfunc.h"
772
773 /* Exported variables --------------------------------------------------------*/
774 /** @defgroup FLASH_Exported_Variables FLASH Exported Variables
775 * @{
776 */
777 extern FLASH_ProcessTypeDef pFlash;
778 /**
779 * @}
780 */
781
782 /* Exported functions --------------------------------------------------------*/
783 /** @addtogroup FLASH_Exported_Functions
784 * @{
785 */
786
787 /* Program operation functions ***********************************************/
788 /** @addtogroup FLASH_Exported_Functions_Group1
789 * @{
790 */
791 HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
792 HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
793 /* FLASH IRQ handler method */
794 void HAL_FLASH_IRQHandler(void);
795 /* Callbacks in non blocking modes */
796 void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
797 void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
798 /**
799 * @}
800 */
801
802 /* Peripheral Control functions **********************************************/
803 /** @addtogroup FLASH_Exported_Functions_Group2
804 * @{
805 */
806 HAL_StatusTypeDef HAL_FLASH_Unlock(void);
807 HAL_StatusTypeDef HAL_FLASH_Lock(void);
808 /* Option bytes control */
809 HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
810 HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
811 HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
812 /**
813 * @}
814 */
815
816 /* Peripheral State functions ************************************************/
817 /** @addtogroup FLASH_Exported_Functions_Group3
818 * @{
819 */
820 uint32_t HAL_FLASH_GetError(void);
821 /**
822 * @}
823 */
824
825 /**
826 * @}
827 */
828
829 /** @addtogroup FLASH_Private_Functions
830 * @{
831 */
832 HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
833 /**
834 * @}
835 */
836
837 /* Private constants --------------------------------------------------------*/
838 /** @defgroup FLASH_Private_Constants FLASH Private Constants
839 * @{
840 */
841 #define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
842
843 // The macro name FLASH_SIZE was renamed to HAL_FLASH_SIZE to avoid name crash with Makefile originated FLASH_SIZE.
844 // The original FLASH_SIZE here was used in this file only, so it was safe to rename it.
845
846 #if defined (FLASH_OPTR_DBANK)
847 #define HAL_FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \
848 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
849 #define FLASH_BANK_SIZE (HAL_FLASH_SIZE >> 1)
850 #define FLASH_PAGE_NB 128U
851 #define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */
852 #else
853 #define HAL_FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
854 (((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
855 #define FLASH_BANK_SIZE (HAL_FLASH_SIZE)
856 #define FLASH_PAGE_NB 64U
857 #endif
858
859 #define FLASH_PAGE_SIZE 0x800U /* 2 KB */
860
861 #define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
862
863 /**
864 * @}
865 */
866
867 /* Private macros ------------------------------------------------------------*/
868 /** @defgroup FLASH_Private_Macros FLASH Private Macros
869 * @{
870 */
871
872 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
873 ((VALUE) == FLASH_TYPEERASE_MASSERASE))
874
875 #if defined (FLASH_OPTR_DBANK)
876 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
877 ((BANK) == FLASH_BANK_2) || \
878 ((BANK) == FLASH_BANK_BOTH))
879
880 #define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
881 ((BANK) == FLASH_BANK_2))
882 #else
883 #define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
884
885 #define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
886 #endif
887
888 #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
889 ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
890 ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
891
892 #define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+HAL_FLASH_SIZE)))
893
894 #define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
895
896 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
897
898 #define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
899
900 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
901 OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
902
903 #if defined (FLASH_OPTR_DBANK)
904 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
905 ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
906 #else
907 #define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
908 #endif
909
910 #define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
911
912 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
913 ((LEVEL) == OB_RDP_LEVEL_1) ||\
914 ((LEVEL) == OB_RDP_LEVEL_2))
915
916 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
917
918 #define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
919 ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
920 ((LEVEL) == OB_BOR_LEVEL_4))
921
922 #define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
923
924 #define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
925
926 #define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
927
928 #define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
929
930 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
931
932 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
933
934 #define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
935
936 #if defined (FLASH_OPTR_DBANK)
937 #define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
938
939 #define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
940 #endif
941
942 #define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
943
944 #define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
945
946 #define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
947
948 #define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
949
950 #define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
951
952 #define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
953 ((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
954
955 #define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
956
957 #define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
958
959 #define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
960
961 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
962 ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
963 ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
964 ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
965 ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
966 ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
967 ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
968 ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
969 /**
970 * @}
971 */
972
973 /**
974 * @}
975 */
976
977 /**
978 * @}
979 */
980
981 #ifdef __cplusplus
982 }
983 #endif
984
985 #endif /* STM32G4xx_HAL_FLASH_H */
986
987 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/