lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of NAND HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                       opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef STM32G4xx_HAL_NAND_H
  22 #define STM32G4xx_HAL_NAND_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 #if defined(FMC_BANK3)
  29
  30 /* Includes ------------------------------------------------------------------*/
  31 #include "stm32g4xx_ll_fmc.h"
  32
  33 /** @addtogroup STM32G4xx_HAL_Driver
  34   * @{
  35   */
  36
  37 /** @addtogroup NAND
  38   * @{
  39   */
  40
  41 /* Exported typedef ----------------------------------------------------------*/
  42 /* Exported types ------------------------------------------------------------*/
  43 /** @defgroup NAND_Exported_Types NAND Exported Types
  44   * @{
  45   */
  46
  47 /**
  48   * @brief  HAL NAND State structures definition
  49   */
  50 typedef enum
  51 {
  52   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  53   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  54   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  55   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  56 } HAL_NAND_StateTypeDef;
  57
  58 /**
  59   * @brief  NAND Memory electronic signature Structure definition
  60   */
  61 typedef struct
  62 {
  63   /*<! NAND memory electronic signature maker and device IDs */
  64
  65   uint8_t Maker_Id;
  66
  67   uint8_t Device_Id;
  68
  69   uint8_t Third_Id;
  70
  71   uint8_t Fourth_Id;
  72 } NAND_IDTypeDef;
  73
  74 /**
  75   * @brief  NAND Memory address Structure definition
  76   */
  77 typedef struct
  78 {
  79   uint16_t Page;   /*!< NAND memory Page address  */
  80
  81   uint16_t Plane;   /*!< NAND memory Zone address  */
  82
  83   uint16_t Block;  /*!< NAND memory Block address */
  84
  85 } NAND_AddressTypeDef;
  86
  87 /**
  88   * @brief  NAND Memory info Structure definition
  89   */
  90 typedef struct
  91 {
  92   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
  93                                               for 8 bits adressing or words for 16 bits addressing             */
  94
  95   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
  96                                               for 8 bits adressing or words for 16 bits addressing             */
  97
  98   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
  99
 100   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 101
 102   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 103
 104   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
 105
 106   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 107                                               parameter is mandatory for some NAND parts after the read
 108                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 109                                               Example: Toshiba THTH58BYG3S0HBAI6.
 110                                               This parameter could be ENABLE or DISABLE
 111                                               Please check the Read Mode sequnece in the NAND device datasheet */
 112 } NAND_DeviceConfigTypeDef;
 113
 114 /**
 115   * @brief  NAND handle Structure definition
 116   */
 117 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 118 typedef struct __NAND_HandleTypeDef
 119 #else
 120 typedef struct
 121 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */
 122 {
 123   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 124
 125   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 126
 127   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 128
 129   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 130
 131   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 132
 133 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 134   void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */
 135   void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */
 136   void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */
 137 #endif
 138 } NAND_HandleTypeDef;
 139
 140 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 141 /**
 142   * @brief  HAL NAND Callback ID enumeration definition
 143   */
 144 typedef enum
 145 {
 146   HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */
 147   HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */
 148   HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */
 149 }HAL_NAND_CallbackIDTypeDef;
 150
 151 /**
 152   * @brief  HAL NAND Callback pointer definition
 153   */
 154 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
 155 #endif
 156
 157 /**
 158   * @}
 159   */
 160
 161 /* Exported constants --------------------------------------------------------*/
 162 /* Exported macro ------------------------------------------------------------*/
 163 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 164  * @{
 165  */
 166
 167 /** @brief Reset NAND handle state
 168   * @param  __HANDLE__ specifies the NAND handle.
 169   * @retval None
 170   */
 171 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 172 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
 173                                                                (__HANDLE__)->State = HAL_NAND_STATE_RESET; \
 174                                                                (__HANDLE__)->MspInitCallback = NULL;       \
 175                                                                (__HANDLE__)->MspDeInitCallback = NULL;     \
 176                                                              } while(0)
 177 #else
 178 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 179 #endif
 180
 181 /**
 182   * @}
 183   */
 184
 185 /* Exported functions --------------------------------------------------------*/
 186 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 187   * @{
 188   */
 189
 190 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 191   * @{
 192   */
 193
 194 /* Initialization/de-initialization functions  ********************************/
 195 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 196 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 197
 198 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 199
 200 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 201
 202 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 203 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 204 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 205 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 206
 207 /**
 208   * @}
 209   */
 210
 211 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 212   * @{
 213   */
 214
 215 /* IO operation functions  ****************************************************/
 216
 217 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 218
 219 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 220 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 221 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 222 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 223
 224 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 225 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 226 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 227 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 228
 229 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 230
 231 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 232
 233 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
 234 /* NAND callback registering/unregistering */
 235 HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);
 236 HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
 237 #endif
 238
 239 /**
 240   * @}
 241   */
 242
 243 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 244   * @{
 245   */
 246
 247 /* NAND Control functions  ****************************************************/
 248 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 249 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 250 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 251
 252 /**
 253   * @}
 254   */
 255
 256 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 257   * @{
 258   */
 259 /* NAND State functions *******************************************************/
 260 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 261 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 262 /**
 263   * @}
 264   */
 265
 266 /**
 267   * @}
 268   */
 269 /* Private types -------------------------------------------------------------*/
 270 /* Private variables ---------------------------------------------------------*/
 271 /* Private constants ---------------------------------------------------------*/
 272 /** @defgroup NAND_Private_Constants NAND Private Constants
 273   * @{
 274   */
 275 #define NAND_DEVICE                ((uint32_t)0x80000000U)
 276 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
 277
 278 #define CMD_AREA                   ((uint32_t)(1UL<<16U))  /* A16 = CLE high */
 279 #define ADDR_AREA                  ((uint32_t)(1UL<<17U))  /* A17 = ALE high */
 280
 281 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
 282 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
 283 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
 284 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
 285
 286 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
 287 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
 288 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
 289 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
 290 #define NAND_CMD_READID            ((uint8_t)0x90U)
 291 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
 292 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
 293 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
 294
 295 /* NAND memory status */
 296 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
 297 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
 298 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
 299 #define NAND_BUSY                  ((uint32_t)0x00000000U)
 300 #define NAND_ERROR                 ((uint32_t)0x00000001U)
 301 #define NAND_READY                 ((uint32_t)0x00000040U)
 302 /**
 303   * @}
 304   */
 305
 306 /* Private macros ------------------------------------------------------------*/
 307 /** @defgroup NAND_Private_Macros NAND Private Macros
 308   * @{
 309   */
 310
 311 /**
 312   * @brief  NAND memory address computation.
 313   * @param  __ADDRESS__ NAND memory address.
 314   * @param  __HANDLE__  NAND handle.
 315   * @retval NAND Raw address value
 316   */
 317 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 318                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 319
 320 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 321
 322 /**
 323   * @brief  NAND memory address cycling.
 324   * @param  __ADDRESS__ NAND memory address.
 325   * @retval NAND address cycling value.
 326   */
 327 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 328 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 329 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 330 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 331
 332 /**
 333   * @brief  NAND memory Columns cycling.
 334   * @param  __ADDRESS__ NAND memory address.
 335   * @retval NAND Column address cycling value.
 336   */
 337 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
 338 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 339
 340 /**
 341   * @}
 342   */
 343
 344 /**
 345   * @}
 346   */
 347
 348 /**
 349   * @}
 350   */
 351
 352 /**
 353   * @}
 354   */
 355
 356 #endif /* FMC_BANK3 */
 357
 358 #ifdef __cplusplus
 359 }
 360 #endif
 361
 362 #endif /* STM32G4xx_HAL_NAND_H */
 363
 364 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/