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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_hal_rcc.h
blob07b307e36c36bb093fafcaf3ece61ddfd9e1cde1
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_HAL_RCC_H
22 #define STM32G4xx_HAL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx_hal_def.h"
30
31 /** @addtogroup STM32G4xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup RCC
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup RCC_Exported_Types RCC Exported Types
41 * @{
42 */
43
44 /**
45 * @brief RCC PLL configuration structure definition
46 */
47 typedef struct
48 {
49 uint32_t PLLState; /*!< The new state of the PLL.
50 This parameter can be a value of @ref RCC_PLL_Config */
51
52 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
53 This parameter must be a value of @ref RCC_PLL_Clock_Source */
54
55 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
56 This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
57
58 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
59 This parameter must be a number between Min_Data = 8 and Max_Data = 127 */
60
61 uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
62 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
63
64 uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks.
65 This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
66
67 uint32_t PLLR; /*!< PLLR: Division for the main system clock.
68 User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ.
69 This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
70
71 }RCC_PLLInitTypeDef;
72
73 /**
74 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
75 */
76 typedef struct
77 {
78 uint32_t OscillatorType; /*!< The oscillators to be configured.
79 This parameter can be a value of @ref RCC_Oscillator_Type */
80
81 uint32_t HSEState; /*!< The new state of the HSE.
82 This parameter can be a value of @ref RCC_HSE_Config */
83
84 uint32_t LSEState; /*!< The new state of the LSE.
85 This parameter can be a value of @ref RCC_LSE_Config */
86
87 uint32_t HSIState; /*!< The new state of the HSI.
88 This parameter can be a value of @ref RCC_HSI_Config */
89
90 uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
91 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
92
93 uint32_t LSIState; /*!< The new state of the LSI.
94 This parameter can be a value of @ref RCC_LSI_Config */
95
96 uint32_t HSI48State; /*!< The new state of the HSI48.
97 This parameter can be a value of @ref RCC_HSI48_Config */
98
99 RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
100
101 }RCC_OscInitTypeDef;
102
103 /**
104 * @brief RCC System, AHB and APB busses clock configuration structure definition
105 */
106 typedef struct
107 {
108 uint32_t ClockType; /*!< The clock to be configured.
109 This parameter can be a value of @ref RCC_System_Clock_Type */
110
111 uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
112 This parameter can be a value of @ref RCC_System_Clock_Source */
113
114 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
115 This parameter can be a value of @ref RCC_AHB_Clock_Source */
116
117 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
118 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
119
120 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
121 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
122
123 }RCC_ClkInitTypeDef;
124
125 /**
126 * @}
127 */
128
129 /* Exported constants --------------------------------------------------------*/
130 /** @defgroup RCC_Exported_Constants RCC Exported Constants
131 * @{
132 */
133
134 /** @defgroup RCC_Timeout_Value Timeout Values
135 * @{
136 */
137 #define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
138 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
139 /**
140 * @}
141 */
142
143 /** @defgroup RCC_Oscillator_Type Oscillator Type
144 * @{
145 */
146 #define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
147 #define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
148 #define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
149 #define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
150 #define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
151 #define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
152 /**
153 * @}
154 */
155
156 /** @defgroup RCC_HSE_Config HSE Config
157 * @{
158 */
159 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
160 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
161 #define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
162 /**
163 * @}
164 */
165
166 /** @defgroup RCC_LSE_Config LSE Config
167 * @{
168 */
169 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
170 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
171 #define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
172 /**
173 * @}
174 */
175
176 /** @defgroup RCC_HSI_Config HSI Config
177 * @{
178 */
179 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
180 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
181 #define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
182 /**
183 * @}
184 */
185
186 /** @defgroup RCC_LSI_Config LSI Config
187 * @{
188 */
189 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
190 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
191 /**
192 * @}
193 */
194
195 /** @defgroup RCC_HSI48_Config HSI48 Config
196 * @{
197 */
198 #define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
199 #define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
200 /**
201 * @}
202 */
203
204 /** @defgroup RCC_PLL_Config PLL Config
205 * @{
206 */
207 #define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
208 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
209 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */
210 /**
211 * @}
212 */
213
214 /** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
215 * @{
216 */
217 #define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
218 #define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
219 #define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
220 #define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
221 #define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
222 #define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
223 #define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
224 #define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
225 #define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
226 #define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
227 #define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
228 #define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
229 #define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
230 #define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
231 #define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
232 #define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
233 /**
234 * @}
235 */
236
237 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
238 * @{
239 */
240 #define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
241 #define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
242 #define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
243 #define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
244 #define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
245 #define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
246 #define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
247 #define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
248 #define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
249 #define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
250 #define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
251 #define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
252 #define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
253 #define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
254 #define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
255 #define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
256 #define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
257 #define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
258 #define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
259 #define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
260 #define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
261 #define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
262 #define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
263 #define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
264 #define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
265 #define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
266 #define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
267 #define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
268 #define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
269 #define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
270 /**
271 * @}
272 */
273
274 /** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
275 * @{
276 */
277 #define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
278 #define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
279 #define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
280 #define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
281 /**
282 * @}
283 */
284
285 /** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
286 * @{
287 */
288 #define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
289 #define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
290 #define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
291 #define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
292 /**
293 * @}
294 */
295
296 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
297 * @{
298 */
299 #define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
300 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
301 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
302 /**
303 * @}
304 */
305
306 /** @defgroup RCC_PLL_Clock_Output PLL Clock Output
307 * @{
308 */
309 #define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
310 #define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
311 #define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
312 /**
313 * @}
314 */
315
316 /** @defgroup RCC_System_Clock_Type System Clock Type
317 * @{
318 */
319 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
320 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
321 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
322 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
323 /**
324 * @}
325 */
326
327 /** @defgroup RCC_System_Clock_Source System Clock Source
328 * @{
329 */
330 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
331 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
332 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
333 /**
334 * @}
335 */
336
337 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
338 * @{
339 */
340 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
341 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
342 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
343 /**
344 * @}
345 */
346
347 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
348 * @{
349 */
350 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
351 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
352 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
353 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
354 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
355 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
356 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
357 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
358 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
359 /**
360 * @}
361 */
362
363 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
364 * @{
365 */
366 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
367 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
368 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
369 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
370 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
371 /**
372 * @}
373 */
374
375 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
376 * @{
377 */
378 #define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
379 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
380 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
381 #define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
382 /**
383 * @}
384 */
385
386 /** @defgroup RCC_MCO_Index MCO Index
387 * @{
388 */
389 #define RCC_MCO1 0x00000000U
390 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
391 /**
392 * @}
393 */
394
395 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
396 * @{
397 */
398 #define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
399 #define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
400 #define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
401 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
402 #define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
403 #define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
404 #define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
405 #define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
406 /**
407 * @}
408 */
409
410 /** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
411 * @{
412 */
413 #define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
414 #define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
415 #define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
416 #define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
417 #define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
418 /**
419 * @}
420 */
421
422 /** @defgroup RCC_Interrupt Interrupts
423 * @{
424 */
425 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
426 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
427 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
428 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
429 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
430 #define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
431 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
432 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
433 /**
434 * @}
435 */
436
437 /** @defgroup RCC_Flag Flags
438 * Elements values convention: XXXYYYYYb
439 * - YYYYY : Flag position in the register
440 * - XXX : Register index
441 * - 001: CR register
442 * - 010: BDCR register
443 * - 011: CSR register
444 * - 100: CRRCR register
445 * @{
446 */
447 /* Flags in the CR register */
448 #define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
449 #define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
450 #define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
451
452 /* Flags in the BDCR register */
453 #define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
454 #define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
455
456 /* Flags in the CSR register */
457 #define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
458 #define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
459 #define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
460 #define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
461 #define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
462 #define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
463 #define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
464 #define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
465
466 /* Flags in the CRRCR register */
467 #define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
468 /**
469 * @}
470 */
471
472 /** @defgroup RCC_LSEDrive_Config LSE Drive Config
473 * @{
474 */
475 #define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
476 #define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
477 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
478 #define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
479 /**
480 * @}
481 */
482
483 /**
484 * @}
485 */
486
487 /* Exported macros -----------------------------------------------------------*/
488
489 /** @defgroup RCC_Exported_Macros RCC Exported Macros
490 * @{
491 */
492
493 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
494 * @brief Enable or disable the AHB1 peripheral clock.
495 * @note After reset, the peripheral clock (used for registers read/write access)
496 * is disabled and the application software has to enable this clock before
497 * using it.
498 * @{
499 */
500
501 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
502 __IO uint32_t tmpreg; \
503 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
504 /* Delay after an RCC peripheral clock enabling */ \
505 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
506 UNUSED(tmpreg); \
507 } while(0)
508
509 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
510 __IO uint32_t tmpreg; \
511 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
512 /* Delay after an RCC peripheral clock enabling */ \
513 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
514 UNUSED(tmpreg); \
515 } while(0)
516
517 #define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
518 __IO uint32_t tmpreg; \
519 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
520 /* Delay after an RCC peripheral clock enabling */ \
521 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
522 UNUSED(tmpreg); \
523 } while(0)
524
525 #define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
526 __IO uint32_t tmpreg; \
527 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
528 /* Delay after an RCC peripheral clock enabling */ \
529 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
530 UNUSED(tmpreg); \
531 } while(0)
532
533 #define __HAL_RCC_FMAC_CLK_ENABLE() do { \
534 __IO uint32_t tmpreg; \
535 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
536 /* Delay after an RCC peripheral clock enabling */ \
537 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
538 UNUSED(tmpreg); \
539 } while(0)
540
541 #define __HAL_RCC_FLASH_CLK_ENABLE() do { \
542 __IO uint32_t tmpreg; \
543 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
544 /* Delay after an RCC peripheral clock enabling */ \
545 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
546 UNUSED(tmpreg); \
547 } while(0)
548
549 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
550 __IO uint32_t tmpreg; \
551 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
552 /* Delay after an RCC peripheral clock enabling */ \
553 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
554 UNUSED(tmpreg); \
555 } while(0)
556
557 #define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
558
559 #define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
560
561 #define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
562
563 #define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
564
565 #define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
566
567 #define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
568
569 #define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
570
571 /**
572 * @}
573 */
574
575 /** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
576 * @brief Enable or disable the AHB2 peripheral clock.
577 * @note After reset, the peripheral clock (used for registers read/write access)
578 * is disabled and the application software has to enable this clock before
579 * using it.
580 * @{
581 */
582
583 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
584 __IO uint32_t tmpreg; \
585 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
586 /* Delay after an RCC peripheral clock enabling */ \
587 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
588 UNUSED(tmpreg); \
589 } while(0)
590
591 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
592 __IO uint32_t tmpreg; \
593 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
594 /* Delay after an RCC peripheral clock enabling */ \
595 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
596 UNUSED(tmpreg); \
597 } while(0)
598
599 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
600 __IO uint32_t tmpreg; \
601 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
602 /* Delay after an RCC peripheral clock enabling */ \
603 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
604 UNUSED(tmpreg); \
605 } while(0)
606
607 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
608 __IO uint32_t tmpreg; \
609 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
610 /* Delay after an RCC peripheral clock enabling */ \
611 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
612 UNUSED(tmpreg); \
613 } while(0)
614
615 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
616 __IO uint32_t tmpreg; \
617 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
618 /* Delay after an RCC peripheral clock enabling */ \
619 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
620 UNUSED(tmpreg); \
621 } while(0)
622
623 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
624 __IO uint32_t tmpreg; \
625 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
626 /* Delay after an RCC peripheral clock enabling */ \
627 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
628 UNUSED(tmpreg); \
629 } while(0)
630
631 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
632 __IO uint32_t tmpreg; \
633 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
634 /* Delay after an RCC peripheral clock enabling */ \
635 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
636 UNUSED(tmpreg); \
637 } while(0)
638
639 #define __HAL_RCC_ADC12_CLK_ENABLE() do { \
640 __IO uint32_t tmpreg; \
641 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
642 /* Delay after an RCC peripheral clock enabling */ \
643 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
644 UNUSED(tmpreg); \
645 } while(0)
646
647 #if defined(ADC345_COMMON)
648 #define __HAL_RCC_ADC345_CLK_ENABLE() do { \
649 __IO uint32_t tmpreg; \
650 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
651 /* Delay after an RCC peripheral clock enabling */ \
652 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
653 UNUSED(tmpreg); \
654 } while(0)
655 #endif /* ADC345_COMMON */
656
657 #define __HAL_RCC_DAC1_CLK_ENABLE() do { \
658 __IO uint32_t tmpreg; \
659 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
660 /* Delay after an RCC peripheral clock enabling */ \
661 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
662 UNUSED(tmpreg); \
663 } while(0)
664
665 #if defined(DAC2)
666 #define __HAL_RCC_DAC2_CLK_ENABLE() do { \
667 __IO uint32_t tmpreg; \
668 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
669 /* Delay after an RCC peripheral clock enabling */ \
670 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
671 UNUSED(tmpreg); \
672 } while(0)
673 #endif /* DAC2 */
674
675 #define __HAL_RCC_DAC3_CLK_ENABLE() do { \
676 __IO uint32_t tmpreg; \
677 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
678 /* Delay after an RCC peripheral clock enabling */ \
679 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
680 UNUSED(tmpreg); \
681 } while(0)
682
683 #if defined(DAC4)
684 #define __HAL_RCC_DAC4_CLK_ENABLE() do { \
685 __IO uint32_t tmpreg; \
686 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
687 /* Delay after an RCC peripheral clock enabling */ \
688 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
689 UNUSED(tmpreg); \
690 } while(0)
691 #endif /* DAC4 */
692
693 #if defined(AES)
694 #define __HAL_RCC_AES_CLK_ENABLE() do { \
695 __IO uint32_t tmpreg; \
696 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
697 /* Delay after an RCC peripheral clock enabling */ \
698 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
699 UNUSED(tmpreg); \
700 } while(0)
701 #endif /* AES */
702
703 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
704 __IO uint32_t tmpreg; \
705 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
706 /* Delay after an RCC peripheral clock enabling */ \
707 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
708 UNUSED(tmpreg); \
709 } while(0)
710
711
712 #define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
713
714 #define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
715
716 #define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
717
718 #define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
719
720 #define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
721
722 #define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
723
724 #define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
725
726 #define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
727
728 #if defined(ADC345_COMMON)
729 #define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
730 #endif /* ADC345_COMMON */
731
732 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
733
734 #if defined(DAC2)
735 #define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
736 #endif /* DAC2 */
737
738 #define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
739
740 #if defined(DAC4)
741 #define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
742 #endif /* DAC4 */
743
744 #if defined(AES)
745 #define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
746 #endif /* AES */
747
748 #define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
749
750 /**
751 * @}
752 */
753
754 /** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
755 * @brief Enable or disable the AHB3 peripheral clock.
756 * @note After reset, the peripheral clock (used for registers read/write access)
757 * is disabled and the application software has to enable this clock before
758 * using it.
759 * @{
760 */
761
762 #if defined(FMC_BANK1)
763 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
764 __IO uint32_t tmpreg; \
765 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
766 /* Delay after an RCC peripheral clock enabling */ \
767 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
768 UNUSED(tmpreg); \
769 } while(0)
770 #endif /* FMC_BANK1 */
771
772 #if defined(QUADSPI)
773 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
774 __IO uint32_t tmpreg; \
775 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
776 /* Delay after an RCC peripheral clock enabling */ \
777 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
778 UNUSED(tmpreg); \
779 } while(0)
780 #endif /* QUADSPI */
781
782 #if defined(FMC_BANK1)
783 #define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
784 #endif /* FMC_BANK1 */
785
786 #if defined(QUADSPI)
787 #define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
788 #endif /* QUADSPI */
789
790 /**
791 * @}
792 */
793
794 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
795 * @brief Enable or disable the APB1 peripheral clock.
796 * @note After reset, the peripheral clock (used for registers read/write access)
797 * is disabled and the application software has to enable this clock before
798 * using it.
799 * @{
800 */
801
802 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
803 __IO uint32_t tmpreg; \
804 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
805 /* Delay after an RCC peripheral clock enabling */ \
806 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
807 UNUSED(tmpreg); \
808 } while(0)
809
810 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
811 __IO uint32_t tmpreg; \
812 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
813 /* Delay after an RCC peripheral clock enabling */ \
814 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
815 UNUSED(tmpreg); \
816 } while(0)
817
818 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
819 __IO uint32_t tmpreg; \
820 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
821 /* Delay after an RCC peripheral clock enabling */ \
822 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
823 UNUSED(tmpreg); \
824 } while(0)
825
826 #if defined(TIM5)
827 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
828 __IO uint32_t tmpreg; \
829 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
830 /* Delay after an RCC peripheral clock enabling */ \
831 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
832 UNUSED(tmpreg); \
833 } while(0)
834 #endif /* TIM5 */
835
836 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
837 __IO uint32_t tmpreg; \
838 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
839 /* Delay after an RCC peripheral clock enabling */ \
840 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
841 UNUSED(tmpreg); \
842 } while(0)
843
844 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
845 __IO uint32_t tmpreg; \
846 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
847 /* Delay after an RCC peripheral clock enabling */ \
848 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
849 UNUSED(tmpreg); \
850 } while(0)
851
852 #define __HAL_RCC_CRS_CLK_ENABLE() do { \
853 __IO uint32_t tmpreg; \
854 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
855 /* Delay after an RCC peripheral clock enabling */ \
856 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
857 UNUSED(tmpreg); \
858 } while(0)
859
860 #define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
861 __IO uint32_t tmpreg; \
862 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
863 /* Delay after an RCC peripheral clock enabling */ \
864 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
865 UNUSED(tmpreg); \
866 } while(0)
867
868 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
869 __IO uint32_t tmpreg; \
870 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
871 /* Delay after an RCC peripheral clock enabling */ \
872 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
873 UNUSED(tmpreg); \
874 } while(0)
875
876 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
877 __IO uint32_t tmpreg; \
878 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
879 /* Delay after an RCC peripheral clock enabling */ \
880 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
881 UNUSED(tmpreg); \
882 } while(0)
883
884 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
885 __IO uint32_t tmpreg; \
886 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
887 /* Delay after an RCC peripheral clock enabling */ \
888 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
889 UNUSED(tmpreg); \
890 } while(0)
891
892 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
893 __IO uint32_t tmpreg; \
894 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
895 /* Delay after an RCC peripheral clock enabling */ \
896 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
897 UNUSED(tmpreg); \
898 } while(0)
899
900 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
901 __IO uint32_t tmpreg; \
902 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
903 /* Delay after an RCC peripheral clock enabling */ \
904 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
905 UNUSED(tmpreg); \
906 } while(0)
907
908 #if defined(UART4)
909 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
910 __IO uint32_t tmpreg; \
911 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
912 /* Delay after an RCC peripheral clock enabling */ \
913 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
914 UNUSED(tmpreg); \
915 } while(0)
916 #endif /* UART4 */
917
918 #if defined(UART5)
919 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
920 __IO uint32_t tmpreg; \
921 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
922 /* Delay after an RCC peripheral clock enabling */ \
923 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
924 UNUSED(tmpreg); \
925 } while(0)
926 #endif /* UART5 */
927
928 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
929 __IO uint32_t tmpreg; \
930 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
931 /* Delay after an RCC peripheral clock enabling */ \
932 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
933 UNUSED(tmpreg); \
934 } while(0)
935
936 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
937 __IO uint32_t tmpreg; \
938 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
939 /* Delay after an RCC peripheral clock enabling */ \
940 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
941 UNUSED(tmpreg); \
942 } while(0)
943
944 #define __HAL_RCC_USB_CLK_ENABLE() do { \
945 __IO uint32_t tmpreg; \
946 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
947 /* Delay after an RCC peripheral clock enabling */ \
948 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
949 UNUSED(tmpreg); \
950 } while(0)
951
952 #if defined(FDCAN1)
953 #define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
954 __IO uint32_t tmpreg; \
955 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
956 /* Delay after an RCC peripheral clock enabling */ \
957 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
958 UNUSED(tmpreg); \
959 } while(0)
960 #endif /* FDCAN1 */
961
962 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
963 __IO uint32_t tmpreg; \
964 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
965 /* Delay after an RCC peripheral clock enabling */ \
966 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
967 UNUSED(tmpreg); \
968 } while(0)
969
970 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
971 __IO uint32_t tmpreg; \
972 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
973 /* Delay after an RCC peripheral clock enabling */ \
974 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
975 UNUSED(tmpreg); \
976 } while(0)
977
978 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
979 __IO uint32_t tmpreg; \
980 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
981 /* Delay after an RCC peripheral clock enabling */ \
982 tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
983 UNUSED(tmpreg); \
984 } while(0)
985
986 #define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
987 __IO uint32_t tmpreg; \
988 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
989 /* Delay after an RCC peripheral clock enabling */ \
990 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
991 UNUSED(tmpreg); \
992 } while(0)
993
994 #if defined(I2C4)
995 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
996 __IO uint32_t tmpreg; \
997 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
998 /* Delay after an RCC peripheral clock enabling */ \
999 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
1000 UNUSED(tmpreg); \
1001 } while(0)
1002 #endif /* I2C4 */
1003
1004 #define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
1005 __IO uint32_t tmpreg; \
1006 SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
1007 /* Delay after an RCC peripheral clock enabling */ \
1008 tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
1009 UNUSED(tmpreg); \
1010 } while(0)
1011
1012 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
1013
1014 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
1015
1016 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
1017
1018 #if defined(TIM5)
1019 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1020 #endif /* TIM5 */
1021
1022 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
1023
1024 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
1025
1026 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
1027
1028 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
1029
1030 #define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN)
1031
1032 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
1033
1034 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
1035
1036 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
1037
1038 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
1039
1040 #if defined(UART4)
1041 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
1042 #endif /* UART4 */
1043
1044 #if defined(UART5)
1045 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
1046 #endif /* UART5 */
1047
1048 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
1049
1050 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
1051
1052 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
1053
1054 #if defined(FDCAN1)
1055 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
1056 #endif /* FDCAN1 */
1057
1058 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
1059
1060 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
1061
1062 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
1063
1064 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
1065
1066 #if defined(I2C4)
1067 #define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
1068 #endif /* I2C4 */
1069
1070 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
1071
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
1077 * @brief Enable or disable the APB2 peripheral clock.
1078 * @note After reset, the peripheral clock (used for registers read/write access)
1079 * is disabled and the application software has to enable this clock before
1080 * using it.
1081 * @{
1082 */
1083
1084 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
1085 __IO uint32_t tmpreg; \
1086 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1087 /* Delay after an RCC peripheral clock enabling */ \
1088 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
1089 UNUSED(tmpreg); \
1090 } while(0)
1091
1092 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
1093 __IO uint32_t tmpreg; \
1094 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1095 /* Delay after an RCC peripheral clock enabling */ \
1096 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
1097 UNUSED(tmpreg); \
1098 } while(0)
1099
1100 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
1101 __IO uint32_t tmpreg; \
1102 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1103 /* Delay after an RCC peripheral clock enabling */ \
1104 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
1105 UNUSED(tmpreg); \
1106 } while(0)
1107
1108 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
1109 __IO uint32_t tmpreg; \
1110 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1111 /* Delay after an RCC peripheral clock enabling */ \
1112 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
1113 UNUSED(tmpreg); \
1114 } while(0)
1115
1116 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
1117 __IO uint32_t tmpreg; \
1118 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1119 /* Delay after an RCC peripheral clock enabling */ \
1120 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
1121 UNUSED(tmpreg); \
1122 } while(0)
1123
1124 #if defined(SPI4)
1125 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
1126 __IO uint32_t tmpreg; \
1127 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
1128 /* Delay after an RCC peripheral clock enabling */ \
1129 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
1130 UNUSED(tmpreg); \
1131 } while(0)
1132 #endif /* SPI4 */
1133
1134 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
1135 __IO uint32_t tmpreg; \
1136 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1137 /* Delay after an RCC peripheral clock enabling */ \
1138 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
1139 UNUSED(tmpreg); \
1140 } while(0)
1141
1142 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
1143 __IO uint32_t tmpreg; \
1144 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1145 /* Delay after an RCC peripheral clock enabling */ \
1146 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
1147 UNUSED(tmpreg); \
1148 } while(0)
1149
1150 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
1151 __IO uint32_t tmpreg; \
1152 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1153 /* Delay after an RCC peripheral clock enabling */ \
1154 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
1155 UNUSED(tmpreg); \
1156 } while(0)
1157
1158 #if defined(TIM20)
1159 #define __HAL_RCC_TIM20_CLK_ENABLE() do { \
1160 __IO uint32_t tmpreg; \
1161 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
1162 /* Delay after an RCC peripheral clock enabling */ \
1163 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
1164 UNUSED(tmpreg); \
1165 } while(0)
1166 #endif /* TIM20 */
1167
1168 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
1169 __IO uint32_t tmpreg; \
1170 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1171 /* Delay after an RCC peripheral clock enabling */ \
1172 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
1173 UNUSED(tmpreg); \
1174 } while(0)
1175
1176 #if defined(HRTIM1)
1177 #define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
1178 __IO uint32_t tmpreg; \
1179 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
1180 /* Delay after an RCC peripheral clock enabling */ \
1181 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
1182 UNUSED(tmpreg); \
1183 } while(0)
1184 #endif /* HRTIM1 */
1185
1186 #define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
1187
1188 #define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
1189
1190 #define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
1191
1192 #define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
1193
1194 #define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
1195
1196 #if defined(SPI4)
1197 #define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
1198 #endif /* SPI4 */
1199
1200 #define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
1201
1202 #define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
1203
1204 #define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
1205
1206 #if defined(TIM20)
1207 #define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
1208 #endif /* TIM20 */
1209
1210 #define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
1211
1212 #if defined(HRTIM1)
1213 #define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
1214 #endif /* HRTIM1 */
1215
1216 /**
1217 * @}
1218 */
1219
1220 /** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
1221 * @brief Check whether the AHB1 peripheral clock is enabled or not.
1222 * @note After reset, the peripheral clock (used for registers read/write access)
1223 * is disabled and the application software has to enable this clock before
1224 * using it.
1225 * @{
1226 */
1227
1228 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
1229
1230 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
1231
1232 #define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
1233
1234 #define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
1235
1236 #define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
1237
1238 #define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
1239
1240 #define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
1241
1242 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
1243
1244 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
1245
1246 #define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
1247
1248 #define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
1249
1250 #define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
1251
1252 #define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
1253
1254 #define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
1255
1256 /**
1257 * @}
1258 */
1259
1260 /** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
1261 * @brief Check whether the AHB2 peripheral clock is enabled or not.
1262 * @note After reset, the peripheral clock (used for registers read/write access)
1263 * is disabled and the application software has to enable this clock before
1264 * using it.
1265 * @{
1266 */
1267
1268 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
1269
1270 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
1271
1272 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
1273
1274 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
1275
1276 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
1277
1278 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
1279
1280 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
1281
1282 #define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
1283
1284 #if defined(ADC345_COMMON)
1285 #define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
1286 #endif /* ADC345_COMMON */
1287
1288 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
1289
1290 #if defined(DAC2)
1291 #define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
1292 #endif /* DAC2 */
1293
1294 #define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
1295
1296 #if defined(DAC4)
1297 #define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
1298 #endif /* DAC4 */
1299
1300 #if defined(AES)
1301 #define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
1302 #endif /* AES */
1303
1304 #define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
1305
1306
1307 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
1308
1309 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
1310
1311 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
1312
1313 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
1314
1315 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
1316
1317 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
1318
1319 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
1320
1321 #define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
1322
1323 #if defined(ADC345_COMMON)
1324 #define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
1325 #endif /* ADC345_COMMON */
1326
1327 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
1328
1329 #if defined(DAC2)
1330 #define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
1331 #endif /* DAC2 */
1332
1333 #define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
1334
1335 #if defined(DAC4)
1336 #define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
1337 #endif /* DAC4 */
1338
1339 #if defined(AES)
1340 #define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
1341 #endif /* AES */
1342
1343 #define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
1344
1345 /**
1346 * @}
1347 */
1348
1349 /** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
1350 * @brief Check whether the AHB3 peripheral clock is enabled or not.
1351 * @note After reset, the peripheral clock (used for registers read/write access)
1352 * is disabled and the application software has to enable this clock before
1353 * using it.
1354 * @{
1355 */
1356
1357 #if defined(FMC_BANK1)
1358 #define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
1359 #endif /* FMC_BANK1 */
1360
1361 #if defined(QUADSPI)
1362 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
1363 #endif /* QUADSPI */
1364
1365 #if defined(FMC_BANK1)
1366 #define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
1367 #endif /* FMC_BANK1 */
1368
1369 #if defined(QUADSPI)
1370 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
1371 #endif /* QUADSPI */
1372
1373 /**
1374 * @}
1375 */
1376
1377 /** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
1378 * @brief Check whether the APB1 peripheral clock is enabled or not.
1379 * @note After reset, the peripheral clock (used for registers read/write access)
1380 * is disabled and the application software has to enable this clock before
1381 * using it.
1382 * @{
1383 */
1384
1385 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
1386
1387 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
1388
1389 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
1390
1391 #if defined(TIM5)
1392 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
1393 #endif /* TIM5 */
1394
1395 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
1396
1397 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
1398
1399 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
1400
1401 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
1402
1403 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
1404
1405 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
1406
1407 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
1408
1409 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
1410
1411 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
1412
1413 #if defined(UART4)
1414 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
1415 #endif /* UART4 */
1416
1417 #if defined(UART5)
1418 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
1419 #endif /* UART5 */
1420
1421 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
1422
1423 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
1424
1425 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
1426
1427 #if defined(FDCAN1)
1428 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
1429 #endif /* FDCAN1 */
1430
1431 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
1432
1433 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
1434
1435 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
1436
1437 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
1438
1439 #if defined(I2C4)
1440 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
1441 #endif /* I2C4 */
1442
1443 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
1444
1445 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
1446
1447 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
1448
1449 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
1450
1451 #if defined(TIM5)
1452 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
1453 #endif /* TIM5 */
1454
1455 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
1456
1457 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
1458
1459 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
1460
1461 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
1462
1463 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
1464
1465 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
1466
1467 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
1468
1469 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
1470
1471 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
1472
1473 #if defined(UART4)
1474 #define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
1475 #endif /* UART4 */
1476
1477 #if defined(UART5)
1478 #define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
1479 #endif /* UART5 */
1480
1481 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
1482
1483 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
1484
1485 #if defined(USB)
1486 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
1487 #endif /* USB */
1488
1489 #if defined(FDCAN1)
1490 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
1491 #endif /* FDCAN1 */
1492
1493 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
1494
1495 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
1496
1497 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
1498
1499 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
1500
1501 #if defined(I2C4)
1502 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
1503 #endif /* I2C4 */
1504
1505 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
1506
1507 /**
1508 * @}
1509 */
1510
1511 /** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
1512 * @brief Check whether the APB2 peripheral clock is enabled or not.
1513 * @note After reset, the peripheral clock (used for registers read/write access)
1514 * is disabled and the application software has to enable this clock before
1515 * using it.
1516 * @{
1517 */
1518
1519 #define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
1520
1521 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
1522
1523 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
1524
1525 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
1526
1527 #define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
1528
1529 #if defined(SPI4)
1530 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
1531 #endif /* SPI4 */
1532
1533 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
1534
1535 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
1536
1537 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
1538
1539 #if defined(TIM20)
1540 #define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
1541 #endif /* TIM20 */
1542
1543 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
1544
1545 #if defined(HRTIM1)
1546 #define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
1547 #endif /* HRTIM1 */
1548
1549
1550 #define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
1551
1552 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
1553
1554 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
1555
1556 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
1557
1558 #define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
1559
1560 #if defined(SPI4)
1561 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
1562 #endif /* SPI4 */
1563
1564 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
1565
1566 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
1567
1568 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
1569
1570 #if defined(TIM20)
1571 #define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
1572 #endif /* TIM20 */
1573
1574 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
1575
1576 #if defined(HRTIM1)
1577 #define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
1578 #endif /* HRTIM1 */
1579
1580 /**
1581 * @}
1582 */
1583
1584 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
1585 * @brief Force or release AHB1 peripheral reset.
1586 * @{
1587 */
1588 #define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
1589
1590 #define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
1591
1592 #define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
1593
1594 #define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
1595
1596 #define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
1597
1598 #define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
1599
1600 #define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
1601
1602 #define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
1603
1604
1605 #define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
1606
1607 #define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
1608
1609 #define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
1610
1611 #define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
1612
1613 #define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
1614
1615 #define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
1616
1617 #define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
1618
1619 #define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
1620
1621 /**
1622 * @}
1623 */
1624
1625 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
1626 * @brief Force or release AHB2 peripheral reset.
1627 * @{
1628 */
1629 #define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
1630
1631 #define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
1632
1633 #define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
1634
1635 #define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
1636
1637 #define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
1638
1639 #define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
1640
1641 #define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
1642
1643 #define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
1644
1645 #define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
1646
1647 #if defined(ADC345_COMMON)
1648 #define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
1649 #endif /* ADC345_COMMON */
1650
1651 #define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
1652
1653 #if defined(DAC2)
1654 #define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
1655 #endif /* DAC2 */
1656
1657 #define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
1658
1659 #if defined(DAC4)
1660 #define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
1661 #endif /* DAC4 */
1662
1663 #if defined(AES)
1664 #define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
1665 #endif /* AES */
1666
1667 #define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
1668
1669
1670 #define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
1671
1672 #define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
1673
1674 #define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
1675
1676 #define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
1677
1678 #define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
1679
1680 #define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
1681
1682 #define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
1683
1684 #define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
1685
1686 #define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
1687
1688 #if defined(ADC345_COMMON)
1689 #define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
1690 #endif /* ADC345_COMMON */
1691
1692 #define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
1693
1694 #if defined(DAC2)
1695 #define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
1696 #endif /* DAC2 */
1697
1698 #define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
1699
1700 #if defined(DAC4)
1701 #define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
1702 #endif /* DAC4 */
1703
1704 #if defined(AES)
1705 #define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
1706 #endif /* AES */
1707
1708 #define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
1709
1710 /**
1711 * @}
1712 */
1713
1714 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
1715 * @brief Force or release AHB3 peripheral reset.
1716 * @{
1717 */
1718 #define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
1719
1720 #if defined(FMC_BANK1)
1721 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
1722 #endif /* FMC_BANK1 */
1723
1724 #if defined(QUADSPI)
1725 #define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
1726 #endif /* QUADSPI */
1727
1728 #define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
1729
1730 #if defined(FMC_BANK1)
1731 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
1732 #endif /* FMC_BANK1 */
1733
1734 #if defined(QUADSPI)
1735 #define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
1736 #endif /* QUADSPI */
1737
1738 /**
1739 * @}
1740 */
1741
1742 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
1743 * @brief Force or release APB1 peripheral reset.
1744 * @{
1745 */
1746 #define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
1747
1748 #define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1749
1750 #define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1751
1752 #define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
1753
1754 #if defined(TIM5)
1755 #define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
1756 #endif /* TIM5 */
1757
1758 #define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
1759
1760 #define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
1761
1762 #define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
1763
1764 #define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
1765
1766 #define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
1767
1768 #define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
1769
1770 #define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
1771
1772 #if defined(UART4)
1773 #define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
1774 #endif /* UART4 */
1775
1776 #if defined(UART5)
1777 #define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
1778 #endif /* UART5 */
1779
1780 #define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
1781
1782 #define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
1783
1784 #define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
1785
1786 #if defined(FDCAN1)
1787 #define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
1788 #endif /* FDCAN1 */
1789
1790 #define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
1791
1792 #define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
1793
1794 #define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
1795
1796 #define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
1797
1798 #if defined(I2C4)
1799 #define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
1800 #endif /* I2C4 */
1801
1802 #define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
1803
1804 #define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
1805
1806 #define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
1807
1808 #define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
1809
1810 #define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
1811
1812 #if defined(TIM5)
1813 #define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
1814 #endif /* TIM5 */
1815
1816 #define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
1817
1818 #define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
1819
1820 #define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
1821
1822 #define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
1823
1824 #define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
1825
1826 #define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
1827
1828 #define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
1829
1830 #if defined(UART4)
1831 #define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
1832 #endif /* UART4 */
1833
1834 #if defined(UART5)
1835 #define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
1836 #endif /* UART5 */
1837
1838 #define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
1839
1840 #define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
1841
1842 #define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
1843
1844 #if defined(FDCAN1)
1845 #define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
1846 #endif /* FDCAN1 */
1847
1848 #define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
1849
1850 #define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
1851
1852 #define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
1853
1854 #define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
1855
1856 #if defined(I2C4)
1857 #define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
1858 #endif /* I2C4 */
1859
1860 #define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
1861
1862 /**
1863 * @}
1864 */
1865
1866 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
1867 * @brief Force or release APB2 peripheral reset.
1868 * @{
1869 */
1870 #define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
1871
1872 #define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
1873
1874 #define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
1875
1876 #define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
1877
1878 #define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
1879
1880 #define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
1881
1882 #if defined(SPI4)
1883 #define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
1884 #endif /* SPI4 */
1885
1886 #define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
1887
1888 #define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
1889
1890 #define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
1891
1892 #if defined(TIM20)
1893 #define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
1894 #endif /* TIM20 */
1895
1896 #define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
1897
1898 #if defined(HRTIM1)
1899 #define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
1900 #endif /* HRTIM1 */
1901
1902
1903 #define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
1904
1905 #define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
1906
1907 #define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
1908
1909 #define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
1910
1911 #define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
1912
1913 #define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
1914
1915 #if defined(SPI4)
1916 #define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
1917 #endif /* SPI4 */
1918
1919 #define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
1920
1921 #define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
1922
1923 #define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
1924
1925 #if defined(TIM20)
1926 #define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
1927 #endif /* TIM20 */
1928
1929 #define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
1930
1931 #if defined(HRTIM1)
1932 #define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
1933 #endif /* HRTIM1 */
1934
1935 /**
1936 * @}
1937 */
1938
1939 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
1940 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
1941 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1942 * power consumption.
1943 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1944 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1945 * @{
1946 */
1947
1948 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
1949
1950 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
1951
1952 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
1953
1954 #define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
1955
1956 #define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
1957
1958 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
1959
1960 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
1961
1962 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
1963
1964
1965 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
1966
1967 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
1968
1969 #define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
1970
1971 #define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
1972
1973 #define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
1974
1975 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
1976
1977 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
1978
1979 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
1980
1981 /**
1982 * @}
1983 */
1984
1985 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
1986 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
1987 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
1988 * power consumption.
1989 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
1990 * @note By default, all peripheral clocks are enabled during SLEEP mode.
1991 * @{
1992 */
1993
1994 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
1995
1996 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
1997
1998 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
1999
2000 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
2001
2002 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
2003
2004 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
2005
2006 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
2007
2008 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
2009
2010 #define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
2011
2012 #define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
2013
2014 #if defined(ADC345_COMMON)
2015 #define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
2016 #endif /* ADC345_COMMON */
2017
2018 #define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
2019
2020 #if defined(DAC2)
2021 #define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
2022 #endif /* DAC2 */
2023
2024 #define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
2025
2026 #if defined(DAC4)
2027 #define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
2028 #endif /* DAC4 */
2029
2030 #if defined(AES)
2031 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
2032 #endif /* AES */
2033
2034 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
2035
2036
2037 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
2038
2039 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
2040
2041 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
2042
2043 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
2044
2045 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
2046
2047 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
2048
2049 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
2050
2051 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
2052
2053 #define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
2054
2055 #define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
2056
2057 #if defined(ADC345_COMMON)
2058 #define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
2059 #endif /* ADC345_COMMON */
2060
2061 #define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
2062
2063 #if defined(DAC2)
2064 #define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
2065 #endif /* DAC2 */
2066
2067 #define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
2068
2069 #if defined(DAC4)
2070 #define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
2071 #endif /* DAC4 */
2072
2073 #if defined(AES)
2074 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
2075 #endif /* AES */
2076
2077 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
2078
2079 /**
2080 * @}
2081 */
2082
2083 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
2084 * @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
2085 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2086 * power consumption.
2087 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2088 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2089 * @{
2090 */
2091
2092 #if defined(FMC_BANK1)
2093 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
2094 #endif /* FMC_BANK1 */
2095
2096 #if defined(QUADSPI)
2097 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
2098 #endif /* QUADSPI */
2099
2100 #if defined(FMC_BANK1)
2101 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
2102 #endif /* FMC_BANK1 */
2103
2104 #if defined(QUADSPI)
2105 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
2106 #endif /* QUADSPI */
2107
2108 /**
2109 * @}
2110 */
2111
2112 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
2113 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
2114 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2115 * power consumption.
2116 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2117 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2118 * @{
2119 */
2120
2121 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
2122
2123 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
2124
2125 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2126
2127 #if defined(TIM5)
2128 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
2129 #endif /* TIM5 */
2130
2131 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
2132
2133 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
2134
2135 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
2136
2137 #define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
2138
2139 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
2140
2141 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
2142
2143 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
2144
2145 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
2146
2147 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
2148
2149 #if defined(UART4)
2150 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
2151 #endif /* UART4 */
2152
2153 #if defined(UART5)
2154 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
2155 #endif /* UART5 */
2156
2157 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
2158
2159 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
2160
2161 #if defined(USB)
2162 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
2163 #endif /* USB */
2164
2165 #if defined(FDCAN1)
2166 #define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
2167 #endif /* FDCAN1 */
2168
2169 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
2170
2171 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
2172
2173 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
2174
2175 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
2176
2177 #if defined(I2C4)
2178 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
2179 #endif /* I2C4 */
2180
2181 #define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
2182
2183
2184 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
2185
2186 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
2187
2188 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
2189
2190 #if defined(TIM5)
2191 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
2192 #endif /* TIM5 */
2193
2194 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
2195
2196 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
2197
2198 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
2199
2200 #define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
2201
2202 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
2203
2204 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
2205
2206 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
2207
2208 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
2209
2210 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
2211
2212 #if defined(UART4)
2213 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
2214 #endif /* UART4 */
2215
2216 #if defined(UART5)
2217 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
2218 #endif /* UART5 */
2219
2220 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
2221
2222 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
2223
2224 #if defined(USB)
2225 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
2226 #endif /* USB */
2227
2228 #if defined(FDCAN1)
2229 #define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
2230 #endif /* FDCAN1 */
2231
2232 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
2233
2234 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
2235
2236 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
2237
2238 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
2239
2240 #if defined(I2C4)
2241 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
2242 #endif /* I2C4 */
2243
2244 #define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
2245
2246 /**
2247 * @}
2248 */
2249
2250 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
2251 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
2252 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2253 * power consumption.
2254 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2255 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2256 * @{
2257 */
2258
2259 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
2260
2261 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
2262
2263 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
2264
2265 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
2266
2267 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
2268
2269 #if defined(SPI4)
2270 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
2271 #endif /* SPI4 */
2272
2273 #define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
2274
2275 #define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
2276
2277 #define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
2278
2279 #if defined(TIM20)
2280 #define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
2281 #endif /* TIM20 */
2282
2283 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
2284
2285 #if defined(HRTIM1)
2286 #define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
2287 #endif /* HRTIM1 */
2288
2289
2290 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
2291
2292 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
2293
2294 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
2295
2296 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
2297
2298 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
2299
2300 #if defined(SPI4)
2301 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
2302 #endif /* SPI4 */
2303
2304 #define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
2305
2306 #define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
2307
2308 #define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
2309
2310 #if defined(TIM20)
2311 #define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
2312 #endif /* TIM20 */
2313
2314 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
2315
2316 #if defined(HRTIM1)
2317 #define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
2318 #endif /* HRTIM1 */
2319
2320 /**
2321 * @}
2322 */
2323
2324 /** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
2325 * @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
2326 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2327 * power consumption.
2328 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2329 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2330 * @{
2331 */
2332
2333 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
2334
2335 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
2336
2337 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
2338
2339 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
2340
2341 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
2342
2343 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
2344
2345 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
2346
2347 #define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
2348
2349
2350 #define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
2351
2352 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
2353
2354 #define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
2355
2356 #define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
2357
2358 #define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
2359
2360 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
2361
2362 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
2363
2364 #define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
2365
2366 /**
2367 * @}
2368 */
2369
2370 /** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
2371 * @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
2372 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2373 * power consumption.
2374 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2375 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2376 * @{
2377 */
2378
2379 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
2380
2381 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
2382
2383 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
2384
2385 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
2386
2387 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
2388
2389 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
2390
2391 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
2392
2393 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
2394
2395 #define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
2396
2397 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
2398
2399 #if defined(ADC345_COMMON)
2400 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
2401 #endif /* ADC345_COMMON */
2402
2403 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
2404
2405 #if defined(DAC2)
2406 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
2407 #endif /* DAC2 */
2408
2409 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
2410
2411 #if defined(DAC4)
2412 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
2413 #endif /* DAC4 */
2414
2415 #if defined(AES)
2416 #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
2417 #endif /* AES */
2418
2419 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
2420
2421
2422 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
2423
2424 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
2425
2426 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
2427
2428 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
2429
2430 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
2431
2432 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
2433
2434 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
2435
2436 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
2437
2438 #define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
2439
2440 #define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
2441
2442 #if defined(ADC345_COMMON)
2443 #define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
2444 #endif /* ADC345_COMMON */
2445
2446 #define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
2447
2448 #if defined(DAC2)
2449 #define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
2450 #endif /* DAC2 */
2451
2452 #define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
2453
2454 #if defined(DAC4)
2455 #define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
2456 #endif /* DAC4 */
2457
2458 #if defined(AES)
2459 #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
2460 #endif /* AES */
2461
2462 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
2463
2464 /**
2465 * @}
2466 */
2467
2468 /** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
2469 * @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
2470 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2471 * power consumption.
2472 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2473 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2474 * @{
2475 */
2476
2477 #if defined(FMC_BANK1)
2478 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
2479 #endif /* FMC_BANK1 */
2480
2481 #if defined(QUADSPI)
2482 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
2483 #endif /* QUADSPI */
2484
2485 #if defined(FMC_BANK1)
2486 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
2487 #endif /* FMC_BANK1 */
2488
2489 #if defined(QUADSPI)
2490 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
2491 #endif /* QUADSPI */
2492
2493 /**
2494 * @}
2495 */
2496
2497 /** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
2498 * @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
2499 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2500 * power consumption.
2501 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2502 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2503 * @{
2504 */
2505
2506 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
2507
2508 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
2509
2510 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
2511
2512 #if defined(TIM5)
2513 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
2514 #endif /* TIM5 */
2515
2516 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
2517
2518 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
2519
2520 #define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
2521
2522 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
2523
2524 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
2525
2526 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
2527
2528 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
2529
2530 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
2531
2532 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
2533
2534 #if defined(UART4)
2535 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
2536 #endif /* UART4 */
2537
2538 #if defined(UART5)
2539 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
2540 #endif /* UART5 */
2541
2542 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
2543
2544 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
2545
2546 #define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
2547
2548 #if defined(FDCAN1)
2549 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
2550 #endif /* FDCAN1 */
2551
2552 #define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
2553
2554 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
2555
2556 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
2557
2558 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
2559
2560 #if defined(I2C4)
2561 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
2562 #endif /* I2C4 */
2563
2564 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
2565
2566
2567 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
2568
2569 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
2570
2571 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
2572
2573 #if defined(TIM5)
2574 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
2575 #endif /* TIM5 */
2576
2577 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
2578
2579 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
2580
2581 #define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
2582
2583 #define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
2584
2585 #define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
2586
2587 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
2588
2589 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
2590
2591 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
2592
2593 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
2594
2595 #if defined(UART4)
2596 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
2597 #endif /* UART4 */
2598
2599 #if defined(UART5)
2600 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
2601 #endif /* UART5 */
2602
2603 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
2604
2605 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
2606
2607 #define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
2608
2609 #if defined(FDCAN1)
2610 #define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
2611 #endif /* FDCAN1 */
2612
2613 #define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
2614
2615 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
2616
2617 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
2618
2619 #define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
2620
2621 #if defined(I2C4)
2622 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
2623 #endif /* I2C4 */
2624
2625 #define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
2626
2627 /**
2628 * @}
2629 */
2630
2631 /** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
2632 * @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
2633 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
2634 * power consumption.
2635 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
2636 * @note By default, all peripheral clocks are enabled during SLEEP mode.
2637 * @{
2638 */
2639
2640 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
2641
2642 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
2643
2644 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
2645
2646 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
2647
2648 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
2649
2650 #if defined(SPI4)
2651 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
2652 #endif /* SPI4 */
2653
2654 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
2655
2656 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
2657
2658 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
2659
2660 #if defined(TIM20)
2661 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
2662 #endif /* TIM20 */
2663
2664 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
2665
2666 #if defined(HRTIM1)
2667 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
2668 #endif /* HRTIM1 */
2669
2670
2671 #define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
2672
2673 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
2674
2675 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
2676
2677 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
2678
2679 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
2680
2681 #if defined(SPI4)
2682 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
2683 #endif /* SPI4 */
2684
2685 #define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
2686
2687 #define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
2688
2689 #define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
2690
2691 #if defined(TIM20)
2692 #define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
2693 #endif /* TIM20 */
2694
2695 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
2696
2697 #if defined(HRTIM1)
2698 #define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
2699 #endif /* HRTIM1 */
2700
2701
2702 /**
2703 * @}
2704 */
2705
2706 /** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
2707 * @{
2708 */
2709
2710 /** @brief Macros to force or release the Backup domain reset.
2711 * @note This function resets the RTC peripheral (including the backup registers)
2712 * and the RTC clock source selection in RCC_CSR register.
2713 * @note The BKPSRAM is not affected by this reset.
2714 * @retval None
2715 */
2716 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
2717
2718 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
2719
2720 /**
2721 * @}
2722 */
2723
2724 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
2725 * @{
2726 */
2727
2728 /** @brief Macros to enable or disable the RTC clock.
2729 * @note As the RTC is in the Backup domain and write access is denied to
2730 * this domain after reset, you have to enable write access using
2731 * HAL_PWR_EnableBkUpAccess() function before to configure the RTC
2732 * (to be done once after reset).
2733 * @note These macros must be used after the RTC clock source was selected.
2734 * @retval None
2735 */
2736 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
2737
2738 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
2739
2740 /**
2741 * @}
2742 */
2743
2744 /** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
2745 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
2746 * It is used (enabled by hardware) as system clock source after startup
2747 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
2748 * of the HSE used directly or indirectly as system clock (if the Clock
2749 * Security System CSS is enabled).
2750 * @note HSI can not be stopped if it is used as system clock source. In this case,
2751 * you have to select another source of the system clock then stop the HSI.
2752 * @note After enabling the HSI, the application software should wait on HSIRDY
2753 * flag to be set indicating that HSI clock is stable and can be used as
2754 * system clock source.
2755 * This parameter can be: ENABLE or DISABLE.
2756 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
2757 * clock cycles.
2758 * @retval None
2759 */
2760 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
2761
2762 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
2763
2764 /** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
2765 * @note The calibration is used to compensate for the variations in voltage
2766 * and temperature that influence the frequency of the internal HSI RC.
2767 * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
2768 * (default is RCC_HSICALIBRATION_DEFAULT).
2769 * This parameter must be a number between 0 and 0x7F.
2770 * @retval None
2771 */
2772 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
2773 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
2774
2775 /**
2776 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
2777 * in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
2778 * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
2779 * speed because of the HSI startup time.
2780 * @note The enable of this function has not effect on the HSION bit.
2781 * This parameter can be: ENABLE or DISABLE.
2782 * @retval None
2783 */
2784 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
2785
2786 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
2787
2788 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
2789 * @note After enabling the LSI, the application software should wait on
2790 * LSIRDY flag to be set indicating that LSI clock is stable and can
2791 * be used to clock the IWDG and/or the RTC.
2792 * @note LSI can not be disabled if the IWDG is running.
2793 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
2794 * clock cycles.
2795 * @retval None
2796 */
2797 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
2798
2799 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
2800
2801 /**
2802 * @brief Macro to configure the External High Speed oscillator (HSE).
2803 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
2804 * supported by this macro. User should request a transition to HSE Off
2805 * first and then HSE On or HSE Bypass.
2806 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
2807 * software should wait on HSERDY flag to be set indicating that HSE clock
2808 * is stable and can be used to clock the PLL and/or system clock.
2809 * @note HSE state can not be changed if it is used directly or through the
2810 * PLL as system clock. In this case, you have to select another source
2811 * of the system clock then change the HSE state (ex. disable it).
2812 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
2813 * @note This function reset the CSSON bit, so if the clock security system(CSS)
2814 * was previously enabled you have to enable it again after calling this
2815 * function.
2816 * @param __STATE__ specifies the new state of the HSE.
2817 * This parameter can be one of the following values:
2818 * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
2819 * 6 HSE oscillator clock cycles.
2820 * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
2821 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
2822 * @retval None
2823 */
2824 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
2825 do { \
2826 if((__STATE__) == RCC_HSE_ON) \
2827 { \
2828 SET_BIT(RCC->CR, RCC_CR_HSEON); \
2829 } \
2830 else if((__STATE__) == RCC_HSE_BYPASS) \
2831 { \
2832 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
2833 SET_BIT(RCC->CR, RCC_CR_HSEON); \
2834 } \
2835 else \
2836 { \
2837 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
2838 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
2839 } \
2840 } while(0)
2841
2842 /**
2843 * @brief Macro to configure the External Low Speed oscillator (LSE).
2844 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
2845 * supported by this macro. User should request a transition to LSE Off
2846 * first and then LSE On or LSE Bypass.
2847 * @note As the LSE is in the Backup domain and write access is denied to
2848 * this domain after reset, you have to enable write access using
2849 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
2850 * (to be done once after reset).
2851 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
2852 * software should wait on LSERDY flag to be set indicating that LSE clock
2853 * is stable and can be used to clock the RTC.
2854 * @param __STATE__ specifies the new state of the LSE.
2855 * This parameter can be one of the following values:
2856 * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
2857 * 6 LSE oscillator clock cycles.
2858 * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
2859 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
2860 * @retval None
2861 */
2862 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
2863 do { \
2864 if((__STATE__) == RCC_LSE_ON) \
2865 { \
2866 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2867 } \
2868 else if((__STATE__) == RCC_LSE_BYPASS) \
2869 { \
2870 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
2871 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2872 } \
2873 else \
2874 { \
2875 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
2876 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
2877 } \
2878 } while(0)
2879
2880 /** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
2881 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
2882 * @note After enabling the HSI48, the application software should wait on HSI48RDY
2883 * flag to be set indicating that HSI48 clock is stable.
2884 * This parameter can be: ENABLE or DISABLE.
2885 * @retval None
2886 */
2887 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
2888
2889 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
2890
2891 /** @brief Macros to configure the RTC clock (RTCCLK).
2892 * @note As the RTC clock configuration bits are in the Backup domain and write
2893 * access is denied to this domain after reset, you have to enable write
2894 * access using the Power Backup Access macro before to configure
2895 * the RTC clock source (to be done once after reset).
2896 * @note Once the RTC clock is configured it cannot be changed unless the
2897 * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
2898 * a Power On Reset (POR).
2899 *
2900 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
2901 * This parameter can be one of the following values:
2902 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
2903 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
2904 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
2905 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
2906 *
2907 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
2908 * work in STOP and STANDBY modes, and can be used as wakeup source.
2909 * However, when the HSE clock is used as RTC clock source, the RTC
2910 * cannot be used in STOP and STANDBY modes.
2911 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
2912 * RTC clock source).
2913 * @retval None
2914 */
2915 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
2916 MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
2917
2918
2919 /** @brief Macro to get the RTC clock source.
2920 * @retval The returned value can be one of the following:
2921 * @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
2922 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
2923 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
2924 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
2925 */
2926 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
2927
2928 /** @brief Macros to enable or disable the main PLL.
2929 * @note After enabling the main PLL, the application software should wait on
2930 * PLLRDY flag to be set indicating that PLL clock is stable and can
2931 * be used as system clock source.
2932 * @note The main PLL can not be disabled if it is used as system clock source
2933 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
2934 * @retval None
2935 */
2936 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
2937
2938 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
2939
2940 /** @brief Macro to configure the PLL clock source.
2941 * @note This function must be used only when the main PLL is disabled.
2942 * @param __PLLSOURCE__ specifies the PLL entry clock source.
2943 * This parameter can be one of the following values:
2944 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
2945 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
2946 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
2947 * @retval None
2948 *
2949 */
2950 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
2951 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
2952
2953 /** @brief Macro to configure the PLL source division factor M.
2954 * @note This function must be used only when the main PLL is disabled.
2955 * @param __PLLM__ specifies the division factor for PLL VCO input clock
2956 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
2957 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2958 * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
2959 * of 8 MHz to limit PLL jitter.
2960 * @retval None
2961 *
2962 */
2963 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
2964 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
2965
2966 /**
2967 * @brief Macro to configure the main PLL clock source, multiplication and division factors.
2968 * @note This macro must be used only when the main PLL is disabled.
2969 * @note This macro preserves the PLL's output clocks enable state.
2970 *
2971 * @param __PLLSOURCE__ specifies the PLL entry clock source.
2972 * This parameter can be one of the following values:
2973 * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
2974 * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
2975 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
2976 *
2977 * @param __PLLM__ specifies the division factor for PLL VCO input clock.
2978 * This parameter must be a value of @ref RCC_PLLM_Clock_Divider
2979 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
2980 * frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
2981 * of 8 MHz to limit PLL jitter.
2982 *
2983 * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
2984 * This parameter must be a number between 8 and 127.
2985 * @note You have to set the PLLN parameter correctly to ensure that the VCO
2986 * output frequency is between 64 and 344 MHz.
2987 *
2988 * @param __PLLP__ specifies the division factor for SAI clock.
2989 * This parameter must be a number in the range (2 to 31).
2990 *
2991 * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
2992 * This parameter must be in the range (2, 4, 6 or 8).
2993 * @note If the USB OTG FS is used in your application, you have to set the
2994 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
2995 * the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
2996 * correctly.
2997 * @param __PLLR__ specifies the division factor for the main system clock.
2998 * @note You have to set the PLLR parameter correctly to not exceed 170MHZ.
2999 * This parameter must be in the range (2, 4, 6 or 8).
3000 * @retval None
3001 */
3002 #define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
3003 MODIFY_REG(RCC->PLLCFGR, \
3004 (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
3005 RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
3006 ((__PLLSOURCE__) | \
3007 (((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
3008 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
3009 ((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
3010 ((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
3011 ((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
3012
3013 /** @brief Macro to get the oscillator used as PLL clock source.
3014 * @retval The oscillator used as PLL clock source. The returned value can be one
3015 * of the following:
3016 * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
3017 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
3018 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
3019 */
3020 #define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
3021
3022 /**
3023 * @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
3024 * @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime
3025 * without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
3026 * be stopped if used as System Clock.
3027 * @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
3028 * This parameter can be one or a combination of the following values:
3029 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
3030 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
3031 * FDCAN (<=48 MHz) and QSPI (<=48 MHz).
3032 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
3033 * @retval None
3034 */
3035 #define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
3036
3037 #define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
3038
3039 /**
3040 * @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
3041 * @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
3042 * This parameter can be one of the following values:
3043 * @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
3044 * @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
3045 * FDCAN (<=48 MHz) and QSPI (<=48 MHz).
3046 * @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
3047 * @retval SET / RESET
3048 */
3049 #define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
3050
3051 /**
3052 * @brief Macro to configure the system clock source.
3053 * @param __SYSCLKSOURCE__ specifies the system clock source.
3054 * This parameter can be one of the following values:
3055 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
3056 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
3057 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
3058 * @retval None
3059 */
3060 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
3061 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
3062
3063 /** @brief Macro to get the clock source used as system clock.
3064 * @retval The clock source used as system clock. The returned value can be one
3065 * of the following:
3066 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
3067 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
3068 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
3069 */
3070 #define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
3071
3072 /**
3073 * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
3074 * @note As the LSE is in the Backup domain and write access is denied to
3075 * this domain after reset, you have to enable write access using
3076 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
3077 * (to be done once after reset).
3078 * @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
3079 * This parameter can be one of the following values:
3080 * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
3081 * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
3082 * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
3083 * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
3084 * @retval None
3085 */
3086 #define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
3087 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
3088
3089 /** @brief Macro to configure the MCO clock.
3090 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
3091 * This parameter can be one of the following values:
3092 * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
3093 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
3094 * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
3095 * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
3096 * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
3097 * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
3098 * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
3099 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
3100 * @param __MCODIV__ specifies the MCO clock prescaler.
3101 * This parameter can be one of the following values:
3102 * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
3103 * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
3104 * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
3105 * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
3106 * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
3107 */
3108 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
3109 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
3110
3111 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
3112 * @brief macros to manage the specified RCC Flags and interrupts.
3113 * @{
3114 */
3115
3116 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
3117 * the selected interrupts).
3118 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
3119 * This parameter can be any combination of the following values:
3120 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3121 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3122 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3123 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3124 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3125 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3126 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3127 * @retval None
3128 */
3129 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
3130
3131 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
3132 * the selected interrupts).
3133 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
3134 * This parameter can be any combination of the following values:
3135 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3136 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3137 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3138 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3139 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3140 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3141 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3142 * @retval None
3143 */
3144 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
3145
3146 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
3147 * bits to clear the selected interrupt pending bits.
3148 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
3149 * This parameter can be any combination of the following values:
3150 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3151 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3152 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3153 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3154 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3155 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
3156 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3157 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3158 * @retval None
3159 */
3160 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
3161
3162 /** @brief Check whether the RCC interrupt has occurred or not.
3163 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
3164 * This parameter can be one of the following values:
3165 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
3166 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
3167 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
3168 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
3169 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
3170 * @arg @ref RCC_IT_CSS HSE Clock security system interrupt
3171 * @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
3172 * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
3173 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
3174 */
3175 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
3176
3177 /** @brief Set RMVF bit to clear the reset flags.
3178 * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
3179 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
3180 * @retval None
3181 */
3182 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
3183
3184 /** @brief Check whether the selected RCC flag is set or not.
3185 * @param __FLAG__ specifies the flag to check.
3186 * This parameter can be one of the following values:
3187 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
3188 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
3189 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
3190 * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
3191 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
3192 * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
3193 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
3194 * @arg @ref RCC_FLAG_BORRST BOR reset
3195 * @arg @ref RCC_FLAG_OBLRST OBLRST reset
3196 * @arg @ref RCC_FLAG_PINRST Pin reset
3197 * @arg @ref RCC_FLAG_SFTRST Software reset
3198 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
3199 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
3200 * @arg @ref RCC_FLAG_LPWRRST Low Power reset
3201 * @retval The new state of __FLAG__ (TRUE or FALSE).
3202 */
3203 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
3204 ((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
3205 ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
3206 ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
3207 ((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
3208 ? 1U : 0U)
3209
3210 /**
3211 * @}
3212 */
3213
3214 /**
3215 * @}
3216 */
3217
3218 /* Private constants ---------------------------------------------------------*/
3219 /** @addtogroup RCC_Private_Constants
3220 * @{
3221 */
3222 /* Defines used for Flags */
3223 #define CR_REG_INDEX 1U
3224 #define BDCR_REG_INDEX 2U
3225 #define CSR_REG_INDEX 3U
3226 #define CRRCR_REG_INDEX 4U
3227
3228 #define RCC_FLAG_MASK 0x1FU
3229
3230 /* Define used for IS_RCC_CLOCKTYPE() */
3231 #define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */
3232
3233 /**
3234 * @}
3235 */
3236
3237 /* Private macros ------------------------------------------------------------*/
3238 /** @addtogroup RCC_Private_Macros
3239 * @{
3240 */
3241
3242 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
3243 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
3244 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
3245 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
3246 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
3247 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
3248
3249 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
3250 ((__HSE__) == RCC_HSE_BYPASS))
3251
3252 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
3253 ((__LSE__) == RCC_LSE_BYPASS))
3254
3255 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
3256
3257 #define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
3258
3259 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
3260
3261 #define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
3262
3263 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
3264 ((__PLL__) == RCC_PLL_ON))
3265
3266 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
3267 ((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
3268 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
3269
3270 #define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
3271
3272 #define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
3273
3274 #define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
3275
3276 #define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3277 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3278
3279 #define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
3280 ((__VALUE__) == 6U) || ((__VALUE__) == 8U))
3281
3282 #define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
3283
3284 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
3285 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
3286 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
3287
3288 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
3289 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
3290 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
3291 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
3292 ((__HCLK__) == RCC_SYSCLK_DIV512))
3293
3294 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
3295 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
3296 ((__PCLK__) == RCC_HCLK_DIV16))
3297
3298 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
3299 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
3300 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
3301 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
3302
3303 #define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1)
3304
3305 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
3306 ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
3307 ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
3308 ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
3309 ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
3310 ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
3311 ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
3312 ((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
3313
3314 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
3315 ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
3316 ((__DIV__) == RCC_MCODIV_16))
3317
3318 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
3319 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
3320 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
3321 ((__DRIVE__) == RCC_LSEDRIVE_HIGH))
3322
3323 /**
3324 * @}
3325 */
3326
3327 /* Include RCC HAL Extended module */
3328 #include "stm32g4xx_hal_rcc_ex.h"
3329
3330 /* Exported functions --------------------------------------------------------*/
3331 /** @addtogroup RCC_Exported_Functions
3332 * @{
3333 */
3334
3335
3336 /** @addtogroup RCC_Exported_Functions_Group1
3337 * @{
3338 */
3339
3340 /* Initialization and de-initialization functions ******************************/
3341 HAL_StatusTypeDef HAL_RCC_DeInit(void);
3342 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
3343 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
3344
3345 /**
3346 * @}
3347 */
3348
3349 /** @addtogroup RCC_Exported_Functions_Group2
3350 * @{
3351 */
3352
3353 /* Peripheral Control functions ************************************************/
3354 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
3355 void HAL_RCC_EnableCSS(void);
3356 void HAL_RCC_EnableLSECSS(void);
3357 void HAL_RCC_DisableLSECSS(void);
3358 uint32_t HAL_RCC_GetSysClockFreq(void);
3359 uint32_t HAL_RCC_GetHCLKFreq(void);
3360 uint32_t HAL_RCC_GetPCLK1Freq(void);
3361 uint32_t HAL_RCC_GetPCLK2Freq(void);
3362 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
3363 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
3364 /* CSS NMI IRQ handler */
3365 void HAL_RCC_NMI_IRQHandler(void);
3366 /* User Callbacks in non blocking mode (IT mode) */
3367 void HAL_RCC_CSSCallback(void);
3368
3369 /**
3370 * @}
3371 */
3372
3373 /**
3374 * @}
3375 */
3376
3377 /**
3378 * @}
3379 */
3380
3381 /**
3382 * @}
3383 */
3384
3385 #ifdef __cplusplus
3386 }
3387 #endif
3388
3389 #endif /* STM32G4xx_HAL_RCC_H */
3390
3391 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/