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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_hal_tim.h
blobf01cdaad7238286ad4acd6fb6c8c909635570c2e
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_HAL_TIM_H
22 #define STM32G4xx_HAL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx_hal_def.h"
30
31 /** @addtogroup STM32G4xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup TIM
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup TIM_Exported_Types TIM Exported Types
41 * @{
42 */
43
44 /**
45 * @brief TIM Time base Configuration Structure definition
46 */
47 typedef struct
48 {
49 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
50 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
51 Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
52
53 uint32_t CounterMode; /*!< Specifies the counter mode.
54 This parameter can be a value of @ref TIM_Counter_Mode */
55
56 uint32_t Period; /*!< Specifies the period value to be loaded into the active
57 Auto-Reload Register at the next update event.
58 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)
59 Macros __HAL_TIM_CALC_PERIOD(), __HAL_TIM_CALC_PERIOD_DITHER(), __HAL_TIM_CALC_PERIOD_BY_DELAY(), __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()
60 can be used to calculate Period value */
61
62 uint32_t ClockDivision; /*!< Specifies the clock division.
63 This parameter can be a value of @ref TIM_ClockDivision */
64
65 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
66 reaches zero, an update event is generated and counting restarts
67 from the RCR value (N).
68 This means in PWM mode that (N+1) corresponds to:
69 - the number of PWM periods in edge-aligned mode
70 - the number of half PWM period in center-aligned mode
71 GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
72 Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
73
74 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
75 This parameter can be a value of @ref TIM_AutoReloadPreload */
76 } TIM_Base_InitTypeDef;
77
78 /**
79 * @brief TIM Output Compare Configuration Structure definition
80 */
81 typedef struct
82 {
83 uint32_t OCMode; /*!< Specifies the TIM mode.
84 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
85
86 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
87 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)
88 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER()
89 can be used to calculate Pulse value */
90
91 uint32_t OCPolarity; /*!< Specifies the output polarity.
92 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
93
94 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
95 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
96 @note This parameter is valid only for timer instances supporting break feature. */
97
98 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
99 This parameter can be a value of @ref TIM_Output_Fast_State
100 @note This parameter is valid only in PWM1 and PWM2 mode. */
101
102
103 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
104 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
105 @note This parameter is valid only for timer instances supporting break feature. */
106
107 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
108 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
109 @note This parameter is valid only for timer instances supporting break feature. */
110 } TIM_OC_InitTypeDef;
111
112 /**
113 * @brief TIM One Pulse Mode Configuration Structure definition
114 */
115 typedef struct
116 {
117 uint32_t OCMode; /*!< Specifies the TIM mode.
118 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
119
120 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
121 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF (or 0xFFEF if dithering is activated)
122 Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER()
123 can be used to calculate Pulse value */
124
125 uint32_t OCPolarity; /*!< Specifies the output polarity.
126 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
127
128 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
129 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
130 @note This parameter is valid only for timer instances supporting break feature. */
131
132 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
133 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
134 @note This parameter is valid only for timer instances supporting break feature. */
135
136 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
137 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
138 @note This parameter is valid only for timer instances supporting break feature. */
139
140 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
141 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
142
143 uint32_t ICSelection; /*!< Specifies the input.
144 This parameter can be a value of @ref TIM_Input_Capture_Selection */
145
146 uint32_t ICFilter; /*!< Specifies the input capture filter.
147 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
148 } TIM_OnePulse_InitTypeDef;
149
150 /**
151 * @brief TIM Input Capture Configuration Structure definition
152 */
153 typedef struct
154 {
155 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
156 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
157
158 uint32_t ICSelection; /*!< Specifies the input.
159 This parameter can be a value of @ref TIM_Input_Capture_Selection */
160
161 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
162 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
163
164 uint32_t ICFilter; /*!< Specifies the input capture filter.
165 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
166 } TIM_IC_InitTypeDef;
167
168 /**
169 * @brief TIM Encoder Configuration Structure definition
170 */
171 typedef struct
172 {
173 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
174 This parameter can be a value of @ref TIM_Encoder_Mode */
175
176 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
177 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
178
179 uint32_t IC1Selection; /*!< Specifies the input.
180 This parameter can be a value of @ref TIM_Input_Capture_Selection */
181
182 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
183 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
184
185 uint32_t IC1Filter; /*!< Specifies the input capture filter.
186 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
187
188 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
189 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
190
191 uint32_t IC2Selection; /*!< Specifies the input.
192 This parameter can be a value of @ref TIM_Input_Capture_Selection */
193
194 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
195 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
196
197 uint32_t IC2Filter; /*!< Specifies the input capture filter.
198 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
199 } TIM_Encoder_InitTypeDef;
200
201 /**
202 * @brief Clock Configuration Handle Structure definition
203 */
204 typedef struct
205 {
206 uint32_t ClockSource; /*!< TIM clock sources
207 This parameter can be a value of @ref TIM_Clock_Source */
208 uint32_t ClockPolarity; /*!< TIM clock polarity
209 This parameter can be a value of @ref TIM_Clock_Polarity */
210 uint32_t ClockPrescaler; /*!< TIM clock prescaler
211 This parameter can be a value of @ref TIM_Clock_Prescaler */
212 uint32_t ClockFilter; /*!< TIM clock filter
213 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
214 } TIM_ClockConfigTypeDef;
215
216 /**
217 * @brief TIM Clear Input Configuration Handle Structure definition
218 */
219 typedef struct
220 {
221 uint32_t ClearInputState; /*!< TIM clear Input state
222 This parameter can be ENABLE or DISABLE */
223 uint32_t ClearInputSource; /*!< TIM clear Input sources
224 This parameter can be a value of @ref TIM_ClearInput_Source */
225 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
226 This parameter can be a value of @ref TIM_ClearInput_Polarity */
227 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
228 This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
229 uint32_t ClearInputFilter; /*!< TIM Clear Input filter
230 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
231 } TIM_ClearInputConfigTypeDef;
232
233 /**
234 * @brief TIM Master configuration Structure definition
235 * @note Advanced timers provide TRGO2 internal line which is redirected
236 * to the ADC
237 */
238 typedef struct
239 {
240 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
241 This parameter can be a value of @ref TIM_Master_Mode_Selection */
242 uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
243 This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
244 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
245 This parameter can be a value of @ref TIM_Master_Slave_Mode */
246 } TIM_MasterConfigTypeDef;
247
248 /**
249 * @brief TIM Slave configuration Structure definition
250 */
251 typedef struct
252 {
253 uint32_t SlaveMode; /*!< Slave mode selection
254 This parameter can be a value of @ref TIM_Slave_Mode */
255 uint32_t InputTrigger; /*!< Input Trigger source
256 This parameter can be a value of @ref TIM_Trigger_Selection */
257 uint32_t TriggerPolarity; /*!< Input Trigger polarity
258 This parameter can be a value of @ref TIM_Trigger_Polarity */
259 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
260 This parameter can be a value of @ref TIM_Trigger_Prescaler */
261 uint32_t TriggerFilter; /*!< Input trigger filter
262 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
263
264 } TIM_SlaveConfigTypeDef;
265
266 /**
267 * @brief TIM Break input(s) and Dead time configuration Structure definition
268 * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
269 * filter and polarity.
270 */
271 typedef struct
272 {
273 uint32_t OffStateRunMode; /*!< TIM off state in run mode
274 This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
275 uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode
276 This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
277 uint32_t LockLevel; /*!< TIM Lock level
278 This parameter can be a value of @ref TIM_Lock_level */
279 uint32_t DeadTime; /*!< TIM dead Time
280 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
281 uint32_t BreakState; /*!< TIM Break State
282 This parameter can be a value of @ref TIM_Break_Input_enable_disable */
283 uint32_t BreakPolarity; /*!< TIM Break input polarity
284 This parameter can be a value of @ref TIM_Break_Polarity */
285 uint32_t BreakFilter; /*!< Specifies the break input filter.
286 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
287 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
288 This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
289 uint32_t Break2State; /*!< TIM Break2 State
290 This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
291 uint32_t Break2Polarity; /*!< TIM Break2 input polarity
292 This parameter can be a value of @ref TIM_Break2_Polarity */
293 uint32_t Break2Filter; /*!< TIM break2 input filter.
294 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
295 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
296 This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
297 uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state
298 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
299 } TIM_BreakDeadTimeConfigTypeDef;
300
301 /**
302 * @brief HAL State structures definition
303 */
304 typedef enum
305 {
306 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
307 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
308 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
309 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
310 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
311 } HAL_TIM_StateTypeDef;
312
313 /**
314 * @brief HAL Active channel structures definition
315 */
316 typedef enum
317 {
318 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
319 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
320 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
321 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
322 HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
323 HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
324 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
325 } HAL_TIM_ActiveChannel;
326
327 /**
328 * @brief TIM Time Base Handle Structure definition
329 */
330 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
331 typedef struct __TIM_HandleTypeDef
332 #else
333 typedef struct
334 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
335 {
336 TIM_TypeDef *Instance; /*!< Register base address */
337 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
338 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
339 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
340 This array is accessed by a @ref DMA_Handle_index */
341 HAL_LockTypeDef Lock; /*!< Locking object */
342 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
343
344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
345 void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
346 void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
347 void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
348 void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
349 void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
350 void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
351 void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
352 void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
353 void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
354 void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
355 void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
356 void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
357 void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
358 void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
359 void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
360 void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
361 void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
362 void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
363 void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
364 void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
365 void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
366 void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
367 void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
368 void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
369 void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
370 void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
371 void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
372 void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
373 void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */
374 void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */
375 void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */
376 void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */
377 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
378 } TIM_HandleTypeDef;
379
380 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
381 /**
382 * @brief HAL TIM Callback ID enumeration definition
383 */
384 typedef enum
385 {
386 HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
387 ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
388 ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
389 ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
390 ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
391 ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
392 ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
393 ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
394 ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
395 ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
396 ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
397 ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
398 ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
399 ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
400 ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
401 ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
402 ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
403 ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
404
405 ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
406 ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
407 ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
408 ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
409 ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
410 ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
411 ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
412 ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
413 ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
414 ,HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
415 ,HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */
416 ,HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */
417 ,HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */
418 ,HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */
419 } HAL_TIM_CallbackIDTypeDef;
420
421 /**
422 * @brief HAL TIM Callback pointer definition
423 */
424 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
425
426 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
427
428 /**
429 * @}
430 */
431 /* End of exported types -----------------------------------------------------*/
432
433 /* Exported constants --------------------------------------------------------*/
434 /** @defgroup TIM_Exported_Constants TIM Exported Constants
435 * @{
436 */
437
438 /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
439 * @{
440 */
441 #define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
442 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
443 #define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
444 #define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
445 #define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */
446 #define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */
447 #if defined (COMP5)
448 #define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */
449 #endif /* COMP5 */
450 #if defined (COMP6)
451 #define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */
452 #endif /* COMP6 */
453 #if defined (COMP7)
454 #define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */
455 #endif /* COMP7 */
456 /**
457 * @}
458 */
459
460 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
461 * @{
462 */
463 #define TIM_DMABASE_CR1 0x00000000U
464 #define TIM_DMABASE_CR2 0x00000001U
465 #define TIM_DMABASE_SMCR 0x00000002U
466 #define TIM_DMABASE_DIER 0x00000003U
467 #define TIM_DMABASE_SR 0x00000004U
468 #define TIM_DMABASE_EGR 0x00000005U
469 #define TIM_DMABASE_CCMR1 0x00000006U
470 #define TIM_DMABASE_CCMR2 0x00000007U
471 #define TIM_DMABASE_CCER 0x00000008U
472 #define TIM_DMABASE_CNT 0x00000009U
473 #define TIM_DMABASE_PSC 0x0000000AU
474 #define TIM_DMABASE_ARR 0x0000000BU
475 #define TIM_DMABASE_RCR 0x0000000CU
476 #define TIM_DMABASE_CCR1 0x0000000DU
477 #define TIM_DMABASE_CCR2 0x0000000EU
478 #define TIM_DMABASE_CCR3 0x0000000FU
479 #define TIM_DMABASE_CCR4 0x00000010U
480 #define TIM_DMABASE_BDTR 0x00000011U
481 #define TIM_DMABASE_CCR5 0x00000012U
482 #define TIM_DMABASE_CCR6 0x00000013U
483 #define TIM_DMABASE_CCMR3 0x00000014U
484 #define TIM_DMABASE_DTR2 0x00000015U
485 #define TIM_DMABASE_ECR 0x00000016U
486 #define TIM_DMABASE_TISEL 0x00000017U
487 #define TIM_DMABASE_AF1 0x00000018U
488 #define TIM_DMABASE_AF2 0x00000019U
489 #define TIM_DMABASE_OR 0x0000001AU
490 /**
491 * @}
492 */
493
494 /** @defgroup TIM_Event_Source TIM Event Source
495 * @{
496 */
497 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
498 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
499 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
500 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
501 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
502 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
503 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
504 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
505 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
506 /**
507 * @}
508 */
509
510 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
511 * @{
512 */
513 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
514 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
515 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
516 /**
517 * @}
518 */
519
520 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
521 * @{
522 */
523 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
524 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
525 /**
526 * @}
527 */
528
529 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
530 * @{
531 */
532 #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
533 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
534 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
535 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
536 /**
537 * @}
538 */
539
540 /** @defgroup TIM_Counter_Mode TIM Counter Mode
541 * @{
542 */
543 #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
544 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
545 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
546 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
547 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
548 /**
549 * @}
550 */
551
552 /** @defgroup TIM_ClockDivision TIM Clock Division
553 * @{
554 */
555 #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
556 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
557 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
558 /**
559 * @}
560 */
561
562 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
563 * @{
564 */
565 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
566 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
567 /**
568 * @}
569 */
570
571 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
572 * @{
573 */
574 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
575 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
576
577 /**
578 * @}
579 */
580
581 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
582 * @{
583 */
584 #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
585 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
591 * @{
592 */
593 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
594 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
595 /**
596 * @}
597 */
598
599 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
600 * @{
601 */
602 #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
603 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
604 /**
605 * @}
606 */
607
608 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
609 * @{
610 */
611 #define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
612 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
613 /**
614 * @}
615 */
616
617 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
618 * @{
619 */
620 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
621 #define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
627 * @{
628 */
629 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
630 #define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
636 * @{
637 */
638 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
639 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
640 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
641 /**
642 * @}
643 */
644
645 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
646 * @{
647 */
648 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
649 connected to IC1, IC2, IC3 or IC4, respectively */
650 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
651 connected to IC2, IC1, IC4 or IC3, respectively */
652 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
653 /**
654 * @}
655 */
656
657 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
658 * @{
659 */
660 #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
661 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
662 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
663 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
664 /**
665 * @}
666 */
667
668 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
669 * @{
670 */
671 #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
672 #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
673 /**
674 * @}
675 */
676
677 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
678 * @{
679 */
680 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
681 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
682 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
683 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */
684 #define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
685 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
686 #define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
687 #define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
688 #define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
694 * @{
695 */
696 #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
697 #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
698 #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
699 #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
700 #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
701 #define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
702 #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
703 #define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
704 #define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */
705 #define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */
706 #define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */
707 #define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */
708 /**
709 * @}
710 */
711
712 /** @defgroup TIM_Commutation_Source TIM Commutation Source
713 * @{
714 */
715 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
716 #define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_DMA_sources TIM DMA Sources
722 * @{
723 */
724 #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
725 #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
726 #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
727 #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
728 #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
729 #define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
730 #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
731 /**
732 * @}
733 */
734
735 /** @defgroup TIM_Flag_definition TIM Flag Definition
736 * @{
737 */
738 #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
739 #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
740 #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
741 #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
742 #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
743 #define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
744 #define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
745 #define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
746 #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
747 #define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
748 #define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
749 #define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
750 #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
751 #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
752 #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
753 #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
754 #define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */
755 #define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */
756 #define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */
757 #define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */
758 /**
759 * @}
760 */
761
762 /** @defgroup TIM_Channel TIM Channel
763 * @{
764 */
765 #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
766 #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
767 #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
768 #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
769 #define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
770 #define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
771 #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
772 /**
773 * @}
774 */
775
776 /** @defgroup TIM_Clock_Source TIM Clock Source
777 * @{
778 */
779 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
780 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
781 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
782 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
783 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
784 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
785 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
786 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
787 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
788 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
789 #if defined (TIM5)
790 #define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
791 #endif /* TIM5 */
792 #define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
793 #define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
794 #define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
795 #define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
796 #if defined (TIM20)
797 #define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */
798 #endif /* TIM20 */
799 #define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */
800 #define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */
801 /**
802 * @}
803 */
804
805 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
806 * @{
807 */
808 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
809 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
810 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
811 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
812 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
813 /**
814 * @}
815 */
816
817 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
818 * @{
819 */
820 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
821 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
822 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
823 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
824 /**
825 * @}
826 */
827
828 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
829 * @{
830 */
831 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
832 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
833 /**
834 * @}
835 */
836
837 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
838 * @{
839 */
840 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
841 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
842 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
843 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
844 /**
845 * @}
846 */
847
848 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
849 * @{
850 */
851 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
852 #define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
853 /**
854 * @}
855 */
856
857 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
858 * @{
859 */
860 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
861 #define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
862 /**
863 * @}
864 */
865 /** @defgroup TIM_Lock_level TIM Lock level
866 * @{
867 */
868 #define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
869 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
870 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
871 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
872 /**
873 * @}
874 */
875
876 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
877 * @{
878 */
879 #define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
880 #define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
881 /**
882 * @}
883 */
884
885 /** @defgroup TIM_Break_Polarity TIM Break Input Polarity
886 * @{
887 */
888 #define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
889 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
890 /**
891 * @}
892 */
893
894 /** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
895 * @{
896 */
897 #define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
898 #define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
899 /**
900 * @}
901 */
902
903 /** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
904 * @{
905 */
906 #define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
907 #define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
908 /**
909 * @}
910 */
911
912 /** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
913 * @{
914 */
915 #define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
916 #define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
917 /**
918 * @}
919 */
920
921 /** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
922 * @{
923 */
924 #define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
925 #define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
926 /**
927 * @}
928 */
929
930 /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
931 * @{
932 */
933 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
934 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event
935 (if none of the break inputs BRK and BRK2 is active) */
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
941 * @{
942 */
943 #define TIM_GROUPCH5_NONE 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
944 #define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
945 #define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
946 #define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
947 /**
948 * @}
949 */
950
951 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
952 * @{
953 */
954 #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
955 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
956 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
957 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
958 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
959 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
960 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
961 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
962 #define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */
963 /**
964 * @}
965 */
966
967 /** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
968 * @{
969 */
970 #define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
971 #define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
972 #define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
973 #define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
974 #define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
975 #define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
976 #define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
977 #define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
978 #define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
979 #define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
980 #define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
981 #define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
982 #define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
983 #define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
984 #define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
985 #define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
986 /**
987 * @}
988 */
989
990 /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
991 * @{
992 */
993 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
994 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
995 /**
996 * @}
997 */
998
999 /** @defgroup TIM_Slave_Mode TIM Slave mode
1000 * @{
1001 */
1002 #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
1003 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
1004 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
1005 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
1006 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
1007 #define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
1008 #define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */
1009 /**
1010 * @}
1011 */
1012
1013 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
1014 * @{
1015 */
1016 #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
1017 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
1018 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
1019 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
1020 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
1021 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
1022 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
1023 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
1024 #define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
1025 #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
1026 #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
1027 #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
1028 #define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
1029 #define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
1030 #define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
1031 #define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
1032 /**
1033 * @}
1034 */
1035
1036 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
1037 * @{
1038 */
1039 #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
1040 #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
1041 #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
1042 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
1043 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
1044 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
1045 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
1046 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
1047 #if defined (TIM5)
1048 #define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */
1049 #endif /* TIM5 */
1050 #define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
1051 #define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
1052 #define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
1053 #define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
1054 #if defined (TIM20)
1055 #define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
1056 #endif /* TIM20 */
1057 #define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
1058 #define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
1059 #define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */
1060 /**
1061 * @}
1062 */
1063
1064 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
1065 * @{
1066 */
1067 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
1068 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
1069 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1070 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1071 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
1072 /**
1073 * @}
1074 */
1075
1076 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
1077 * @{
1078 */
1079 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
1080 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
1081 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
1082 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
1083 /**
1084 * @}
1085 */
1086
1087 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
1088 * @{
1089 */
1090 #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
1091 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
1092 /**
1093 * @}
1094 */
1095
1096 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
1097 * @{
1098 */
1099 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
1100 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1101 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1102 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1103 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1104 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1105 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1106 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1107 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1108 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1109 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1110 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1111 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1112 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1113 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1114 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1115 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1116 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1117 #define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1118 #define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1119 #define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1120 #define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1121 #define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1122 #define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1123 #define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1124 #define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
1125 /**
1126 * @}
1127 */
1128
1129 /** @defgroup DMA_Handle_index TIM DMA Handle Index
1130 * @{
1131 */
1132 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
1133 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
1134 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
1135 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
1136 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
1137 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
1138 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
1139 /**
1140 * @}
1141 */
1142
1143 /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
1144 * @{
1145 */
1146 #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
1147 #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
1148 #define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
1149 #define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup TIM_Break_System TIM Break System
1155 * @{
1156 */
1157 #define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */
1158 #define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */
1159 #define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
1160 #define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
1161 /**
1162 * @}
1163 */
1164
1165 /**
1166 * @}
1167 */
1168 /* End of exported constants -------------------------------------------------*/
1169
1170 /* Exported macros -----------------------------------------------------------*/
1171 /** @defgroup TIM_Exported_Macros TIM Exported Macros
1172 * @{
1173 */
1174
1175 /** @brief Reset TIM handle state.
1176 * @param __HANDLE__ TIM handle.
1177 * @retval None
1178 */
1179 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1180 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1181 (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1182 (__HANDLE__)->Base_MspInitCallback = NULL; \
1183 (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1184 (__HANDLE__)->IC_MspInitCallback = NULL; \
1185 (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1186 (__HANDLE__)->OC_MspInitCallback = NULL; \
1187 (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1188 (__HANDLE__)->PWM_MspInitCallback = NULL; \
1189 (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1190 (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1191 (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1192 (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1193 (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1194 (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1195 (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1196 } while(0)
1197 #else
1198 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
1199 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1200
1201 /**
1202 * @brief Enable the TIM peripheral.
1203 * @param __HANDLE__ TIM handle
1204 * @retval None
1205 */
1206 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1207
1208 /**
1209 * @brief Enable the TIM main Output.
1210 * @param __HANDLE__ TIM handle
1211 * @retval None
1212 */
1213 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1214
1215 /**
1216 * @brief Disable the TIM peripheral.
1217 * @param __HANDLE__ TIM handle
1218 * @retval None
1219 */
1220 #define __HAL_TIM_DISABLE(__HANDLE__) \
1221 do { \
1222 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1223 { \
1224 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1225 { \
1226 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1227 } \
1228 } \
1229 } while(0)
1230
1231 /**
1232 * @brief Disable the TIM main Output.
1233 * @param __HANDLE__ TIM handle
1234 * @retval None
1235 * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
1236 */
1237 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1238 do { \
1239 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1240 { \
1241 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1242 { \
1243 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1244 } \
1245 } \
1246 } while(0)
1247
1248 /**
1249 * @brief Disable the TIM main Output.
1250 * @param __HANDLE__ TIM handle
1251 * @retval None
1252 * @note The Main Output Enable of a timer instance is disabled unconditionally
1253 */
1254 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1255
1256 /** @brief Enable the specified TIM interrupt.
1257 * @param __HANDLE__ specifies the TIM Handle.
1258 * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
1259 * This parameter can be one of the following values:
1260 * @arg TIM_IT_UPDATE: Update interrupt
1261 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1262 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1263 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1264 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1265 * @arg TIM_IT_COM: Commutation interrupt
1266 * @arg TIM_IT_TRIGGER: Trigger interrupt
1267 * @arg TIM_IT_BREAK: Break interrupt
1268 * @arg TIM_IT_IDX: Index interrupt
1269 * @arg TIM_IT_DIR: Direction change interrupt
1270 * @arg TIM_IT_IERR: Index error interrupt
1271 * @arg TIM_IT_TERR: Transition error interrupt
1272 * @retval None
1273 */
1274 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1275
1276 /** @brief Disable the specified TIM interrupt.
1277 * @param __HANDLE__ specifies the TIM Handle.
1278 * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
1279 * This parameter can be one of the following values:
1280 * @arg TIM_IT_UPDATE: Update interrupt
1281 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1282 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1283 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1284 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1285 * @arg TIM_IT_COM: Commutation interrupt
1286 * @arg TIM_IT_TRIGGER: Trigger interrupt
1287 * @arg TIM_IT_BREAK: Break interrupt
1288 * @arg TIM_IT_IDX: Index interrupt
1289 * @arg TIM_IT_DIR: Direction change interrupt
1290 * @arg TIM_IT_IERR: Index error interrupt
1291 * @arg TIM_IT_TERR: Transition error interrupt
1292 * @retval None
1293 */
1294 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1295
1296 /** @brief Enable the specified DMA request.
1297 * @param __HANDLE__ specifies the TIM Handle.
1298 * @param __DMA__ specifies the TIM DMA request to enable.
1299 * This parameter can be one of the following values:
1300 * @arg TIM_DMA_UPDATE: Update DMA request
1301 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1302 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1303 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1304 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1305 * @arg TIM_DMA_COM: Commutation DMA request
1306 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1307 * @retval None
1308 */
1309 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1310
1311 /** @brief Disable the specified DMA request.
1312 * @param __HANDLE__ specifies the TIM Handle.
1313 * @param __DMA__ specifies the TIM DMA request to disable.
1314 * This parameter can be one of the following values:
1315 * @arg TIM_DMA_UPDATE: Update DMA request
1316 * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
1317 * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
1318 * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
1319 * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
1320 * @arg TIM_DMA_COM: Commutation DMA request
1321 * @arg TIM_DMA_TRIGGER: Trigger DMA request
1322 * @retval None
1323 */
1324 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1325
1326 /** @brief Check whether the specified TIM interrupt flag is set or not.
1327 * @param __HANDLE__ specifies the TIM Handle.
1328 * @param __FLAG__ specifies the TIM interrupt flag to check.
1329 * This parameter can be one of the following values:
1330 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1331 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1332 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1333 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1334 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1335 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1336 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1337 * @arg TIM_FLAG_COM: Commutation interrupt flag
1338 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1339 * @arg TIM_FLAG_BREAK: Break interrupt flag
1340 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1341 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1342 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1343 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1344 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1345 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1346 * @arg TIM_FLAG_IDX: Index interrupt flag
1347 * @arg TIM_FLAG_DIR: Direction change interrupt flag
1348 * @arg TIM_FLAG_IERR: Index error interrupt flag
1349 * @arg TIM_FLAG_TERR: Transition error interrupt flag
1350 * @retval The new state of __FLAG__ (TRUE or FALSE).
1351 */
1352 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1353
1354 /** @brief Clear the specified TIM interrupt flag.
1355 * @param __HANDLE__ specifies the TIM Handle.
1356 * @param __FLAG__ specifies the TIM interrupt flag to clear.
1357 * This parameter can be one of the following values:
1358 * @arg TIM_FLAG_UPDATE: Update interrupt flag
1359 * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
1360 * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
1361 * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
1362 * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
1363 * @arg TIM_FLAG_CC5: Compare 5 interrupt flag
1364 * @arg TIM_FLAG_CC6: Compare 6 interrupt flag
1365 * @arg TIM_FLAG_COM: Commutation interrupt flag
1366 * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
1367 * @arg TIM_FLAG_BREAK: Break interrupt flag
1368 * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
1369 * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
1370 * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
1371 * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
1372 * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
1373 * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
1374 * @arg TIM_FLAG_IDX: Index interrupt flag
1375 * @arg TIM_FLAG_DIR: Direction change interrupt flag
1376 * @arg TIM_FLAG_IERR: Index error interrupt flag
1377 * @arg TIM_FLAG_TERR: Transition error interrupt flag
1378 * @retval The new state of __FLAG__ (TRUE or FALSE).
1379 */
1380 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1381
1382 /**
1383 * @brief Check whether the specified TIM interrupt source is enabled or not.
1384 * @param __HANDLE__ TIM handle
1385 * @param __INTERRUPT__ specifies the TIM interrupt source to check.
1386 * This parameter can be one of the following values:
1387 * @arg TIM_IT_UPDATE: Update interrupt
1388 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1389 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1390 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1391 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1392 * @arg TIM_IT_COM: Commutation interrupt
1393 * @arg TIM_IT_TRIGGER: Trigger interrupt
1394 * @arg TIM_IT_BREAK: Break interrupt
1395 * @arg TIM_IT_IDX: Index interrupt
1396 * @arg TIM_IT_DIR: Direction change interrupt
1397 * @arg TIM_IT_IERR: Index error interrupt
1398 * @arg TIM_IT_TERR: Transition error interrupt
1399 * @retval The state of TIM_IT (SET or RESET).
1400 */
1401 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1402 == (__INTERRUPT__)) ? SET : RESET)
1403
1404 /** @brief Clear the TIM interrupt pending bits.
1405 * @param __HANDLE__ TIM handle
1406 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1407 * This parameter can be one of the following values:
1408 * @arg TIM_IT_UPDATE: Update interrupt
1409 * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
1410 * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
1411 * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
1412 * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
1413 * @arg TIM_IT_COM: Commutation interrupt
1414 * @arg TIM_IT_TRIGGER: Trigger interrupt
1415 * @arg TIM_IT_BREAK: Break interrupt
1416 * @arg TIM_IT_IDX: Index interrupt
1417 * @arg TIM_IT_DIR: Direction change interrupt
1418 * @arg TIM_IT_IERR: Index error interrupt
1419 * @arg TIM_IT_TERR: Transition error interrupt
1420 * @retval None
1421 */
1422 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1423
1424 /**
1425 * @brief Indicates whether or not the TIM Counter is used as downcounter.
1426 * @param __HANDLE__ TIM handle.
1427 * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
1428 * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
1429 mode.
1430 */
1431 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1432
1433 /**
1434 * @brief Set the TIM Prescaler on runtime.
1435 * @param __HANDLE__ TIM handle.
1436 * @param __PRESC__ specifies the Prescaler new value.
1437 * @retval None
1438 */
1439 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1440
1441 /**
1442 * @brief Set the TIM Counter Register value on runtime.
1443 * @param __HANDLE__ TIM handle.
1444 * @param __COUNTER__ specifies the Counter register new value.
1445 * @retval None
1446 */
1447 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1448
1449 /**
1450 * @brief Get the TIM Counter Register value on runtime.
1451 * @param __HANDLE__ TIM handle.
1452 * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
1453 */
1454 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1455
1456 /**
1457 * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
1458 * @param __HANDLE__ TIM handle.
1459 * @param __AUTORELOAD__ specifies the Counter register new value.
1460 * @retval None
1461 */
1462 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1463 do{ \
1464 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1465 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1466 } while(0)
1467
1468 /**
1469 * @brief Get the TIM Autoreload Register value on runtime.
1470 * @param __HANDLE__ TIM handle.
1471 * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
1472 */
1473 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1474
1475 /**
1476 * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
1477 * @param __HANDLE__ TIM handle.
1478 * @param __CKD__ specifies the clock division value.
1479 * This parameter can be one of the following value:
1480 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1481 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1482 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1483 * @retval None
1484 */
1485 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1486 do{ \
1487 (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1488 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1489 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1490 } while(0)
1491
1492 /**
1493 * @brief Get the TIM Clock Division value on runtime.
1494 * @param __HANDLE__ TIM handle.
1495 * @retval The clock division can be one of the following values:
1496 * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
1497 * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
1498 * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
1499 */
1500 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1501
1502 /**
1503 * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
1504 * @param __HANDLE__ TIM handle.
1505 * @param __CHANNEL__ TIM Channels to be configured.
1506 * This parameter can be one of the following values:
1507 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1508 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1509 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1510 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1511 * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
1512 * This parameter can be one of the following values:
1513 * @arg TIM_ICPSC_DIV1: no prescaler
1514 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1515 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1516 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1517 * @retval None
1518 */
1519 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1520 do{ \
1521 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1522 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1523 } while(0)
1524
1525 /**
1526 * @brief Get the TIM Input Capture prescaler on runtime.
1527 * @param __HANDLE__ TIM handle.
1528 * @param __CHANNEL__ TIM Channels to be configured.
1529 * This parameter can be one of the following values:
1530 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1531 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1532 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1533 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1534 * @retval The input capture prescaler can be one of the following values:
1535 * @arg TIM_ICPSC_DIV1: no prescaler
1536 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1537 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1538 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1539 */
1540 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1541 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1542 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1543 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1544 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1545
1546 /**
1547 * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
1548 * @param __HANDLE__ TIM handle.
1549 * @param __CHANNEL__ TIM Channels to be configured.
1550 * This parameter can be one of the following values:
1551 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1552 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1553 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1554 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1555 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1556 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1557 * @param __COMPARE__ specifies the Capture Compare register new value.
1558 * @retval None
1559 */
1560 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1561 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1562 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1563 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1564 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
1565 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
1566 ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
1567
1568 /**
1569 * @brief Get the TIM Capture Compare Register value on runtime.
1570 * @param __HANDLE__ TIM handle.
1571 * @param __CHANNEL__ TIM Channel associated with the capture compare register
1572 * This parameter can be one of the following values:
1573 * @arg TIM_CHANNEL_1: get capture/compare 1 register value
1574 * @arg TIM_CHANNEL_2: get capture/compare 2 register value
1575 * @arg TIM_CHANNEL_3: get capture/compare 3 register value
1576 * @arg TIM_CHANNEL_4: get capture/compare 4 register value
1577 * @arg TIM_CHANNEL_5: get capture/compare 5 register value
1578 * @arg TIM_CHANNEL_6: get capture/compare 6 register value
1579 * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
1580 */
1581 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1582 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1583 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1584 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1585 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
1586 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
1587 ((__HANDLE__)->Instance->CCR6))
1588
1589 /**
1590 * @brief Set the TIM Output compare preload.
1591 * @param __HANDLE__ TIM handle.
1592 * @param __CHANNEL__ TIM Channels to be configured.
1593 * This parameter can be one of the following values:
1594 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1595 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1596 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1597 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1598 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1599 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1600 * @retval None
1601 */
1602 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1603 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1604 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1605 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1606 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
1607 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
1608 ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
1609
1610 /**
1611 * @brief Reset the TIM Output compare preload.
1612 * @param __HANDLE__ TIM handle.
1613 * @param __CHANNEL__ TIM Channels to be configured.
1614 * This parameter can be one of the following values:
1615 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1616 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1617 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1618 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1619 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1620 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1621 * @retval None
1622 */
1623 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1624 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
1625 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
1626 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
1627 ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
1628 ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
1629 ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
1630
1631 /**
1632 * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
1633 * @param __HANDLE__ TIM handle.
1634 * @note When the URS bit of the TIMx_CR1 register is set, only counter
1635 * overflow/underflow generates an update interrupt or DMA request (if
1636 * enabled)
1637 * @retval None
1638 */
1639 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1640
1641 /**
1642 * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
1643 * @param __HANDLE__ TIM handle.
1644 * @note When the URS bit of the TIMx_CR1 register is reset, any of the
1645 * following events generate an update interrupt or DMA request (if
1646 * enabled):
1647 * _ Counter overflow underflow
1648 * _ Setting the UG bit
1649 * _ Update generation through the slave mode controller
1650 * @retval None
1651 */
1652 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1653
1654 /**
1655 * @brief Set the TIM Capture x input polarity on runtime.
1656 * @param __HANDLE__ TIM handle.
1657 * @param __CHANNEL__ TIM Channels to be configured.
1658 * This parameter can be one of the following values:
1659 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1660 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1661 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1662 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1663 * @param __POLARITY__ Polarity for TIx source
1664 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1665 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1666 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1667 * @retval None
1668 */
1669 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1670 do{ \
1671 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1672 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1673 }while(0)
1674
1675 /**
1676 * @}
1677 */
1678 /* End of exported macros ----------------------------------------------------*/
1679
1680 /* Private constants ---------------------------------------------------------*/
1681 /** @defgroup TIM_Private_Constants TIM Private Constants
1682 * @{
1683 */
1684 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1685 channels have been disabled */
1686 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1687 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
1688 /**
1689 * @}
1690 */
1691 /* End of private constants --------------------------------------------------*/
1692
1693 /* Private macros ------------------------------------------------------------*/
1694 /** @defgroup TIM_Private_Macros TIM Private Macros
1695 * @{
1696 */
1697 #if defined(COMP5) && defined(COMP6) && defined(COMP7)
1698 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
1699 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
1700 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
1701 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
1702 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
1703 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \
1704 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \
1705 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \
1706 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1707 #else /* COMP5 && COMP6 && COMP7 */
1708 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
1709 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
1710 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
1711 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
1712 ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
1713 ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
1714 #endif /* COMP5 && COMP6 && COMP7 */
1715
1716 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1717 ((__BASE__) == TIM_DMABASE_CR2) || \
1718 ((__BASE__) == TIM_DMABASE_SMCR) || \
1719 ((__BASE__) == TIM_DMABASE_DIER) || \
1720 ((__BASE__) == TIM_DMABASE_SR) || \
1721 ((__BASE__) == TIM_DMABASE_EGR) || \
1722 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1723 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1724 ((__BASE__) == TIM_DMABASE_CCER) || \
1725 ((__BASE__) == TIM_DMABASE_CNT) || \
1726 ((__BASE__) == TIM_DMABASE_PSC) || \
1727 ((__BASE__) == TIM_DMABASE_ARR) || \
1728 ((__BASE__) == TIM_DMABASE_RCR) || \
1729 ((__BASE__) == TIM_DMABASE_CCR1) || \
1730 ((__BASE__) == TIM_DMABASE_CCR2) || \
1731 ((__BASE__) == TIM_DMABASE_CCR3) || \
1732 ((__BASE__) == TIM_DMABASE_CCR4) || \
1733 ((__BASE__) == TIM_DMABASE_BDTR) || \
1734 ((__BASE__) == TIM_DMABASE_CCMR3) || \
1735 ((__BASE__) == TIM_DMABASE_CCR5) || \
1736 ((__BASE__) == TIM_DMABASE_CCR6) || \
1737 ((__BASE__) == TIM_DMABASE_AF1) || \
1738 ((__BASE__) == TIM_DMABASE_AF2) || \
1739 ((__BASE__) == TIM_DMABASE_TISEL) || \
1740 ((__BASE__) == TIM_DMABASE_DTR2) || \
1741 ((__BASE__) == TIM_DMABASE_ECR) || \
1742 ((__BASE__) == TIM_DMABASE_OR))
1743
1744 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1745
1746 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1747 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1748 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1749 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1750 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1751
1752 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1753 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1754 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1755
1756 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1757 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1758
1759 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1760 ((__STATE__) == TIM_OCFAST_ENABLE))
1761
1762 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1763 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1764
1765 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1766 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1767
1768 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1769 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1770
1771 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1772 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1773
1774 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1775 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1776 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1777
1778 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1779 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1780 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1781
1782 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1783 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1784 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1785 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1786
1787 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1788 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1789
1790 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1791 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1792 ((__MODE__) == TIM_ENCODERMODE_TI12) || \
1793 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \
1794 ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \
1795 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \
1796 ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
1797 ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \
1798 ((__MODE__) == TIM_ENCODERMODE_X1_TI2))
1799
1800 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1801
1802 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1803 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1804 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1805 ((__CHANNEL__) == TIM_CHANNEL_4) || \
1806 ((__CHANNEL__) == TIM_CHANNEL_5) || \
1807 ((__CHANNEL__) == TIM_CHANNEL_6) || \
1808 ((__CHANNEL__) == TIM_CHANNEL_ALL))
1809
1810 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1811 ((__CHANNEL__) == TIM_CHANNEL_2))
1812
1813 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1814 ((__CHANNEL__) == TIM_CHANNEL_2) || \
1815 ((__CHANNEL__) == TIM_CHANNEL_3) || \
1816 ((__CHANNEL__) == TIM_CHANNEL_4))
1817
1818 #if defined(TIM5) && defined(TIM20)
1819 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1820 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1821 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1822 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1823 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1824 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1825 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1826 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1827 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1828 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1829 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
1830 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
1831 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
1832 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
1833 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
1834 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
1835 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
1836 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
1837 #elif defined(TIM5)
1838 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1839 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1840 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1841 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1842 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1843 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1844 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1845 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1846 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1847 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1848 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
1849 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
1850 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
1851 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
1852 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
1853 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
1854 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
1855 #else
1856 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1857 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1858 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1859 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1860 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1861 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1862 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1863 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1864 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1865 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
1866 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
1867 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
1868 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
1869 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
1870 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
1871 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
1872 #endif /* TIM5 && TIM20 */
1873
1874 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1875 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1876 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1877 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1878 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1879
1880 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1881 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1882 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1883 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1884
1885 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1886
1887 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1888 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1889
1890 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1891 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1892 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1893 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1894
1895 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1896
1897 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1898 ((__STATE__) == TIM_OSSR_DISABLE))
1899
1900 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1901 ((__STATE__) == TIM_OSSI_DISABLE))
1902
1903 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1904 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1905 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1906 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1907
1908 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1909
1910
1911 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1912 ((__STATE__) == TIM_BREAK_DISABLE))
1913
1914 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1915 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1916
1917 #define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
1918 ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
1919
1920
1921 #define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
1922 ((__STATE__) == TIM_BREAK2_DISABLE))
1923
1924 #define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
1925 ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
1926
1927 #define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
1928 ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
1929
1930
1931 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1932 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1933
1934 #define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
1935
1936 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1937 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1938 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1939 ((__SOURCE__) == TIM_TRGO_OC1) || \
1940 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1941 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1942 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1943 ((__SOURCE__) == TIM_TRGO_OC4REF) || \
1944 ((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
1945
1946 #define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
1947 ((__SOURCE__) == TIM_TRGO2_ENABLE) || \
1948 ((__SOURCE__) == TIM_TRGO2_UPDATE) || \
1949 ((__SOURCE__) == TIM_TRGO2_OC1) || \
1950 ((__SOURCE__) == TIM_TRGO2_OC1REF) || \
1951 ((__SOURCE__) == TIM_TRGO2_OC2REF) || \
1952 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1953 ((__SOURCE__) == TIM_TRGO2_OC3REF) || \
1954 ((__SOURCE__) == TIM_TRGO2_OC4REF) || \
1955 ((__SOURCE__) == TIM_TRGO2_OC5REF) || \
1956 ((__SOURCE__) == TIM_TRGO2_OC6REF) || \
1957 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
1958 ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
1959 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
1960 ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
1961 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
1962 ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
1963
1964 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1965 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1966
1967 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1968 ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1969 ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1970 ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1971 ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
1972 ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
1973 ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
1974
1975 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1976 ((__MODE__) == TIM_OCMODE_PWM2) || \
1977 ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
1978 ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
1979 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
1980 ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
1981
1982 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1983 ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1984 ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1985 ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1986 ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1987 ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
1988 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
1989 ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
1990 ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
1991 ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
1992
1993 #if defined (TIM5) && defined(TIM20)
1994 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1995 ((__SELECTION__) == TIM_TS_ITR1) || \
1996 ((__SELECTION__) == TIM_TS_ITR2) || \
1997 ((__SELECTION__) == TIM_TS_ITR3) || \
1998 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1999 ((__SELECTION__) == TIM_TS_TI1FP1) || \
2000 ((__SELECTION__) == TIM_TS_TI2FP2) || \
2001 ((__SELECTION__) == TIM_TS_ITR4) || \
2002 ((__SELECTION__) == TIM_TS_ITR5) || \
2003 ((__SELECTION__) == TIM_TS_ITR6) || \
2004 ((__SELECTION__) == TIM_TS_ITR7) || \
2005 ((__SELECTION__) == TIM_TS_ITR8) || \
2006 ((__SELECTION__) == TIM_TS_ITR9) || \
2007 ((__SELECTION__) == TIM_TS_ITR10) || \
2008 ((__SELECTION__) == TIM_TS_ITR11) || \
2009 ((__SELECTION__) == TIM_TS_ETRF))
2010
2011 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2012 ((__SELECTION__) == TIM_TS_ITR1) || \
2013 ((__SELECTION__) == TIM_TS_ITR2) || \
2014 ((__SELECTION__) == TIM_TS_ITR3) || \
2015 ((__SELECTION__) == TIM_TS_ITR4) || \
2016 ((__SELECTION__) == TIM_TS_ITR5) || \
2017 ((__SELECTION__) == TIM_TS_ITR6) || \
2018 ((__SELECTION__) == TIM_TS_ITR7) || \
2019 ((__SELECTION__) == TIM_TS_ITR8) || \
2020 ((__SELECTION__) == TIM_TS_ITR9) || \
2021 ((__SELECTION__) == TIM_TS_ITR10)|| \
2022 ((__SELECTION__) == TIM_TS_ITR11)|| \
2023 ((__SELECTION__) == TIM_TS_NONE))
2024 #elif defined (TIM5)
2025 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2026 ((__SELECTION__) == TIM_TS_ITR1) || \
2027 ((__SELECTION__) == TIM_TS_ITR2) || \
2028 ((__SELECTION__) == TIM_TS_ITR3) || \
2029 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2030 ((__SELECTION__) == TIM_TS_TI1FP1) || \
2031 ((__SELECTION__) == TIM_TS_TI2FP2) || \
2032 ((__SELECTION__) == TIM_TS_ITR4) || \
2033 ((__SELECTION__) == TIM_TS_ITR5) || \
2034 ((__SELECTION__) == TIM_TS_ITR6) || \
2035 ((__SELECTION__) == TIM_TS_ITR7) || \
2036 ((__SELECTION__) == TIM_TS_ITR8) || \
2037 ((__SELECTION__) == TIM_TS_ITR10) || \
2038 ((__SELECTION__) == TIM_TS_ITR11) || \
2039 ((__SELECTION__) == TIM_TS_ETRF))
2040
2041 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2042 ((__SELECTION__) == TIM_TS_ITR1) || \
2043 ((__SELECTION__) == TIM_TS_ITR2) || \
2044 ((__SELECTION__) == TIM_TS_ITR3) || \
2045 ((__SELECTION__) == TIM_TS_ITR4) || \
2046 ((__SELECTION__) == TIM_TS_ITR5) || \
2047 ((__SELECTION__) == TIM_TS_ITR6) || \
2048 ((__SELECTION__) == TIM_TS_ITR7) || \
2049 ((__SELECTION__) == TIM_TS_ITR8) || \
2050 ((__SELECTION__) == TIM_TS_ITR10)|| \
2051 ((__SELECTION__) == TIM_TS_ITR11)|| \
2052 ((__SELECTION__) == TIM_TS_NONE))
2053 #else
2054 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2055 ((__SELECTION__) == TIM_TS_ITR1) || \
2056 ((__SELECTION__) == TIM_TS_ITR2) || \
2057 ((__SELECTION__) == TIM_TS_ITR3) || \
2058 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
2059 ((__SELECTION__) == TIM_TS_TI1FP1) || \
2060 ((__SELECTION__) == TIM_TS_TI2FP2) || \
2061 ((__SELECTION__) == TIM_TS_ITR5) || \
2062 ((__SELECTION__) == TIM_TS_ITR6) || \
2063 ((__SELECTION__) == TIM_TS_ITR7) || \
2064 ((__SELECTION__) == TIM_TS_ITR8) || \
2065 ((__SELECTION__) == TIM_TS_ITR10) || \
2066 ((__SELECTION__) == TIM_TS_ITR11) || \
2067 ((__SELECTION__) == TIM_TS_ETRF))
2068
2069 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
2070 ((__SELECTION__) == TIM_TS_ITR1) || \
2071 ((__SELECTION__) == TIM_TS_ITR2) || \
2072 ((__SELECTION__) == TIM_TS_ITR3) || \
2073 ((__SELECTION__) == TIM_TS_ITR5) || \
2074 ((__SELECTION__) == TIM_TS_ITR6) || \
2075 ((__SELECTION__) == TIM_TS_ITR7) || \
2076 ((__SELECTION__) == TIM_TS_ITR8) || \
2077 ((__SELECTION__) == TIM_TS_ITR10)|| \
2078 ((__SELECTION__) == TIM_TS_ITR11)|| \
2079 ((__SELECTION__) == TIM_TS_NONE))
2080 #endif /* TIM5 && TIM20 */
2081
2082 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
2083 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
2084 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
2085 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
2086 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
2087
2088 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
2089 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
2090 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
2091 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
2092
2093 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2094
2095 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
2096 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
2097
2098 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
2099 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
2100 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
2101 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
2102 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
2103 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
2104 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
2105 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
2106 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
2107 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
2108 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
2109 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
2110 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
2111 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
2112 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
2113 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
2114 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
2115 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
2116 ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
2117 ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
2118 ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
2119 ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
2120 ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
2121 ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
2122 ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
2123 ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
2124
2125 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
2126
2127 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
2128
2129 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
2130
2131 #define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
2132 ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
2133 ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
2134 ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
2135
2136 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
2137 ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
2138
2139 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
2140 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
2141 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
2142 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
2143 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
2144
2145 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
2146 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
2147 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
2148 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
2149 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
2150
2151 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
2152 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
2153 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
2154 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
2155 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
2156
2157 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
2158 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
2159 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
2160 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
2161 ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
2162
2163 /**
2164 * @}
2165 */
2166 /* End of private macros -----------------------------------------------------*/
2167
2168 /* Include TIM HAL Extended module */
2169 #include "stm32g4xx_hal_tim_ex.h"
2170
2171 /* Exported functions --------------------------------------------------------*/
2172 /** @addtogroup TIM_Exported_Functions TIM Exported Functions
2173 * @{
2174 */
2175
2176 /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
2177 * @brief Time Base functions
2178 * @{
2179 */
2180 /* Time Base functions ********************************************************/
2181 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
2182 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
2183 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
2184 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
2185 /* Blocking mode: Polling */
2186 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
2187 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
2188 /* Non-Blocking mode: Interrupt */
2189 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
2190 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
2191 /* Non-Blocking mode: DMA */
2192 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
2193 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
2194 /**
2195 * @}
2196 */
2197
2198 /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
2199 * @brief TIM Output Compare functions
2200 * @{
2201 */
2202 /* Timer Output Compare functions *********************************************/
2203 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
2204 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
2205 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
2206 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
2207 /* Blocking mode: Polling */
2208 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2209 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2210 /* Non-Blocking mode: Interrupt */
2211 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2212 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2213 /* Non-Blocking mode: DMA */
2214 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2215 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2216 /**
2217 * @}
2218 */
2219
2220 /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
2221 * @brief TIM PWM functions
2222 * @{
2223 */
2224 /* Timer PWM functions ********************************************************/
2225 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
2226 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
2227 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
2228 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
2229 /* Blocking mode: Polling */
2230 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2231 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2232 /* Non-Blocking mode: Interrupt */
2233 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2234 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2235 /* Non-Blocking mode: DMA */
2236 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2237 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2238 /**
2239 * @}
2240 */
2241
2242 /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
2243 * @brief TIM Input Capture functions
2244 * @{
2245 */
2246 /* Timer Input Capture functions **********************************************/
2247 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
2248 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
2249 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
2250 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
2251 /* Blocking mode: Polling */
2252 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2253 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2254 /* Non-Blocking mode: Interrupt */
2255 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2256 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2257 /* Non-Blocking mode: DMA */
2258 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
2259 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2260 /**
2261 * @}
2262 */
2263
2264 /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2265 * @brief TIM One Pulse functions
2266 * @{
2267 */
2268 /* Timer One Pulse functions **************************************************/
2269 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
2270 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
2271 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
2272 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
2273 /* Blocking mode: Polling */
2274 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2275 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2276 /* Non-Blocking mode: Interrupt */
2277 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2278 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
2279 /**
2280 * @}
2281 */
2282
2283 /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
2284 * @brief TIM Encoder functions
2285 * @{
2286 */
2287 /* Timer Encoder functions ****************************************************/
2288 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
2289 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
2290 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
2291 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
2292 /* Blocking mode: Polling */
2293 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
2294 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
2295 /* Non-Blocking mode: Interrupt */
2296 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2297 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
2298 /* Non-Blocking mode: DMA */
2299 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
2300 uint32_t *pData2, uint16_t Length);
2301 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
2302 /**
2303 * @}
2304 */
2305
2306 /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
2307 * @brief IRQ handler management
2308 * @{
2309 */
2310 /* Interrupt Handler functions ***********************************************/
2311 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2312 /**
2313 * @}
2314 */
2315
2316 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
2317 * @brief Peripheral Control functions
2318 * @{
2319 */
2320 /* Control functions *********************************************************/
2321 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2322 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2323 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2324 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2325 uint32_t OutputChannel, uint32_t InputChannel);
2326 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2327 uint32_t Channel);
2328 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2329 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2330 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2331 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2332 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2333 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2334 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2335 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2336 uint32_t DataLength);
2337 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2338 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2339 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2340 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2341 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2342 uint32_t DataLength);
2343 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2344 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2345 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2346 /**
2347 * @}
2348 */
2349
2350 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
2351 * @brief TIM Callbacks functions
2352 * @{
2353 */
2354 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2355 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2356 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2357 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2358 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2359 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2360 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2361 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2362 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2363 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2364 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2365
2366 /* Callbacks Register/UnRegister functions ***********************************/
2367 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2368 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2369 pTIM_CallbackTypeDef pCallback);
2370 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2371 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2372
2373 /**
2374 * @}
2375 */
2376
2377 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
2378 * @brief Peripheral State functions
2379 * @{
2380 */
2381 /* Peripheral State functions ************************************************/
2382 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2383 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2384 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2385 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2386 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2387 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2388 /**
2389 * @}
2390 */
2391
2392 /**
2393 * @}
2394 */
2395 /* End of exported functions -------------------------------------------------*/
2396
2397 /* Private functions----------------------------------------------------------*/
2398 /** @defgroup TIM_Private_Functions TIM Private Functions
2399 * @{
2400 */
2401 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2402 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2403 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2404 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2405 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2406
2407 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
2408 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2409 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2410 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2411 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2412 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2413
2414 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2415 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2416 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2417
2418 /**
2419 * @}
2420 */
2421 /* End of private functions --------------------------------------------------*/
2422
2423 /**
2424 * @}
2425 */
2426
2427 /**
2428 * @}
2429 */
2430
2431 #ifdef __cplusplus
2432 }
2433 #endif
2434
2435 #endif /* STM32G4xx_HAL_TIM_H */
2436
2437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/