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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_adc.h
blob0103ea430c5bbdca0e8d39057cbfa4cf00b4f36a
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_adc.h
4 * @author MCD Application Team
5 * @brief Header file of ADC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_ADC_H
22 #define STM32G4xx_LL_ADC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
36
37 /** @defgroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46 * @{
47 */
48
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET (0x00000000UL)
57 #define ADC_SQR2_REGOFFSET (0x00000100UL)
58 #define ADC_SQR3_REGOFFSET (0x00000200UL)
59 #define ADC_SQR4_REGOFFSET (0x00000300UL)
60
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
63 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
64
65 /* Definition of ADC group regular sequencer bits information to be inserted */
66 /* into ADC group regular sequencer ranks literals definition. */
67 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
68 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
69 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
70 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
71 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
72 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
73 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
74 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
75 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
76 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
77 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
78 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
79 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
80 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
81 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
82 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
83
84
85
86 /* Internal mask for ADC group injected sequencer: */
87 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
88 /* - data register offset */
89 /* - sequencer rank bits position into the selected register */
90
91 /* Internal register offset for ADC group injected data register */
92 /* (offset placed into a spare area of literal definition) */
93 #define ADC_JDR1_REGOFFSET (0x00000000UL)
94 #define ADC_JDR2_REGOFFSET (0x00000100UL)
95 #define ADC_JDR3_REGOFFSET (0x00000200UL)
96 #define ADC_JDR4_REGOFFSET (0x00000300UL)
97
98 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
99 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
100 #define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
101
102 /* Definition of ADC group injected sequencer bits information to be inserted */
103 /* into ADC group injected sequencer ranks literals definition. */
104 #define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
105 #define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
106 #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
107 #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
108
109
110
111 /* Internal mask for ADC group regular trigger: */
112 /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
113 /* - regular trigger source */
114 /* - regular trigger edge */
115 #define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
116
117 /* Mask containing trigger source masks for each of possible */
118 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
119 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
120 #define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
121 ((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
122 ((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
123 ((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
124
125 /* Mask containing trigger edge masks for each of possible */
126 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
127 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
128 #define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
129 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
130 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
131 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
132
133 /* Definition of ADC group regular trigger bits information. */
134 #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
135 #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
136
137
138
139 /* Internal mask for ADC group injected trigger: */
140 /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
141 /* - injected trigger source */
142 /* - injected trigger edge */
143 #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
144
145 /* Mask containing trigger source masks for each of possible */
146 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
147 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
148 #define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
149 ((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
150 ((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
151 ((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
152
153 /* Mask containing trigger edge masks for each of possible */
154 /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
155 /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
156 #define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
157 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
158 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
159 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
160
161 /* Definition of ADC group injected trigger bits information. */
162 #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
163 #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
164
165
166
167
168
169
170 /* Internal mask for ADC channel: */
171 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
172 /* - channel identifier defined by number */
173 /* - channel identifier defined by bitfield */
174 /* - channel differentiation between external channels (connected to */
175 /* GPIO pins) and internal channels (connected to internal paths) */
176 /* - channel sampling time defined by SMPRx register offset */
177 /* and SMPx bits positions into SMPRx register */
178 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
179 #define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
180 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
181 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
182 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
183 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
184
185 /* Channel differentiation between external and internal channels */
186 #define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
187 #define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
188 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
189
190 /* Internal register offset for ADC channel sampling time configuration */
191 /* (offset placed into a spare area of literal definition) */
192 #define ADC_SMPR1_REGOFFSET (0x00000000UL)
193 #define ADC_SMPR2_REGOFFSET (0x02000000UL)
194 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
195 #define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
196
197 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
198 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
199
200 /* Definition of channels ID number information to be inserted into */
201 /* channels literals definition. */
202 #define ADC_CHANNEL_0_NUMBER (0x00000000UL)
203 #define ADC_CHANNEL_1_NUMBER ( ADC_CFGR_AWD1CH_0)
204 #define ADC_CHANNEL_2_NUMBER ( ADC_CFGR_AWD1CH_1 )
205 #define ADC_CHANNEL_3_NUMBER ( ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
206 #define ADC_CHANNEL_4_NUMBER ( ADC_CFGR_AWD1CH_2 )
207 #define ADC_CHANNEL_5_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
208 #define ADC_CHANNEL_6_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
209 #define ADC_CHANNEL_7_NUMBER ( ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
210 #define ADC_CHANNEL_8_NUMBER ( ADC_CFGR_AWD1CH_3 )
211 #define ADC_CHANNEL_9_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
212 #define ADC_CHANNEL_10_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 )
213 #define ADC_CHANNEL_11_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
214 #define ADC_CHANNEL_12_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 )
215 #define ADC_CHANNEL_13_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
216 #define ADC_CHANNEL_14_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 )
217 #define ADC_CHANNEL_15_NUMBER ( ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
218 #define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4 )
219 #define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
220 #define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1 )
221
222 /* Definition of channels ID bitfield information to be inserted into */
223 /* channels literals definition. */
224 #define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
225 #define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
226 #define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
227 #define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
228 #define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
229 #define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
230 #define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
231 #define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
232 #define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
233 #define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
234 #define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
235 #define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
236 #define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
237 #define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
238 #define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
239 #define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
240 #define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
241 #define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
242 #define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
243
244 /* Definition of channels sampling time information to be inserted into */
245 /* channels literals definition. */
246 #define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
247 #define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
248 #define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
249 #define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
250 #define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
251 #define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
252 #define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
253 #define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
254 #define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
255 #define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
256 #define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
257 #define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
258 #define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
259 #define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
260 #define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
261 #define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
262 #define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
263 #define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
264 #define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
265
266
267 /* Internal mask for ADC mode single or differential ended: */
268 /* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
269 /* the relevant bits for: */
270 /* (concatenation of multiple bits used in different registers) */
271 /* - ADC calibration: calibration start, calibration factor get or set */
272 /* - ADC channels: set each ADC channel ending mode */
273 #define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
274 #define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
275 #define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
276 #define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
277 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
278 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
279 #define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
280
281 /* Internal mask for ADC analog watchdog: */
282 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
283 /* (concatenation of multiple bits used in different analog watchdogs, */
284 /* (feature of several watchdogs not available on all STM32 families)). */
285 /* - analog watchdog 1: monitored channel defined by number, */
286 /* selection of ADC group (ADC groups regular and-or injected). */
287 /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
288 /* selection on groups. */
289
290 /* Internal register offset for ADC analog watchdog channel configuration */
291 #define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
292 #define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
293 #define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
294
295 /* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
296 /* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
297 #define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
298 #define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
299
300 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
301
302 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
303 #define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
304 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
305
306 #define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
307
308 /* Internal register offset for ADC analog watchdog threshold configuration */
309 #define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
310 #define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
311 #define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
312 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
313 #define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
314 #define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
315 #define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
316 #define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
317
318 /* Internal mask for ADC offset: */
319 /* Internal register offset for ADC offset number configuration */
320 #define ADC_OFR1_REGOFFSET (0x00000000UL)
321 #define ADC_OFR2_REGOFFSET (0x00000001UL)
322 #define ADC_OFR3_REGOFFSET (0x00000002UL)
323 #define ADC_OFR4_REGOFFSET (0x00000003UL)
324 #define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
325
326
327 /* ADC registers bits positions */
328 #define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
329 #define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
330 #define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
331 #define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
332 #define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
333
334
335 /* ADC registers bits groups */
336 #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
337
338
339 /* ADC internal channels related definitions */
340 /* Internal voltage reference VrefInt */
341 #define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
342 #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
343 /* Temperature sensor */
344 #define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
345 #define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
346 #define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
347 #define TEMPSENSOR_CAL2_TEMP (110L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
348 #define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
349
350
351 /**
352 * @}
353 */
354
355
356 /* Private macros ------------------------------------------------------------*/
357 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
358 * @{
359 */
360
361 /**
362 * @brief Driver macro reserved for internal use: set a pointer to
363 * a register from a register basis from which an offset
364 * is applied.
365 * @param __REG__ Register basis from which the offset is applied.
366 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
367 * @retval Pointer to register address
368 */
369 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
370 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
371
372 /**
373 * @}
374 */
375
376
377 /* Exported types ------------------------------------------------------------*/
378 #if defined(USE_FULL_LL_DRIVER)
379 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
380 * @{
381 */
382
383 /**
384 * @brief Structure definition of some features of ADC common parameters
385 * and multimode
386 * (all ADC instances belonging to the same ADC common instance).
387 * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
388 * is conditioned to ADC instances state (all ADC instances
389 * sharing the same ADC common instance):
390 * All ADC instances sharing the same ADC common instance must be
391 * disabled.
392 */
393 typedef struct
394 {
395 uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
396 This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
397 @note On this STM32 serie, if ADC group injected is used, some
398 clock ratio constraints between ADC clock and AHB clock
399 must be respected. Refer to reference manual.
400
401 This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
402
403 #if defined(ADC_MULTIMODE_SUPPORT)
404 uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
405 This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
406
407 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
408
409 uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
410 This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
411
412 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
413
414 uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
415 This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
416
417 This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
418 #endif /* ADC_MULTIMODE_SUPPORT */
419
420 } LL_ADC_CommonInitTypeDef;
421
422 /**
423 * @brief Structure definition of some features of ADC instance.
424 * @note These parameters have an impact on ADC scope: ADC instance.
425 * Affects both group regular and group injected (availability
426 * of ADC group injected depends on STM32 families).
427 * Refer to corresponding unitary functions into
428 * @ref ADC_LL_EF_Configuration_ADC_Instance .
429 * @note The setting of these parameters by function @ref LL_ADC_Init()
430 * is conditioned to ADC state:
431 * ADC instance must be disabled.
432 * This condition is applied to all ADC features, for efficiency
433 * and compatibility over all STM32 families. However, the different
434 * features can be set under different ADC state conditions
435 * (setting possible with ADC enabled without conversion on going,
436 * ADC enabled with conversion on going, ...)
437 * Each feature can be updated afterwards with a unitary function
438 * and potentially with ADC in a different state than disabled,
439 * refer to description of each function for setting
440 * conditioned to ADC state.
441 */
442 typedef struct
443 {
444 uint32_t Resolution; /*!< Set ADC resolution.
445 This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
446
447 This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
448
449 uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
450 This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
451
452 This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
453
454 uint32_t LowPowerMode; /*!< Set ADC low power mode.
455 This parameter can be a value of @ref ADC_LL_EC_LP_MODE
456
457 This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
458
459 } LL_ADC_InitTypeDef;
460
461 /**
462 * @brief Structure definition of some features of ADC group regular.
463 * @note These parameters have an impact on ADC scope: ADC group regular.
464 * Refer to corresponding unitary functions into
465 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
466 * (functions with prefix "REG").
467 * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
468 * is conditioned to ADC state:
469 * ADC instance must be disabled.
470 * This condition is applied to all ADC features, for efficiency
471 * and compatibility over all STM32 families. However, the different
472 * features can be set under different ADC state conditions
473 * (setting possible with ADC enabled without conversion on going,
474 * ADC enabled with conversion on going, ...)
475 * Each feature can be updated afterwards with a unitary function
476 * and potentially with ADC in a different state than disabled,
477 * refer to description of each function for setting
478 * conditioned to ADC state.
479 */
480 typedef struct
481 {
482 uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
483 This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
484 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
485 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
486 In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
487
488 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
489
490 uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
491 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
492
493 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
494
495 uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
496 This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
497 @note This parameter has an effect only if group regular sequencer is enabled
498 (scan length of 2 ranks or more).
499
500 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
501
502 uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
503 This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
504 Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
505
506 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
507
508 uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
509 This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
510
511 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
512
513 uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
514 data preserved or overwritten.
515 This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
516
517 This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
518
519 } LL_ADC_REG_InitTypeDef;
520
521 /**
522 * @brief Structure definition of some features of ADC group injected.
523 * @note These parameters have an impact on ADC scope: ADC group injected.
524 * Refer to corresponding unitary functions into
525 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
526 * (functions with prefix "INJ").
527 * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
528 * is conditioned to ADC state:
529 * ADC instance must be disabled.
530 * This condition is applied to all ADC features, for efficiency
531 * and compatibility over all STM32 families. However, the different
532 * features can be set under different ADC state conditions
533 * (setting possible with ADC enabled without conversion on going,
534 * ADC enabled with conversion on going, ...)
535 * Each feature can be updated afterwards with a unitary function
536 * and potentially with ADC in a different state than disabled,
537 * refer to description of each function for setting
538 * conditioned to ADC state.
539 */
540 typedef struct
541 {
542 uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
543 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
544 @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
545 (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
546 In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
547
548 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
549
550 uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
551 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
552
553 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
554
555 uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
556 This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
557 @note This parameter has an effect only if group injected sequencer is enabled
558 (scan length of 2 ranks or more).
559
560 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
561
562 uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
563 This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
564 Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
565
566 This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
567
568 } LL_ADC_INJ_InitTypeDef;
569
570 /**
571 * @}
572 */
573 #endif /* USE_FULL_LL_DRIVER */
574
575 /* Exported constants --------------------------------------------------------*/
576 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
577 * @{
578 */
579
580 /** @defgroup ADC_LL_EC_FLAG ADC flags
581 * @brief Flags defines which can be used with LL_ADC_ReadReg function
582 * @{
583 */
584 #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
585 #define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
586 #define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
587 #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
588 #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
589 #define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
590 #define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
591 #define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
592 #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
593 #define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
594 #define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
595 #if defined(ADC_MULTIMODE_SUPPORT)
596 #define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
597 #define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
598 #define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
599 #define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
600 #define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
601 #define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
602 #define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
603 #define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
604 #define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
605 #define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
606 #define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
607 #define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
608 #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
609 #define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
610 #define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
611 #define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
612 #define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
613 #define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
614 #define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
615 #define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
616 #define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
617 #define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
618 #endif
619 /**
620 * @}
621 */
622
623 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
624 * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
625 * @{
626 */
627 #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
628 #define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
629 #define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
630 #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
631 #define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
632 #define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
633 #define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
634 #define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
635 #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
636 #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
637 #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
638 /**
639 * @}
640 */
641
642 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
643 * @{
644 */
645 /* List of ADC registers intended to be used (most commonly) with */
646 /* DMA transfer. */
647 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
648 #define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
649 #if defined(ADC_MULTIMODE_SUPPORT)
650 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
651 #endif
652 /**
653 * @}
654 */
655
656 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
657 * @{
658 */
659 #define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
660 #define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
661 #define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
662 #define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
663 #define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
664 #define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
665 #define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
666 #define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
667 #define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
668 #define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
669 #define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
670 #define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
671 #define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
672 #define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
673 #define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
674 /**
675 * @}
676 */
677
678 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
679 * @{
680 */
681 /* Note: Other measurement paths to internal channels may be available */
682 /* (connections to other peripherals). */
683 /* If they are not listed below, they do not require any specific */
684 /* path enable. In this case, Access to measurement path is done */
685 /* only by selecting the corresponding ADC internal channel. */
686 #define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement pathes all disabled */
687 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
688 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */
689 #define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
690 /**
691 * @}
692 */
693
694 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
695 * @{
696 */
697 #define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
698 #define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
699 #define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
700 #define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
701 /**
702 * @}
703 */
704
705 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
706 * @{
707 */
708 #define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
709 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
710 /**
711 * @}
712 */
713
714 /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
715 * @{
716 */
717 #define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
718 #define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
719 /**
720 * @}
721 */
722
723 /** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
724 * @{
725 */
726 #define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
727 #define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
728 #define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
729 #define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
730 /**
731 * @}
732 */
733
734 /** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
735 * @{
736 */
737 #define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
738 #define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
739 /**
740 * @}
741 */
742
743 /** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
744 * @{
745 */
746 #define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
747 #define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
748 /**
749 * @}
750 */
751
752 /** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
753 * @{
754 */
755 #define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
756 #define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
757 /**
758 * @}
759 */
760 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
761 * @{
762 */
763 #define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
764 #define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
765 #define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
766 /**
767 * @}
768 */
769
770 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
771 * @{
772 */
773 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
774 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
775 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
776 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
777 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
778 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
779 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
780 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
781 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
782 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
783 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
784 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
785 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
786 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
787 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
788 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
789 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
790 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
791 #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
792 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 serie, ADC channel available on all instances but ADC2. */
793 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC1 instance. */
794 #define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
795 #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 serie, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
796 #define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 serie, ADC channel available only on ADC1 instance. */
797 #define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 serie, ADC channel available only on ADC2 instance. */
798 #define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC2 instance. */
799 #define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 serie, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
800 #define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */
801 #define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 serie, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */
802 #define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 serie, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */
803 /**
804 * @}
805 */
806
807 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
808 * @{
809 */
810 #define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!<
811 ADC group regular conversion trigger internal: SW start. */
812 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
813 ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
814 #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
815 ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
816 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
817 ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
818 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
819 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
820 ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
821 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
822 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
823 ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
824 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
825 ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
826 #define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
827 ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
828 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
829 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
830 ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
831 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
832 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
833 ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
834 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
835 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
836 ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
837 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
838 ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
839 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
840 #define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
841 ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
842 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
843 #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
844 ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
845 #define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
846 ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
847 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
848 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
849 ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
850 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
851 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
852 ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
853 #define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
854 ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
855 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
856 ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
857 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
858 ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
859 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
860 ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
861 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
862 #define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
863 ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
864 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
865 ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
866 Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
867 #define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
868 ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
869 Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
870 #define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
871 ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
872 Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
873 #define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
874 ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
875 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
876 #define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
877 ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
878 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
879 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
880 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
881 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
882 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
883 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
884 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
885 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
886 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
887 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
888 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
889 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
890 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
891 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
892 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
893 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
894 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
895 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
896 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
897 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
898 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
899 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
900 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
901 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
902 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
903 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
904 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
905 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
906 #define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
907 ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
908 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
909 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
910 ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).
911 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
912 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
913 ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting).
914 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
915 #define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
916 ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
917 /**
918 * @}
919 */
920
921 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
922 * @{
923 */
924 #define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
925 #define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
926 #define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
927 /**
928 * @}
929 */
930
931 /** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
932 * @{
933 */
934 #define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
935 #define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
936 Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
937 #define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
938 Trigger rising edge = start sampling
939 Trigger falling edge = stop sampling and start conversion */
940 /**
941 * @}
942 */
943
944 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
945 * @{
946 */
947 #define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
948 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
949 /**
950 * @}
951 */
952
953 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
954 * @{
955 */
956 #define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
957 #define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
958 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
959 /**
960 * @}
961 */
962
963 #if defined(ADC_SMPR1_SMPPLUS)
964 /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
965 * @{
966 */
967 #define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
968 #define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
969 /**
970 * @}
971 */
972 #endif
973
974 /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
975 * @{
976 */
977 #define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
978 #define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
979 /**
980 * @}
981 */
982
983 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
984 * @{
985 */
986 #define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
987 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
988 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
989 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
990 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
991 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
992 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
993 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
994 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
995 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
996 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
997 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
998 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
999 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
1000 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
1001 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
1002 /**
1003 * @}
1004 */
1005
1006 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
1007 * @{
1008 */
1009 #define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
1010 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
1011 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
1012 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
1013 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
1014 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
1015 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
1016 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
1017 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
1023 * @{
1024 */
1025 #define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
1026 #define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
1027 #define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
1028 #define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
1029 #define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
1030 #define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
1031 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
1032 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
1033 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
1034 #define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
1035 #define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
1036 #define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
1037 #define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
1038 #define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
1039 #define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
1040 #define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
1041 /**
1042 * @}
1043 */
1044
1045 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
1046 * @{
1047 */
1048 #define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!<
1049 ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
1050 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1051 ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
1052 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1053 ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
1054 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1055 ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1056 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1057 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1058 ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1059 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1060 ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
1061 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1062 ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1063 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
1064 #define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1065 ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
1066 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1067 ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1068 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
1069 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1070 ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1071 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
1072 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1073 ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1074 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
1075 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1076 ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
1077 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1078 ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1079 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1080 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1081 ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1082 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1083 #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1084 ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
1085 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1086 ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
1087 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1088 ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
1089 #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1090 ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
1091 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1092 ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1093 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1094 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1095 ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
1096 #define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1097 ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
1098 #define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1099 ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1100 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances */
1101 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1102 ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
1103 Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
1104 #define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1105 ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
1106 Note: On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
1107 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1108 ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1109 Trigger available only on ADC3/4/5 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
1110 #define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1111 ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
1112 Trigger available only on ADC1/2 instances. On this STM32 serie, TIM20 is not available on all devices. Refer to device datasheet for more details */
1113 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1114 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
1115 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
1116 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1117 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
1118 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1119 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1120 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
1121 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
1122 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1123 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
1124 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1125 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1126 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
1127 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1128 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1129 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
1130 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1131 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1132 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
1133 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1134 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1135 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
1136 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1137 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1138 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
1139 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1140 #define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1141 ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
1142 Note: On this STM32 serie, HRTIM is not available on all devices. Refer to device datasheet for more details */
1143 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1144 ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting).
1145 Note: On this STM32 serie, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
1146 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1147 ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).
1148 Note: On this STM32 serie, this trigger is available only on ADC1/2 instances. */
1149 #define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
1150 ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
1151 /**
1152 * @}
1153 */
1154
1155 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
1156 * @{
1157 */
1158 #define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
1159 #define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
1160 #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
1161 /**
1162 * @}
1163 */
1164
1165 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
1166 * @{
1167 */
1168 #define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
1169 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
1175 * @{
1176 */
1177 #define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
1178 #define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
1179 #define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
1180 /**
1181 * @}
1182 */
1183
1184 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
1185 * @{
1186 */
1187 #define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
1188 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
1189 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
1190 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
1196 * @{
1197 */
1198 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
1199 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
1200 /**
1201 * @}
1202 */
1203
1204 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
1205 * @{
1206 */
1207 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
1208 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
1209 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
1210 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
1216 * @{
1217 */
1218 #define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
1219 #define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
1220 #define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
1221 #define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
1222 #define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
1223 #define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
1224 #define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
1225 #define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
1226 /**
1227 * @}
1228 */
1229
1230 /** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
1231 * @{
1232 */
1233 #define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
1234 #define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
1235 #define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
1236 /**
1237 * @}
1238 */
1239
1240 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
1241 * @{
1242 */
1243 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
1244 #define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
1245 #define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
1246 /**
1247 * @}
1248 */
1249
1250 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
1251 * @{
1252 */
1253 #define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
1254 #define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
1255 #define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
1256 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
1257 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
1258 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
1259 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
1260 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
1261 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
1262 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
1263 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
1264 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
1265 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
1266 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
1267 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
1268 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
1269 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
1270 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
1271 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
1272 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
1273 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
1274 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
1275 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
1276 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
1277 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
1278 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
1279 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
1280 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
1281 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
1282 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
1283 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
1284 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
1285 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
1286 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
1287 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
1288 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
1289 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
1290 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
1291 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
1292 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
1293 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
1294 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
1295 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
1296 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
1297 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
1298 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
1299 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
1300 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
1301 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
1302 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
1303 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
1304 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
1305 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
1306 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
1307 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
1308 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
1309 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
1310 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
1311 #define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
1312 #define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
1313 #define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
1314 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
1315 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
1316 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
1317 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */
1318 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */
1319 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */
1320 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */
1321 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */
1322 #define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */
1323 #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
1324 #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
1325 #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
1326 #define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */
1327 #define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */
1328 #define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */
1329 #define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */
1330 #define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */
1331 #define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */
1332 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */
1333 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */
1334 #define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */
1335 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */
1336 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */
1337 #define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */
1338 #define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */
1339 #define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */
1340 #define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */
1341 #define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */
1342 #define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */
1343 #define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */
1344 #define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */
1345 #define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */
1346 #define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */
1347 /**
1348 * @}
1349 */
1350
1351 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
1352 * @{
1353 */
1354 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
1355 #define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
1356 #define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
1357 /**
1358 * @}
1359 */
1360
1361 /** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
1362 * @{
1363 */
1364 #define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
1365 #define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
1366 #define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
1367 #define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
1368 #define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
1369 #define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
1370 #define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
1371 #define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
1372 /**
1373 * @}
1374 */
1375
1376 /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
1377 * @{
1378 */
1379 #define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
1380 #define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
1381 #define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1382 #define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
1383 #define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
1384 /**
1385 * @}
1386 */
1387
1388 /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
1389 * @{
1390 */
1391 #define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
1392 #define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
1393 /**
1394 * @}
1395 */
1396
1397 /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
1398 * @{
1399 */
1400 #define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1401 #define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1402 #define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1403 #define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1404 #define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1405 #define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1406 #define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1407 #define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
1413 * @{
1414 */
1415 #define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
1416 #define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
1417 #define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
1418 #define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
1419 #define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
1420 #define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
1421 #define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
1422 #define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
1423 #define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
1424 /**
1425 * @}
1426 */
1427
1428 #if defined(ADC_MULTIMODE_SUPPORT)
1429 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
1430 * @{
1431 */
1432 #define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
1433 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
1434 #define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
1435 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
1436 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
1437 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
1438 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
1439 #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
1440 /**
1441 * @}
1442 */
1443
1444 /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
1445 * @{
1446 */
1447 #define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
1448 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
1449 #define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
1450 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
1451 #define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
1452 /**
1453 * @}
1454 */
1455
1456 /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
1457 * @{
1458 */
1459 #define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
1460 #define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
1461 #define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
1462 #define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
1463 #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
1464 #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
1465 #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
1466 #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
1467 #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
1468 #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
1469 #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
1470 #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
1471 /**
1472 * @}
1473 */
1474
1475 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
1476 * @{
1477 */
1478 #define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
1479 #define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
1480 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
1481 /**
1482 * @}
1483 */
1484
1485 #endif /* ADC_MULTIMODE_SUPPORT */
1486
1487
1488 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
1489 * @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
1490 * not timeout values.
1491 * For details on delays values, refer to descriptions in source code
1492 * above each literal definition.
1493 * @{
1494 */
1495
1496 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
1497 /* not timeout values. */
1498 /* Timeout values for ADC operations are dependent to device clock */
1499 /* configuration (system clock versus ADC clock), */
1500 /* and therefore must be defined in user application. */
1501 /* Indications for estimation of ADC timeout delays, for this */
1502 /* STM32 serie: */
1503 /* - ADC calibration time: maximum delay is 112/fADC. */
1504 /* (refer to device datasheet, parameter "tCAL") */
1505 /* - ADC enable time: maximum delay is 1 conversion cycle. */
1506 /* (refer to device datasheet, parameter "tSTAB") */
1507 /* - ADC disable time: maximum delay should be a few ADC clock cycles */
1508 /* - ADC stop conversion time: maximum delay should be a few ADC clock */
1509 /* cycles */
1510 /* - ADC conversion time: duration depending on ADC clock and ADC */
1511 /* configuration. */
1512 /* (refer to device reference manual, section "Timing") */
1513
1514 /* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1515 /* Delay set to maximum value (refer to device datasheet, */
1516 /* parameter "tADCVREG_STUP"). */
1517 /* Unit: us */
1518 #define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
1519
1520 /* Delay for internal voltage reference stabilization time. */
1521 /* Delay set to maximum value (refer to device datasheet, */
1522 /* parameter "tstart_vrefint"). */
1523 /* Unit: us */
1524 #define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
1525
1526 /* Delay for temperature sensor stabilization time. */
1527 /* Literal set to maximum value (refer to device datasheet, */
1528 /* parameter "tSTART"). */
1529 /* Unit: us */
1530 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
1531
1532 /* Delay required between ADC end of calibration and ADC enable. */
1533 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
1534 /* are required between ADC end of calibration and ADC enable. */
1535 /* Wait time can be computed in user application by waiting for the */
1536 /* equivalent number of CPU cycles, by taking into account */
1537 /* ratio of CPU clock versus ADC clock prescalers. */
1538 /* Unit: ADC clock cycles. */
1539 #define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
1540
1541 /**
1542 * @}
1543 */
1544
1545 /**
1546 * @}
1547 */
1548
1549
1550 /* Exported macro ------------------------------------------------------------*/
1551 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
1552 * @{
1553 */
1554
1555 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
1556 * @{
1557 */
1558
1559 /**
1560 * @brief Write a value in ADC register
1561 * @param __INSTANCE__ ADC Instance
1562 * @param __REG__ Register to be written
1563 * @param __VALUE__ Value to be written in the register
1564 * @retval None
1565 */
1566 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1567
1568 /**
1569 * @brief Read a value in ADC register
1570 * @param __INSTANCE__ ADC Instance
1571 * @param __REG__ Register to be read
1572 * @retval Register value
1573 */
1574 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1575 /**
1576 * @}
1577 */
1578
1579 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
1580 * @{
1581 */
1582
1583 /**
1584 * @brief Helper macro to get ADC channel number in decimal format
1585 * from literals LL_ADC_CHANNEL_x.
1586 * @note Example:
1587 * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
1588 * will return decimal number "4".
1589 * @note The input can be a value from functions where a channel
1590 * number is returned, either defined with number
1591 * or with bitfield (only one bit must be set).
1592 * @param __CHANNEL__ This parameter can be one of the following values:
1593 * @arg @ref LL_ADC_CHANNEL_0
1594 * @arg @ref LL_ADC_CHANNEL_1 (8)
1595 * @arg @ref LL_ADC_CHANNEL_2 (8)
1596 * @arg @ref LL_ADC_CHANNEL_3 (8)
1597 * @arg @ref LL_ADC_CHANNEL_4 (8)
1598 * @arg @ref LL_ADC_CHANNEL_5 (8)
1599 * @arg @ref LL_ADC_CHANNEL_6
1600 * @arg @ref LL_ADC_CHANNEL_7
1601 * @arg @ref LL_ADC_CHANNEL_8
1602 * @arg @ref LL_ADC_CHANNEL_9
1603 * @arg @ref LL_ADC_CHANNEL_10
1604 * @arg @ref LL_ADC_CHANNEL_11
1605 * @arg @ref LL_ADC_CHANNEL_12
1606 * @arg @ref LL_ADC_CHANNEL_13
1607 * @arg @ref LL_ADC_CHANNEL_14
1608 * @arg @ref LL_ADC_CHANNEL_15
1609 * @arg @ref LL_ADC_CHANNEL_16
1610 * @arg @ref LL_ADC_CHANNEL_17
1611 * @arg @ref LL_ADC_CHANNEL_18
1612 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1613 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1614 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1615 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1616 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1617 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1618 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1619 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1620 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1621 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1622 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1623 *
1624 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1625 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1626 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1627 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1628 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1629 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1630 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1631 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1632 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1633 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1634 * @retval Value between Min_Data=0 and Max_Data=18
1635 */
1636 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1637 ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) \
1638 ? ( \
1639 ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
1640 ) \
1641 : \
1642 ( \
1643 (uint32_t)POSITION_VAL((__CHANNEL__)) \
1644 ) \
1645 )
1646
1647 /**
1648 * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1649 * from number in decimal format.
1650 * @note Example:
1651 * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1652 * will return a data equivalent to "LL_ADC_CHANNEL_4".
1653 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
1654 * @retval Returned value can be one of the following values:
1655 * @arg @ref LL_ADC_CHANNEL_0
1656 * @arg @ref LL_ADC_CHANNEL_1 (8)
1657 * @arg @ref LL_ADC_CHANNEL_2 (8)
1658 * @arg @ref LL_ADC_CHANNEL_3 (8)
1659 * @arg @ref LL_ADC_CHANNEL_4 (8)
1660 * @arg @ref LL_ADC_CHANNEL_5 (8)
1661 * @arg @ref LL_ADC_CHANNEL_6
1662 * @arg @ref LL_ADC_CHANNEL_7
1663 * @arg @ref LL_ADC_CHANNEL_8
1664 * @arg @ref LL_ADC_CHANNEL_9
1665 * @arg @ref LL_ADC_CHANNEL_10
1666 * @arg @ref LL_ADC_CHANNEL_11
1667 * @arg @ref LL_ADC_CHANNEL_12
1668 * @arg @ref LL_ADC_CHANNEL_13
1669 * @arg @ref LL_ADC_CHANNEL_14
1670 * @arg @ref LL_ADC_CHANNEL_15
1671 * @arg @ref LL_ADC_CHANNEL_16
1672 * @arg @ref LL_ADC_CHANNEL_17
1673 * @arg @ref LL_ADC_CHANNEL_18
1674 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1675 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1676 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1677 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1678 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1679 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1680 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1681 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1682 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1683 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1684 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1685 *
1686 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1687 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1688 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1689 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1690 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1691 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1692 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1693 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1694 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1695 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1696 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
1697 * comparison with internal channel parameter to be done
1698 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1699 */
1700 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1701 (((__DECIMAL_NB__) <= 9UL) \
1702 ? ( \
1703 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1704 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1705 (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1706 ) \
1707 : \
1708 ( \
1709 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1710 (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
1711 (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1712 ) \
1713 )
1714
1715 /**
1716 * @brief Helper macro to determine whether the selected channel
1717 * corresponds to literal definitions of driver.
1718 * @note The different literal definitions of ADC channels are:
1719 * - ADC internal channel:
1720 * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1721 * - ADC external channel (channel connected to a GPIO pin):
1722 * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1723 * @note The channel parameter must be a value defined from literal
1724 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1725 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1726 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1727 * must not be a value from functions where a channel number is
1728 * returned from ADC registers,
1729 * because internal and external channels share the same channel
1730 * number in ADC registers. The differentiation is made only with
1731 * parameters definitions of driver.
1732 * @param __CHANNEL__ This parameter can be one of the following values:
1733 * @arg @ref LL_ADC_CHANNEL_0
1734 * @arg @ref LL_ADC_CHANNEL_1 (8)
1735 * @arg @ref LL_ADC_CHANNEL_2 (8)
1736 * @arg @ref LL_ADC_CHANNEL_3 (8)
1737 * @arg @ref LL_ADC_CHANNEL_4 (8)
1738 * @arg @ref LL_ADC_CHANNEL_5 (8)
1739 * @arg @ref LL_ADC_CHANNEL_6
1740 * @arg @ref LL_ADC_CHANNEL_7
1741 * @arg @ref LL_ADC_CHANNEL_8
1742 * @arg @ref LL_ADC_CHANNEL_9
1743 * @arg @ref LL_ADC_CHANNEL_10
1744 * @arg @ref LL_ADC_CHANNEL_11
1745 * @arg @ref LL_ADC_CHANNEL_12
1746 * @arg @ref LL_ADC_CHANNEL_13
1747 * @arg @ref LL_ADC_CHANNEL_14
1748 * @arg @ref LL_ADC_CHANNEL_15
1749 * @arg @ref LL_ADC_CHANNEL_16
1750 * @arg @ref LL_ADC_CHANNEL_17
1751 * @arg @ref LL_ADC_CHANNEL_18
1752 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1753 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1754 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1755 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1756 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1757 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1758 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1759 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1760 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1761 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1762 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1763 *
1764 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1765 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1766 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1767 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1768 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1769 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1770 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1771 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1772 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1773 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1774 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1775 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1776 */
1777 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1778 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1779
1780 /**
1781 * @brief Helper macro to convert a channel defined from parameter
1782 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1783 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1784 * to its equivalent parameter definition of a ADC external channel
1785 * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1786 * @note The channel parameter can be, additionally to a value
1787 * defined from parameter definition of a ADC internal channel
1788 * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1789 * a value defined from parameter definition of
1790 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1791 * or a value from functions where a channel number is returned
1792 * from ADC registers.
1793 * @param __CHANNEL__ This parameter can be one of the following values:
1794 * @arg @ref LL_ADC_CHANNEL_0
1795 * @arg @ref LL_ADC_CHANNEL_1 (8)
1796 * @arg @ref LL_ADC_CHANNEL_2 (8)
1797 * @arg @ref LL_ADC_CHANNEL_3 (8)
1798 * @arg @ref LL_ADC_CHANNEL_4 (8)
1799 * @arg @ref LL_ADC_CHANNEL_5 (8)
1800 * @arg @ref LL_ADC_CHANNEL_6
1801 * @arg @ref LL_ADC_CHANNEL_7
1802 * @arg @ref LL_ADC_CHANNEL_8
1803 * @arg @ref LL_ADC_CHANNEL_9
1804 * @arg @ref LL_ADC_CHANNEL_10
1805 * @arg @ref LL_ADC_CHANNEL_11
1806 * @arg @ref LL_ADC_CHANNEL_12
1807 * @arg @ref LL_ADC_CHANNEL_13
1808 * @arg @ref LL_ADC_CHANNEL_14
1809 * @arg @ref LL_ADC_CHANNEL_15
1810 * @arg @ref LL_ADC_CHANNEL_16
1811 * @arg @ref LL_ADC_CHANNEL_17
1812 * @arg @ref LL_ADC_CHANNEL_18
1813 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1814 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1815 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1816 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1817 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1818 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1819 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1820 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1821 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1822 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1823 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1824 *
1825 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1826 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1827 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1828 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1829 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1830 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1831 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1832 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1833 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
1834 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
1835 * @retval Returned value can be one of the following values:
1836 * @arg @ref LL_ADC_CHANNEL_0
1837 * @arg @ref LL_ADC_CHANNEL_1
1838 * @arg @ref LL_ADC_CHANNEL_2
1839 * @arg @ref LL_ADC_CHANNEL_3
1840 * @arg @ref LL_ADC_CHANNEL_4
1841 * @arg @ref LL_ADC_CHANNEL_5
1842 * @arg @ref LL_ADC_CHANNEL_6
1843 * @arg @ref LL_ADC_CHANNEL_7
1844 * @arg @ref LL_ADC_CHANNEL_8
1845 * @arg @ref LL_ADC_CHANNEL_9
1846 * @arg @ref LL_ADC_CHANNEL_10
1847 * @arg @ref LL_ADC_CHANNEL_11
1848 * @arg @ref LL_ADC_CHANNEL_12
1849 * @arg @ref LL_ADC_CHANNEL_13
1850 * @arg @ref LL_ADC_CHANNEL_14
1851 * @arg @ref LL_ADC_CHANNEL_15
1852 * @arg @ref LL_ADC_CHANNEL_16
1853 * @arg @ref LL_ADC_CHANNEL_17
1854 * @arg @ref LL_ADC_CHANNEL_18
1855 */
1856 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1857 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1858
1859 /**
1860 * @brief Helper macro to determine whether the internal channel
1861 * selected is available on the ADC instance selected.
1862 * @note The channel parameter must be a value defined from parameter
1863 * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1864 * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1865 * must not be a value defined from parameter definition of
1866 * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1867 * or a value from functions where a channel number is
1868 * returned from ADC registers,
1869 * because internal and external channels share the same channel
1870 * number in ADC registers. The differentiation is made only with
1871 * parameters definitions of driver.
1872 * @param __ADC_INSTANCE__ ADC instance
1873 * @param __CHANNEL__ This parameter can be one of the following values:
1874 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1875 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1876 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1877 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1878 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1879 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1880 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1881 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1882 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1883 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1884 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
1885 *
1886 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
1887 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
1888 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
1889 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
1890 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
1891 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
1892 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
1893 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
1894 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1895 * Value "1" if the internal channel selected is available on the ADC instance selected.
1896 */
1897 #if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
1898 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1899 ((((__ADC_INSTANCE__) == ADC1) \
1900 &&( \
1901 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1902 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1903 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1904 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1905 ) \
1906 ) \
1907 || \
1908 (((__ADC_INSTANCE__) == ADC2) \
1909 &&( \
1910 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1911 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
1912 ) \
1913 ) \
1914 || \
1915 (((__ADC_INSTANCE__) == ADC3) \
1916 &&( \
1917 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
1918 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1919 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1920 ) \
1921 ) \
1922 || \
1923 (((__ADC_INSTANCE__) == ADC4) \
1924 &&( \
1925 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
1926 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1927 ) \
1928 ) \
1929 || \
1930 (((__ADC_INSTANCE__) == ADC5) \
1931 &&( \
1932 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
1933 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
1934 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
1935 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1936 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1937 ) \
1938 ) \
1939 )
1940 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
1941 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1942 ((((__ADC_INSTANCE__) == ADC1) \
1943 &&( \
1944 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
1945 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
1946 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
1947 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
1948 ) \
1949 ) \
1950 || \
1951 (((__ADC_INSTANCE__) == ADC2) \
1952 &&( \
1953 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
1954 ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
1955 ) \
1956 ) \
1957 )
1958 #endif
1959
1960 /**
1961 * @brief Helper macro to define ADC analog watchdog parameter:
1962 * define a single channel to monitor with analog watchdog
1963 * from sequencer channel and groups definition.
1964 * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1965 * Example:
1966 * LL_ADC_SetAnalogWDMonitChannels(
1967 * ADC1, LL_ADC_AWD1,
1968 * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1969 * @param __CHANNEL__ This parameter can be one of the following values:
1970 * @arg @ref LL_ADC_CHANNEL_0
1971 * @arg @ref LL_ADC_CHANNEL_1 (8)
1972 * @arg @ref LL_ADC_CHANNEL_2 (8)
1973 * @arg @ref LL_ADC_CHANNEL_3 (8)
1974 * @arg @ref LL_ADC_CHANNEL_4 (8)
1975 * @arg @ref LL_ADC_CHANNEL_5 (8)
1976 * @arg @ref LL_ADC_CHANNEL_6
1977 * @arg @ref LL_ADC_CHANNEL_7
1978 * @arg @ref LL_ADC_CHANNEL_8
1979 * @arg @ref LL_ADC_CHANNEL_9
1980 * @arg @ref LL_ADC_CHANNEL_10
1981 * @arg @ref LL_ADC_CHANNEL_11
1982 * @arg @ref LL_ADC_CHANNEL_12
1983 * @arg @ref LL_ADC_CHANNEL_13
1984 * @arg @ref LL_ADC_CHANNEL_14
1985 * @arg @ref LL_ADC_CHANNEL_15
1986 * @arg @ref LL_ADC_CHANNEL_16
1987 * @arg @ref LL_ADC_CHANNEL_17
1988 * @arg @ref LL_ADC_CHANNEL_18
1989 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
1990 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
1991 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
1992 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
1993 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
1994 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
1995 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
1996 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
1997 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
1998 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
1999 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
2000 *
2001 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2002 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2003 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2004 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2005 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2006 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2007 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2008 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
2009 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
2010 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
2011 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
2012 * comparison with internal channel parameter to be done
2013 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2014 * @param __GROUP__ This parameter can be one of the following values:
2015 * @arg @ref LL_ADC_GROUP_REGULAR
2016 * @arg @ref LL_ADC_GROUP_INJECTED
2017 * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
2018 * @retval Returned value can be one of the following values:
2019 * @arg @ref LL_ADC_AWD_DISABLE
2020 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
2021 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
2022 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2023 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
2024 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
2025 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2026 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
2027 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
2028 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2029 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
2030 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
2031 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2032 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
2033 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
2034 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2035 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
2036 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
2037 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2038 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
2039 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
2040 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2041 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
2042 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
2043 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2044 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
2045 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
2046 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2047 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
2048 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
2049 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2050 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
2051 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
2052 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2053 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
2054 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
2055 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2056 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
2057 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
2058 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2059 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
2060 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
2061 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2062 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
2063 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
2064 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2065 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
2066 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
2067 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2068 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
2069 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
2070 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
2071 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
2072 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
2073 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
2074 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
2075 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
2076 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
2077 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
2078 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
2079 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
2080 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
2081 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
2082 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
2083 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
2084 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
2085 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
2086 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
2087 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
2088 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
2089 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
2090 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
2091 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
2092 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
2093 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
2094 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
2095 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
2096 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
2097 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
2098 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
2099 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
2100 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
2101 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
2102 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
2103 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
2104 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
2105 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
2106 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
2107 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
2108 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
2109 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
2110 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
2111 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
2112 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
2113 *
2114 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
2115 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
2116 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
2117 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
2118 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
2119 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
2120 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
2121 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
2122 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
2123 */
2124 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
2125 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
2126 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2127 : \
2128 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
2129 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
2130 : \
2131 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
2132 )
2133
2134 /**
2135 * @brief Helper macro to set the value of ADC analog watchdog threshold high
2136 * or low in function of ADC resolution, when ADC resolution is
2137 * different of 12 bits.
2138 * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
2139 * or @ref LL_ADC_SetAnalogWDThresholds().
2140 * Example, with a ADC resolution of 8 bits, to set the value of
2141 * analog watchdog threshold high (on 8 bits):
2142 * LL_ADC_SetAnalogWDThresholds
2143 * (< ADCx param >,
2144 * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
2145 * );
2146 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2147 * @arg @ref LL_ADC_RESOLUTION_12B
2148 * @arg @ref LL_ADC_RESOLUTION_10B
2149 * @arg @ref LL_ADC_RESOLUTION_8B
2150 * @arg @ref LL_ADC_RESOLUTION_6B
2151 * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
2152 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2153 */
2154 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
2155 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2156
2157 /**
2158 * @brief Helper macro to get the value of ADC analog watchdog threshold high
2159 * or low in function of ADC resolution, when ADC resolution is
2160 * different of 12 bits.
2161 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2162 * Example, with a ADC resolution of 8 bits, to get the value of
2163 * analog watchdog threshold high (on 8 bits):
2164 * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
2165 * (LL_ADC_RESOLUTION_8B,
2166 * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
2167 * );
2168 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2169 * @arg @ref LL_ADC_RESOLUTION_12B
2170 * @arg @ref LL_ADC_RESOLUTION_10B
2171 * @arg @ref LL_ADC_RESOLUTION_8B
2172 * @arg @ref LL_ADC_RESOLUTION_6B
2173 * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
2174 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2175 */
2176 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
2177 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
2178
2179 /**
2180 * @brief Helper macro to get the ADC analog watchdog threshold high
2181 * or low from raw value containing both thresholds concatenated.
2182 * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
2183 * Example, to get analog watchdog threshold high from the register raw value:
2184 * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
2185 * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
2186 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
2187 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
2188 * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2189 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2190 */
2191 #define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
2192 (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
2193
2194 /**
2195 * @brief Helper macro to set the ADC calibration value with both single ended
2196 * and differential modes calibration factors concatenated.
2197 * @note To be used with function @ref LL_ADC_SetCalibrationFactor().
2198 * Example, to set calibration factors single ended to 0x55
2199 * and differential ended to 0x2A:
2200 * LL_ADC_SetCalibrationFactor(
2201 * ADC1,
2202 * __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
2203 * @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
2204 * @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
2205 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
2206 */
2207 #define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
2208 (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
2209
2210 #if defined(ADC_MULTIMODE_SUPPORT)
2211 /**
2212 * @brief Helper macro to get the ADC multimode conversion data of ADC master
2213 * or ADC slave from raw value with both ADC conversion data concatenated.
2214 * @note This macro is intended to be used when multimode transfer by DMA
2215 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
2216 * In this case the transferred data need to processed with this macro
2217 * to separate the conversion data of ADC master and ADC slave.
2218 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
2219 * @arg @ref LL_ADC_MULTI_MASTER
2220 * @arg @ref LL_ADC_MULTI_SLAVE
2221 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
2222 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2223 */
2224 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
2225 (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
2226 #endif
2227
2228 #if defined(ADC_MULTIMODE_SUPPORT)
2229 /**
2230 * @brief Helper macro to select, from a ADC instance, to which ADC instance
2231 * it has a dependence in multimode (ADC master of the corresponding
2232 * ADC common instance).
2233 * @note In case of device with multimode available and a mix of
2234 * ADC instances compliant and not compliant with multimode feature,
2235 * ADC instances not compliant with multimode feature are
2236 * considered as master instances (do not depend to
2237 * any other ADC instance).
2238 * @param __ADCx__ ADC instance
2239 * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
2240 */
2241 #if defined(ADC5)
2242 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2243 ( ( ((__ADCx__) == ADC2) \
2244 )? \
2245 (ADC1) \
2246 : \
2247 ( ( ((__ADCx__) == ADC4) \
2248 )? \
2249 (ADC3) \
2250 : \
2251 (__ADCx__) \
2252 ) \
2253 )
2254 #else
2255 #define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
2256 ( ( ((__ADCx__) == ADC2) \
2257 )? \
2258 (ADC1) \
2259 : \
2260 (__ADCx__) \
2261 )
2262 #endif
2263 #endif
2264
2265 /**
2266 * @brief Helper macro to select the ADC common instance
2267 * to which is belonging the selected ADC instance.
2268 * @note ADC common register instance can be used for:
2269 * - Set parameters common to several ADC instances
2270 * - Multimode (for devices with several ADC instances)
2271 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2272 * @param __ADCx__ ADC instance
2273 * @retval ADC common register instance
2274 */
2275 #if defined(ADC345_COMMON)
2276 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
2277 ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
2278 ? ( \
2279 (ADC12_COMMON) \
2280 ) \
2281 : \
2282 ( \
2283 (ADC345_COMMON) \
2284 ) \
2285 )
2286 #else
2287 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
2288 #endif
2289 /**
2290 * @brief Helper macro to check if all ADC instances sharing the same
2291 * ADC common instance are disabled.
2292 * @note This check is required by functions with setting conditioned to
2293 * ADC state:
2294 * All ADC instances of the ADC common group must be disabled.
2295 * Refer to functions having argument "ADCxy_COMMON" as parameter.
2296 * @note On devices with only 1 ADC common instance, parameter of this macro
2297 * is useless and can be ignored (parameter kept for compatibility
2298 * with devices featuring several ADC common instances).
2299 * @param __ADCXY_COMMON__ ADC common instance
2300 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2301 * @retval Value "0" if all ADC instances sharing the same ADC common instance
2302 * are disabled.
2303 * Value "1" if at least one ADC instance sharing the same ADC common instance
2304 * is enabled.
2305 */
2306 #if defined(ADC345_COMMON)
2307 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2308 (((__ADCXY_COMMON__) == ADC12_COMMON) \
2309 ? ( \
2310 (LL_ADC_IsEnabled(ADC1) | \
2311 LL_ADC_IsEnabled(ADC2) ) \
2312 ) \
2313 : \
2314 ( \
2315 (LL_ADC_IsEnabled(ADC3) | \
2316 LL_ADC_IsEnabled(ADC4) | \
2317 LL_ADC_IsEnabled(ADC5) ) \
2318 ) \
2319 )
2320 #else
2321 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
2322 (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
2323 #endif
2324
2325 /**
2326 * @brief Helper macro to define the ADC conversion data full-scale digital
2327 * value corresponding to the selected ADC resolution.
2328 * @note ADC conversion data full-scale corresponds to voltage range
2329 * determined by analog voltage references Vref+ and Vref-
2330 * (refer to reference manual).
2331 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2332 * @arg @ref LL_ADC_RESOLUTION_12B
2333 * @arg @ref LL_ADC_RESOLUTION_10B
2334 * @arg @ref LL_ADC_RESOLUTION_8B
2335 * @arg @ref LL_ADC_RESOLUTION_6B
2336 * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
2337 */
2338 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2339 (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
2340
2341 /**
2342 * @brief Helper macro to convert the ADC conversion data from
2343 * a resolution to another resolution.
2344 * @param __DATA__ ADC conversion data to be converted
2345 * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
2346 * This parameter can be one of the following values:
2347 * @arg @ref LL_ADC_RESOLUTION_12B
2348 * @arg @ref LL_ADC_RESOLUTION_10B
2349 * @arg @ref LL_ADC_RESOLUTION_8B
2350 * @arg @ref LL_ADC_RESOLUTION_6B
2351 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
2352 * This parameter can be one of the following values:
2353 * @arg @ref LL_ADC_RESOLUTION_12B
2354 * @arg @ref LL_ADC_RESOLUTION_10B
2355 * @arg @ref LL_ADC_RESOLUTION_8B
2356 * @arg @ref LL_ADC_RESOLUTION_6B
2357 * @retval ADC conversion data to the requested resolution
2358 */
2359 #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
2360 __ADC_RESOLUTION_CURRENT__,\
2361 __ADC_RESOLUTION_TARGET__) \
2362 (((__DATA__) \
2363 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
2364 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
2365 )
2366
2367 /**
2368 * @brief Helper macro to calculate the voltage (unit: mVolt)
2369 * corresponding to a ADC conversion data (unit: digital value).
2370 * @note Analog reference voltage (Vref+) must be either known from
2371 * user board environment or can be calculated using ADC measurement
2372 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2373 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2374 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
2375 * (unit: digital value).
2376 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2377 * @arg @ref LL_ADC_RESOLUTION_12B
2378 * @arg @ref LL_ADC_RESOLUTION_10B
2379 * @arg @ref LL_ADC_RESOLUTION_8B
2380 * @arg @ref LL_ADC_RESOLUTION_6B
2381 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
2382 */
2383 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
2384 __ADC_DATA__,\
2385 __ADC_RESOLUTION__) \
2386 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
2387 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
2388 )
2389
2390 /**
2391 * @brief Helper macro to calculate analog reference voltage (Vref+)
2392 * (unit: mVolt) from ADC conversion data of internal voltage
2393 * reference VrefInt.
2394 * @note Computation is using VrefInt calibration value
2395 * stored in system memory for each device during production.
2396 * @note This voltage depends on user board environment: voltage level
2397 * connected to pin Vref+.
2398 * On devices with small package, the pin Vref+ is not present
2399 * and internally bonded to pin Vdda.
2400 * @note On this STM32 serie, calibration data of internal voltage reference
2401 * VrefInt corresponds to a resolution of 12 bits,
2402 * this is the recommended ADC resolution to convert voltage of
2403 * internal voltage reference VrefInt.
2404 * Otherwise, this macro performs the processing to scale
2405 * ADC conversion data to 12 bits.
2406 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
2407 * of internal voltage reference VrefInt (unit: digital value).
2408 * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
2409 * @arg @ref LL_ADC_RESOLUTION_12B
2410 * @arg @ref LL_ADC_RESOLUTION_10B
2411 * @arg @ref LL_ADC_RESOLUTION_8B
2412 * @arg @ref LL_ADC_RESOLUTION_6B
2413 * @retval Analog reference voltage (unit: mV)
2414 */
2415 #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
2416 __ADC_RESOLUTION__) \
2417 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
2418 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
2419 (__ADC_RESOLUTION__), \
2420 LL_ADC_RESOLUTION_12B))
2421
2422 /**
2423 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2424 * from ADC conversion data of internal temperature sensor.
2425 * @note Computation is using temperature sensor calibration values
2426 * stored in system memory for each device during production.
2427 * @note Calculation formula:
2428 * Temperature = ((TS_ADC_DATA - TS_CAL1)
2429 * * (TS_CAL2_TEMP - TS_CAL1_TEMP))
2430 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
2431 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2432 * Avg_Slope = (TS_CAL2 - TS_CAL1)
2433 * / (TS_CAL2_TEMP - TS_CAL1_TEMP)
2434 * TS_CAL1 = equivalent TS_ADC_DATA at temperature
2435 * TEMP_DEGC_CAL1 (calibrated in factory)
2436 * TS_CAL2 = equivalent TS_ADC_DATA at temperature
2437 * TEMP_DEGC_CAL2 (calibrated in factory)
2438 * Caution: Calculation relevancy under reserve that calibration
2439 * parameters are correct (address and data).
2440 * To calculate temperature using temperature sensor
2441 * datasheet typical values (generic values less, therefore
2442 * less accurate than calibrated values),
2443 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
2444 * @note As calculation input, the analog reference voltage (Vref+) must be
2445 * defined as it impacts the ADC LSB equivalent voltage.
2446 * @note Analog reference voltage (Vref+) must be either known from
2447 * user board environment or can be calculated using ADC measurement
2448 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2449 * @note On this STM32 serie, calibration data of temperature sensor
2450 * corresponds to a resolution of 12 bits,
2451 * this is the recommended ADC resolution to convert voltage of
2452 * temperature sensor.
2453 * Otherwise, this macro performs the processing to scale
2454 * ADC conversion data to 12 bits.
2455 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
2456 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
2457 * temperature sensor (unit: digital value).
2458 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
2459 * sensor voltage has been measured.
2460 * This parameter can be one of the following values:
2461 * @arg @ref LL_ADC_RESOLUTION_12B
2462 * @arg @ref LL_ADC_RESOLUTION_10B
2463 * @arg @ref LL_ADC_RESOLUTION_8B
2464 * @arg @ref LL_ADC_RESOLUTION_6B
2465 * @retval Temperature (unit: degree Celsius)
2466 */
2467 #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
2468 __TEMPSENSOR_ADC_DATA__,\
2469 __ADC_RESOLUTION__) \
2470 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
2471 (__ADC_RESOLUTION__), \
2472 LL_ADC_RESOLUTION_12B) \
2473 * (__VREFANALOG_VOLTAGE__)) \
2474 / TEMPSENSOR_CAL_VREFANALOG) \
2475 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
2476 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
2477 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
2478 ) + TEMPSENSOR_CAL1_TEMP \
2479 )
2480
2481 /**
2482 * @brief Helper macro to calculate the temperature (unit: degree Celsius)
2483 * from ADC conversion data of internal temperature sensor.
2484 * @note Computation is using temperature sensor typical values
2485 * (refer to device datasheet).
2486 * @note Calculation formula:
2487 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
2488 * / Avg_Slope + CALx_TEMP
2489 * with TS_ADC_DATA = temperature sensor raw data measured by ADC
2490 * (unit: digital value)
2491 * Avg_Slope = temperature sensor slope
2492 * (unit: uV/Degree Celsius)
2493 * TS_TYP_CALx_VOLT = temperature sensor digital value at
2494 * temperature CALx_TEMP (unit: mV)
2495 * Caution: Calculation relevancy under reserve the temperature sensor
2496 * of the current device has characteristics in line with
2497 * datasheet typical values.
2498 * If temperature sensor calibration values are available on
2499 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
2500 * temperature calculation will be more accurate using
2501 * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
2502 * @note As calculation input, the analog reference voltage (Vref+) must be
2503 * defined as it impacts the ADC LSB equivalent voltage.
2504 * @note Analog reference voltage (Vref+) must be either known from
2505 * user board environment or can be calculated using ADC measurement
2506 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
2507 * @note ADC measurement data must correspond to a resolution of 12 bits
2508 * (full scale digital value 4095). If not the case, the data must be
2509 * preliminarily rescaled to an equivalent resolution of 12 bits.
2510 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
2511 * On STM32G4, refer to device datasheet parameter "Avg_Slope".
2512 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
2513 * On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
2514 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
2515 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
2516 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
2517 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
2518 * This parameter can be one of the following values:
2519 * @arg @ref LL_ADC_RESOLUTION_12B
2520 * @arg @ref LL_ADC_RESOLUTION_10B
2521 * @arg @ref LL_ADC_RESOLUTION_8B
2522 * @arg @ref LL_ADC_RESOLUTION_6B
2523 * @retval Temperature (unit: degree Celsius)
2524 */
2525 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
2526 __TEMPSENSOR_TYP_CALX_V__,\
2527 __TEMPSENSOR_CALX_TEMP__,\
2528 __VREFANALOG_VOLTAGE__,\
2529 __TEMPSENSOR_ADC_DATA__,\
2530 __ADC_RESOLUTION__) \
2531 ((( ( \
2532 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
2533 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
2534 * 1000UL) \
2535 - \
2536 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
2537 * 1000UL) \
2538 ) \
2539 ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
2540 ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
2541 )
2542
2543 /**
2544 * @}
2545 */
2546
2547 /**
2548 * @}
2549 */
2550
2551
2552 /* Exported functions --------------------------------------------------------*/
2553 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
2554 * @{
2555 */
2556
2557 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
2558 * @{
2559 */
2560 /* Note: LL ADC functions to set DMA transfer are located into sections of */
2561 /* configuration of ADC instance, groups and multimode (if available): */
2562 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
2563
2564 /**
2565 * @brief Function to help to configure DMA transfer from ADC: retrieve the
2566 * ADC register address from ADC instance and a list of ADC registers
2567 * intended to be used (most commonly) with DMA transfer.
2568 * @note These ADC registers are data registers:
2569 * when ADC conversion data is available in ADC data registers,
2570 * ADC generates a DMA transfer request.
2571 * @note This macro is intended to be used with LL DMA driver, refer to
2572 * function "LL_DMA_ConfigAddresses()".
2573 * Example:
2574 * LL_DMA_ConfigAddresses(DMA1,
2575 * LL_DMA_CHANNEL_1,
2576 * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
2577 * (uint32_t)&< array or variable >,
2578 * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
2579 * @note For devices with several ADC: in multimode, some devices
2580 * use a different data register outside of ADC instance scope
2581 * (common data register). This macro manages this register difference,
2582 * only ADC instance has to be set as parameter.
2583 * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
2584 * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
2585 * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
2586 * @param ADCx ADC instance
2587 * @param Register This parameter can be one of the following values:
2588 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
2589 * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
2590 *
2591 * (1) Available on devices with several ADC instances.
2592 * @retval ADC register address
2593 */
2594 #if defined(ADC_MULTIMODE_SUPPORT)
2595 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2596 {
2597 register uint32_t data_reg_addr;
2598
2599 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
2600 {
2601 /* Retrieve address of register DR */
2602 data_reg_addr = (uint32_t) &(ADCx->DR);
2603 }
2604 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
2605 {
2606 /* Retrieve address of register CDR */
2607 data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
2608 }
2609
2610 return data_reg_addr;
2611 }
2612 #else
2613 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
2614 {
2615 /* Prevent unused argument(s) compilation warning */
2616 (void)(Register);
2617
2618 /* Retrieve address of register DR */
2619 return (uint32_t) &(ADCx->DR);
2620 }
2621 #endif
2622
2623 /**
2624 * @}
2625 */
2626
2627 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
2628 * @{
2629 */
2630
2631 /**
2632 * @brief Set parameter common to several ADC: Clock source and prescaler.
2633 * @note On this STM32 serie, if ADC group injected is used, some
2634 * clock ratio constraints between ADC clock and AHB clock
2635 * must be respected.
2636 * Refer to reference manual.
2637 * @note On this STM32 serie, setting of this feature is conditioned to
2638 * ADC state:
2639 * All ADC instances of the ADC common group must be disabled.
2640 * This check can be done with function @ref LL_ADC_IsEnabled() for each
2641 * ADC instance or by using helper macro helper macro
2642 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
2643 * @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
2644 * CCR PRESC LL_ADC_SetCommonClock
2645 * @param ADCxy_COMMON ADC common instance
2646 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2647 * @param CommonClock This parameter can be one of the following values:
2648 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2649 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2650 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2651 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2652 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2653 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2654 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2655 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2656 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2657 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2658 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2659 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2660 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2661 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2662 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2663 * @retval None
2664 */
2665 __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
2666 {
2667 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
2668 }
2669
2670 /**
2671 * @brief Get parameter common to several ADC: Clock source and prescaler.
2672 * @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
2673 * CCR PRESC LL_ADC_GetCommonClock
2674 * @param ADCxy_COMMON ADC common instance
2675 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2676 * @retval Returned value can be one of the following values:
2677 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
2678 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
2679 * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
2680 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
2681 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
2682 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
2683 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
2684 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
2685 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
2686 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
2687 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
2688 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
2689 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
2690 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
2691 * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
2692 */
2693 __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
2694 {
2695 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
2696 }
2697
2698 /**
2699 * @brief Set parameter common to several ADC: measurement path to internal
2700 * channels (VrefInt, temperature sensor, ...).
2701 * @note One or several values can be selected.
2702 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2703 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2704 * @note Stabilization time of measurement path to internal channel:
2705 * After enabling internal paths, before starting ADC conversion,
2706 * a delay is required for internal voltage reference and
2707 * temperature sensor stabilization time.
2708 * Refer to device datasheet.
2709 * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
2710 * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
2711 * @note ADC internal channel sampling time constraint:
2712 * For ADC conversion of internal channels,
2713 * a sampling time minimum value is required.
2714 * Refer to device datasheet.
2715 * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
2716 * CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
2717 * CCR VBATSEL LL_ADC_SetCommonPathInternalCh
2718 * @param ADCxy_COMMON ADC common instance
2719 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2720 * @param PathInternal This parameter can be a combination of the following values:
2721 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2722 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2723 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2724 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2725 * @retval None
2726 */
2727 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
2728 {
2729 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
2730 }
2731
2732 /**
2733 * @brief Get parameter common to several ADC: measurement path to internal
2734 * channels (VrefInt, temperature sensor, ...).
2735 * @note One or several values can be selected.
2736 * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
2737 * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
2738 * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
2739 * CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
2740 * CCR VBATSEL LL_ADC_GetCommonPathInternalCh
2741 * @param ADCxy_COMMON ADC common instance
2742 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
2743 * @retval Returned value can be a combination of the following values:
2744 * @arg @ref LL_ADC_PATH_INTERNAL_NONE
2745 * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
2746 * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
2747 * @arg @ref LL_ADC_PATH_INTERNAL_VBAT
2748 */
2749 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
2750 {
2751 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
2752 }
2753
2754 /**
2755 * @}
2756 */
2757
2758 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
2759 * @{
2760 */
2761
2762 /**
2763 * @brief Set ADC calibration factor in the mode single-ended
2764 * or differential (for devices with differential mode available).
2765 * @note This function is intended to set calibration parameters
2766 * without having to perform a new calibration using
2767 * @ref LL_ADC_StartCalibration().
2768 * @note For devices with differential mode available:
2769 * Calibration of offset is specific to each of
2770 * single-ended and differential modes
2771 * (calibration factor must be specified for each of these
2772 * differential modes, if used afterwards and if the application
2773 * requires their calibration).
2774 * @note In case of setting calibration factors of both modes single ended
2775 * and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
2776 * both calibration factors must be concatenated.
2777 * To perform this processing, use helper macro
2778 * @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
2779 * @note On this STM32 serie, setting of this feature is conditioned to
2780 * ADC state:
2781 * ADC must be enabled, without calibration on going, without conversion
2782 * on going on group regular.
2783 * @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
2784 * CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
2785 * @param ADCx ADC instance
2786 * @param SingleDiff This parameter can be one of the following values:
2787 * @arg @ref LL_ADC_SINGLE_ENDED
2788 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2789 * @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
2790 * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
2791 * @retval None
2792 */
2793 __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
2794 {
2795 MODIFY_REG(ADCx->CALFACT,
2796 SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
2797 CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
2798 }
2799
2800 /**
2801 * @brief Get ADC calibration factor in the mode single-ended
2802 * or differential (for devices with differential mode available).
2803 * @note Calibration factors are set by hardware after performing
2804 * a calibration run using function @ref LL_ADC_StartCalibration().
2805 * @note For devices with differential mode available:
2806 * Calibration of offset is specific to each of
2807 * single-ended and differential modes
2808 * @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
2809 * CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
2810 * @param ADCx ADC instance
2811 * @param SingleDiff This parameter can be one of the following values:
2812 * @arg @ref LL_ADC_SINGLE_ENDED
2813 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
2814 * @retval Value between Min_Data=0x00 and Max_Data=0x7F
2815 */
2816 __STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
2817 {
2818 /* Retrieve bits with position in register depending on parameter */
2819 /* "SingleDiff". */
2820 /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
2821 /* containing other bits reserved for other purpose. */
2822 return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
2823 }
2824
2825 /**
2826 * @brief Set ADC resolution.
2827 * Refer to reference manual for alignments formats
2828 * dependencies to ADC resolutions.
2829 * @note On this STM32 serie, setting of this feature is conditioned to
2830 * ADC state:
2831 * ADC must be disabled or enabled without conversion on going
2832 * on either groups regular or injected.
2833 * @rmtoll CFGR RES LL_ADC_SetResolution
2834 * @param ADCx ADC instance
2835 * @param Resolution This parameter can be one of the following values:
2836 * @arg @ref LL_ADC_RESOLUTION_12B
2837 * @arg @ref LL_ADC_RESOLUTION_10B
2838 * @arg @ref LL_ADC_RESOLUTION_8B
2839 * @arg @ref LL_ADC_RESOLUTION_6B
2840 * @retval None
2841 */
2842 __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2843 {
2844 MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
2845 }
2846
2847 /**
2848 * @brief Get ADC resolution.
2849 * Refer to reference manual for alignments formats
2850 * dependencies to ADC resolutions.
2851 * @rmtoll CFGR RES LL_ADC_GetResolution
2852 * @param ADCx ADC instance
2853 * @retval Returned value can be one of the following values:
2854 * @arg @ref LL_ADC_RESOLUTION_12B
2855 * @arg @ref LL_ADC_RESOLUTION_10B
2856 * @arg @ref LL_ADC_RESOLUTION_8B
2857 * @arg @ref LL_ADC_RESOLUTION_6B
2858 */
2859 __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
2860 {
2861 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
2862 }
2863
2864 /**
2865 * @brief Set ADC conversion data alignment.
2866 * @note Refer to reference manual for alignments formats
2867 * dependencies to ADC resolutions.
2868 * @note On this STM32 serie, setting of this feature is conditioned to
2869 * ADC state:
2870 * ADC must be disabled or enabled without conversion on going
2871 * on either groups regular or injected.
2872 * @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
2873 * @param ADCx ADC instance
2874 * @param DataAlignment This parameter can be one of the following values:
2875 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2876 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2877 * @retval None
2878 */
2879 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2880 {
2881 MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
2882 }
2883
2884 /**
2885 * @brief Get ADC conversion data alignment.
2886 * @note Refer to reference manual for alignments formats
2887 * dependencies to ADC resolutions.
2888 * @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
2889 * @param ADCx ADC instance
2890 * @retval Returned value can be one of the following values:
2891 * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
2892 * @arg @ref LL_ADC_DATA_ALIGN_LEFT
2893 */
2894 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
2895 {
2896 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
2897 }
2898
2899 /**
2900 * @brief Set ADC low power mode.
2901 * @note Description of ADC low power modes:
2902 * - ADC low power mode "auto wait": Dynamic low power mode,
2903 * ADC conversions occurrences are limited to the minimum necessary
2904 * in order to reduce power consumption.
2905 * New ADC conversion starts only when the previous
2906 * unitary conversion data (for ADC group regular)
2907 * or previous sequence conversions data (for ADC group injected)
2908 * has been retrieved by user software.
2909 * In the meantime, ADC remains idle: does not performs any
2910 * other conversion.
2911 * This mode allows to automatically adapt the ADC conversions
2912 * triggers to the speed of the software that reads the data.
2913 * Moreover, this avoids risk of overrun for low frequency
2914 * applications.
2915 * How to use this low power mode:
2916 * - Do not use with interruption or DMA since these modes
2917 * have to clear immediately the EOC flag to free the
2918 * IRQ vector sequencer.
2919 * - Do use with polling: 1. Start conversion,
2920 * 2. Later on, when conversion data is needed: poll for end of
2921 * conversion to ensure that conversion is completed and
2922 * retrieve ADC conversion data. This will trig another
2923 * ADC conversion start.
2924 * - ADC low power mode "auto power-off" (feature available on
2925 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2926 * the ADC automatically powers-off after a conversion and
2927 * automatically wakes up when a new conversion is triggered
2928 * (with startup time between trigger and start of sampling).
2929 * This feature can be combined with low power mode "auto wait".
2930 * @note With ADC low power mode "auto wait", the ADC conversion data read
2931 * is corresponding to previous ADC conversion start, independently
2932 * of delay during which ADC was idle.
2933 * Therefore, the ADC conversion data may be outdated: does not
2934 * correspond to the current voltage level on the selected
2935 * ADC channel.
2936 * @note On this STM32 serie, setting of this feature is conditioned to
2937 * ADC state:
2938 * ADC must be disabled or enabled without conversion on going
2939 * on either groups regular or injected.
2940 * @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
2941 * @param ADCx ADC instance
2942 * @param LowPowerMode This parameter can be one of the following values:
2943 * @arg @ref LL_ADC_LP_MODE_NONE
2944 * @arg @ref LL_ADC_LP_AUTOWAIT
2945 * @retval None
2946 */
2947 __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
2948 {
2949 MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
2950 }
2951
2952 /**
2953 * @brief Get ADC low power mode:
2954 * @note Description of ADC low power modes:
2955 * - ADC low power mode "auto wait": Dynamic low power mode,
2956 * ADC conversions occurrences are limited to the minimum necessary
2957 * in order to reduce power consumption.
2958 * New ADC conversion starts only when the previous
2959 * unitary conversion data (for ADC group regular)
2960 * or previous sequence conversions data (for ADC group injected)
2961 * has been retrieved by user software.
2962 * In the meantime, ADC remains idle: does not performs any
2963 * other conversion.
2964 * This mode allows to automatically adapt the ADC conversions
2965 * triggers to the speed of the software that reads the data.
2966 * Moreover, this avoids risk of overrun for low frequency
2967 * applications.
2968 * How to use this low power mode:
2969 * - Do not use with interruption or DMA since these modes
2970 * have to clear immediately the EOC flag to free the
2971 * IRQ vector sequencer.
2972 * - Do use with polling: 1. Start conversion,
2973 * 2. Later on, when conversion data is needed: poll for end of
2974 * conversion to ensure that conversion is completed and
2975 * retrieve ADC conversion data. This will trig another
2976 * ADC conversion start.
2977 * - ADC low power mode "auto power-off" (feature available on
2978 * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
2979 * the ADC automatically powers-off after a conversion and
2980 * automatically wakes up when a new conversion is triggered
2981 * (with startup time between trigger and start of sampling).
2982 * This feature can be combined with low power mode "auto wait".
2983 * @note With ADC low power mode "auto wait", the ADC conversion data read
2984 * is corresponding to previous ADC conversion start, independently
2985 * of delay during which ADC was idle.
2986 * Therefore, the ADC conversion data may be outdated: does not
2987 * correspond to the current voltage level on the selected
2988 * ADC channel.
2989 * @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
2990 * @param ADCx ADC instance
2991 * @retval Returned value can be one of the following values:
2992 * @arg @ref LL_ADC_LP_MODE_NONE
2993 * @arg @ref LL_ADC_LP_AUTOWAIT
2994 */
2995 __STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
2996 {
2997 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
2998 }
2999
3000 /**
3001 * @brief Set ADC selected offset number 1, 2, 3 or 4.
3002 * @note This function set the 2 items of offset configuration:
3003 * - ADC channel to which the offset programmed will be applied
3004 * (independently of channel mapped on ADC group regular
3005 * or group injected)
3006 * - Offset level (offset to be subtracted from the raw
3007 * converted data).
3008 * @note Caution: Offset format is dependent to ADC resolution:
3009 * offset has to be left-aligned on bit 11, the LSB (right bits)
3010 * are set to 0.
3011 * @note This function enables the offset, by default. It can be forced
3012 * to disable state using function LL_ADC_SetOffsetState().
3013 * @note If a channel is mapped on several offsets numbers, only the offset
3014 * with the lowest value is considered for the subtraction.
3015 * @note On this STM32 serie, setting of this feature is conditioned to
3016 * ADC state:
3017 * ADC must be disabled or enabled without conversion on going
3018 * on either groups regular or injected.
3019 * @note On STM32G4, some fast channels are available: fast analog inputs
3020 * coming from GPIO pads (ADC_IN1..5).
3021 * @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
3022 * OFR1 OFFSET1 LL_ADC_SetOffset\n
3023 * OFR1 OFFSET1_EN LL_ADC_SetOffset\n
3024 * OFR2 OFFSET2_CH LL_ADC_SetOffset\n
3025 * OFR2 OFFSET2 LL_ADC_SetOffset\n
3026 * OFR2 OFFSET2_EN LL_ADC_SetOffset\n
3027 * OFR3 OFFSET3_CH LL_ADC_SetOffset\n
3028 * OFR3 OFFSET3 LL_ADC_SetOffset\n
3029 * OFR3 OFFSET3_EN LL_ADC_SetOffset\n
3030 * OFR4 OFFSET4_CH LL_ADC_SetOffset\n
3031 * OFR4 OFFSET4 LL_ADC_SetOffset\n
3032 * OFR4 OFFSET4_EN LL_ADC_SetOffset
3033 * @param ADCx ADC instance
3034 * @param Offsety This parameter can be one of the following values:
3035 * @arg @ref LL_ADC_OFFSET_1
3036 * @arg @ref LL_ADC_OFFSET_2
3037 * @arg @ref LL_ADC_OFFSET_3
3038 * @arg @ref LL_ADC_OFFSET_4
3039 * @param Channel This parameter can be one of the following values:
3040 * @arg @ref LL_ADC_CHANNEL_0
3041 * @arg @ref LL_ADC_CHANNEL_1 (8)
3042 * @arg @ref LL_ADC_CHANNEL_2 (8)
3043 * @arg @ref LL_ADC_CHANNEL_3 (8)
3044 * @arg @ref LL_ADC_CHANNEL_4 (8)
3045 * @arg @ref LL_ADC_CHANNEL_5 (8)
3046 * @arg @ref LL_ADC_CHANNEL_6
3047 * @arg @ref LL_ADC_CHANNEL_7
3048 * @arg @ref LL_ADC_CHANNEL_8
3049 * @arg @ref LL_ADC_CHANNEL_9
3050 * @arg @ref LL_ADC_CHANNEL_10
3051 * @arg @ref LL_ADC_CHANNEL_11
3052 * @arg @ref LL_ADC_CHANNEL_12
3053 * @arg @ref LL_ADC_CHANNEL_13
3054 * @arg @ref LL_ADC_CHANNEL_14
3055 * @arg @ref LL_ADC_CHANNEL_15
3056 * @arg @ref LL_ADC_CHANNEL_16
3057 * @arg @ref LL_ADC_CHANNEL_17
3058 * @arg @ref LL_ADC_CHANNEL_18
3059 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
3060 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
3061 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
3062 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
3063 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3064 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3065 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
3066 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
3067 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
3068 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
3069 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
3070 *
3071 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3072 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3073 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3074 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3075 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3076 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3077 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3078 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
3079 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
3080 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
3081 * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
3082 * @retval None
3083 */
3084 __STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
3085 {
3086 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3087
3088 MODIFY_REG(*preg,
3089 ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
3090 ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
3091 }
3092
3093 /**
3094 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3095 * Channel to which the offset programmed will be applied
3096 * (independently of channel mapped on ADC group regular
3097 * or group injected)
3098 * @note Usage of the returned channel number:
3099 * - To reinject this channel into another function LL_ADC_xxx:
3100 * the returned channel number is only partly formatted on definition
3101 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3102 * with parts of literals LL_ADC_CHANNEL_x or using
3103 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3104 * Then the selected literal LL_ADC_CHANNEL_x can be used
3105 * as parameter for another function.
3106 * - To get the channel number in decimal format:
3107 * process the returned value with the helper macro
3108 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3109 * @note On STM32G4, some fast channels are available: fast analog inputs
3110 * coming from GPIO pads (ADC_IN1..5).
3111 * @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
3112 * OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
3113 * OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
3114 * OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
3115 * @param ADCx ADC instance
3116 * @param Offsety This parameter can be one of the following values:
3117 * @arg @ref LL_ADC_OFFSET_1
3118 * @arg @ref LL_ADC_OFFSET_2
3119 * @arg @ref LL_ADC_OFFSET_3
3120 * @arg @ref LL_ADC_OFFSET_4
3121 * @retval Returned value can be one of the following values:
3122 * @arg @ref LL_ADC_CHANNEL_0
3123 * @arg @ref LL_ADC_CHANNEL_1 (8)
3124 * @arg @ref LL_ADC_CHANNEL_2 (8)
3125 * @arg @ref LL_ADC_CHANNEL_3 (8)
3126 * @arg @ref LL_ADC_CHANNEL_4 (8)
3127 * @arg @ref LL_ADC_CHANNEL_5 (8)
3128 * @arg @ref LL_ADC_CHANNEL_6
3129 * @arg @ref LL_ADC_CHANNEL_7
3130 * @arg @ref LL_ADC_CHANNEL_8
3131 * @arg @ref LL_ADC_CHANNEL_9
3132 * @arg @ref LL_ADC_CHANNEL_10
3133 * @arg @ref LL_ADC_CHANNEL_11
3134 * @arg @ref LL_ADC_CHANNEL_12
3135 * @arg @ref LL_ADC_CHANNEL_13
3136 * @arg @ref LL_ADC_CHANNEL_14
3137 * @arg @ref LL_ADC_CHANNEL_15
3138 * @arg @ref LL_ADC_CHANNEL_16
3139 * @arg @ref LL_ADC_CHANNEL_17
3140 * @arg @ref LL_ADC_CHANNEL_18
3141 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
3142 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
3143 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
3144 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
3145 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3146 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3147 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
3148 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
3149 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
3150 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
3151 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
3152 *
3153 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3154 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3155 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3156 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3157 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3158 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3159 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3160 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
3161 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
3162 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
3163 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
3164 * comparison with internal channel parameter to be done
3165 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
3166 */
3167 __STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
3168 {
3169 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3170
3171 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
3172 }
3173
3174 /**
3175 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3176 * Offset level (offset to be subtracted from the raw
3177 * converted data).
3178 * @note Caution: Offset format is dependent to ADC resolution:
3179 * offset has to be left-aligned on bit 11, the LSB (right bits)
3180 * are set to 0.
3181 * @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
3182 * OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
3183 * OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
3184 * OFR4 OFFSET4 LL_ADC_GetOffsetLevel
3185 * @param ADCx ADC instance
3186 * @param Offsety This parameter can be one of the following values:
3187 * @arg @ref LL_ADC_OFFSET_1
3188 * @arg @ref LL_ADC_OFFSET_2
3189 * @arg @ref LL_ADC_OFFSET_3
3190 * @arg @ref LL_ADC_OFFSET_4
3191 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3192 */
3193 __STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
3194 {
3195 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3196
3197 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
3198 }
3199
3200 /**
3201 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3202 * force offset state disable or enable
3203 * without modifying offset channel or offset value.
3204 * @note This function should be needed only in case of offset to be
3205 * enabled-disabled dynamically, and should not be needed in other cases:
3206 * function LL_ADC_SetOffset() automatically enables the offset.
3207 * @note On this STM32 serie, setting of this feature is conditioned to
3208 * ADC state:
3209 * ADC must be disabled or enabled without conversion on going
3210 * on either groups regular or injected.
3211 * @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
3212 * OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
3213 * OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
3214 * OFR4 OFFSET4_EN LL_ADC_SetOffsetState
3215 * @param ADCx ADC instance
3216 * @param Offsety This parameter can be one of the following values:
3217 * @arg @ref LL_ADC_OFFSET_1
3218 * @arg @ref LL_ADC_OFFSET_2
3219 * @arg @ref LL_ADC_OFFSET_3
3220 * @arg @ref LL_ADC_OFFSET_4
3221 * @param OffsetState This parameter can be one of the following values:
3222 * @arg @ref LL_ADC_OFFSET_DISABLE
3223 * @arg @ref LL_ADC_OFFSET_ENABLE
3224 * @retval None
3225 */
3226 __STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
3227 {
3228 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3229
3230 MODIFY_REG(*preg,
3231 ADC_OFR1_OFFSET1_EN,
3232 OffsetState);
3233 }
3234
3235 /**
3236 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3237 * offset state disabled or enabled.
3238 * @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
3239 * OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
3240 * OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
3241 * OFR4 OFFSET4_EN LL_ADC_GetOffsetState
3242 * @param ADCx ADC instance
3243 * @param Offsety This parameter can be one of the following values:
3244 * @arg @ref LL_ADC_OFFSET_1
3245 * @arg @ref LL_ADC_OFFSET_2
3246 * @arg @ref LL_ADC_OFFSET_3
3247 * @arg @ref LL_ADC_OFFSET_4
3248 * @retval Returned value can be one of the following values:
3249 * @arg @ref LL_ADC_OFFSET_DISABLE
3250 * @arg @ref LL_ADC_OFFSET_ENABLE
3251 */
3252 __STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
3253 {
3254 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3255
3256 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
3257 }
3258
3259 /**
3260 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3261 * choose offset sign.
3262 * @note On this STM32 serie, setting of this feature is conditioned to
3263 * ADC state:
3264 * ADC must be disabled or enabled without conversion on going
3265 * on either groups regular or injected.
3266 * @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
3267 * OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
3268 * OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
3269 * OFR4 OFFSETPOS LL_ADC_SetOffsetSign
3270 * @param ADCx ADC instance
3271 * @param Offsety This parameter can be one of the following values:
3272 * @arg @ref LL_ADC_OFFSET_1
3273 * @arg @ref LL_ADC_OFFSET_2
3274 * @arg @ref LL_ADC_OFFSET_3
3275 * @arg @ref LL_ADC_OFFSET_4
3276 * @param OffsetSign This parameter can be one of the following values:
3277 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3278 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3279 * @retval None
3280 */
3281 __STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
3282 {
3283 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3284
3285 MODIFY_REG(*preg,
3286 ADC_OFR1_OFFSETPOS,
3287 OffsetSign);
3288 }
3289
3290 /**
3291 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3292 * offset sign if positive or negative.
3293 * @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
3294 * OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
3295 * OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
3296 * OFR4 OFFSETPOS LL_ADC_GetOffsetSign
3297 * @param ADCx ADC instance
3298 * @param Offsety This parameter can be one of the following values:
3299 * @arg @ref LL_ADC_OFFSET_1
3300 * @arg @ref LL_ADC_OFFSET_2
3301 * @arg @ref LL_ADC_OFFSET_3
3302 * @arg @ref LL_ADC_OFFSET_4
3303 * @retval Returned value can be one of the following values:
3304 * @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
3305 * @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
3306 */
3307 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
3308 {
3309 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3310
3311 return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
3312 }
3313
3314 /**
3315 * @brief Set for the ADC selected offset number 1, 2, 3 or 4:
3316 * choose offset saturation mode.
3317 * @note On this STM32 serie, setting of this feature is conditioned to
3318 * ADC state:
3319 * ADC must be disabled or enabled without conversion on going
3320 * on either groups regular or injected.
3321 * @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
3322 * OFR2 SATEN LL_ADC_SetOffsetSaturation\n
3323 * OFR3 SATEN LL_ADC_SetOffsetSaturation\n
3324 * OFR4 SATEN LL_ADC_SetOffsetSaturation
3325 * @param ADCx ADC instance
3326 * @param Offsety This parameter can be one of the following values:
3327 * @arg @ref LL_ADC_OFFSET_1
3328 * @arg @ref LL_ADC_OFFSET_2
3329 * @arg @ref LL_ADC_OFFSET_3
3330 * @arg @ref LL_ADC_OFFSET_4
3331 * @param OffsetSaturation This parameter can be one of the following values:
3332 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3333 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3334 * @retval None
3335 */
3336 __STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
3337 {
3338 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3339
3340 MODIFY_REG(*preg,
3341 ADC_OFR1_SATEN,
3342 OffsetSaturation);
3343 }
3344
3345 /**
3346 * @brief Get for the ADC selected offset number 1, 2, 3 or 4:
3347 * offset saturation if enabled or disabled.
3348 * @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
3349 * OFR2 SATEN LL_ADC_GetOffsetSaturation\n
3350 * OFR3 SATEN LL_ADC_GetOffsetSaturation\n
3351 * OFR4 SATEN LL_ADC_GetOffsetSaturation
3352 * @param ADCx ADC instance
3353 * @param Offsety This parameter can be one of the following values:
3354 * @arg @ref LL_ADC_OFFSET_1
3355 * @arg @ref LL_ADC_OFFSET_2
3356 * @arg @ref LL_ADC_OFFSET_3
3357 * @arg @ref LL_ADC_OFFSET_4
3358 * @retval Returned value can be one of the following values:
3359 * @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
3360 * @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
3361 */
3362 __STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
3363 {
3364 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
3365
3366 return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
3367 }
3368
3369 /**
3370 * @brief Set ADC gain compensation.
3371 * @note This function set the gain compensation coefficient
3372 * that is applied to raw converted data using the formula:
3373 * DATA = DATA(raw) * (gain compensation coef) / 4096
3374 * @note This function enables the gain compensation if given
3375 * coefficient is above 0, otherwise it disables it.
3376 * @note Gain compensation when enabled is appied to all channels.
3377 * @note On this STM32 serie, setting of this feature is conditioned to
3378 * ADC state:
3379 * ADC must be disabled or enabled without conversion on going
3380 * on either groups regular or injected.
3381 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
3382 * CFGR2 GCOMP LL_ADC_SetGainCompensation
3383 * @param ADCx ADC instance
3384 * @param GainCompensation This parameter can be:
3385 * 0 Gain compensation will be disabled and value set to 0
3386 * 1 -> 16393 Gain compensation will be enabled with specified value
3387 * @retval None
3388 */
3389 __STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
3390 {
3391 MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
3392 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
3393 }
3394
3395 /**
3396 * @brief Get the ADC gain compensation value
3397 * @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
3398 * CFGR2 GCOMP LL_ADC_GetGainCompensation
3399 * @param ADCx ADC instance
3400 * @retval Returned value can be:
3401 * 0 Gain compensation is disabled
3402 * 1 -> 16393 Gain compensation is enabled with returned value
3403 */
3404 __STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
3405 {
3406 return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
3407 }
3408
3409 #if defined(ADC_SMPR1_SMPPLUS)
3410 /**
3411 * @brief Set ADC sampling time common configuration impacting
3412 * settings of sampling time channel wise.
3413 * @note On this STM32 serie, setting of this feature is conditioned to
3414 * ADC state:
3415 * ADC must be disabled or enabled without conversion on going
3416 * on either groups regular or injected.
3417 * @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
3418 * @param ADCx ADC instance
3419 * @param SamplingTimeCommonConfig This parameter can be one of the following values:
3420 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3421 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3422 * @retval None
3423 */
3424 __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
3425 {
3426 MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
3427 }
3428
3429 /**
3430 * @brief Get ADC sampling time common configuration impacting
3431 * settings of sampling time channel wise.
3432 * @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
3433 * @param ADCx ADC instance
3434 * @retval Returned value can be one of the following values:
3435 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
3436 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
3437 */
3438 __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
3439 {
3440 return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
3441 }
3442 #endif /* ADC_SMPR1_SMPPLUS */
3443
3444 /**
3445 * @}
3446 */
3447
3448 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
3449 * @{
3450 */
3451
3452 /**
3453 * @brief Set ADC group regular conversion trigger source:
3454 * internal (SW start) or from external peripheral (timer event,
3455 * external interrupt line).
3456 * @note On this STM32 serie, setting trigger source to external trigger
3457 * also set trigger polarity to rising edge
3458 * (default setting for compatibility with some ADC on other
3459 * STM32 families having this setting set by HW default value).
3460 * In case of need to modify trigger edge, use
3461 * function @ref LL_ADC_REG_SetTriggerEdge().
3462 * @note Availability of parameters of trigger sources from timer
3463 * depends on timers availability on the selected device.
3464 * @note On this STM32 serie, setting of this feature is conditioned to
3465 * ADC state:
3466 * ADC must be disabled or enabled without conversion on going
3467 * on group regular.
3468 * @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
3469 * CFGR EXTEN LL_ADC_REG_SetTriggerSource
3470 * @param ADCx ADC instance
3471 * @param TriggerSource This parameter can be one of the following values:
3472 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3473 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3474 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3475 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3476 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3477 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3478 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3479 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
3480 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
3481 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3482 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3483 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
3484 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
3485 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3486 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
3487 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
3488 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3489 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3490 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3491 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3492 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
3493 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3494 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
3495 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
3496 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
3497 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
3498 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
3499 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3500 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
3501 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3502 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
3503 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
3504 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
3505 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
3506 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
3507 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
3508 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
3509 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
3510 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
3511 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
3512 *
3513 * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n
3514 * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
3515 * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
3516 * @retval None
3517 */
3518 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
3519 {
3520 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
3521 }
3522
3523 /**
3524 * @brief Get ADC group regular conversion trigger source:
3525 * internal (SW start) or from external peripheral (timer event,
3526 * external interrupt line).
3527 * @note To determine whether group regular trigger source is
3528 * internal (SW start) or external, without detail
3529 * of which peripheral is selected as external trigger,
3530 * (equivalent to
3531 * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
3532 * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
3533 * @note Availability of parameters of trigger sources from timer
3534 * depends on timers availability on the selected device.
3535 * @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
3536 * CFGR EXTEN LL_ADC_REG_GetTriggerSource
3537 * @param ADCx ADC instance
3538 * @retval Returned value can be one of the following values:
3539 * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
3540 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
3541 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
3542 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
3543 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
3544 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
3545 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
3546 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
3547 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
3548 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
3549 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
3550 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
3551 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
3552 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
3553 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
3554 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
3555 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
3556 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
3557 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
3558 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
3559 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
3560 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
3561 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
3562 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
3563 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
3564 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
3565 * @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
3566 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
3567 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
3568 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
3569 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
3570 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
3571 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
3572 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
3573 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
3574 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
3575 * @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
3576 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
3577 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
3578 * @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
3579 *
3580 * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n
3581 * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
3582 * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
3583 */
3584 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
3585 {
3586 register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
3587
3588 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
3589 /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
3590 register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
3591
3592 /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
3593 /* to match with triggers literals definition. */
3594 return ((TriggerSource
3595 & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
3596 | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
3597 );
3598 }
3599
3600 /**
3601 * @brief Get ADC group regular conversion trigger source internal (SW start)
3602 * or external.
3603 * @note In case of group regular trigger source set to external trigger,
3604 * to determine which peripheral is selected as external trigger,
3605 * use function @ref LL_ADC_REG_GetTriggerSource().
3606 * @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
3607 * @param ADCx ADC instance
3608 * @retval Value "0" if trigger source external trigger
3609 * Value "1" if trigger source SW start.
3610 */
3611 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
3612 {
3613 return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
3614 }
3615
3616 /**
3617 * @brief Set ADC group regular conversion trigger polarity.
3618 * @note Applicable only for trigger source set to external trigger.
3619 * @note On this STM32 serie, setting of this feature is conditioned to
3620 * ADC state:
3621 * ADC must be disabled or enabled without conversion on going
3622 * on group regular.
3623 * @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
3624 * @param ADCx ADC instance
3625 * @param ExternalTriggerEdge This parameter can be one of the following values:
3626 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3627 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3628 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3629 * @retval None
3630 */
3631 __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3632 {
3633 MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
3634 }
3635
3636 /**
3637 * @brief Get ADC group regular conversion trigger polarity.
3638 * @note Applicable only for trigger source set to external trigger.
3639 * @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
3640 * @param ADCx ADC instance
3641 * @retval Returned value can be one of the following values:
3642 * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3643 * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
3644 * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
3645 */
3646 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
3647 {
3648 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
3649 }
3650
3651 /**
3652 * @brief Set ADC sampling mode.
3653 * @note This function set the ADC conversion sampling mode
3654 * @note This mode applies to regular group only.
3655 * @note Set sampling mode is appied to all conversion of regular group.
3656 * @note On this STM32 serie, setting of this feature is conditioned to
3657 * ADC state:
3658 * ADC must be disabled or enabled without conversion on going
3659 * on group regular.
3660 * @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
3661 * CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
3662 * @param ADCx ADC instance
3663 * @param SamplingMode This parameter can be one of the following values:
3664 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3665 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3666 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3667 * @retval None
3668 */
3669 __STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
3670 {
3671 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
3672 }
3673
3674 /**
3675 * @brief Get the ADC sampling mode
3676 * @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
3677 * CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
3678 * @param ADCx ADC instance
3679 * @retval Returned value can be one of the following values:
3680 * @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
3681 * @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
3682 * @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
3683 */
3684 __STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
3685 {
3686 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
3687 }
3688
3689 /**
3690 * @brief Set ADC group regular sequencer length and scan direction.
3691 * @note Description of ADC group regular sequencer features:
3692 * - For devices with sequencer fully configurable
3693 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3694 * sequencer length and each rank affectation to a channel
3695 * are configurable.
3696 * This function performs configuration of:
3697 * - Sequence length: Number of ranks in the scan sequence.
3698 * - Sequence direction: Unless specified in parameters, sequencer
3699 * scan direction is forward (from rank 1 to rank n).
3700 * Sequencer ranks are selected using
3701 * function "LL_ADC_REG_SetSequencerRanks()".
3702 * - For devices with sequencer not fully configurable
3703 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3704 * sequencer length and each rank affectation to a channel
3705 * are defined by channel number.
3706 * This function performs configuration of:
3707 * - Sequence length: Number of ranks in the scan sequence is
3708 * defined by number of channels set in the sequence,
3709 * rank of each channel is fixed by channel HW number.
3710 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3711 * - Sequence direction: Unless specified in parameters, sequencer
3712 * scan direction is forward (from lowest channel number to
3713 * highest channel number).
3714 * Sequencer ranks are selected using
3715 * function "LL_ADC_REG_SetSequencerChannels()".
3716 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3717 * ADC conversion on only 1 channel.
3718 * @note On this STM32 serie, setting of this feature is conditioned to
3719 * ADC state:
3720 * ADC must be disabled or enabled without conversion on going
3721 * on group regular.
3722 * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
3723 * @param ADCx ADC instance
3724 * @param SequencerNbRanks This parameter can be one of the following values:
3725 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3726 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3727 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3728 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3729 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3730 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3731 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3732 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3733 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3734 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3735 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3736 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3737 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3738 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3739 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3740 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3741 * @retval None
3742 */
3743 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
3744 {
3745 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
3746 }
3747
3748 /**
3749 * @brief Get ADC group regular sequencer length and scan direction.
3750 * @note Description of ADC group regular sequencer features:
3751 * - For devices with sequencer fully configurable
3752 * (function "LL_ADC_REG_SetSequencerRanks()" available):
3753 * sequencer length and each rank affectation to a channel
3754 * are configurable.
3755 * This function retrieves:
3756 * - Sequence length: Number of ranks in the scan sequence.
3757 * - Sequence direction: Unless specified in parameters, sequencer
3758 * scan direction is forward (from rank 1 to rank n).
3759 * Sequencer ranks are selected using
3760 * function "LL_ADC_REG_SetSequencerRanks()".
3761 * - For devices with sequencer not fully configurable
3762 * (function "LL_ADC_REG_SetSequencerChannels()" available):
3763 * sequencer length and each rank affectation to a channel
3764 * are defined by channel number.
3765 * This function retrieves:
3766 * - Sequence length: Number of ranks in the scan sequence is
3767 * defined by number of channels set in the sequence,
3768 * rank of each channel is fixed by channel HW number.
3769 * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
3770 * - Sequence direction: Unless specified in parameters, sequencer
3771 * scan direction is forward (from lowest channel number to
3772 * highest channel number).
3773 * Sequencer ranks are selected using
3774 * function "LL_ADC_REG_SetSequencerChannels()".
3775 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
3776 * ADC conversion on only 1 channel.
3777 * @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
3778 * @param ADCx ADC instance
3779 * @retval Returned value can be one of the following values:
3780 * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
3781 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
3782 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
3783 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
3784 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
3785 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
3786 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
3787 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
3788 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
3789 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
3790 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
3791 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
3792 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
3793 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
3794 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
3795 * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
3796 */
3797 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
3798 {
3799 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
3800 }
3801
3802 /**
3803 * @brief Set ADC group regular sequencer discontinuous mode:
3804 * sequence subdivided and scan conversions interrupted every selected
3805 * number of ranks.
3806 * @note It is not possible to enable both ADC group regular
3807 * continuous mode and sequencer discontinuous mode.
3808 * @note It is not possible to enable both ADC auto-injected mode
3809 * and ADC group regular sequencer discontinuous mode.
3810 * @note On this STM32 serie, setting of this feature is conditioned to
3811 * ADC state:
3812 * ADC must be disabled or enabled without conversion on going
3813 * on group regular.
3814 * @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
3815 * CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
3816 * @param ADCx ADC instance
3817 * @param SeqDiscont This parameter can be one of the following values:
3818 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3819 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3820 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3821 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3822 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3823 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3824 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3825 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3826 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3827 * @retval None
3828 */
3829 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
3830 {
3831 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
3832 }
3833
3834 /**
3835 * @brief Get ADC group regular sequencer discontinuous mode:
3836 * sequence subdivided and scan conversions interrupted every selected
3837 * number of ranks.
3838 * @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
3839 * CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
3840 * @param ADCx ADC instance
3841 * @retval Returned value can be one of the following values:
3842 * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
3843 * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
3844 * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
3845 * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
3846 * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
3847 * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
3848 * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
3849 * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
3850 * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
3851 */
3852 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
3853 {
3854 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
3855 }
3856
3857 /**
3858 * @brief Set ADC group regular sequence: channel on the selected
3859 * scan sequence rank.
3860 * @note This function performs configuration of:
3861 * - Channels ordering into each rank of scan sequence:
3862 * whatever channel can be placed into whatever rank.
3863 * @note On this STM32 serie, ADC group regular sequencer is
3864 * fully configurable: sequencer length and each rank
3865 * affectation to a channel are configurable.
3866 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3867 * @note Depending on devices and packages, some channels may not be available.
3868 * Refer to device datasheet for channels availability.
3869 * @note On this STM32 serie, to measure internal channels (VrefInt,
3870 * TempSensor, ...), measurement paths to internal channels must be
3871 * enabled separately.
3872 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
3873 * @note On this STM32 serie, setting of this feature is conditioned to
3874 * ADC state:
3875 * ADC must be disabled or enabled without conversion on going
3876 * on group regular.
3877 * @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
3878 * SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
3879 * SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
3880 * SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
3881 * SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
3882 * SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
3883 * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
3884 * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
3885 * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
3886 * SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
3887 * SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
3888 * SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
3889 * SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
3890 * SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
3891 * SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
3892 * SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
3893 * @param ADCx ADC instance
3894 * @param Rank This parameter can be one of the following values:
3895 * @arg @ref LL_ADC_REG_RANK_1
3896 * @arg @ref LL_ADC_REG_RANK_2
3897 * @arg @ref LL_ADC_REG_RANK_3
3898 * @arg @ref LL_ADC_REG_RANK_4
3899 * @arg @ref LL_ADC_REG_RANK_5
3900 * @arg @ref LL_ADC_REG_RANK_6
3901 * @arg @ref LL_ADC_REG_RANK_7
3902 * @arg @ref LL_ADC_REG_RANK_8
3903 * @arg @ref LL_ADC_REG_RANK_9
3904 * @arg @ref LL_ADC_REG_RANK_10
3905 * @arg @ref LL_ADC_REG_RANK_11
3906 * @arg @ref LL_ADC_REG_RANK_12
3907 * @arg @ref LL_ADC_REG_RANK_13
3908 * @arg @ref LL_ADC_REG_RANK_14
3909 * @arg @ref LL_ADC_REG_RANK_15
3910 * @arg @ref LL_ADC_REG_RANK_16
3911 * @param Channel This parameter can be one of the following values:
3912 * @arg @ref LL_ADC_CHANNEL_0
3913 * @arg @ref LL_ADC_CHANNEL_1 (8)
3914 * @arg @ref LL_ADC_CHANNEL_2 (8)
3915 * @arg @ref LL_ADC_CHANNEL_3 (8)
3916 * @arg @ref LL_ADC_CHANNEL_4 (8)
3917 * @arg @ref LL_ADC_CHANNEL_5 (8)
3918 * @arg @ref LL_ADC_CHANNEL_6
3919 * @arg @ref LL_ADC_CHANNEL_7
3920 * @arg @ref LL_ADC_CHANNEL_8
3921 * @arg @ref LL_ADC_CHANNEL_9
3922 * @arg @ref LL_ADC_CHANNEL_10
3923 * @arg @ref LL_ADC_CHANNEL_11
3924 * @arg @ref LL_ADC_CHANNEL_12
3925 * @arg @ref LL_ADC_CHANNEL_13
3926 * @arg @ref LL_ADC_CHANNEL_14
3927 * @arg @ref LL_ADC_CHANNEL_15
3928 * @arg @ref LL_ADC_CHANNEL_16
3929 * @arg @ref LL_ADC_CHANNEL_17
3930 * @arg @ref LL_ADC_CHANNEL_18
3931 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
3932 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
3933 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
3934 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
3935 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
3936 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
3937 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
3938 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
3939 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
3940 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
3941 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
3942 *
3943 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
3944 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
3945 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
3946 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
3947 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
3948 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
3949 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
3950 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
3951 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
3952 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
3953 * @retval None
3954 */
3955 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3956 {
3957 /* Set bits with content of parameter "Channel" with bits position */
3958 /* in register and register position depending on parameter "Rank". */
3959 /* Parameters "Rank" and "Channel" are used with masks because containing */
3960 /* other bits reserved for other purpose. */
3961 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
3962
3963 MODIFY_REG(*preg,
3964 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
3965 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
3966 }
3967
3968 /**
3969 * @brief Get ADC group regular sequence: channel on the selected
3970 * scan sequence rank.
3971 * @note On this STM32 serie, ADC group regular sequencer is
3972 * fully configurable: sequencer length and each rank
3973 * affectation to a channel are configurable.
3974 * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
3975 * @note Depending on devices and packages, some channels may not be available.
3976 * Refer to device datasheet for channels availability.
3977 * @note Usage of the returned channel number:
3978 * - To reinject this channel into another function LL_ADC_xxx:
3979 * the returned channel number is only partly formatted on definition
3980 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3981 * with parts of literals LL_ADC_CHANNEL_x or using
3982 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3983 * Then the selected literal LL_ADC_CHANNEL_x can be used
3984 * as parameter for another function.
3985 * - To get the channel number in decimal format:
3986 * process the returned value with the helper macro
3987 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3988 * @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
3989 * SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
3990 * SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
3991 * SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
3992 * SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
3993 * SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
3994 * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
3995 * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
3996 * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
3997 * SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
3998 * SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
3999 * SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
4000 * SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
4001 * SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
4002 * SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
4003 * SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
4004 * @param ADCx ADC instance
4005 * @param Rank This parameter can be one of the following values:
4006 * @arg @ref LL_ADC_REG_RANK_1
4007 * @arg @ref LL_ADC_REG_RANK_2
4008 * @arg @ref LL_ADC_REG_RANK_3
4009 * @arg @ref LL_ADC_REG_RANK_4
4010 * @arg @ref LL_ADC_REG_RANK_5
4011 * @arg @ref LL_ADC_REG_RANK_6
4012 * @arg @ref LL_ADC_REG_RANK_7
4013 * @arg @ref LL_ADC_REG_RANK_8
4014 * @arg @ref LL_ADC_REG_RANK_9
4015 * @arg @ref LL_ADC_REG_RANK_10
4016 * @arg @ref LL_ADC_REG_RANK_11
4017 * @arg @ref LL_ADC_REG_RANK_12
4018 * @arg @ref LL_ADC_REG_RANK_13
4019 * @arg @ref LL_ADC_REG_RANK_14
4020 * @arg @ref LL_ADC_REG_RANK_15
4021 * @arg @ref LL_ADC_REG_RANK_16
4022 * @retval Returned value can be one of the following values:
4023 * @arg @ref LL_ADC_CHANNEL_0
4024 * @arg @ref LL_ADC_CHANNEL_1 (8)
4025 * @arg @ref LL_ADC_CHANNEL_2 (8)
4026 * @arg @ref LL_ADC_CHANNEL_3 (8)
4027 * @arg @ref LL_ADC_CHANNEL_4 (8)
4028 * @arg @ref LL_ADC_CHANNEL_5 (8)
4029 * @arg @ref LL_ADC_CHANNEL_6
4030 * @arg @ref LL_ADC_CHANNEL_7
4031 * @arg @ref LL_ADC_CHANNEL_8
4032 * @arg @ref LL_ADC_CHANNEL_9
4033 * @arg @ref LL_ADC_CHANNEL_10
4034 * @arg @ref LL_ADC_CHANNEL_11
4035 * @arg @ref LL_ADC_CHANNEL_12
4036 * @arg @ref LL_ADC_CHANNEL_13
4037 * @arg @ref LL_ADC_CHANNEL_14
4038 * @arg @ref LL_ADC_CHANNEL_15
4039 * @arg @ref LL_ADC_CHANNEL_16
4040 * @arg @ref LL_ADC_CHANNEL_17
4041 * @arg @ref LL_ADC_CHANNEL_18
4042 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4043 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4044 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4045 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4046 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4047 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4048 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4049 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4050 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4051 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4052 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4053 *
4054 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4055 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4056 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4057 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4058 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4059 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4060 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4061 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4062 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4063 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4064 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
4065 * comparison with internal channel parameter to be done
4066 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4067 */
4068 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4069 {
4070 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
4071
4072 return (uint32_t)((READ_BIT(*preg,
4073 ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
4074 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4075 );
4076 }
4077
4078 /**
4079 * @brief Set ADC continuous conversion mode on ADC group regular.
4080 * @note Description of ADC continuous conversion mode:
4081 * - single mode: one conversion per trigger
4082 * - continuous mode: after the first trigger, following
4083 * conversions launched successively automatically.
4084 * @note It is not possible to enable both ADC group regular
4085 * continuous mode and sequencer discontinuous mode.
4086 * @note On this STM32 serie, setting of this feature is conditioned to
4087 * ADC state:
4088 * ADC must be disabled or enabled without conversion on going
4089 * on group regular.
4090 * @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
4091 * @param ADCx ADC instance
4092 * @param Continuous This parameter can be one of the following values:
4093 * @arg @ref LL_ADC_REG_CONV_SINGLE
4094 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4095 * @retval None
4096 */
4097 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
4098 {
4099 MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
4100 }
4101
4102 /**
4103 * @brief Get ADC continuous conversion mode on ADC group regular.
4104 * @note Description of ADC continuous conversion mode:
4105 * - single mode: one conversion per trigger
4106 * - continuous mode: after the first trigger, following
4107 * conversions launched successively automatically.
4108 * @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
4109 * @param ADCx ADC instance
4110 * @retval Returned value can be one of the following values:
4111 * @arg @ref LL_ADC_REG_CONV_SINGLE
4112 * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
4113 */
4114 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
4115 {
4116 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
4117 }
4118
4119 /**
4120 * @brief Set ADC group regular conversion data transfer: no transfer or
4121 * transfer by DMA, and DMA requests mode.
4122 * @note If transfer by DMA selected, specifies the DMA requests
4123 * mode:
4124 * - Limited mode (One shot mode): DMA transfer requests are stopped
4125 * when number of DMA data transfers (number of
4126 * ADC conversions) is reached.
4127 * This ADC mode is intended to be used with DMA mode non-circular.
4128 * - Unlimited mode: DMA transfer requests are unlimited,
4129 * whatever number of DMA data transfers (number of
4130 * ADC conversions).
4131 * This ADC mode is intended to be used with DMA mode circular.
4132 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4133 * mode non-circular:
4134 * when DMA transfers size will be reached, DMA will stop transfers of
4135 * ADC conversions data ADC will raise an overrun error
4136 * (overrun flag and interruption if enabled).
4137 * @note For devices with several ADC instances: ADC multimode DMA
4138 * settings are available using function @ref LL_ADC_SetMultiDMATransfer().
4139 * @note To configure DMA source address (peripheral address),
4140 * use function @ref LL_ADC_DMA_GetRegAddr().
4141 * @note On this STM32 serie, setting of this feature is conditioned to
4142 * ADC state:
4143 * ADC must be disabled or enabled without conversion on going
4144 * on either groups regular or injected.
4145 * @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
4146 * CFGR DMACFG LL_ADC_REG_SetDMATransfer
4147 * @param ADCx ADC instance
4148 * @param DMATransfer This parameter can be one of the following values:
4149 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4150 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4151 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4152 * @retval None
4153 */
4154 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
4155 {
4156 MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
4157 }
4158
4159 /**
4160 * @brief Get ADC group regular conversion data transfer: no transfer or
4161 * transfer by DMA, and DMA requests mode.
4162 * @note If transfer by DMA selected, specifies the DMA requests
4163 * mode:
4164 * - Limited mode (One shot mode): DMA transfer requests are stopped
4165 * when number of DMA data transfers (number of
4166 * ADC conversions) is reached.
4167 * This ADC mode is intended to be used with DMA mode non-circular.
4168 * - Unlimited mode: DMA transfer requests are unlimited,
4169 * whatever number of DMA data transfers (number of
4170 * ADC conversions).
4171 * This ADC mode is intended to be used with DMA mode circular.
4172 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
4173 * mode non-circular:
4174 * when DMA transfers size will be reached, DMA will stop transfers of
4175 * ADC conversions data ADC will raise an overrun error
4176 * (overrun flag and interruption if enabled).
4177 * @note For devices with several ADC instances: ADC multimode DMA
4178 * settings are available using function @ref LL_ADC_GetMultiDMATransfer().
4179 * @note To configure DMA source address (peripheral address),
4180 * use function @ref LL_ADC_DMA_GetRegAddr().
4181 * @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
4182 * CFGR DMACFG LL_ADC_REG_GetDMATransfer
4183 * @param ADCx ADC instance
4184 * @retval Returned value can be one of the following values:
4185 * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
4186 * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
4187 * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
4188 */
4189 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
4190 {
4191 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
4192 }
4193
4194 /**
4195 * @brief Set ADC group regular behavior in case of overrun:
4196 * data preserved or overwritten.
4197 * @note Compatibility with devices without feature overrun:
4198 * other devices without this feature have a behavior
4199 * equivalent to data overwritten.
4200 * The default setting of overrun is data preserved.
4201 * Therefore, for compatibility with all devices, parameter
4202 * overrun should be set to data overwritten.
4203 * @note On this STM32 serie, setting of this feature is conditioned to
4204 * ADC state:
4205 * ADC must be disabled or enabled without conversion on going
4206 * on group regular.
4207 * @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
4208 * @param ADCx ADC instance
4209 * @param Overrun This parameter can be one of the following values:
4210 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4211 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4212 * @retval None
4213 */
4214 __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
4215 {
4216 MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
4217 }
4218
4219 /**
4220 * @brief Get ADC group regular behavior in case of overrun:
4221 * data preserved or overwritten.
4222 * @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
4223 * @param ADCx ADC instance
4224 * @retval Returned value can be one of the following values:
4225 * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
4226 * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
4227 */
4228 __STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
4229 {
4230 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
4231 }
4232
4233 /**
4234 * @}
4235 */
4236
4237 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
4238 * @{
4239 */
4240
4241 /**
4242 * @brief Set ADC group injected conversion trigger source:
4243 * internal (SW start) or from external peripheral (timer event,
4244 * external interrupt line).
4245 * @note On this STM32 serie, setting trigger source to external trigger
4246 * also set trigger polarity to rising edge
4247 * (default setting for compatibility with some ADC on other
4248 * STM32 families having this setting set by HW default value).
4249 * In case of need to modify trigger edge, use
4250 * function @ref LL_ADC_INJ_SetTriggerEdge().
4251 * @note Availability of parameters of trigger sources from timer
4252 * depends on timers availability on the selected device.
4253 * @note On this STM32 serie, setting of this feature is conditioned to
4254 * ADC state:
4255 * ADC must not be disabled. Can be enabled with or without conversion
4256 * on going on either groups regular or injected.
4257 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
4258 * JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
4259 * @param ADCx ADC instance
4260 * @param TriggerSource This parameter can be one of the following values:
4261 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4262 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4263 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4264 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4265 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4266 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4267 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4268 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4269 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4270 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4271 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4272 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4273 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4274 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4275 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4276 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4277 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4278 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4279 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4280 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4281 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4282 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4283 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4284 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4285 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4286 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4287 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4288 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4289 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4290 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4291 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4292 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4293 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4294 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4295 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4296 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4297 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4298 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4299 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4300 *
4301 * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n
4302 * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4303 * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4304 * @retval None
4305 */
4306 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
4307 {
4308 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
4309 }
4310
4311 /**
4312 * @brief Get ADC group injected conversion trigger source:
4313 * internal (SW start) or from external peripheral (timer event,
4314 * external interrupt line).
4315 * @note To determine whether group injected trigger source is
4316 * internal (SW start) or external, without detail
4317 * of which peripheral is selected as external trigger,
4318 * (equivalent to
4319 * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
4320 * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
4321 * @note Availability of parameters of trigger sources from timer
4322 * depends on timers availability on the selected device.
4323 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
4324 * JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
4325 * @param ADCx ADC instance
4326 * @retval Returned value can be one of the following values:
4327 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4328 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4329 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4330 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4331 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4332 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4333 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4334 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4335 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4336 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4337 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4338 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4339 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4340 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4341 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4342 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4343 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4344 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4345 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4346 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4347 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4348 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4349 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4350 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4351 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4352 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4353 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4354 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4355 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4356 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4357 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4358 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4359 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4360 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4361 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4362 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4363 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4364 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4365 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4366 *
4367 * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n
4368 * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4369 * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4370 */
4371 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
4372 {
4373 register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
4374
4375 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
4376 /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
4377 register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
4378
4379 /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
4380 /* to match with triggers literals definition. */
4381 return ((TriggerSource
4382 & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
4383 | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
4384 );
4385 }
4386
4387 /**
4388 * @brief Get ADC group injected conversion trigger source internal (SW start)
4389 or external
4390 * @note In case of group injected trigger source set to external trigger,
4391 * to determine which peripheral is selected as external trigger,
4392 * use function @ref LL_ADC_INJ_GetTriggerSource.
4393 * @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
4394 * @param ADCx ADC instance
4395 * @retval Value "0" if trigger source external trigger
4396 * Value "1" if trigger source SW start.
4397 */
4398 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
4399 {
4400 return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
4401 }
4402
4403 /**
4404 * @brief Set ADC group injected conversion trigger polarity.
4405 * Applicable only for trigger source set to external trigger.
4406 * @note On this STM32 serie, setting of this feature is conditioned to
4407 * ADC state:
4408 * ADC must not be disabled. Can be enabled with or without conversion
4409 * on going on either groups regular or injected.
4410 * @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
4411 * @param ADCx ADC instance
4412 * @param ExternalTriggerEdge This parameter can be one of the following values:
4413 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4414 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4415 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4416 * @retval None
4417 */
4418 __STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4419 {
4420 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
4421 }
4422
4423 /**
4424 * @brief Get ADC group injected conversion trigger polarity.
4425 * Applicable only for trigger source set to external trigger.
4426 * @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
4427 * @param ADCx ADC instance
4428 * @retval Returned value can be one of the following values:
4429 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4430 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4431 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4432 */
4433 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
4434 {
4435 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
4436 }
4437
4438 /**
4439 * @brief Set ADC group injected sequencer length and scan direction.
4440 * @note This function performs configuration of:
4441 * - Sequence length: Number of ranks in the scan sequence.
4442 * - Sequence direction: Unless specified in parameters, sequencer
4443 * scan direction is forward (from rank 1 to rank n).
4444 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4445 * ADC conversion on only 1 channel.
4446 * @note On this STM32 serie, setting of this feature is conditioned to
4447 * ADC state:
4448 * ADC must not be disabled. Can be enabled with or without conversion
4449 * on going on either groups regular or injected.
4450 * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
4451 * @param ADCx ADC instance
4452 * @param SequencerNbRanks This parameter can be one of the following values:
4453 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4454 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4455 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4456 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4457 * @retval None
4458 */
4459 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
4460 {
4461 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
4462 }
4463
4464 /**
4465 * @brief Get ADC group injected sequencer length and scan direction.
4466 * @note This function retrieves:
4467 * - Sequence length: Number of ranks in the scan sequence.
4468 * - Sequence direction: Unless specified in parameters, sequencer
4469 * scan direction is forward (from rank 1 to rank n).
4470 * @note Sequencer disabled is equivalent to sequencer of 1 rank:
4471 * ADC conversion on only 1 channel.
4472 * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
4473 * @param ADCx ADC instance
4474 * @retval Returned value can be one of the following values:
4475 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4476 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4477 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4478 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4479 */
4480 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
4481 {
4482 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
4483 }
4484
4485 /**
4486 * @brief Set ADC group injected sequencer discontinuous mode:
4487 * sequence subdivided and scan conversions interrupted every selected
4488 * number of ranks.
4489 * @note It is not possible to enable both ADC group injected
4490 * auto-injected mode and sequencer discontinuous mode.
4491 * @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
4492 * @param ADCx ADC instance
4493 * @param SeqDiscont This parameter can be one of the following values:
4494 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4495 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4496 * @retval None
4497 */
4498 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
4499 {
4500 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
4501 }
4502
4503 /**
4504 * @brief Get ADC group injected sequencer discontinuous mode:
4505 * sequence subdivided and scan conversions interrupted every selected
4506 * number of ranks.
4507 * @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
4508 * @param ADCx ADC instance
4509 * @retval Returned value can be one of the following values:
4510 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
4511 * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
4512 */
4513 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
4514 {
4515 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
4516 }
4517
4518 /**
4519 * @brief Set ADC group injected sequence: channel on the selected
4520 * sequence rank.
4521 * @note Depending on devices and packages, some channels may not be available.
4522 * Refer to device datasheet for channels availability.
4523 * @note On this STM32 serie, to measure internal channels (VrefInt,
4524 * TempSensor, ...), measurement paths to internal channels must be
4525 * enabled separately.
4526 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4527 * @note On STM32G4, some fast channels are available: fast analog inputs
4528 * coming from GPIO pads (ADC_IN1..5).
4529 * @note On this STM32 serie, setting of this feature is conditioned to
4530 * ADC state:
4531 * ADC must not be disabled. Can be enabled with or without conversion
4532 * on going on either groups regular or injected.
4533 * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
4534 * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
4535 * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
4536 * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
4537 * @param ADCx ADC instance
4538 * @param Rank This parameter can be one of the following values:
4539 * @arg @ref LL_ADC_INJ_RANK_1
4540 * @arg @ref LL_ADC_INJ_RANK_2
4541 * @arg @ref LL_ADC_INJ_RANK_3
4542 * @arg @ref LL_ADC_INJ_RANK_4
4543 * @param Channel This parameter can be one of the following values:
4544 * @arg @ref LL_ADC_CHANNEL_0
4545 * @arg @ref LL_ADC_CHANNEL_1 (8)
4546 * @arg @ref LL_ADC_CHANNEL_2 (8)
4547 * @arg @ref LL_ADC_CHANNEL_3 (8)
4548 * @arg @ref LL_ADC_CHANNEL_4 (8)
4549 * @arg @ref LL_ADC_CHANNEL_5 (8)
4550 * @arg @ref LL_ADC_CHANNEL_6
4551 * @arg @ref LL_ADC_CHANNEL_7
4552 * @arg @ref LL_ADC_CHANNEL_8
4553 * @arg @ref LL_ADC_CHANNEL_9
4554 * @arg @ref LL_ADC_CHANNEL_10
4555 * @arg @ref LL_ADC_CHANNEL_11
4556 * @arg @ref LL_ADC_CHANNEL_12
4557 * @arg @ref LL_ADC_CHANNEL_13
4558 * @arg @ref LL_ADC_CHANNEL_14
4559 * @arg @ref LL_ADC_CHANNEL_15
4560 * @arg @ref LL_ADC_CHANNEL_16
4561 * @arg @ref LL_ADC_CHANNEL_17
4562 * @arg @ref LL_ADC_CHANNEL_18
4563 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4564 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4565 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4566 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4567 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4568 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4569 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4570 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4571 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4572 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4573 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4574 *
4575 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4576 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4577 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4578 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4579 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4580 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4581 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4582 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4583 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4584 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4585 * @retval None
4586 */
4587 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
4588 {
4589 /* Set bits with content of parameter "Channel" with bits position */
4590 /* in register depending on parameter "Rank". */
4591 /* Parameters "Rank" and "Channel" are used with masks because containing */
4592 /* other bits reserved for other purpose. */
4593 MODIFY_REG(ADCx->JSQR,
4594 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
4595 ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
4596 }
4597
4598 /**
4599 * @brief Get ADC group injected sequence: channel on the selected
4600 * sequence rank.
4601 * @note Depending on devices and packages, some channels may not be available.
4602 * Refer to device datasheet for channels availability.
4603 * @note Usage of the returned channel number:
4604 * - To reinject this channel into another function LL_ADC_xxx:
4605 * the returned channel number is only partly formatted on definition
4606 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
4607 * with parts of literals LL_ADC_CHANNEL_x or using
4608 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4609 * Then the selected literal LL_ADC_CHANNEL_x can be used
4610 * as parameter for another function.
4611 * - To get the channel number in decimal format:
4612 * process the returned value with the helper macro
4613 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
4614 * @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
4615 * JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
4616 * JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
4617 * JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
4618 * @param ADCx ADC instance
4619 * @param Rank This parameter can be one of the following values:
4620 * @arg @ref LL_ADC_INJ_RANK_1
4621 * @arg @ref LL_ADC_INJ_RANK_2
4622 * @arg @ref LL_ADC_INJ_RANK_3
4623 * @arg @ref LL_ADC_INJ_RANK_4
4624 * @retval Returned value can be one of the following values:
4625 * @arg @ref LL_ADC_CHANNEL_0
4626 * @arg @ref LL_ADC_CHANNEL_1 (8)
4627 * @arg @ref LL_ADC_CHANNEL_2 (8)
4628 * @arg @ref LL_ADC_CHANNEL_3 (8)
4629 * @arg @ref LL_ADC_CHANNEL_4 (8)
4630 * @arg @ref LL_ADC_CHANNEL_5 (8)
4631 * @arg @ref LL_ADC_CHANNEL_6
4632 * @arg @ref LL_ADC_CHANNEL_7
4633 * @arg @ref LL_ADC_CHANNEL_8
4634 * @arg @ref LL_ADC_CHANNEL_9
4635 * @arg @ref LL_ADC_CHANNEL_10
4636 * @arg @ref LL_ADC_CHANNEL_11
4637 * @arg @ref LL_ADC_CHANNEL_12
4638 * @arg @ref LL_ADC_CHANNEL_13
4639 * @arg @ref LL_ADC_CHANNEL_14
4640 * @arg @ref LL_ADC_CHANNEL_15
4641 * @arg @ref LL_ADC_CHANNEL_16
4642 * @arg @ref LL_ADC_CHANNEL_17
4643 * @arg @ref LL_ADC_CHANNEL_18
4644 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4645 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4646 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4647 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4648 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4649 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4650 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4651 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4652 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4653 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4654 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4655 *
4656 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4657 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4658 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4659 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4660 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4661 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4662 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4663 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4664 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4665 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4666 * (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
4667 * comparison with internal channel parameter to be done
4668 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
4669 */
4670 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
4671 {
4672 return (uint32_t)((READ_BIT(ADCx->JSQR,
4673 (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
4674 >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
4675 );
4676 }
4677
4678 /**
4679 * @brief Set ADC group injected conversion trigger:
4680 * independent or from ADC group regular.
4681 * @note This mode can be used to extend number of data registers
4682 * updated after one ADC conversion trigger and with data
4683 * permanently kept (not erased by successive conversions of scan of
4684 * ADC sequencer ranks), up to 5 data registers:
4685 * 1 data register on ADC group regular, 4 data registers
4686 * on ADC group injected.
4687 * @note If ADC group injected injected trigger source is set to an
4688 * external trigger, this feature must be must be set to
4689 * independent trigger.
4690 * ADC group injected automatic trigger is compliant only with
4691 * group injected trigger source set to SW start, without any
4692 * further action on ADC group injected conversion start or stop:
4693 * in this case, ADC group injected is controlled only
4694 * from ADC group regular.
4695 * @note It is not possible to enable both ADC group injected
4696 * auto-injected mode and sequencer discontinuous mode.
4697 * @note On this STM32 serie, setting of this feature is conditioned to
4698 * ADC state:
4699 * ADC must be disabled or enabled without conversion on going
4700 * on either groups regular or injected.
4701 * @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
4702 * @param ADCx ADC instance
4703 * @param TrigAuto This parameter can be one of the following values:
4704 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4705 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4706 * @retval None
4707 */
4708 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
4709 {
4710 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
4711 }
4712
4713 /**
4714 * @brief Get ADC group injected conversion trigger:
4715 * independent or from ADC group regular.
4716 * @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
4717 * @param ADCx ADC instance
4718 * @retval Returned value can be one of the following values:
4719 * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
4720 * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
4721 */
4722 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
4723 {
4724 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
4725 }
4726
4727 /**
4728 * @brief Set ADC group injected contexts queue mode.
4729 * @note A context is a setting of group injected sequencer:
4730 * - group injected trigger
4731 * - sequencer length
4732 * - sequencer ranks
4733 * If contexts queue is disabled:
4734 * - only 1 sequence can be configured
4735 * and is active perpetually.
4736 * If contexts queue is enabled:
4737 * - up to 2 contexts can be queued
4738 * and are checked in and out as a FIFO stack (first-in, first-out).
4739 * - If a new context is set when queues is full, error is triggered
4740 * by interruption "Injected Queue Overflow".
4741 * - Two behaviors are possible when all contexts have been processed:
4742 * the contexts queue can maintain the last context active perpetually
4743 * or can be empty and injected group triggers are disabled.
4744 * - Triggers can be only external (not internal SW start)
4745 * - Caution: The sequence must be fully configured in one time
4746 * (one write of register JSQR makes a check-in of a new context
4747 * into the queue).
4748 * Therefore functions to set separately injected trigger and
4749 * sequencer channels cannot be used, register JSQR must be set
4750 * using function @ref LL_ADC_INJ_ConfigQueueContext().
4751 * @note This parameter can be modified only when no conversion is on going
4752 * on either groups regular or injected.
4753 * @note A modification of the context mode (bit JQDIS) causes the contexts
4754 * queue to be flushed and the register JSQR is cleared.
4755 * @note On this STM32 serie, setting of this feature is conditioned to
4756 * ADC state:
4757 * ADC must be disabled or enabled without conversion on going
4758 * on either groups regular or injected.
4759 * @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
4760 * CFGR JQDIS LL_ADC_INJ_SetQueueMode
4761 * @param ADCx ADC instance
4762 * @param QueueMode This parameter can be one of the following values:
4763 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4764 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4765 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4766 * @retval None
4767 */
4768 __STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
4769 {
4770 MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
4771 }
4772
4773 /**
4774 * @brief Get ADC group injected context queue mode.
4775 * @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
4776 * CFGR JQDIS LL_ADC_INJ_GetQueueMode
4777 * @param ADCx ADC instance
4778 * @retval Returned value can be one of the following values:
4779 * @arg @ref LL_ADC_INJ_QUEUE_DISABLE
4780 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
4781 * @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
4782 */
4783 __STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
4784 {
4785 return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
4786 }
4787
4788 /**
4789 * @brief Set one context on ADC group injected that will be checked in
4790 * contexts queue.
4791 * @note A context is a setting of group injected sequencer:
4792 * - group injected trigger
4793 * - sequencer length
4794 * - sequencer ranks
4795 * This function is intended to be used when contexts queue is enabled,
4796 * because the sequence must be fully configured in one time
4797 * (functions to set separately injected trigger and sequencer channels
4798 * cannot be used):
4799 * Refer to function @ref LL_ADC_INJ_SetQueueMode().
4800 * @note In the contexts queue, only the active context can be read.
4801 * The parameters of this function can be read using functions:
4802 * @arg @ref LL_ADC_INJ_GetTriggerSource()
4803 * @arg @ref LL_ADC_INJ_GetTriggerEdge()
4804 * @arg @ref LL_ADC_INJ_GetSequencerRanks()
4805 * @note On this STM32 serie, to measure internal channels (VrefInt,
4806 * TempSensor, ...), measurement paths to internal channels must be
4807 * enabled separately.
4808 * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
4809 * @note On STM32G4, some fast channels are available: fast analog inputs
4810 * coming from GPIO pads (ADC_IN1..5).
4811 * @note On this STM32 serie, setting of this feature is conditioned to
4812 * ADC state:
4813 * ADC must not be disabled. Can be enabled with or without conversion
4814 * on going on either groups regular or injected.
4815 * @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
4816 * JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
4817 * JSQR JL LL_ADC_INJ_ConfigQueueContext\n
4818 * JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
4819 * JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
4820 * JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
4821 * JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
4822 * @param ADCx ADC instance
4823 * @param TriggerSource This parameter can be one of the following values:
4824 * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
4825 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
4826 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
4827 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
4828 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
4829 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
4830 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
4831 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
4832 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
4833 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
4834 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
4835 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
4836 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
4837 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
4838 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
4839 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
4840 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
4841 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
4842 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
4843 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
4844 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
4845 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
4846 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
4847 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
4848 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
4849 * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
4850 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
4851 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
4852 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
4853 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
4854 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
4855 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
4856 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
4857 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
4858 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
4859 * @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
4860 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
4861 * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
4862 * @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
4863 *
4864 * (1) On STM32G4 serie, parameter not available on all ADC instances: ADC1, ADC2.\n
4865 * (2) On STM32G4 serie, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
4866 * On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4867 * @param ExternalTriggerEdge This parameter can be one of the following values:
4868 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
4869 * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
4870 * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
4871 *
4872 * Note: This parameter is discarded in case of SW start:
4873 * parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
4874 * @param SequencerNbRanks This parameter can be one of the following values:
4875 * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
4876 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
4877 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
4878 * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
4879 * @param Rank1_Channel This parameter can be one of the following values:
4880 * @arg @ref LL_ADC_CHANNEL_0
4881 * @arg @ref LL_ADC_CHANNEL_1 (8)
4882 * @arg @ref LL_ADC_CHANNEL_2 (8)
4883 * @arg @ref LL_ADC_CHANNEL_3 (8)
4884 * @arg @ref LL_ADC_CHANNEL_4 (8)
4885 * @arg @ref LL_ADC_CHANNEL_5 (8)
4886 * @arg @ref LL_ADC_CHANNEL_6
4887 * @arg @ref LL_ADC_CHANNEL_7
4888 * @arg @ref LL_ADC_CHANNEL_8
4889 * @arg @ref LL_ADC_CHANNEL_9
4890 * @arg @ref LL_ADC_CHANNEL_10
4891 * @arg @ref LL_ADC_CHANNEL_11
4892 * @arg @ref LL_ADC_CHANNEL_12
4893 * @arg @ref LL_ADC_CHANNEL_13
4894 * @arg @ref LL_ADC_CHANNEL_14
4895 * @arg @ref LL_ADC_CHANNEL_15
4896 * @arg @ref LL_ADC_CHANNEL_16
4897 * @arg @ref LL_ADC_CHANNEL_17
4898 * @arg @ref LL_ADC_CHANNEL_18
4899 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4900 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4901 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4902 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4903 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4904 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4905 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4906 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4907 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4908 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4909 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4910 *
4911 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4912 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4913 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4914 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4915 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4916 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4917 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4918 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4919 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4920 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4921 * @param Rank2_Channel This parameter can be one of the following values:
4922 * @arg @ref LL_ADC_CHANNEL_0
4923 * @arg @ref LL_ADC_CHANNEL_1 (8)
4924 * @arg @ref LL_ADC_CHANNEL_2 (8)
4925 * @arg @ref LL_ADC_CHANNEL_3 (8)
4926 * @arg @ref LL_ADC_CHANNEL_4 (8)
4927 * @arg @ref LL_ADC_CHANNEL_5 (8)
4928 * @arg @ref LL_ADC_CHANNEL_6
4929 * @arg @ref LL_ADC_CHANNEL_7
4930 * @arg @ref LL_ADC_CHANNEL_8
4931 * @arg @ref LL_ADC_CHANNEL_9
4932 * @arg @ref LL_ADC_CHANNEL_10
4933 * @arg @ref LL_ADC_CHANNEL_11
4934 * @arg @ref LL_ADC_CHANNEL_12
4935 * @arg @ref LL_ADC_CHANNEL_13
4936 * @arg @ref LL_ADC_CHANNEL_14
4937 * @arg @ref LL_ADC_CHANNEL_15
4938 * @arg @ref LL_ADC_CHANNEL_16
4939 * @arg @ref LL_ADC_CHANNEL_17
4940 * @arg @ref LL_ADC_CHANNEL_18
4941 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4942 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4943 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4944 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4945 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4946 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4947 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4948 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4949 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4950 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4951 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4952 *
4953 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4954 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4955 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4956 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4957 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
4958 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
4959 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
4960 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
4961 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
4962 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
4963 * @param Rank3_Channel This parameter can be one of the following values:
4964 * @arg @ref LL_ADC_CHANNEL_0
4965 * @arg @ref LL_ADC_CHANNEL_1 (8)
4966 * @arg @ref LL_ADC_CHANNEL_2 (8)
4967 * @arg @ref LL_ADC_CHANNEL_3 (8)
4968 * @arg @ref LL_ADC_CHANNEL_4 (8)
4969 * @arg @ref LL_ADC_CHANNEL_5 (8)
4970 * @arg @ref LL_ADC_CHANNEL_6
4971 * @arg @ref LL_ADC_CHANNEL_7
4972 * @arg @ref LL_ADC_CHANNEL_8
4973 * @arg @ref LL_ADC_CHANNEL_9
4974 * @arg @ref LL_ADC_CHANNEL_10
4975 * @arg @ref LL_ADC_CHANNEL_11
4976 * @arg @ref LL_ADC_CHANNEL_12
4977 * @arg @ref LL_ADC_CHANNEL_13
4978 * @arg @ref LL_ADC_CHANNEL_14
4979 * @arg @ref LL_ADC_CHANNEL_15
4980 * @arg @ref LL_ADC_CHANNEL_16
4981 * @arg @ref LL_ADC_CHANNEL_17
4982 * @arg @ref LL_ADC_CHANNEL_18
4983 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
4984 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
4985 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
4986 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
4987 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
4988 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
4989 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
4990 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
4991 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
4992 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
4993 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
4994 *
4995 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
4996 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
4997 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
4998 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
4999 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5000 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5001 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5002 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
5003 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5004 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5005 * @param Rank4_Channel This parameter can be one of the following values:
5006 * @arg @ref LL_ADC_CHANNEL_0
5007 * @arg @ref LL_ADC_CHANNEL_1 (8)
5008 * @arg @ref LL_ADC_CHANNEL_2 (8)
5009 * @arg @ref LL_ADC_CHANNEL_3 (8)
5010 * @arg @ref LL_ADC_CHANNEL_4 (8)
5011 * @arg @ref LL_ADC_CHANNEL_5 (8)
5012 * @arg @ref LL_ADC_CHANNEL_6
5013 * @arg @ref LL_ADC_CHANNEL_7
5014 * @arg @ref LL_ADC_CHANNEL_8
5015 * @arg @ref LL_ADC_CHANNEL_9
5016 * @arg @ref LL_ADC_CHANNEL_10
5017 * @arg @ref LL_ADC_CHANNEL_11
5018 * @arg @ref LL_ADC_CHANNEL_12
5019 * @arg @ref LL_ADC_CHANNEL_13
5020 * @arg @ref LL_ADC_CHANNEL_14
5021 * @arg @ref LL_ADC_CHANNEL_15
5022 * @arg @ref LL_ADC_CHANNEL_16
5023 * @arg @ref LL_ADC_CHANNEL_17
5024 * @arg @ref LL_ADC_CHANNEL_18
5025 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5026 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5027 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5028 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5029 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5030 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5031 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5032 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5033 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5034 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5035 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5036 *
5037 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5038 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5039 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5040 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5041 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5042 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5043 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5044 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
5045 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5046 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5047 * @retval None
5048 */
5049 __STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
5050 uint32_t TriggerSource,
5051 uint32_t ExternalTriggerEdge,
5052 uint32_t SequencerNbRanks,
5053 uint32_t Rank1_Channel,
5054 uint32_t Rank2_Channel,
5055 uint32_t Rank3_Channel,
5056 uint32_t Rank4_Channel)
5057 {
5058 /* Set bits with content of parameter "Rankx_Channel" with bits position */
5059 /* in register depending on literal "LL_ADC_INJ_RANK_x". */
5060 /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
5061 /* because containing other bits reserved for other purpose. */
5062 /* If parameter "TriggerSource" is set to SW start, then parameter */
5063 /* "ExternalTriggerEdge" is discarded. */
5064 register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
5065 MODIFY_REG(ADCx->JSQR,
5066 ADC_JSQR_JEXTSEL |
5067 ADC_JSQR_JEXTEN |
5068 ADC_JSQR_JSQ4 |
5069 ADC_JSQR_JSQ3 |
5070 ADC_JSQR_JSQ2 |
5071 ADC_JSQR_JSQ1 |
5072 ADC_JSQR_JL,
5073 TriggerSource |
5074 (ExternalTriggerEdge * (is_trigger_not_sw)) |
5075 (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5076 (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5077 (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5078 (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
5079 SequencerNbRanks
5080 );
5081 }
5082
5083 /**
5084 * @}
5085 */
5086
5087 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
5088 * @{
5089 */
5090
5091 /**
5092 * @brief Set sampling time of the selected ADC channel
5093 * Unit: ADC clock cycles.
5094 * @note On this device, sampling time is on channel scope: independently
5095 * of channel mapped on ADC group regular or injected.
5096 * @note In case of internal channel (VrefInt, TempSensor, ...) to be
5097 * converted:
5098 * sampling time constraints must be respected (sampling time can be
5099 * adjusted in function of ADC clock frequency and sampling time
5100 * setting).
5101 * Refer to device datasheet for timings values (parameters TS_vrefint,
5102 * TS_temp, ...).
5103 * @note Conversion time is the addition of sampling time and processing time.
5104 * On this STM32 serie, ADC processing time is:
5105 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5106 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5107 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5108 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5109 * @note In case of ADC conversion of internal channel (VrefInt,
5110 * temperature sensor, ...), a sampling time minimum value
5111 * is required.
5112 * Refer to device datasheet.
5113 * @note On this STM32 serie, setting of this feature is conditioned to
5114 * ADC state:
5115 * ADC must be disabled or enabled without conversion on going
5116 * on either groups regular or injected.
5117 * @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
5118 * SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
5119 * SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
5120 * SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
5121 * SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
5122 * SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
5123 * SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
5124 * SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
5125 * SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
5126 * SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
5127 * SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
5128 * SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
5129 * SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
5130 * SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
5131 * SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
5132 * SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
5133 * SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
5134 * SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
5135 * SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
5136 * @param ADCx ADC instance
5137 * @param Channel This parameter can be one of the following values:
5138 * @arg @ref LL_ADC_CHANNEL_0
5139 * @arg @ref LL_ADC_CHANNEL_1 (8)
5140 * @arg @ref LL_ADC_CHANNEL_2 (8)
5141 * @arg @ref LL_ADC_CHANNEL_3 (8)
5142 * @arg @ref LL_ADC_CHANNEL_4 (8)
5143 * @arg @ref LL_ADC_CHANNEL_5 (8)
5144 * @arg @ref LL_ADC_CHANNEL_6
5145 * @arg @ref LL_ADC_CHANNEL_7
5146 * @arg @ref LL_ADC_CHANNEL_8
5147 * @arg @ref LL_ADC_CHANNEL_9
5148 * @arg @ref LL_ADC_CHANNEL_10
5149 * @arg @ref LL_ADC_CHANNEL_11
5150 * @arg @ref LL_ADC_CHANNEL_12
5151 * @arg @ref LL_ADC_CHANNEL_13
5152 * @arg @ref LL_ADC_CHANNEL_14
5153 * @arg @ref LL_ADC_CHANNEL_15
5154 * @arg @ref LL_ADC_CHANNEL_16
5155 * @arg @ref LL_ADC_CHANNEL_17
5156 * @arg @ref LL_ADC_CHANNEL_18
5157 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5158 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5159 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5160 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5161 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5162 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5163 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5164 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5165 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5166 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5167 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5168 *
5169 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5170 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5171 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5172 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5173 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5174 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5175 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5176 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
5177 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5178 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5179 * @param SamplingTime This parameter can be one of the following values:
5180 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5181 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5182 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5183 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5184 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5185 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5186 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5187 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5188 *
5189 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5190 * can be replaced by 3.5 ADC clock cycles.
5191 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5192 * @retval None
5193 */
5194 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
5195 {
5196 /* Set bits with content of parameter "SamplingTime" with bits position */
5197 /* in register and register position depending on parameter "Channel". */
5198 /* Parameter "Channel" is used with masks because containing */
5199 /* other bits reserved for other purpose. */
5200 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5201
5202 MODIFY_REG(*preg,
5203 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
5204 SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
5205 }
5206
5207 /**
5208 * @brief Get sampling time of the selected ADC channel
5209 * Unit: ADC clock cycles.
5210 * @note On this device, sampling time is on channel scope: independently
5211 * of channel mapped on ADC group regular or injected.
5212 * @note Conversion time is the addition of sampling time and processing time.
5213 * On this STM32 serie, ADC processing time is:
5214 * - 12.5 ADC clock cycles at ADC resolution 12 bits
5215 * - 10.5 ADC clock cycles at ADC resolution 10 bits
5216 * - 8.5 ADC clock cycles at ADC resolution 8 bits
5217 * - 6.5 ADC clock cycles at ADC resolution 6 bits
5218 * @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
5219 * SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
5220 * SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
5221 * SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
5222 * SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
5223 * SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
5224 * SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
5225 * SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
5226 * SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
5227 * SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
5228 * SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
5229 * SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
5230 * SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
5231 * SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
5232 * SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
5233 * SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
5234 * SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
5235 * SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
5236 * SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
5237 * @param ADCx ADC instance
5238 * @param Channel This parameter can be one of the following values:
5239 * @arg @ref LL_ADC_CHANNEL_0
5240 * @arg @ref LL_ADC_CHANNEL_1 (8)
5241 * @arg @ref LL_ADC_CHANNEL_2 (8)
5242 * @arg @ref LL_ADC_CHANNEL_3 (8)
5243 * @arg @ref LL_ADC_CHANNEL_4 (8)
5244 * @arg @ref LL_ADC_CHANNEL_5 (8)
5245 * @arg @ref LL_ADC_CHANNEL_6
5246 * @arg @ref LL_ADC_CHANNEL_7
5247 * @arg @ref LL_ADC_CHANNEL_8
5248 * @arg @ref LL_ADC_CHANNEL_9
5249 * @arg @ref LL_ADC_CHANNEL_10
5250 * @arg @ref LL_ADC_CHANNEL_11
5251 * @arg @ref LL_ADC_CHANNEL_12
5252 * @arg @ref LL_ADC_CHANNEL_13
5253 * @arg @ref LL_ADC_CHANNEL_14
5254 * @arg @ref LL_ADC_CHANNEL_15
5255 * @arg @ref LL_ADC_CHANNEL_16
5256 * @arg @ref LL_ADC_CHANNEL_17
5257 * @arg @ref LL_ADC_CHANNEL_18
5258 * @arg @ref LL_ADC_CHANNEL_VREFINT (7)
5259 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
5260 * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
5261 * @arg @ref LL_ADC_CHANNEL_VBAT (6)
5262 * @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
5263 * @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
5264 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
5265 * @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
5266 * @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
5267 * @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
5268 * @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
5269 *
5270 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5271 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5272 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5273 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5274 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5275 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5276 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5277 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
5278 * (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
5279 * Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
5280 * @retval Returned value can be one of the following values:
5281 * @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
5282 * @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
5283 * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
5284 * @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
5285 * @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
5286 * @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
5287 * @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
5288 * @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
5289 *
5290 * (1) On some devices, ADC sampling time 2.5 ADC clock cycles
5291 * can be replaced by 3.5 ADC clock cycles.
5292 * Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
5293 */
5294 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
5295 {
5296 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
5297
5298 return (uint32_t)(READ_BIT(*preg,
5299 ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
5300 >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
5301 );
5302 }
5303
5304 /**
5305 * @brief Set mode single-ended or differential input of the selected
5306 * ADC channel.
5307 * @note Channel ending is on channel scope: independently of channel mapped
5308 * on ADC group regular or injected.
5309 * In differential mode: Differential measurement is carried out
5310 * between the selected channel 'i' (positive input) and
5311 * channel 'i+1' (negative input). Only channel 'i' has to be
5312 * configured, channel 'i+1' is configured automatically.
5313 * @note Refer to Reference Manual to ensure the selected channel is
5314 * available in differential mode.
5315 * For example, internal channels (VrefInt, TempSensor, ...) are
5316 * not available in differential mode.
5317 * @note When configuring a channel 'i' in differential mode,
5318 * the channel 'i+1' is not usable separately.
5319 * @note On STM32G4, some channels are internally fixed to single-ended inputs
5320 * configuration:
5321 * - ADC1: Channels 12, 15, 16, 17 and 18
5322 * - ADC2: Channels 15, 17 and 18
5323 * - ADC3: Channels 12, 16, 17 and 18 (1)
5324 * - ADC4: Channels 16, 17 and 18 (1)
5325 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
5326 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
5327 * for more details.
5328 * @note For ADC channels configured in differential mode, both inputs
5329 * should be biased at (Vref+)/2 +/-200mV.
5330 * (Vref+ is the analog voltage reference)
5331 * @note On this STM32 serie, setting of this feature is conditioned to
5332 * ADC state:
5333 * ADC must be ADC disabled.
5334 * @note One or several values can be selected.
5335 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5336 * @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
5337 * @param ADCx ADC instance
5338 * @param Channel This parameter can be one of the following values:
5339 * @arg @ref LL_ADC_CHANNEL_1
5340 * @arg @ref LL_ADC_CHANNEL_2
5341 * @arg @ref LL_ADC_CHANNEL_3
5342 * @arg @ref LL_ADC_CHANNEL_4
5343 * @arg @ref LL_ADC_CHANNEL_5
5344 * @arg @ref LL_ADC_CHANNEL_6
5345 * @arg @ref LL_ADC_CHANNEL_7
5346 * @arg @ref LL_ADC_CHANNEL_8
5347 * @arg @ref LL_ADC_CHANNEL_9
5348 * @arg @ref LL_ADC_CHANNEL_10
5349 * @arg @ref LL_ADC_CHANNEL_11
5350 * @arg @ref LL_ADC_CHANNEL_12
5351 * @arg @ref LL_ADC_CHANNEL_13
5352 * @arg @ref LL_ADC_CHANNEL_14
5353 * @arg @ref LL_ADC_CHANNEL_15
5354 * @param SingleDiff This parameter can be a combination of the following values:
5355 * @arg @ref LL_ADC_SINGLE_ENDED
5356 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
5357 * @retval None
5358 */
5359 __STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
5360 {
5361 /* Bits of channels in single or differential mode are set only for */
5362 /* differential mode (for single mode, mask of bits allowed to be set is */
5363 /* shifted out of range of bits of channels in single or differential mode. */
5364 MODIFY_REG(ADCx->DIFSEL,
5365 Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
5366 (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
5367 }
5368
5369 /**
5370 * @brief Get mode single-ended or differential input of the selected
5371 * ADC channel.
5372 * @note When configuring a channel 'i' in differential mode,
5373 * the channel 'i+1' is not usable separately.
5374 * Therefore, to ensure a channel is configured in single-ended mode,
5375 * the configuration of channel itself and the channel 'i-1' must be
5376 * read back (to ensure that the selected channel channel has not been
5377 * configured in differential mode by the previous channel).
5378 * @note Refer to Reference Manual to ensure the selected channel is
5379 * available in differential mode.
5380 * For example, internal channels (VrefInt, TempSensor, ...) are
5381 * not available in differential mode.
5382 * @note When configuring a channel 'i' in differential mode,
5383 * the channel 'i+1' is not usable separately.
5384 * @note On STM32G4, some channels are internally fixed to single-ended inputs
5385 * configuration:
5386 * - ADC1: Channels 12, 15, 16, 17 and 18
5387 * - ADC2: Channels 15, 17 and 18
5388 * - ADC3: Channels 12, 16, 17 and 18 (1)
5389 * - ADC4: Channels 16, 17 and 18 (1)
5390 * - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
5391 * (1) ADC3/4/5 are not available on all devices, refer to device datasheet
5392 * for more details.
5393 * @note One or several values can be selected. In this case, the value
5394 * returned is null if all channels are in single ended-mode.
5395 * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
5396 * @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
5397 * @param ADCx ADC instance
5398 * @param Channel This parameter can be a combination of the following values:
5399 * @arg @ref LL_ADC_CHANNEL_1
5400 * @arg @ref LL_ADC_CHANNEL_2
5401 * @arg @ref LL_ADC_CHANNEL_3
5402 * @arg @ref LL_ADC_CHANNEL_4
5403 * @arg @ref LL_ADC_CHANNEL_5
5404 * @arg @ref LL_ADC_CHANNEL_6
5405 * @arg @ref LL_ADC_CHANNEL_7
5406 * @arg @ref LL_ADC_CHANNEL_8
5407 * @arg @ref LL_ADC_CHANNEL_9
5408 * @arg @ref LL_ADC_CHANNEL_10
5409 * @arg @ref LL_ADC_CHANNEL_11
5410 * @arg @ref LL_ADC_CHANNEL_12
5411 * @arg @ref LL_ADC_CHANNEL_13
5412 * @arg @ref LL_ADC_CHANNEL_14
5413 * @arg @ref LL_ADC_CHANNEL_15
5414 * @retval 0: channel in single-ended mode, else: channel in differential mode
5415 */
5416 __STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
5417 {
5418 return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
5419 }
5420
5421 /**
5422 * @}
5423 */
5424
5425 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
5426 * @{
5427 */
5428
5429 /**
5430 * @brief Set ADC analog watchdog monitored channels:
5431 * a single channel, multiple channels or all channels,
5432 * on ADC groups regular and-or injected.
5433 * @note Once monitored channels are selected, analog watchdog
5434 * is enabled.
5435 * @note In case of need to define a single channel to monitor
5436 * with analog watchdog from sequencer channel definition,
5437 * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
5438 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5439 * instance:
5440 * - AWD standard (instance AWD1):
5441 * - channels monitored: can monitor 1 channel or all channels.
5442 * - groups monitored: ADC groups regular and-or injected.
5443 * - resolution: resolution is not limited (corresponds to
5444 * ADC resolution configured).
5445 * - AWD flexible (instances AWD2, AWD3):
5446 * - channels monitored: flexible on channels monitored, selection is
5447 * channel wise, from from 1 to all channels.
5448 * Specificity of this analog watchdog: Multiple channels can
5449 * be selected. For example:
5450 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5451 * - groups monitored: not selection possible (monitoring on both
5452 * groups regular and injected).
5453 * Channels selected are monitored on groups regular and injected:
5454 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5455 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5456 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5457 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5458 * the 2 LSB are ignored.
5459 * @note On this STM32 serie, setting of this feature is conditioned to
5460 * ADC state:
5461 * ADC must be disabled or enabled without conversion on going
5462 * on either groups regular or injected.
5463 * @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
5464 * CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
5465 * CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5466 * CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
5467 * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
5468 * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
5469 * @param ADCx ADC instance
5470 * @param AWDy This parameter can be one of the following values:
5471 * @arg @ref LL_ADC_AWD1
5472 * @arg @ref LL_ADC_AWD2
5473 * @arg @ref LL_ADC_AWD3
5474 * @param AWDChannelGroup This parameter can be one of the following values:
5475 * @arg @ref LL_ADC_AWD_DISABLE
5476 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5477 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5478 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5479 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5480 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5481 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5482 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5483 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5484 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5485 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5486 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5487 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5488 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5489 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5490 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5491 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5492 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5493 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5494 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5495 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5496 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5497 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5498 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5499 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5500 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5501 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5502 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5503 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5504 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5505 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5506 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5507 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5508 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5509 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5510 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5511 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5512 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5513 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5514 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5515 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5516 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5517 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5518 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5519 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5520 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5521 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5522 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5523 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5524 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5525 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5526 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5527 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5528 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5529 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5530 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5531 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5532 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5533 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5534 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5535 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5536 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
5537 * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
5538 * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
5539 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
5540 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
5541 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
5542 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
5543 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
5544 * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
5545 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
5546 * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
5547 * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
5548 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
5549 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
5550 * @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
5551 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
5552 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
5553 * @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
5554 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
5555 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
5556 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
5557 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
5558 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
5559 * @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
5560 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
5561 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
5562 * @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
5563 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
5564 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
5565 * @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
5566 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
5567 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
5568 * @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
5569 *
5570 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
5571 * (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
5572 * (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
5573 * (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
5574 * (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
5575 * (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
5576 * (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
5577 * (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
5578 * - On this STM32 serie, all ADCx are not available on all devices. Refer to device datasheet for more details.
5579 * @retval None
5580 */
5581 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
5582 {
5583 /* Set bits with content of parameter "AWDChannelGroup" with bits position */
5584 /* in register and register position depending on parameter "AWDy". */
5585 /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
5586 /* containing other bits reserved for other purpose. */
5587 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5588 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5589
5590 MODIFY_REG(*preg,
5591 (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
5592 AWDChannelGroup & AWDy);
5593 }
5594
5595 /**
5596 * @brief Get ADC analog watchdog monitored channel.
5597 * @note Usage of the returned channel number:
5598 * - To reinject this channel into another function LL_ADC_xxx:
5599 * the returned channel number is only partly formatted on definition
5600 * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
5601 * with parts of literals LL_ADC_CHANNEL_x or using
5602 * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5603 * Then the selected literal LL_ADC_CHANNEL_x can be used
5604 * as parameter for another function.
5605 * - To get the channel number in decimal format:
5606 * process the returned value with the helper macro
5607 * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
5608 * Applicable only when the analog watchdog is set to monitor
5609 * one channel.
5610 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5611 * instance:
5612 * - AWD standard (instance AWD1):
5613 * - channels monitored: can monitor 1 channel or all channels.
5614 * - groups monitored: ADC groups regular and-or injected.
5615 * - resolution: resolution is not limited (corresponds to
5616 * ADC resolution configured).
5617 * - AWD flexible (instances AWD2, AWD3):
5618 * - channels monitored: flexible on channels monitored, selection is
5619 * channel wise, from from 1 to all channels.
5620 * Specificity of this analog watchdog: Multiple channels can
5621 * be selected. For example:
5622 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5623 * - groups monitored: not selection possible (monitoring on both
5624 * groups regular and injected).
5625 * Channels selected are monitored on groups regular and injected:
5626 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5627 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5628 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5629 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5630 * the 2 LSB are ignored.
5631 * @note On this STM32 serie, setting of this feature is conditioned to
5632 * ADC state:
5633 * ADC must be disabled or enabled without conversion on going
5634 * on either groups regular or injected.
5635 * @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
5636 * CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
5637 * CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5638 * CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
5639 * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
5640 * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
5641 * @param ADCx ADC instance
5642 * @param AWDy This parameter can be one of the following values:
5643 * @arg @ref LL_ADC_AWD1
5644 * @arg @ref LL_ADC_AWD2 (1)
5645 * @arg @ref LL_ADC_AWD3 (1)
5646 *
5647 * (1) On this AWD number, monitored channel can be retrieved
5648 * if only 1 channel is programmed (or none or all channels).
5649 * This function cannot retrieve monitored channel if
5650 * multiple channels are programmed simultaneously
5651 * by bitfield.
5652 * @retval Returned value can be one of the following values:
5653 * @arg @ref LL_ADC_AWD_DISABLE
5654 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
5655 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
5656 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
5657 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
5658 * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
5659 * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
5660 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
5661 * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
5662 * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
5663 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
5664 * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
5665 * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
5666 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
5667 * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
5668 * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
5669 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
5670 * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
5671 * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
5672 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
5673 * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
5674 * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
5675 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
5676 * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
5677 * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
5678 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
5679 * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
5680 * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
5681 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
5682 * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
5683 * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
5684 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
5685 * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
5686 * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
5687 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
5688 * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
5689 * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
5690 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
5691 * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
5692 * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
5693 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
5694 * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
5695 * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
5696 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
5697 * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
5698 * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
5699 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
5700 * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
5701 * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
5702 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
5703 * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
5704 * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
5705 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
5706 * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
5707 * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
5708 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
5709 * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
5710 * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
5711 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
5712 * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
5713 * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
5714 *
5715 * (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
5716 */
5717 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
5718 {
5719 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
5720 + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
5721
5722 register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
5723
5724 /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
5725 /* (parameter value LL_ADC_AWD_DISABLE). */
5726 /* Else, the selected AWD is enabled and is monitoring a group of channels */
5727 /* or a single channel. */
5728 if (AnalogWDMonitChannels != 0UL)
5729 {
5730 if (AWDy == LL_ADC_AWD1)
5731 {
5732 if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
5733 {
5734 /* AWD monitoring a group of channels */
5735 AnalogWDMonitChannels = ((AnalogWDMonitChannels
5736 | (ADC_AWD_CR23_CHANNEL_MASK)
5737 )
5738 & (~(ADC_CFGR_AWD1CH))
5739 );
5740 }
5741 else
5742 {
5743 /* AWD monitoring a single channel */
5744 AnalogWDMonitChannels = (AnalogWDMonitChannels
5745 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
5746 );
5747 }
5748 }
5749 else
5750 {
5751 if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
5752 {
5753 /* AWD monitoring a group of channels */
5754 AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
5755 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
5756 );
5757 }
5758 else
5759 {
5760 /* AWD monitoring a single channel */
5761 /* AWD monitoring a group of channels */
5762 AnalogWDMonitChannels = (AnalogWDMonitChannels
5763 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
5764 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
5765 );
5766 }
5767 }
5768 }
5769
5770 return AnalogWDMonitChannels;
5771 }
5772
5773 /**
5774 * @brief Set ADC analog watchdog thresholds value of both thresholds
5775 * high and low.
5776 * @note If value of only one threshold high or low must be set,
5777 * use function @ref LL_ADC_SetAnalogWDThresholds().
5778 * @note In case of ADC resolution different of 12 bits,
5779 * analog watchdog thresholds data require a specific shift.
5780 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5781 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5782 * instance:
5783 * - AWD standard (instance AWD1):
5784 * - channels monitored: can monitor 1 channel or all channels.
5785 * - groups monitored: ADC groups regular and-or injected.
5786 * - resolution: resolution is not limited (corresponds to
5787 * ADC resolution configured).
5788 * - AWD flexible (instances AWD2, AWD3):
5789 * - channels monitored: flexible on channels monitored, selection is
5790 * channel wise, from from 1 to all channels.
5791 * Specificity of this analog watchdog: Multiple channels can
5792 * be selected. For example:
5793 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5794 * - groups monitored: not selection possible (monitoring on both
5795 * groups regular and injected).
5796 * Channels selected are monitored on groups regular and injected:
5797 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5798 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5799 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5800 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5801 * the 2 LSB are ignored.
5802 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5803 * impacted: the comparison of analog watchdog thresholds is done on
5804 * oversampling final computation (after ratio and shift application):
5805 * ADC data register bitfield [15:4] (12 most significant bits).
5806 * @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
5807 * TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
5808 * TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
5809 * TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
5810 * TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
5811 * TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
5812 * @param ADCx ADC instance
5813 * @param AWDy This parameter can be one of the following values:
5814 * @arg @ref LL_ADC_AWD1
5815 * @arg @ref LL_ADC_AWD2
5816 * @arg @ref LL_ADC_AWD3
5817 * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
5818 * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
5819 * @retval None
5820 */
5821 __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
5822 uint32_t AWDThresholdLowValue)
5823 {
5824 /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
5825 /* position in register and register position depending on parameter */
5826 /* "AWDy". */
5827 /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
5828 /* containing other bits reserved for other purpose. */
5829 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5830
5831 MODIFY_REG(*preg,
5832 ADC_TR1_HT1 | ADC_TR1_LT1,
5833 (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
5834 }
5835
5836 /**
5837 * @brief Set ADC analog watchdog threshold value of threshold
5838 * high or low.
5839 * @note If values of both thresholds high or low must be set,
5840 * use function @ref LL_ADC_ConfigAnalogWDThresholds().
5841 * @note In case of ADC resolution different of 12 bits,
5842 * analog watchdog thresholds data require a specific shift.
5843 * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
5844 * @note On this STM32 serie, there are 2 kinds of analog watchdog
5845 * instance:
5846 * - AWD standard (instance AWD1):
5847 * - channels monitored: can monitor 1 channel or all channels.
5848 * - groups monitored: ADC groups regular and-or injected.
5849 * - resolution: resolution is not limited (corresponds to
5850 * ADC resolution configured).
5851 * - AWD flexible (instances AWD2, AWD3):
5852 * - channels monitored: flexible on channels monitored, selection is
5853 * channel wise, from from 1 to all channels.
5854 * Specificity of this analog watchdog: Multiple channels can
5855 * be selected. For example:
5856 * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
5857 * - groups monitored: not selection possible (monitoring on both
5858 * groups regular and injected).
5859 * Channels selected are monitored on groups regular and injected:
5860 * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
5861 * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
5862 * - resolution: resolution is limited to 8 bits: if ADC resolution is
5863 * 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
5864 * the 2 LSB are ignored.
5865 * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
5866 * impacted: the comparison of analog watchdog thresholds is done on
5867 * oversampling final computation (after ratio and shift application):
5868 * ADC data register bitfield [15:4] (12 most significant bits).
5869 * @note On this STM32 serie, setting of this feature is not conditioned to
5870 * ADC state:
5871 * ADC can be disabled, enabled with or without conversion on going
5872 * on either ADC groups regular or injected.
5873 * @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
5874 * TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
5875 * TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
5876 * TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
5877 * TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
5878 * TR3 LT3 LL_ADC_SetAnalogWDThresholds
5879 * @param ADCx ADC instance
5880 * @param AWDy This parameter can be one of the following values:
5881 * @arg @ref LL_ADC_AWD1
5882 * @arg @ref LL_ADC_AWD2
5883 * @arg @ref LL_ADC_AWD3
5884 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5885 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5886 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5887 * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
5888 * @retval None
5889 */
5890 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
5891 uint32_t AWDThresholdValue)
5892 {
5893 /* Set bits with content of parameter "AWDThresholdValue" with bits */
5894 /* position in register and register position depending on parameters */
5895 /* "AWDThresholdsHighLow" and "AWDy". */
5896 /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
5897 /* containing other bits reserved for other purpose. */
5898 register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5899
5900 MODIFY_REG(*preg,
5901 AWDThresholdsHighLow,
5902 AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
5903 }
5904
5905 /**
5906 * @brief Get ADC analog watchdog threshold value of threshold high,
5907 * threshold low or raw data with ADC thresholds high and low
5908 * concatenated.
5909 * @note If raw data with ADC thresholds high and low is retrieved,
5910 * the data of each threshold high or low can be isolated
5911 * using helper macro:
5912 * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
5913 * @note In case of ADC resolution different of 12 bits,
5914 * analog watchdog thresholds data require a specific shift.
5915 * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
5916 * @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
5917 * TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
5918 * TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
5919 * TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
5920 * TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
5921 * TR3 LT3 LL_ADC_GetAnalogWDThresholds
5922 * @param ADCx ADC instance
5923 * @param AWDy This parameter can be one of the following values:
5924 * @arg @ref LL_ADC_AWD1
5925 * @arg @ref LL_ADC_AWD2
5926 * @arg @ref LL_ADC_AWD3
5927 * @param AWDThresholdsHighLow This parameter can be one of the following values:
5928 * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
5929 * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
5930 * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
5931 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
5932 */
5933 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
5934 {
5935 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
5936
5937 return (uint32_t)(READ_BIT(*preg,
5938 (AWDThresholdsHighLow | ADC_TR1_LT1))
5939 >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~(AWDThresholdsHighLow & ADC_TR1_LT1))
5940 );
5941 }
5942
5943 /**
5944 * @brief Set ADC analog watchdog filtering configuration
5945 * @note On this STM32 serie, setting of this feature is conditioned to
5946 * ADC state:
5947 * ADC must be disabled or enabled without conversion on going
5948 * on either groups regular or injected.
5949 * @note On this STM32 serie, this feature is only available on first
5950 * analog watchdog (AWD1)
5951 * @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
5952 * @param ADCx ADC instance
5953 * @param AWDy This parameter can be one of the following values:
5954 * @arg @ref LL_ADC_AWD1
5955 * @param FilteringConfig This parameter can be one of the following values:
5956 * @arg @ref LL_ADC_AWD_FILTERING_NONE
5957 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
5958 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
5959 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
5960 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
5961 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
5962 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
5963 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
5964 * @retval None
5965 */
5966 __STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
5967 {
5968 /* Prevent unused argument(s) compilation warning */
5969 (void)(AWDy);
5970 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
5971 }
5972
5973 /**
5974 * @brief Get ADC analog watchdog filtering configuration
5975 * @note On this STM32 serie, this feature is only available on first
5976 * analog watchdog (AWD1)
5977 * @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
5978 * @param ADCx ADC instance
5979 * @param AWDy This parameter can be one of the following values:
5980 * @arg @ref LL_ADC_AWD1
5981 * @retval Returned value can be:
5982 * @arg @ref LL_ADC_AWD_FILTERING_NONE
5983 * @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
5984 * @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
5985 * @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
5986 * @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
5987 * @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
5988 * @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
5989 * @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
5990 */
5991 __STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
5992 {
5993 /* Prevent unused argument(s) compilation warning */
5994 (void)(AWDy);
5995 return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
5996 }
5997
5998 /**
5999 * @}
6000 */
6001
6002 /** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
6003 * @{
6004 */
6005
6006 /**
6007 * @brief Set ADC oversampling scope: ADC groups regular and-or injected
6008 * (availability of ADC group injected depends on STM32 families).
6009 * @note If both groups regular and injected are selected,
6010 * specify behavior of ADC group injected interrupting
6011 * group regular: when ADC group injected is triggered,
6012 * the oversampling on ADC group regular is either
6013 * temporary stopped and continued, or resumed from start
6014 * (oversampler buffer reset).
6015 * @note On this STM32 serie, setting of this feature is conditioned to
6016 * ADC state:
6017 * ADC must be disabled or enabled without conversion on going
6018 * on either groups regular or injected.
6019 * @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
6020 * CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
6021 * CFGR2 ROVSM LL_ADC_SetOverSamplingScope
6022 * @param ADCx ADC instance
6023 * @param OvsScope This parameter can be one of the following values:
6024 * @arg @ref LL_ADC_OVS_DISABLE
6025 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6026 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6027 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6028 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6029 * @retval None
6030 */
6031 __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
6032 {
6033 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
6034 }
6035
6036 /**
6037 * @brief Get ADC oversampling scope: ADC groups regular and-or injected
6038 * (availability of ADC group injected depends on STM32 families).
6039 * @note If both groups regular and injected are selected,
6040 * specify behavior of ADC group injected interrupting
6041 * group regular: when ADC group injected is triggered,
6042 * the oversampling on ADC group regular is either
6043 * temporary stopped and continued, or resumed from start
6044 * (oversampler buffer reset).
6045 * @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
6046 * CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
6047 * CFGR2 ROVSM LL_ADC_GetOverSamplingScope
6048 * @param ADCx ADC instance
6049 * @retval Returned value can be one of the following values:
6050 * @arg @ref LL_ADC_OVS_DISABLE
6051 * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
6052 * @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
6053 * @arg @ref LL_ADC_OVS_GRP_INJECTED
6054 * @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
6055 */
6056 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
6057 {
6058 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
6059 }
6060
6061 /**
6062 * @brief Set ADC oversampling discontinuous mode (triggered mode)
6063 * on the selected ADC group.
6064 * @note Number of oversampled conversions are done either in:
6065 * - continuous mode (all conversions of oversampling ratio
6066 * are done from 1 trigger)
6067 * - discontinuous mode (each conversion of oversampling ratio
6068 * needs a trigger)
6069 * @note On this STM32 serie, setting of this feature is conditioned to
6070 * ADC state:
6071 * ADC must be disabled or enabled without conversion on going
6072 * on group regular.
6073 * @note On this STM32 serie, oversampling discontinuous mode
6074 * (triggered mode) can be used only when oversampling is
6075 * set on group regular only and in resumed mode.
6076 * @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
6077 * @param ADCx ADC instance
6078 * @param OverSamplingDiscont This parameter can be one of the following values:
6079 * @arg @ref LL_ADC_OVS_REG_CONT
6080 * @arg @ref LL_ADC_OVS_REG_DISCONT
6081 * @retval None
6082 */
6083 __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
6084 {
6085 MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
6086 }
6087
6088 /**
6089 * @brief Get ADC oversampling discontinuous mode (triggered mode)
6090 * on the selected ADC group.
6091 * @note Number of oversampled conversions are done either in:
6092 * - continuous mode (all conversions of oversampling ratio
6093 * are done from 1 trigger)
6094 * - discontinuous mode (each conversion of oversampling ratio
6095 * needs a trigger)
6096 * @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
6097 * @param ADCx ADC instance
6098 * @retval Returned value can be one of the following values:
6099 * @arg @ref LL_ADC_OVS_REG_CONT
6100 * @arg @ref LL_ADC_OVS_REG_DISCONT
6101 */
6102 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
6103 {
6104 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
6105 }
6106
6107 /**
6108 * @brief Set ADC oversampling
6109 * (impacting both ADC groups regular and injected)
6110 * @note This function set the 2 items of oversampling configuration:
6111 * - ratio
6112 * - shift
6113 * @note On this STM32 serie, setting of this feature is conditioned to
6114 * ADC state:
6115 * ADC must be disabled or enabled without conversion on going
6116 * on either groups regular or injected.
6117 * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
6118 * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
6119 * @param ADCx ADC instance
6120 * @param Ratio This parameter can be one of the following values:
6121 * @arg @ref LL_ADC_OVS_RATIO_2
6122 * @arg @ref LL_ADC_OVS_RATIO_4
6123 * @arg @ref LL_ADC_OVS_RATIO_8
6124 * @arg @ref LL_ADC_OVS_RATIO_16
6125 * @arg @ref LL_ADC_OVS_RATIO_32
6126 * @arg @ref LL_ADC_OVS_RATIO_64
6127 * @arg @ref LL_ADC_OVS_RATIO_128
6128 * @arg @ref LL_ADC_OVS_RATIO_256
6129 * @param Shift This parameter can be one of the following values:
6130 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6131 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6132 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6133 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6134 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6135 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6136 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6137 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6138 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6139 * @retval None
6140 */
6141 __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
6142 {
6143 MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
6144 }
6145
6146 /**
6147 * @brief Get ADC oversampling ratio
6148 * (impacting both ADC groups regular and injected)
6149 * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
6150 * @param ADCx ADC instance
6151 * @retval Ratio This parameter can be one of the following values:
6152 * @arg @ref LL_ADC_OVS_RATIO_2
6153 * @arg @ref LL_ADC_OVS_RATIO_4
6154 * @arg @ref LL_ADC_OVS_RATIO_8
6155 * @arg @ref LL_ADC_OVS_RATIO_16
6156 * @arg @ref LL_ADC_OVS_RATIO_32
6157 * @arg @ref LL_ADC_OVS_RATIO_64
6158 * @arg @ref LL_ADC_OVS_RATIO_128
6159 * @arg @ref LL_ADC_OVS_RATIO_256
6160 */
6161 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
6162 {
6163 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
6164 }
6165
6166 /**
6167 * @brief Get ADC oversampling shift
6168 * (impacting both ADC groups regular and injected)
6169 * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
6170 * @param ADCx ADC instance
6171 * @retval Shift This parameter can be one of the following values:
6172 * @arg @ref LL_ADC_OVS_SHIFT_NONE
6173 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
6174 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
6175 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
6176 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
6177 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
6178 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
6179 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
6180 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
6181 */
6182 __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
6183 {
6184 return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
6185 }
6186
6187 /**
6188 * @}
6189 */
6190
6191 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
6192 * @{
6193 */
6194
6195 #if defined(ADC_MULTIMODE_SUPPORT)
6196 /**
6197 * @brief Set ADC multimode configuration to operate in independent mode
6198 * or multimode (for devices with several ADC instances).
6199 * @note If multimode configuration: the selected ADC instance is
6200 * either master or slave depending on hardware.
6201 * Refer to reference manual.
6202 * @note On this STM32 serie, setting of this feature is conditioned to
6203 * ADC state:
6204 * All ADC instances of the ADC common group must be disabled.
6205 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6206 * ADC instance or by using helper macro
6207 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6208 * @rmtoll CCR DUAL LL_ADC_SetMultimode
6209 * @param ADCxy_COMMON ADC common instance
6210 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6211 * @param Multimode This parameter can be one of the following values:
6212 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6213 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6214 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6215 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6216 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6217 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6218 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6219 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6220 * @retval None
6221 */
6222 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
6223 {
6224 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
6225 }
6226
6227 /**
6228 * @brief Get ADC multimode configuration to operate in independent mode
6229 * or multimode (for devices with several ADC instances).
6230 * @note If multimode configuration: the selected ADC instance is
6231 * either master or slave depending on hardware.
6232 * Refer to reference manual.
6233 * @rmtoll CCR DUAL LL_ADC_GetMultimode
6234 * @param ADCxy_COMMON ADC common instance
6235 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6236 * @retval Returned value can be one of the following values:
6237 * @arg @ref LL_ADC_MULTI_INDEPENDENT
6238 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
6239 * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
6240 * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
6241 * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
6242 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
6243 * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
6244 * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
6245 */
6246 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
6247 {
6248 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
6249 }
6250
6251 /**
6252 * @brief Set ADC multimode conversion data transfer: no transfer
6253 * or transfer by DMA.
6254 * @note If ADC multimode transfer by DMA is not selected:
6255 * each ADC uses its own DMA channel, with its individual
6256 * DMA transfer settings.
6257 * If ADC multimode transfer by DMA is selected:
6258 * One DMA channel is used for both ADC (DMA of ADC master)
6259 * Specifies the DMA requests mode:
6260 * - Limited mode (One shot mode): DMA transfer requests are stopped
6261 * when number of DMA data transfers (number of
6262 * ADC conversions) is reached.
6263 * This ADC mode is intended to be used with DMA mode non-circular.
6264 * - Unlimited mode: DMA transfer requests are unlimited,
6265 * whatever number of DMA data transfers (number of
6266 * ADC conversions).
6267 * This ADC mode is intended to be used with DMA mode circular.
6268 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6269 * mode non-circular:
6270 * when DMA transfers size will be reached, DMA will stop transfers of
6271 * ADC conversions data ADC will raise an overrun error
6272 * (overrun flag and interruption if enabled).
6273 * @note How to retrieve multimode conversion data:
6274 * Whatever multimode transfer by DMA setting: using function
6275 * @ref LL_ADC_REG_ReadMultiConversionData32().
6276 * If ADC multimode transfer by DMA is selected: conversion data
6277 * is a raw data with ADC master and slave concatenated.
6278 * A macro is available to get the conversion data of
6279 * ADC master or ADC slave: see helper macro
6280 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6281 * @note On this STM32 serie, setting of this feature is conditioned to
6282 * ADC state:
6283 * All ADC instances of the ADC common group must be disabled
6284 * or enabled without conversion on going on group regular.
6285 * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
6286 * CCR DMACFG LL_ADC_SetMultiDMATransfer
6287 * @param ADCxy_COMMON ADC common instance
6288 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6289 * @param MultiDMATransfer This parameter can be one of the following values:
6290 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6291 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6292 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6293 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6294 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6295 * @retval None
6296 */
6297 __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
6298 {
6299 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
6300 }
6301
6302 /**
6303 * @brief Get ADC multimode conversion data transfer: no transfer
6304 * or transfer by DMA.
6305 * @note If ADC multimode transfer by DMA is not selected:
6306 * each ADC uses its own DMA channel, with its individual
6307 * DMA transfer settings.
6308 * If ADC multimode transfer by DMA is selected:
6309 * One DMA channel is used for both ADC (DMA of ADC master)
6310 * Specifies the DMA requests mode:
6311 * - Limited mode (One shot mode): DMA transfer requests are stopped
6312 * when number of DMA data transfers (number of
6313 * ADC conversions) is reached.
6314 * This ADC mode is intended to be used with DMA mode non-circular.
6315 * - Unlimited mode: DMA transfer requests are unlimited,
6316 * whatever number of DMA data transfers (number of
6317 * ADC conversions).
6318 * This ADC mode is intended to be used with DMA mode circular.
6319 * @note If ADC DMA requests mode is set to unlimited and DMA is set to
6320 * mode non-circular:
6321 * when DMA transfers size will be reached, DMA will stop transfers of
6322 * ADC conversions data ADC will raise an overrun error
6323 * (overrun flag and interruption if enabled).
6324 * @note How to retrieve multimode conversion data:
6325 * Whatever multimode transfer by DMA setting: using function
6326 * @ref LL_ADC_REG_ReadMultiConversionData32().
6327 * If ADC multimode transfer by DMA is selected: conversion data
6328 * is a raw data with ADC master and slave concatenated.
6329 * A macro is available to get the conversion data of
6330 * ADC master or ADC slave: see helper macro
6331 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6332 * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
6333 * CCR DMACFG LL_ADC_GetMultiDMATransfer
6334 * @param ADCxy_COMMON ADC common instance
6335 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6336 * @retval Returned value can be one of the following values:
6337 * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
6338 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
6339 * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
6340 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
6341 * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
6342 */
6343 __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
6344 {
6345 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
6346 }
6347
6348 /**
6349 * @brief Set ADC multimode delay between 2 sampling phases.
6350 * @note The sampling delay range depends on ADC resolution:
6351 * - ADC resolution 12 bits can have maximum delay of 12 cycles.
6352 * - ADC resolution 10 bits can have maximum delay of 10 cycles.
6353 * - ADC resolution 8 bits can have maximum delay of 8 cycles.
6354 * - ADC resolution 6 bits can have maximum delay of 6 cycles.
6355 * @note On this STM32 serie, setting of this feature is conditioned to
6356 * ADC state:
6357 * All ADC instances of the ADC common group must be disabled.
6358 * This check can be done with function @ref LL_ADC_IsEnabled() for each
6359 * ADC instance or by using helper macro helper macro
6360 * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
6361 * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
6362 * @param ADCxy_COMMON ADC common instance
6363 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6364 * @param MultiTwoSamplingDelay This parameter can be one of the following values:
6365 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6366 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6367 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6368 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6369 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6370 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6371 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6372 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6373 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6374 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6375 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6376 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6377 *
6378 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6379 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6380 * (3) Parameter available only if ADC resolution is 12 bits.
6381 * @retval None
6382 */
6383 __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
6384 {
6385 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
6386 }
6387
6388 /**
6389 * @brief Get ADC multimode delay between 2 sampling phases.
6390 * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
6391 * @param ADCxy_COMMON ADC common instance
6392 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6393 * @retval Returned value can be one of the following values:
6394 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
6395 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
6396 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
6397 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
6398 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
6399 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
6400 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
6401 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
6402 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
6403 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
6404 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
6405 * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
6406 *
6407 * (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
6408 * (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
6409 * (3) Parameter available only if ADC resolution is 12 bits.
6410 */
6411 __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
6412 {
6413 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
6414 }
6415 #endif /* ADC_MULTIMODE_SUPPORT */
6416
6417 /**
6418 * @}
6419 */
6420 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
6421 * @{
6422 */
6423
6424 /**
6425 * @brief Put ADC instance in deep power down state.
6426 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6427 * state, the internal analog calibration is lost. After exiting from
6428 * deep power down, calibration must be relaunched or calibration factor
6429 * (preliminarily saved) must be set back into calibration register.
6430 * @note On this STM32 serie, setting of this feature is conditioned to
6431 * ADC state:
6432 * ADC must be ADC disabled.
6433 * @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
6434 * @param ADCx ADC instance
6435 * @retval None
6436 */
6437 __STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
6438 {
6439 /* Note: Write register with some additional bits forced to state reset */
6440 /* instead of modifying only the selected bit for this function, */
6441 /* to not interfere with bits with HW property "rs". */
6442 MODIFY_REG(ADCx->CR,
6443 ADC_CR_BITS_PROPERTY_RS,
6444 ADC_CR_DEEPPWD);
6445 }
6446
6447 /**
6448 * @brief Disable ADC deep power down mode.
6449 * @note In case of ADC calibration necessary: When ADC is in deep-power-down
6450 * state, the internal analog calibration is lost. After exiting from
6451 * deep power down, calibration must be relaunched or calibration factor
6452 * (preliminarily saved) must be set back into calibration register.
6453 * @note On this STM32 serie, setting of this feature is conditioned to
6454 * ADC state:
6455 * ADC must be ADC disabled.
6456 * @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
6457 * @param ADCx ADC instance
6458 * @retval None
6459 */
6460 __STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
6461 {
6462 /* Note: Write register with some additional bits forced to state reset */
6463 /* instead of modifying only the selected bit for this function, */
6464 /* to not interfere with bits with HW property "rs". */
6465 CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
6466 }
6467
6468 /**
6469 * @brief Get the selected ADC instance deep power down state.
6470 * @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
6471 * @param ADCx ADC instance
6472 * @retval 0: deep power down is disabled, 1: deep power down is enabled.
6473 */
6474 __STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
6475 {
6476 return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
6477 }
6478
6479 /**
6480 * @brief Enable ADC instance internal voltage regulator.
6481 * @note On this STM32 serie, after ADC internal voltage regulator enable,
6482 * a delay for ADC internal voltage regulator stabilization
6483 * is required before performing a ADC calibration or ADC enable.
6484 * Refer to device datasheet, parameter tADCVREG_STUP.
6485 * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
6486 * @note On this STM32 serie, setting of this feature is conditioned to
6487 * ADC state:
6488 * ADC must be ADC disabled.
6489 * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
6490 * @param ADCx ADC instance
6491 * @retval None
6492 */
6493 __STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
6494 {
6495 /* Note: Write register with some additional bits forced to state reset */
6496 /* instead of modifying only the selected bit for this function, */
6497 /* to not interfere with bits with HW property "rs". */
6498 MODIFY_REG(ADCx->CR,
6499 ADC_CR_BITS_PROPERTY_RS,
6500 ADC_CR_ADVREGEN);
6501 }
6502
6503 /**
6504 * @brief Disable ADC internal voltage regulator.
6505 * @note On this STM32 serie, setting of this feature is conditioned to
6506 * ADC state:
6507 * ADC must be ADC disabled.
6508 * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
6509 * @param ADCx ADC instance
6510 * @retval None
6511 */
6512 __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
6513 {
6514 CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
6515 }
6516
6517 /**
6518 * @brief Get the selected ADC instance internal voltage regulator state.
6519 * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
6520 * @param ADCx ADC instance
6521 * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
6522 */
6523 __STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
6524 {
6525 return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
6526 }
6527
6528 /**
6529 * @brief Enable the selected ADC instance.
6530 * @note On this STM32 serie, after ADC enable, a delay for
6531 * ADC internal analog stabilization is required before performing a
6532 * ADC conversion start.
6533 * Refer to device datasheet, parameter tSTAB.
6534 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6535 * is enabled and when conversion clock is active.
6536 * (not only core clock: this ADC has a dual clock domain)
6537 * @note On this STM32 serie, setting of this feature is conditioned to
6538 * ADC state:
6539 * ADC must be ADC disabled and ADC internal voltage regulator enabled.
6540 * @rmtoll CR ADEN LL_ADC_Enable
6541 * @param ADCx ADC instance
6542 * @retval None
6543 */
6544 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
6545 {
6546 /* Note: Write register with some additional bits forced to state reset */
6547 /* instead of modifying only the selected bit for this function, */
6548 /* to not interfere with bits with HW property "rs". */
6549 MODIFY_REG(ADCx->CR,
6550 ADC_CR_BITS_PROPERTY_RS,
6551 ADC_CR_ADEN);
6552 }
6553
6554 /**
6555 * @brief Disable the selected ADC instance.
6556 * @note On this STM32 serie, setting of this feature is conditioned to
6557 * ADC state:
6558 * ADC must be not disabled. Must be enabled without conversion on going
6559 * on either groups regular or injected.
6560 * @rmtoll CR ADDIS LL_ADC_Disable
6561 * @param ADCx ADC instance
6562 * @retval None
6563 */
6564 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
6565 {
6566 /* Note: Write register with some additional bits forced to state reset */
6567 /* instead of modifying only the selected bit for this function, */
6568 /* to not interfere with bits with HW property "rs". */
6569 MODIFY_REG(ADCx->CR,
6570 ADC_CR_BITS_PROPERTY_RS,
6571 ADC_CR_ADDIS);
6572 }
6573
6574 /**
6575 * @brief Get the selected ADC instance enable state.
6576 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
6577 * is enabled and when conversion clock is active.
6578 * (not only core clock: this ADC has a dual clock domain)
6579 * @rmtoll CR ADEN LL_ADC_IsEnabled
6580 * @param ADCx ADC instance
6581 * @retval 0: ADC is disabled, 1: ADC is enabled.
6582 */
6583 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
6584 {
6585 return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
6586 }
6587
6588 /**
6589 * @brief Get the selected ADC instance disable state.
6590 * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
6591 * @param ADCx ADC instance
6592 * @retval 0: no ADC disable command on going.
6593 */
6594 __STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
6595 {
6596 return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
6597 }
6598
6599 /**
6600 * @brief Start ADC calibration in the mode single-ended
6601 * or differential (for devices with differential mode available).
6602 * @note On this STM32 serie, a minimum number of ADC clock cycles
6603 * are required between ADC end of calibration and ADC enable.
6604 * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
6605 * @note For devices with differential mode available:
6606 * Calibration of offset is specific to each of
6607 * single-ended and differential modes
6608 * (calibration run must be performed for each of these
6609 * differential modes, if used afterwards and if the application
6610 * requires their calibration).
6611 * @note On this STM32 serie, setting of this feature is conditioned to
6612 * ADC state:
6613 * ADC must be ADC disabled.
6614 * @rmtoll CR ADCAL LL_ADC_StartCalibration\n
6615 * CR ADCALDIF LL_ADC_StartCalibration
6616 * @param ADCx ADC instance
6617 * @param SingleDiff This parameter can be one of the following values:
6618 * @arg @ref LL_ADC_SINGLE_ENDED
6619 * @arg @ref LL_ADC_DIFFERENTIAL_ENDED
6620 * @retval None
6621 */
6622 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
6623 {
6624 /* Note: Write register with some additional bits forced to state reset */
6625 /* instead of modifying only the selected bit for this function, */
6626 /* to not interfere with bits with HW property "rs". */
6627 MODIFY_REG(ADCx->CR,
6628 ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
6629 ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
6630 }
6631
6632 /**
6633 * @brief Get ADC calibration state.
6634 * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
6635 * @param ADCx ADC instance
6636 * @retval 0: calibration complete, 1: calibration in progress.
6637 */
6638 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
6639 {
6640 return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
6641 }
6642
6643 /**
6644 * @}
6645 */
6646
6647 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
6648 * @{
6649 */
6650
6651 /**
6652 * @brief Start ADC group regular conversion.
6653 * @note On this STM32 serie, this function is relevant for both
6654 * internal trigger (SW start) and external trigger:
6655 * - If ADC trigger has been set to software start, ADC conversion
6656 * starts immediately.
6657 * - If ADC trigger has been set to external trigger, ADC conversion
6658 * will start at next trigger event (on the selected trigger edge)
6659 * following the ADC start conversion command.
6660 * @note On this STM32 serie, setting of this feature is conditioned to
6661 * ADC state:
6662 * ADC must be enabled without conversion on going on group regular,
6663 * without conversion stop command on going on group regular,
6664 * without ADC disable command on going.
6665 * @rmtoll CR ADSTART LL_ADC_REG_StartConversion
6666 * @param ADCx ADC instance
6667 * @retval None
6668 */
6669 __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
6670 {
6671 /* Note: Write register with some additional bits forced to state reset */
6672 /* instead of modifying only the selected bit for this function, */
6673 /* to not interfere with bits with HW property "rs". */
6674 MODIFY_REG(ADCx->CR,
6675 ADC_CR_BITS_PROPERTY_RS,
6676 ADC_CR_ADSTART);
6677 }
6678
6679 /**
6680 * @brief Stop ADC group regular conversion.
6681 * @note On this STM32 serie, setting of this feature is conditioned to
6682 * ADC state:
6683 * ADC must be enabled with conversion on going on group regular,
6684 * without ADC disable command on going.
6685 * @rmtoll CR ADSTP LL_ADC_REG_StopConversion
6686 * @param ADCx ADC instance
6687 * @retval None
6688 */
6689 __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
6690 {
6691 /* Note: Write register with some additional bits forced to state reset */
6692 /* instead of modifying only the selected bit for this function, */
6693 /* to not interfere with bits with HW property "rs". */
6694 MODIFY_REG(ADCx->CR,
6695 ADC_CR_BITS_PROPERTY_RS,
6696 ADC_CR_ADSTP);
6697 }
6698
6699 /**
6700 * @brief Get ADC group regular conversion state.
6701 * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
6702 * @param ADCx ADC instance
6703 * @retval 0: no conversion is on going on ADC group regular.
6704 */
6705 __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
6706 {
6707 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
6708 }
6709
6710 /**
6711 * @brief Get ADC group regular command of conversion stop state
6712 * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
6713 * @param ADCx ADC instance
6714 * @retval 0: no command of conversion stop is on going on ADC group regular.
6715 */
6716 __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6717 {
6718 return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
6719 }
6720
6721 /**
6722 * @brief Start ADC sampling phase for sampling time trigger mode
6723 * @note This function is relevant only when
6724 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6725 * using @ref LL_ADC_REG_SetSamplingMode
6726 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6727 * @note On this STM32 serie, setting of this feature is conditioned to
6728 * ADC state:
6729 * ADC must be enabled without conversion on going on group regular,
6730 * without conversion stop command on going on group regular,
6731 * without ADC disable command on going.
6732 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
6733 * @param ADCx ADC instance
6734 * @retval None
6735 */
6736 __STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
6737 {
6738 SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6739 }
6740
6741 /**
6742 * @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
6743 * @note This function is relevant only when
6744 * - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
6745 * using @ref LL_ADC_REG_SetSamplingMode
6746 * - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
6747 * - @ref LL_ADC_REG_StartSamplingPhase has been called to start
6748 * the sampling phase
6749 * @note On this STM32 serie, setting of this feature is conditioned to
6750 * ADC state:
6751 * ADC must be enabled without conversion on going on group regular,
6752 * without conversion stop command on going on group regular,
6753 * without ADC disable command on going.
6754 * @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
6755 * @param ADCx ADC instance
6756 * @retval None
6757 */
6758 __STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
6759 {
6760 CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
6761 }
6762
6763 /**
6764 * @brief Get ADC group regular conversion data, range fit for
6765 * all ADC configurations: all ADC resolutions and
6766 * all oversampling increased data width (for devices
6767 * with feature oversampling).
6768 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
6769 * @param ADCx ADC instance
6770 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6771 */
6772 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
6773 {
6774 return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6775 }
6776
6777 /**
6778 * @brief Get ADC group regular conversion data, range fit for
6779 * ADC resolution 12 bits.
6780 * @note For devices with feature oversampling: Oversampling
6781 * can increase data width, function for extended range
6782 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6783 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
6784 * @param ADCx ADC instance
6785 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6786 */
6787 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
6788 {
6789 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6790 }
6791
6792 /**
6793 * @brief Get ADC group regular conversion data, range fit for
6794 * ADC resolution 10 bits.
6795 * @note For devices with feature oversampling: Oversampling
6796 * can increase data width, function for extended range
6797 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6798 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
6799 * @param ADCx ADC instance
6800 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
6801 */
6802 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
6803 {
6804 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6805 }
6806
6807 /**
6808 * @brief Get ADC group regular conversion data, range fit for
6809 * ADC resolution 8 bits.
6810 * @note For devices with feature oversampling: Oversampling
6811 * can increase data width, function for extended range
6812 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6813 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
6814 * @param ADCx ADC instance
6815 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
6816 */
6817 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
6818 {
6819 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6820 }
6821
6822 /**
6823 * @brief Get ADC group regular conversion data, range fit for
6824 * ADC resolution 6 bits.
6825 * @note For devices with feature oversampling: Oversampling
6826 * can increase data width, function for extended range
6827 * may be needed: @ref LL_ADC_REG_ReadConversionData32.
6828 * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
6829 * @param ADCx ADC instance
6830 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
6831 */
6832 __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
6833 {
6834 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
6835 }
6836
6837 #if defined(ADC_MULTIMODE_SUPPORT)
6838 /**
6839 * @brief Get ADC multimode conversion data of ADC master, ADC slave
6840 * or raw data with ADC master and slave concatenated.
6841 * @note If raw data with ADC master and slave concatenated is retrieved,
6842 * a macro is available to get the conversion data of
6843 * ADC master or ADC slave: see helper macro
6844 * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
6845 * (however this macro is mainly intended for multimode
6846 * transfer by DMA, because this function can do the same
6847 * by getting multimode conversion data of ADC master or ADC slave
6848 * separately).
6849 * @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
6850 * CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
6851 * @param ADCxy_COMMON ADC common instance
6852 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
6853 * @param ConversionData This parameter can be one of the following values:
6854 * @arg @ref LL_ADC_MULTI_MASTER
6855 * @arg @ref LL_ADC_MULTI_SLAVE
6856 * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
6857 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6858 */
6859 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
6860 {
6861 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
6862 ConversionData)
6863 >> (POSITION_VAL(ConversionData) & 0x1FUL)
6864 );
6865 }
6866 #endif /* ADC_MULTIMODE_SUPPORT */
6867
6868 /**
6869 * @}
6870 */
6871
6872 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
6873 * @{
6874 */
6875
6876 /**
6877 * @brief Start ADC group injected conversion.
6878 * @note On this STM32 serie, this function is relevant for both
6879 * internal trigger (SW start) and external trigger:
6880 * - If ADC trigger has been set to software start, ADC conversion
6881 * starts immediately.
6882 * - If ADC trigger has been set to external trigger, ADC conversion
6883 * will start at next trigger event (on the selected trigger edge)
6884 * following the ADC start conversion command.
6885 * @note On this STM32 serie, setting of this feature is conditioned to
6886 * ADC state:
6887 * ADC must be enabled without conversion on going on group injected,
6888 * without conversion stop command on going on group injected,
6889 * without ADC disable command on going.
6890 * @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
6891 * @param ADCx ADC instance
6892 * @retval None
6893 */
6894 __STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
6895 {
6896 /* Note: Write register with some additional bits forced to state reset */
6897 /* instead of modifying only the selected bit for this function, */
6898 /* to not interfere with bits with HW property "rs". */
6899 MODIFY_REG(ADCx->CR,
6900 ADC_CR_BITS_PROPERTY_RS,
6901 ADC_CR_JADSTART);
6902 }
6903
6904 /**
6905 * @brief Stop ADC group injected conversion.
6906 * @note On this STM32 serie, setting of this feature is conditioned to
6907 * ADC state:
6908 * ADC must be enabled with conversion on going on group injected,
6909 * without ADC disable command on going.
6910 * @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
6911 * @param ADCx ADC instance
6912 * @retval None
6913 */
6914 __STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
6915 {
6916 /* Note: Write register with some additional bits forced to state reset */
6917 /* instead of modifying only the selected bit for this function, */
6918 /* to not interfere with bits with HW property "rs". */
6919 MODIFY_REG(ADCx->CR,
6920 ADC_CR_BITS_PROPERTY_RS,
6921 ADC_CR_JADSTP);
6922 }
6923
6924 /**
6925 * @brief Get ADC group injected conversion state.
6926 * @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
6927 * @param ADCx ADC instance
6928 * @retval 0: no conversion is on going on ADC group injected.
6929 */
6930 __STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
6931 {
6932 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
6933 }
6934
6935 /**
6936 * @brief Get ADC group injected command of conversion stop state
6937 * @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
6938 * @param ADCx ADC instance
6939 * @retval 0: no command of conversion stop is on going on ADC group injected.
6940 */
6941 __STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
6942 {
6943 return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
6944 }
6945
6946 /**
6947 * @brief Get ADC group regular conversion data, range fit for
6948 * all ADC configurations: all ADC resolutions and
6949 * all oversampling increased data width (for devices
6950 * with feature oversampling).
6951 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
6952 * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
6953 * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
6954 * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
6955 * @param ADCx ADC instance
6956 * @param Rank This parameter can be one of the following values:
6957 * @arg @ref LL_ADC_INJ_RANK_1
6958 * @arg @ref LL_ADC_INJ_RANK_2
6959 * @arg @ref LL_ADC_INJ_RANK_3
6960 * @arg @ref LL_ADC_INJ_RANK_4
6961 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
6962 */
6963 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
6964 {
6965 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6966
6967 return (uint32_t)(READ_BIT(*preg,
6968 ADC_JDR1_JDATA)
6969 );
6970 }
6971
6972 /**
6973 * @brief Get ADC group injected conversion data, range fit for
6974 * ADC resolution 12 bits.
6975 * @note For devices with feature oversampling: Oversampling
6976 * can increase data width, function for extended range
6977 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
6978 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
6979 * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
6980 * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
6981 * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
6982 * @param ADCx ADC instance
6983 * @param Rank This parameter can be one of the following values:
6984 * @arg @ref LL_ADC_INJ_RANK_1
6985 * @arg @ref LL_ADC_INJ_RANK_2
6986 * @arg @ref LL_ADC_INJ_RANK_3
6987 * @arg @ref LL_ADC_INJ_RANK_4
6988 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
6989 */
6990 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
6991 {
6992 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
6993
6994 return (uint16_t)(READ_BIT(*preg,
6995 ADC_JDR1_JDATA)
6996 );
6997 }
6998
6999 /**
7000 * @brief Get ADC group injected conversion data, range fit for
7001 * ADC resolution 10 bits.
7002 * @note For devices with feature oversampling: Oversampling
7003 * can increase data width, function for extended range
7004 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7005 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
7006 * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
7007 * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
7008 * JDR4 JDATA LL_ADC_INJ_ReadConversionData10
7009 * @param ADCx ADC instance
7010 * @param Rank This parameter can be one of the following values:
7011 * @arg @ref LL_ADC_INJ_RANK_1
7012 * @arg @ref LL_ADC_INJ_RANK_2
7013 * @arg @ref LL_ADC_INJ_RANK_3
7014 * @arg @ref LL_ADC_INJ_RANK_4
7015 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
7016 */
7017 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
7018 {
7019 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7020
7021 return (uint16_t)(READ_BIT(*preg,
7022 ADC_JDR1_JDATA)
7023 );
7024 }
7025
7026 /**
7027 * @brief Get ADC group injected conversion data, range fit for
7028 * ADC resolution 8 bits.
7029 * @note For devices with feature oversampling: Oversampling
7030 * can increase data width, function for extended range
7031 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7032 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
7033 * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
7034 * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
7035 * JDR4 JDATA LL_ADC_INJ_ReadConversionData8
7036 * @param ADCx ADC instance
7037 * @param Rank This parameter can be one of the following values:
7038 * @arg @ref LL_ADC_INJ_RANK_1
7039 * @arg @ref LL_ADC_INJ_RANK_2
7040 * @arg @ref LL_ADC_INJ_RANK_3
7041 * @arg @ref LL_ADC_INJ_RANK_4
7042 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
7043 */
7044 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
7045 {
7046 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7047
7048 return (uint8_t)(READ_BIT(*preg,
7049 ADC_JDR1_JDATA)
7050 );
7051 }
7052
7053 /**
7054 * @brief Get ADC group injected conversion data, range fit for
7055 * ADC resolution 6 bits.
7056 * @note For devices with feature oversampling: Oversampling
7057 * can increase data width, function for extended range
7058 * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
7059 * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
7060 * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
7061 * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
7062 * JDR4 JDATA LL_ADC_INJ_ReadConversionData6
7063 * @param ADCx ADC instance
7064 * @param Rank This parameter can be one of the following values:
7065 * @arg @ref LL_ADC_INJ_RANK_1
7066 * @arg @ref LL_ADC_INJ_RANK_2
7067 * @arg @ref LL_ADC_INJ_RANK_3
7068 * @arg @ref LL_ADC_INJ_RANK_4
7069 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
7070 */
7071 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
7072 {
7073 register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
7074
7075 return (uint8_t)(READ_BIT(*preg,
7076 ADC_JDR1_JDATA)
7077 );
7078 }
7079
7080 /**
7081 * @}
7082 */
7083
7084 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
7085 * @{
7086 */
7087
7088 /**
7089 * @brief Get flag ADC ready.
7090 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7091 * is enabled and when conversion clock is active.
7092 * (not only core clock: this ADC has a dual clock domain)
7093 * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
7094 * @param ADCx ADC instance
7095 * @retval State of bit (1 or 0).
7096 */
7097 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
7098 {
7099 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
7100 }
7101
7102 /**
7103 * @brief Get flag ADC group regular end of unitary conversion.
7104 * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
7105 * @param ADCx ADC instance
7106 * @retval State of bit (1 or 0).
7107 */
7108 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
7109 {
7110 return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
7111 }
7112
7113 /**
7114 * @brief Get flag ADC group regular end of sequence conversions.
7115 * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
7116 * @param ADCx ADC instance
7117 * @retval State of bit (1 or 0).
7118 */
7119 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
7120 {
7121 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
7122 }
7123
7124 /**
7125 * @brief Get flag ADC group regular overrun.
7126 * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
7127 * @param ADCx ADC instance
7128 * @retval State of bit (1 or 0).
7129 */
7130 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
7131 {
7132 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
7133 }
7134
7135 /**
7136 * @brief Get flag ADC group regular end of sampling phase.
7137 * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
7138 * @param ADCx ADC instance
7139 * @retval State of bit (1 or 0).
7140 */
7141 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
7142 {
7143 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
7144 }
7145
7146 /**
7147 * @brief Get flag ADC group injected end of unitary conversion.
7148 * @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
7149 * @param ADCx ADC instance
7150 * @retval State of bit (1 or 0).
7151 */
7152 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
7153 {
7154 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
7155 }
7156
7157 /**
7158 * @brief Get flag ADC group injected end of sequence conversions.
7159 * @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
7160 * @param ADCx ADC instance
7161 * @retval State of bit (1 or 0).
7162 */
7163 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
7164 {
7165 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
7166 }
7167
7168 /**
7169 * @brief Get flag ADC group injected contexts queue overflow.
7170 * @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
7171 * @param ADCx ADC instance
7172 * @retval State of bit (1 or 0).
7173 */
7174 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
7175 {
7176 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
7177 }
7178
7179 /**
7180 * @brief Get flag ADC analog watchdog 1 flag
7181 * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
7182 * @param ADCx ADC instance
7183 * @retval State of bit (1 or 0).
7184 */
7185 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
7186 {
7187 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
7188 }
7189
7190 /**
7191 * @brief Get flag ADC analog watchdog 2.
7192 * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
7193 * @param ADCx ADC instance
7194 * @retval State of bit (1 or 0).
7195 */
7196 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
7197 {
7198 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
7199 }
7200
7201 /**
7202 * @brief Get flag ADC analog watchdog 3.
7203 * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
7204 * @param ADCx ADC instance
7205 * @retval State of bit (1 or 0).
7206 */
7207 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
7208 {
7209 return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
7210 }
7211
7212 /**
7213 * @brief Clear flag ADC ready.
7214 * @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
7215 * is enabled and when conversion clock is active.
7216 * (not only core clock: this ADC has a dual clock domain)
7217 * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
7218 * @param ADCx ADC instance
7219 * @retval None
7220 */
7221 __STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
7222 {
7223 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
7224 }
7225
7226 /**
7227 * @brief Clear flag ADC group regular end of unitary conversion.
7228 * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
7229 * @param ADCx ADC instance
7230 * @retval None
7231 */
7232 __STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
7233 {
7234 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
7235 }
7236
7237 /**
7238 * @brief Clear flag ADC group regular end of sequence conversions.
7239 * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
7240 * @param ADCx ADC instance
7241 * @retval None
7242 */
7243 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
7244 {
7245 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
7246 }
7247
7248 /**
7249 * @brief Clear flag ADC group regular overrun.
7250 * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
7251 * @param ADCx ADC instance
7252 * @retval None
7253 */
7254 __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
7255 {
7256 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
7257 }
7258
7259 /**
7260 * @brief Clear flag ADC group regular end of sampling phase.
7261 * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
7262 * @param ADCx ADC instance
7263 * @retval None
7264 */
7265 __STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
7266 {
7267 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
7268 }
7269
7270 /**
7271 * @brief Clear flag ADC group injected end of unitary conversion.
7272 * @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
7273 * @param ADCx ADC instance
7274 * @retval None
7275 */
7276 __STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
7277 {
7278 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
7279 }
7280
7281 /**
7282 * @brief Clear flag ADC group injected end of sequence conversions.
7283 * @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
7284 * @param ADCx ADC instance
7285 * @retval None
7286 */
7287 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
7288 {
7289 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
7290 }
7291
7292 /**
7293 * @brief Clear flag ADC group injected contexts queue overflow.
7294 * @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
7295 * @param ADCx ADC instance
7296 * @retval None
7297 */
7298 __STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
7299 {
7300 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
7301 }
7302
7303 /**
7304 * @brief Clear flag ADC analog watchdog 1.
7305 * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
7306 * @param ADCx ADC instance
7307 * @retval None
7308 */
7309 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
7310 {
7311 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
7312 }
7313
7314 /**
7315 * @brief Clear flag ADC analog watchdog 2.
7316 * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
7317 * @param ADCx ADC instance
7318 * @retval None
7319 */
7320 __STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
7321 {
7322 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
7323 }
7324
7325 /**
7326 * @brief Clear flag ADC analog watchdog 3.
7327 * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
7328 * @param ADCx ADC instance
7329 * @retval None
7330 */
7331 __STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
7332 {
7333 WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
7334 }
7335
7336 #if defined(ADC_MULTIMODE_SUPPORT)
7337 /**
7338 * @brief Get flag multimode ADC ready of the ADC master.
7339 * @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
7340 * @param ADCxy_COMMON ADC common instance
7341 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7342 * @retval State of bit (1 or 0).
7343 */
7344 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7345 {
7346 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
7347 }
7348
7349 /**
7350 * @brief Get flag multimode ADC ready of the ADC slave.
7351 * @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
7352 * @param ADCxy_COMMON ADC common instance
7353 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7354 * @retval State of bit (1 or 0).
7355 */
7356 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
7357 {
7358 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
7359 }
7360
7361 /**
7362 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
7363 * @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
7364 * @param ADCxy_COMMON ADC common instance
7365 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7366 * @retval State of bit (1 or 0).
7367 */
7368 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7369 {
7370 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7371 }
7372
7373 /**
7374 * @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
7375 * @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
7376 * @param ADCxy_COMMON ADC common instance
7377 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7378 * @retval State of bit (1 or 0).
7379 */
7380 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
7381 {
7382 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
7383 }
7384
7385 /**
7386 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
7387 * @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
7388 * @param ADCxy_COMMON ADC common instance
7389 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7390 * @retval State of bit (1 or 0).
7391 */
7392 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7393 {
7394 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
7395 }
7396
7397 /**
7398 * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
7399 * @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
7400 * @param ADCxy_COMMON ADC common instance
7401 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7402 * @retval State of bit (1 or 0).
7403 */
7404 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
7405 {
7406 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
7407 }
7408
7409 /**
7410 * @brief Get flag multimode ADC group regular overrun of the ADC master.
7411 * @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
7412 * @param ADCxy_COMMON ADC common instance
7413 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7414 * @retval State of bit (1 or 0).
7415 */
7416 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7417 {
7418 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
7419 }
7420
7421 /**
7422 * @brief Get flag multimode ADC group regular overrun of the ADC slave.
7423 * @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
7424 * @param ADCxy_COMMON ADC common instance
7425 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7426 * @retval State of bit (1 or 0).
7427 */
7428 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
7429 {
7430 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
7431 }
7432
7433 /**
7434 * @brief Get flag multimode ADC group regular end of sampling of the ADC master.
7435 * @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
7436 * @param ADCxy_COMMON ADC common instance
7437 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7438 * @retval State of bit (1 or 0).
7439 */
7440 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7441 {
7442 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
7443 }
7444
7445 /**
7446 * @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
7447 * @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
7448 * @param ADCxy_COMMON ADC common instance
7449 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7450 * @retval State of bit (1 or 0).
7451 */
7452 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
7453 {
7454 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
7455 }
7456
7457 /**
7458 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
7459 * @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
7460 * @param ADCxy_COMMON ADC common instance
7461 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7462 * @retval State of bit (1 or 0).
7463 */
7464 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7465 {
7466 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
7467 }
7468
7469 /**
7470 * @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
7471 * @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
7472 * @param ADCxy_COMMON ADC common instance
7473 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7474 * @retval State of bit (1 or 0).
7475 */
7476 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
7477 {
7478 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
7479 }
7480
7481 /**
7482 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
7483 * @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
7484 * @param ADCxy_COMMON ADC common instance
7485 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7486 * @retval State of bit (1 or 0).
7487 */
7488 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7489 {
7490 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
7491 }
7492
7493 /**
7494 * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
7495 * @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
7496 * @param ADCxy_COMMON ADC common instance
7497 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7498 * @retval State of bit (1 or 0).
7499 */
7500 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
7501 {
7502 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
7503 }
7504
7505 /**
7506 * @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
7507 * @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
7508 * @param ADCxy_COMMON ADC common instance
7509 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7510 * @retval State of bit (1 or 0).
7511 */
7512 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7513 {
7514 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
7515 }
7516
7517 /**
7518 * @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
7519 * @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
7520 * @param ADCxy_COMMON ADC common instance
7521 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7522 * @retval State of bit (1 or 0).
7523 */
7524 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
7525 {
7526 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
7527 }
7528
7529 /**
7530 * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
7531 * @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
7532 * @param ADCxy_COMMON ADC common instance
7533 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7534 * @retval State of bit (1 or 0).
7535 */
7536 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7537 {
7538 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
7539 }
7540
7541 /**
7542 * @brief Get flag multimode analog watchdog 1 of the ADC slave.
7543 * @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
7544 * @param ADCxy_COMMON ADC common instance
7545 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7546 * @retval State of bit (1 or 0).
7547 */
7548 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
7549 {
7550 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
7551 }
7552
7553 /**
7554 * @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
7555 * @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
7556 * @param ADCxy_COMMON ADC common instance
7557 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7558 * @retval State of bit (1 or 0).
7559 */
7560 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7561 {
7562 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
7563 }
7564
7565 /**
7566 * @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
7567 * @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
7568 * @param ADCxy_COMMON ADC common instance
7569 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7570 * @retval State of bit (1 or 0).
7571 */
7572 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
7573 {
7574 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
7575 }
7576
7577 /**
7578 * @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
7579 * @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
7580 * @param ADCxy_COMMON ADC common instance
7581 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7582 * @retval State of bit (1 or 0).
7583 */
7584 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7585 {
7586 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
7587 }
7588
7589 /**
7590 * @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
7591 * @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
7592 * @param ADCxy_COMMON ADC common instance
7593 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
7594 * @retval State of bit (1 or 0).
7595 */
7596 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
7597 {
7598 return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
7599 }
7600 #endif /* ADC_MULTIMODE_SUPPORT */
7601
7602 /**
7603 * @}
7604 */
7605
7606 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
7607 * @{
7608 */
7609
7610 /**
7611 * @brief Enable ADC ready.
7612 * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
7613 * @param ADCx ADC instance
7614 * @retval None
7615 */
7616 __STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
7617 {
7618 SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7619 }
7620
7621 /**
7622 * @brief Enable interruption ADC group regular end of unitary conversion.
7623 * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
7624 * @param ADCx ADC instance
7625 * @retval None
7626 */
7627 __STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
7628 {
7629 SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
7630 }
7631
7632 /**
7633 * @brief Enable interruption ADC group regular end of sequence conversions.
7634 * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
7635 * @param ADCx ADC instance
7636 * @retval None
7637 */
7638 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
7639 {
7640 SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
7641 }
7642
7643 /**
7644 * @brief Enable ADC group regular interruption overrun.
7645 * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
7646 * @param ADCx ADC instance
7647 * @retval None
7648 */
7649 __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
7650 {
7651 SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
7652 }
7653
7654 /**
7655 * @brief Enable interruption ADC group regular end of sampling.
7656 * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
7657 * @param ADCx ADC instance
7658 * @retval None
7659 */
7660 __STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
7661 {
7662 SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7663 }
7664
7665 /**
7666 * @brief Enable interruption ADC group injected end of unitary conversion.
7667 * @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
7668 * @param ADCx ADC instance
7669 * @retval None
7670 */
7671 __STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
7672 {
7673 SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7674 }
7675
7676 /**
7677 * @brief Enable interruption ADC group injected end of sequence conversions.
7678 * @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
7679 * @param ADCx ADC instance
7680 * @retval None
7681 */
7682 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
7683 {
7684 SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7685 }
7686
7687 /**
7688 * @brief Enable interruption ADC group injected context queue overflow.
7689 * @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
7690 * @param ADCx ADC instance
7691 * @retval None
7692 */
7693 __STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
7694 {
7695 SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7696 }
7697
7698 /**
7699 * @brief Enable interruption ADC analog watchdog 1.
7700 * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
7701 * @param ADCx ADC instance
7702 * @retval None
7703 */
7704 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
7705 {
7706 SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7707 }
7708
7709 /**
7710 * @brief Enable interruption ADC analog watchdog 2.
7711 * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
7712 * @param ADCx ADC instance
7713 * @retval None
7714 */
7715 __STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
7716 {
7717 SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7718 }
7719
7720 /**
7721 * @brief Enable interruption ADC analog watchdog 3.
7722 * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
7723 * @param ADCx ADC instance
7724 * @retval None
7725 */
7726 __STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
7727 {
7728 SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7729 }
7730
7731 /**
7732 * @brief Disable interruption ADC ready.
7733 * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
7734 * @param ADCx ADC instance
7735 * @retval None
7736 */
7737 __STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
7738 {
7739 CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
7740 }
7741
7742 /**
7743 * @brief Disable interruption ADC group regular end of unitary conversion.
7744 * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
7745 * @param ADCx ADC instance
7746 * @retval None
7747 */
7748 __STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
7749 {
7750 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
7751 }
7752
7753 /**
7754 * @brief Disable interruption ADC group regular end of sequence conversions.
7755 * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
7756 * @param ADCx ADC instance
7757 * @retval None
7758 */
7759 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
7760 {
7761 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
7762 }
7763
7764 /**
7765 * @brief Disable interruption ADC group regular overrun.
7766 * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
7767 * @param ADCx ADC instance
7768 * @retval None
7769 */
7770 __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
7771 {
7772 CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
7773 }
7774
7775 /**
7776 * @brief Disable interruption ADC group regular end of sampling.
7777 * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
7778 * @param ADCx ADC instance
7779 * @retval None
7780 */
7781 __STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
7782 {
7783 CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
7784 }
7785
7786 /**
7787 * @brief Disable interruption ADC group regular end of unitary conversion.
7788 * @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
7789 * @param ADCx ADC instance
7790 * @retval None
7791 */
7792 __STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
7793 {
7794 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
7795 }
7796
7797 /**
7798 * @brief Disable interruption ADC group injected end of sequence conversions.
7799 * @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
7800 * @param ADCx ADC instance
7801 * @retval None
7802 */
7803 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
7804 {
7805 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
7806 }
7807
7808 /**
7809 * @brief Disable interruption ADC group injected context queue overflow.
7810 * @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
7811 * @param ADCx ADC instance
7812 * @retval None
7813 */
7814 __STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
7815 {
7816 CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
7817 }
7818
7819 /**
7820 * @brief Disable interruption ADC analog watchdog 1.
7821 * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
7822 * @param ADCx ADC instance
7823 * @retval None
7824 */
7825 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
7826 {
7827 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
7828 }
7829
7830 /**
7831 * @brief Disable interruption ADC analog watchdog 2.
7832 * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
7833 * @param ADCx ADC instance
7834 * @retval None
7835 */
7836 __STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
7837 {
7838 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
7839 }
7840
7841 /**
7842 * @brief Disable interruption ADC analog watchdog 3.
7843 * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
7844 * @param ADCx ADC instance
7845 * @retval None
7846 */
7847 __STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
7848 {
7849 CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
7850 }
7851
7852 /**
7853 * @brief Get state of interruption ADC ready
7854 * (0: interrupt disabled, 1: interrupt enabled).
7855 * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
7856 * @param ADCx ADC instance
7857 * @retval State of bit (1 or 0).
7858 */
7859 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
7860 {
7861 return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
7862 }
7863
7864 /**
7865 * @brief Get state of interruption ADC group regular end of unitary conversion
7866 * (0: interrupt disabled, 1: interrupt enabled).
7867 * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
7868 * @param ADCx ADC instance
7869 * @retval State of bit (1 or 0).
7870 */
7871 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
7872 {
7873 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
7874 }
7875
7876 /**
7877 * @brief Get state of interruption ADC group regular end of sequence conversions
7878 * (0: interrupt disabled, 1: interrupt enabled).
7879 * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
7880 * @param ADCx ADC instance
7881 * @retval State of bit (1 or 0).
7882 */
7883 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
7884 {
7885 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
7886 }
7887
7888 /**
7889 * @brief Get state of interruption ADC group regular overrun
7890 * (0: interrupt disabled, 1: interrupt enabled).
7891 * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
7892 * @param ADCx ADC instance
7893 * @retval State of bit (1 or 0).
7894 */
7895 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
7896 {
7897 return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
7898 }
7899
7900 /**
7901 * @brief Get state of interruption ADC group regular end of sampling
7902 * (0: interrupt disabled, 1: interrupt enabled).
7903 * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
7904 * @param ADCx ADC instance
7905 * @retval State of bit (1 or 0).
7906 */
7907 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
7908 {
7909 return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
7910 }
7911
7912 /**
7913 * @brief Get state of interruption ADC group injected end of unitary conversion
7914 * (0: interrupt disabled, 1: interrupt enabled).
7915 * @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
7916 * @param ADCx ADC instance
7917 * @retval State of bit (1 or 0).
7918 */
7919 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
7920 {
7921 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
7922 }
7923
7924 /**
7925 * @brief Get state of interruption ADC group injected end of sequence conversions
7926 * (0: interrupt disabled, 1: interrupt enabled).
7927 * @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
7928 * @param ADCx ADC instance
7929 * @retval State of bit (1 or 0).
7930 */
7931 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
7932 {
7933 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
7934 }
7935
7936 /**
7937 * @brief Get state of interruption ADC group injected context queue overflow interrupt state
7938 * (0: interrupt disabled, 1: interrupt enabled).
7939 * @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
7940 * @param ADCx ADC instance
7941 * @retval State of bit (1 or 0).
7942 */
7943 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
7944 {
7945 return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
7946 }
7947
7948 /**
7949 * @brief Get state of interruption ADC analog watchdog 1
7950 * (0: interrupt disabled, 1: interrupt enabled).
7951 * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
7952 * @param ADCx ADC instance
7953 * @retval State of bit (1 or 0).
7954 */
7955 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
7956 {
7957 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
7958 }
7959
7960 /**
7961 * @brief Get state of interruption Get ADC analog watchdog 2
7962 * (0: interrupt disabled, 1: interrupt enabled).
7963 * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
7964 * @param ADCx ADC instance
7965 * @retval State of bit (1 or 0).
7966 */
7967 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
7968 {
7969 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
7970 }
7971
7972 /**
7973 * @brief Get state of interruption Get ADC analog watchdog 3
7974 * (0: interrupt disabled, 1: interrupt enabled).
7975 * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
7976 * @param ADCx ADC instance
7977 * @retval State of bit (1 or 0).
7978 */
7979 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
7980 {
7981 return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
7982 }
7983
7984 /**
7985 * @}
7986 */
7987
7988 #if defined(USE_FULL_LL_DRIVER)
7989 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
7990 * @{
7991 */
7992
7993 /* Initialization of some features of ADC common parameters and multimode */
7994 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
7995 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7996 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
7997
7998 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
7999 /* (availability of ADC group injected depends on STM32 families) */
8000 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
8001
8002 /* Initialization of some features of ADC instance */
8003 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
8004 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
8005
8006 /* Initialization of some features of ADC instance and ADC group regular */
8007 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8008 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
8009
8010 /* Initialization of some features of ADC instance and ADC group injected */
8011 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8012 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
8013
8014 /**
8015 * @}
8016 */
8017 #endif /* USE_FULL_LL_DRIVER */
8018
8019 /**
8020 * @}
8021 */
8022
8023 /**
8024 * @}
8025 */
8026
8027 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
8028
8029 /**
8030 * @}
8031 */
8032
8033 #ifdef __cplusplus
8034 }
8035 #endif
8036
8037 #endif /* STM32G4xx_LL_ADC_H */
8038
8039 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/