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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_bus.h
blob3e02519a74f26716359505b4c152d661dc2e1369
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
27 * All rights reserved.</center></h2>
28 *
29 * This software component is licensed by ST under BSD 3-Clause license,
30 * the "License"; You may not use this file except in compliance with the
31 * License. You may obtain a copy of the License at:
32 * opensource.org/licenses/BSD-3-Clause
33 *
34 ******************************************************************************
35 */
36
37 /* Define to prevent recursive inclusion -------------------------------------*/
38 #ifndef STM32G4xx_LL_BUS_H
39 #define STM32G4xx_LL_BUS_H
40
41 #ifdef __cplusplus
42 extern "C" {
43 #endif
44
45 /* Includes ------------------------------------------------------------------*/
46 #include "stm32g4xx.h"
47
48 /** @addtogroup STM32G4xx_LL_Driver
49 * @{
50 */
51
52 #if defined(RCC)
53
54 /** @defgroup BUS_LL BUS
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60
61 /* Private constants ---------------------------------------------------------*/
62
63 /* Private macros ------------------------------------------------------------*/
64
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
68 * @{
69 */
70
71 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
72 * @{
73 */
74 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
75 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
76 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
77 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
78 #define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
79 #define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
80 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
81 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
82 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
83 /**
84 * @}
85 */
86
87 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
88 * @{
89 */
90 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
91 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
92 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
93 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
94 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
95 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
96 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
97 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
98 #define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
99 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
100 #define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
101 #if defined(ADC345_COMMON)
102 #define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN
103 #endif /* ADC345_COMMON */
104 #define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
105 #if defined(DAC2)
106 #define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN
107 #endif /* DAC2 */
108 #define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
109 #if defined(DAC4)
110 #define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN
111 #endif /* DAC4 */
112 #if defined(AES)
113 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
114 #endif /* AES */
115 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
116 /**
117 * @}
118 */
119
120 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
121 * @{
122 */
123 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
124 #if defined(FMC_Bank1_R)
125 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
126 #endif /* FMC_Bank1_R */
127 #if defined(QUADSPI)
128 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
129 #endif /* QUADSPI */
130 /**
131 * @}
132 */
133
134 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
135 * @{
136 */
137 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
138 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
139 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
140 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
141 #if defined(TIM5)
142 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
143 #endif /* TIM5 */
144 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
145 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
146 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
147 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
148 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
149 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
150 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
151 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
152 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
153 #if defined(UART4)
154 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
155 #endif /* UART4 */
156 #if defined(UART5)
157 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
158 #endif /* UART5 */
159 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
160 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
161 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
162 #if defined(FDCAN1)
163 #define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
164 #endif /* FDCAN1 */
165 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
166 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
167 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
168 /**
169 * @}
170 */
171
172
173 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
174 * @{
175 */
176 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
177 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
178 #if defined(I2C4)
179 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
180 #endif /* I2C4 */
181 #define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
182 /**
183 * @}
184 */
185
186 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
187 * @{
188 */
189 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
190 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
191 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
192 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
193 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
194 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
195 #if defined(SPI4)
196 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
197 #endif /* SPI4 */
198 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
199 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
200 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
201 #if defined(TIM20)
202 #define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
203 #endif /* TIM20 */
204 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
205 #if defined(HRTIM1)
206 #define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
207 #endif /* HRTIM1 */
208 /**
209 * @}
210 */
211
212 /**
213 * @}
214 */
215
216 /* Exported macro ------------------------------------------------------------*/
217 /* Exported functions --------------------------------------------------------*/
218 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
219 * @{
220 */
221
222 /** @defgroup BUS_LL_EF_AHB1 AHB1
223 * @{
224 */
225
226 /**
227 * @brief Enable AHB1 peripherals clock.
228 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
229 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
230 * AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock\n
231 * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
232 * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
233 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
234 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
235 * @param Periphs This parameter can be a combination of the following values:
236 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
237 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
238 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
239 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
240 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
241 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
242 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
243 * @retval None
244 */
245 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
246 {
247 __IO uint32_t tmpreg;
248 SET_BIT(RCC->AHB1ENR, Periphs);
249 /* Delay after an RCC peripheral clock enabling */
250 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
251 (void)tmpreg;
252 }
253
254 /**
255 * @brief Check if AHB1 peripheral clock is enabled or not
256 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
257 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
258 * AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock\n
259 * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
260 * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
261 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
262 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
263 * @param Periphs This parameter can be a combination of the following values:
264 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
265 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
266 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
267 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
268 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
269 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
270 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
271 * @retval State of Periphs (1 or 0).
272 */
273 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
274 {
275 return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
276 }
277
278 /**
279 * @brief Disable AHB1 peripherals clock.
280 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
281 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
282 * AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock\n
283 * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
284 * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
285 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
286 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
287 * @param Periphs This parameter can be a combination of the following values:
288 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
289 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
290 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
291 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
292 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
293 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
294 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
295 * @retval None
296 */
297 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
298 {
299 CLEAR_BIT(RCC->AHB1ENR, Periphs);
300 }
301
302 /**
303 * @brief Force AHB1 peripherals reset.
304 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
305 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
306 * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset\n
307 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
308 * AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
309 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
310 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
311 * @param Periphs This parameter can be a combination of the following values:
312 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
313 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
314 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
315 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
316 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
317 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
318 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
319 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
320 * @retval None
321 */
322 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
323 {
324 SET_BIT(RCC->AHB1RSTR, Periphs);
325 }
326
327 /**
328 * @brief Release AHB1 peripherals reset.
329 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
330 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
331 * AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset\n
332 * AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
333 * AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
334 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
335 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
336 * @param Periphs This parameter can be a combination of the following values:
337 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
338 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
339 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
340 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
341 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
342 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
343 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
344 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
345 * @retval None
346 */
347 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
348 {
349 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
350 }
351
352 /**
353 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
354 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
355 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
356 * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
357 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
358 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
359 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
360 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
361 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
362 * @param Periphs This parameter can be a combination of the following values:
363 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
364 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
365 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
366 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
367 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
368 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
369 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
370 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
371 * @retval None
372 */
373 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
374 {
375 __IO uint32_t tmpreg;
376 SET_BIT(RCC->AHB1SMENR, Periphs);
377 /* Delay after an RCC peripheral clock enabling */
378 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
379 (void)tmpreg;
380 }
381
382 /**
383 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
384 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
385 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
386 * AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
387 * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
388 * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
389 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
390 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
391 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
392 * @param Periphs This parameter can be a combination of the following values:
393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
394 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
395 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
396 * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
397 * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
398 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
399 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
400 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
401 * @retval None
402 */
403 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
404 {
405 CLEAR_BIT(RCC->AHB1SMENR, Periphs);
406 }
407
408 /**
409 * @}
410 */
411
412 /** @defgroup BUS_LL_EF_AHB2 AHB2
413 * @{
414 */
415
416 /**
417 * @brief Enable AHB2 peripherals clock.
418 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
419 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
420 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
421 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
422 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
423 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
424 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
425 * AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock\n
426 * AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock\n
427 * AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
428 * AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock\n
429 * AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock\n
430 * AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock\n
431 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
432 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
433 * @param Periphs This parameter can be a combination of the following values:
434 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
435 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
436 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
437 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
438 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
439 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
440 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
441 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
442 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
443 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
444 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
445 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
446 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
447 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
448 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
449 *
450 * (*) value not defined in all devices.
451 * @retval None
452 */
453 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
454 {
455 __IO uint32_t tmpreg;
456 SET_BIT(RCC->AHB2ENR, Periphs);
457 /* Delay after an RCC peripheral clock enabling */
458 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
459 (void)tmpreg;
460 }
461
462 /**
463 * @brief Check if AHB2 peripheral clock is enabled or not
464 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
465 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
466 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
467 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
468 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
469 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
470 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
471 * AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
472 * AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock\n
473 * AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
474 * AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock\n
475 * AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock\n
476 * AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock\n
477 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
478 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
479 * @param Periphs This parameter can be a combination of the following values:
480 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
481 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
482 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
483 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
484 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
485 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
486 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
487 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
488 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
489 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
490 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
491 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
492 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
493 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
494 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
495 *
496 * (*) value not defined in all devices.
497 * @retval State of Periphs (1 or 0).
498 */
499 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
500 {
501 return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
502 }
503
504 /**
505 * @brief Disable AHB2 peripherals clock.
506 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
507 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
508 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
509 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
510 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
511 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
512 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
513 * AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock\n
514 * AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock\n
515 * AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
516 * AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock\n
517 * AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock\n
518 * AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock\n
519 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
520 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
521 * @param Periphs This parameter can be a combination of the following values:
522 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
523 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
524 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
525 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
526 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
527 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
528 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
529 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
530 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
531 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
532 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
533 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
534 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
535 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
536 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
537 *
538 * (*) value not defined in all devices.
539 * @retval None
540 */
541 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
542 {
543 CLEAR_BIT(RCC->AHB2ENR, Periphs);
544 }
545
546 /**
547 * @brief Force AHB2 peripherals reset.
548 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
549 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
550 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
551 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
552 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
553 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
554 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
555 * AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset\n
556 * AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset\n
557 * AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset\n
558 * AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset\n
559 * AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset\n
560 * AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset\n
561 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
562 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
563 * @param Periphs This parameter can be a combination of the following values:
564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
565 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
566 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
567 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
568 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
569 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
570 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
571 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
572 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
573 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
574 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
575 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
576 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
577 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
578 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
579 *
580 * (*) value not defined in all devices.
581 * @retval None
582 */
583 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
584 {
585 SET_BIT(RCC->AHB2RSTR, Periphs);
586 }
587
588 /**
589 * @brief Release AHB2 peripherals reset.
590 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
591 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
592 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
593 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
594 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
595 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
596 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
597 * AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset\n
598 * AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset\n
599 * AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset\n
600 * AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset\n
601 * AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset\n
602 * AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset\n
603 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
604 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
605 * @param Periphs This parameter can be a combination of the following values:
606 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
613 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
614 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
615 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
616 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
617 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
618 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
619 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
620 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
621 *
622 * (*) value not defined in all devices.
623 * @retval None
624 */
625 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
626 {
627 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
628 }
629
630 /**
631 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
632 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
633 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
634 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
635 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
636 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
637 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
638 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
639 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
640 * AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
641 * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
642 * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
643 * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
644 * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
645 * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
646 * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
647 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
648 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
649 * @param Periphs This parameter can be a combination of the following values:
650 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
651 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
652 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
653 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
654 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
655 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
656 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
657 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
658 * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
659 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
660 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
661 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
662 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
663 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
664 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
665 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
666 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
667 *
668 * (*) value not defined in all devices.
669 * @retval None
670 */
671 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
672 {
673 __IO uint32_t tmpreg;
674 SET_BIT(RCC->AHB2SMENR, Periphs);
675 /* Delay after an RCC peripheral clock enabling */
676 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
677 (void)tmpreg;
678 }
679
680 /**
681 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
682 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
683 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
684 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
685 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
686 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
687 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
688 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
689 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
690 * AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
691 * AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
692 * AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
693 * AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
694 * AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
695 * AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
696 * AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
697 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
698 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
699 * @param Periphs This parameter can be a combination of the following values:
700 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
701 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
702 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
703 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
704 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
705 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
706 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
707 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
708 * @arg @ref LL_AHB2_GRP1_PERIPH_CCM
709 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
710 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
711 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
712 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
713 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
714 * @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
715 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
716 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
717 *
718 * (*) value not defined in all devices.
719 * @retval None
720 */
721 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
722 {
723 CLEAR_BIT(RCC->AHB2SMENR, Periphs);
724 }
725
726 /**
727 * @}
728 */
729
730 /** @defgroup BUS_LL_EF_AHB3 AHB3
731 * @{
732 */
733
734 /**
735 * @brief Enable AHB3 peripherals clock.
736 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
737 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
738 * @param Periphs This parameter can be a combination of the following values:
739 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
740 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
741 *
742 * (*) value not defined in all devices.
743 * @retval None
744 */
745 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
746 {
747 __IO uint32_t tmpreg;
748 SET_BIT(RCC->AHB3ENR, Periphs);
749 /* Delay after an RCC peripheral clock enabling */
750 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
751 (void)tmpreg;
752 }
753
754 /**
755 * @brief Check if AHB3 peripheral clock is enabled or not
756 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
757 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
758 * @param Periphs This parameter can be a combination of the following values:
759 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
760 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
761 *
762 * (*) value not defined in all devices.
763 * @retval State of Periphs (1 or 0).
764 */
765 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
766 {
767 return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
768 }
769
770 /**
771 * @brief Disable AHB3 peripherals clock.
772 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
773 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
774 * @param Periphs This parameter can be a combination of the following values:
775 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
776 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
777 *
778 * (*) value not defined in all devices.
779 * @retval None
780 */
781 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
782 {
783 CLEAR_BIT(RCC->AHB3ENR, Periphs);
784 }
785
786 /**
787 * @brief Force AHB3 peripherals reset.
788 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
789 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
790 * @param Periphs This parameter can be a combination of the following values:
791 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
792 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
793 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
794 *
795 * (*) value not defined in all devices.
796 * @retval None
797 */
798 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
799 {
800 SET_BIT(RCC->AHB3RSTR, Periphs);
801 }
802
803 /**
804 * @brief Release AHB3 peripherals reset.
805 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
806 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
807 * @param Periphs This parameter can be a combination of the following values:
808 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
809 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
810 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
811 *
812 * (*) value not defined in all devices.
813 * @retval None
814 */
815 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
816 {
817 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
818 }
819
820 /**
821 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
822 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
823 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
824 * @param Periphs This parameter can be a combination of the following values:
825 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
826 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
827 *
828 * (*) value not defined in all devices.
829 * @retval None
830 */
831 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
832 {
833 __IO uint32_t tmpreg;
834 SET_BIT(RCC->AHB3SMENR, Periphs);
835 /* Delay after an RCC peripheral clock enabling */
836 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
837 (void)tmpreg;
838 }
839
840 /**
841 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
842 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
843 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
844 * @param Periphs This parameter can be a combination of the following values:
845 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
846 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
847 *
848 * (*) value not defined in all devices.
849 * @retval None
850 */
851 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
852 {
853 CLEAR_BIT(RCC->AHB3SMENR, Periphs);
854 }
855
856 /**
857 * @}
858 */
859
860 /** @defgroup BUS_LL_EF_APB1 APB1
861 * @{
862 */
863
864 /**
865 * @brief Enable APB1 peripherals clock.
866 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
867 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
868 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
869 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
870 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
871 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
872 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
873 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
874 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
875 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
876 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
877 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
878 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
879 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
880 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
881 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
882 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
883 * APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
884 * APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
885 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
886 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
887 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
888 * @param Periphs This parameter can be a combination of the following values:
889 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
890 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
891 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
892 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
893 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
894 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
895 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
896 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
897 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
898 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
899 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
900 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
901 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
902 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
903 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
904 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
905 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
906 * @arg @ref LL_APB1_GRP1_PERIPH_USB
907 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
908 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
909 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
910 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
911 *
912 * (*) value not defined in all devices.
913 * @retval None
914 */
915 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
916 {
917 __IO uint32_t tmpreg;
918 SET_BIT(RCC->APB1ENR1, Periphs);
919 /* Delay after an RCC peripheral clock enabling */
920 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
921 (void)tmpreg;
922 }
923
924 /**
925 * @brief Enable APB1 peripherals clock.
926 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
927 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
928 * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
929 * @param Periphs This parameter can be a combination of the following values:
930 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
931 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
932 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
933 *
934 * (*) value not defined in all devices.
935 * @retval None
936 */
937 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
938 {
939 __IO uint32_t tmpreg;
940 SET_BIT(RCC->APB1ENR2, Periphs);
941 /* Delay after an RCC peripheral clock enabling */
942 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
943 (void)tmpreg;
944 }
945
946 /**
947 * @brief Check if APB1 peripheral clock is enabled or not
948 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
949 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
950 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
951 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
952 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
953 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
954 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
955 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
956 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
957 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
958 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
959 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
960 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
961 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
962 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
963 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
964 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
965 * APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
966 * APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
967 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
968 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
969 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
970 * @param Periphs This parameter can be a combination of the following values:
971 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
972 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
973 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
974 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
975 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
976 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
977 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
978 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
979 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
980 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
981 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
982 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
983 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
984 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
985 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
986 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
987 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
988 * @arg @ref LL_APB1_GRP1_PERIPH_USB
989 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
990 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
991 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
992 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
993 *
994 * (*) value not defined in all devices.
995 * @retval State of Periphs (1 or 0).
996 */
997 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
998 {
999 return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
1000 }
1001
1002 /**
1003 * @brief Check if APB1 peripheral clock is enabled or not
1004 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
1005 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
1006 * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
1007 * @param Periphs This parameter can be a combination of the following values:
1008 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1009 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1010 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1011 *
1012 * (*) value not defined in all devices.
1013 * @retval State of Periphs (1 or 0).
1014 */
1015 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
1016 {
1017 return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
1018 }
1019
1020 /**
1021 * @brief Disable APB1 peripherals clock.
1022 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
1023 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
1024 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
1025 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
1026 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
1027 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
1028 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
1029 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
1030 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
1031 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
1032 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
1033 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
1034 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
1035 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
1036 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
1037 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
1038 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
1039 * APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
1040 * APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
1041 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
1042 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
1043 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
1044 * @param Periphs This parameter can be a combination of the following values:
1045 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1046 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1047 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1048 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1049 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1050 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1051 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1052 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1053 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1054 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1055 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1056 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1057 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1058 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1059 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1060 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1061 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1062 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1063 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1064 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1065 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1066 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1067 *
1068 * (*) value not defined in all devices.
1069 * @retval None
1070 */
1071 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1072 {
1073 CLEAR_BIT(RCC->APB1ENR1, Periphs);
1074 }
1075
1076 /**
1077 * @brief Disable APB1 peripherals clock.
1078 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
1079 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
1080 * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
1081 * @param Periphs This parameter can be a combination of the following values:
1082 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1083 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1084 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1085 *
1086 * (*) value not defined in all devices.
1087 * @retval None
1088 */
1089 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
1090 {
1091 CLEAR_BIT(RCC->APB1ENR2, Periphs);
1092 }
1093
1094 /**
1095 * @brief Force APB1 peripherals reset.
1096 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
1097 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
1098 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
1099 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
1100 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
1101 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
1102 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
1103 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
1104 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
1105 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
1106 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
1107 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
1108 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
1109 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
1110 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
1111 * APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
1112 * APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
1113 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
1114 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
1115 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
1116 * @param Periphs This parameter can be a combination of the following values:
1117 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1118 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1119 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1120 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1121 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1122 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1123 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1124 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1125 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1126 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1127 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1128 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1129 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1130 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1131 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1132 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1133 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1134 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1135 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1136 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1137 *
1138 * (*) value not defined in all devices.
1139 * @retval None
1140 */
1141 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1142 {
1143 SET_BIT(RCC->APB1RSTR1, Periphs);
1144 }
1145
1146 /**
1147 * @brief Force APB1 peripherals reset.
1148 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
1149 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
1150 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
1151 * @param Periphs This parameter can be a combination of the following values:
1152 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1153 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1154 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1155 *
1156 * (*) value not defined in all devices.
1157 * @retval None
1158 */
1159 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
1160 {
1161 SET_BIT(RCC->APB1RSTR2, Periphs);
1162 }
1163
1164 /**
1165 * @brief Release APB1 peripherals reset.
1166 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
1167 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
1168 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
1169 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
1170 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
1171 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
1172 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
1173 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
1174 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
1175 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
1176 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
1177 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
1178 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
1179 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
1180 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
1181 * APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
1182 * APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
1183 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
1184 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
1185 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
1186 * @param Periphs This parameter can be a combination of the following values:
1187 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1188 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1189 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1190 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1191 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1192 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1193 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1194 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1195 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1196 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1197 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1198 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1199 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1200 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1201 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1202 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1203 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1204 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1205 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1206 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1207 *
1208 * (*) value not defined in all devices.
1209 * @retval None
1210 */
1211 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1212 {
1213 CLEAR_BIT(RCC->APB1RSTR1, Periphs);
1214 }
1215
1216 /**
1217 * @brief Release APB1 peripherals reset.
1218 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
1219 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
1220 * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
1221 * @param Periphs This parameter can be a combination of the following values:
1222 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1223 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1224 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
1225 *
1226 * (*) value not defined in all devices.
1227 * @retval None
1228 */
1229 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
1230 {
1231 CLEAR_BIT(RCC->APB1RSTR2, Periphs);
1232 }
1233
1234 /**
1235 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1236 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1237 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1238 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1239 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1240 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1241 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1242 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1243 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1244 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1245 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1246 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1247 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1248 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1249 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1250 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1251 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1252 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1253 * APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1254 * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1255 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
1256 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
1257 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
1258 * @param Periphs This parameter can be a combination of the following values:
1259 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1260 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1261 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1262 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1263 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1264 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1265 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1266 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1267 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1268 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1269 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1270 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1271 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1272 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1273 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1274 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1275 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1276 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1277 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1278 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1279 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1280 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1281 *
1282 * (*) value not defined in all devices.
1283 * @retval None
1284 */
1285 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
1286 {
1287 __IO uint32_t tmpreg;
1288 SET_BIT(RCC->APB1SMENR1, Periphs);
1289 /* Delay after an RCC peripheral clock enabling */
1290 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
1291 (void)tmpreg;
1292 }
1293
1294 /**
1295 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes
1296 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1297 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
1298 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
1299 * @param Periphs This parameter can be a combination of the following values:
1300 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1301 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1302 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1303 *
1304 * (*) value not defined in all devices.
1305 * @retval None
1306 */
1307 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
1308 {
1309 __IO uint32_t tmpreg;
1310 SET_BIT(RCC->APB1SMENR2, Periphs);
1311 /* Delay after an RCC peripheral clock enabling */
1312 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
1313 (void)tmpreg;
1314 }
1315
1316 /**
1317 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1318 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1319 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1320 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1321 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1322 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1323 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1324 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1325 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1326 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1327 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1328 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1329 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1330 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1331 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1332 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1333 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1334 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1335 * APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1336 * APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1337 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
1338 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
1339 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
1340 * @param Periphs This parameter can be a combination of the following values:
1341 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1342 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1343 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1344 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
1345 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1346 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1347 * @arg @ref LL_APB1_GRP1_PERIPH_CRS
1348 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
1349 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1350 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1351 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1352 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1353 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1354 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1355 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1356 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1357 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1358 * @arg @ref LL_APB1_GRP1_PERIPH_USB
1359 * @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
1360 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1361 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1362 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1363 *
1364 * (*) value not defined in all devices.
1365 * @retval None
1366 */
1367 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
1368 {
1369 CLEAR_BIT(RCC->APB1SMENR1, Periphs);
1370 }
1371
1372 /**
1373 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes
1374 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1375 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
1376 * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
1377 * @param Periphs This parameter can be a combination of the following values:
1378 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
1379 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
1380 * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
1381 *
1382 * (*) value not defined in all devices.
1383 * @retval None
1384 */
1385 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
1386 {
1387 CLEAR_BIT(RCC->APB1SMENR2, Periphs);
1388 }
1389
1390 /**
1391 * @}
1392 */
1393
1394 /** @defgroup BUS_LL_EF_APB2 APB2
1395 * @{
1396 */
1397
1398 /**
1399 * @brief Enable APB2 peripherals clock.
1400 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1401 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1402 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1403 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1404 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1405 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1406 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
1407 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
1408 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
1409 * APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
1410 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1411 * APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
1412 * @param Periphs This parameter can be a combination of the following values:
1413 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1414 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1415 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1416 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1417 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1418 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1419 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1420 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1421 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1422 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1423 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1424 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1425 *
1426 * (*) value not defined in all devices.
1427 * @retval None
1428 */
1429 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1430 {
1431 __IO uint32_t tmpreg;
1432 SET_BIT(RCC->APB2ENR, Periphs);
1433 /* Delay after an RCC peripheral clock enabling */
1434 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1435 (void)tmpreg;
1436 }
1437
1438 /**
1439 * @brief Check if APB2 peripheral clock is enabled or not
1440 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1441 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1442 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1443 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1444 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1445 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1446 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
1447 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
1448 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
1449 * APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
1450 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1451 * APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
1452 * @param Periphs This parameter can be a combination of the following values:
1453 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1454 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1455 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1456 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1457 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1458 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1459 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1460 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1461 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1462 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1463 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1464 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1465 *
1466 * (*) value not defined in all devices.
1467 * @retval State of Periphs (1 or 0).
1468 */
1469 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1470 {
1471 return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
1472 }
1473
1474 /**
1475 * @brief Disable APB2 peripherals clock.
1476 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1477 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1478 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1479 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1480 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1481 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1482 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
1483 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
1484 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
1485 * APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
1486 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1487 * APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
1488 * @param Periphs This parameter can be a combination of the following values:
1489 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1490 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1491 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1492 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1493 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1494 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1495 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1496 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1497 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1498 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1499 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1500 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1501 *
1502 * (*) value not defined in all devices.
1503 * @retval None
1504 */
1505 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1506 {
1507 CLEAR_BIT(RCC->APB2ENR, Periphs);
1508 }
1509
1510 /**
1511 * @brief Force APB2 peripherals reset.
1512 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1513 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1514 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1515 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1516 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1517 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1518 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1519 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1520 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1521 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
1522 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1523 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
1524 * @param Periphs This parameter can be a combination of the following values:
1525 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1526 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1527 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1528 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1529 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1530 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1531 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1532 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1533 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1534 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1535 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1536 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1537 *
1538 * (*) value not defined in all devices.
1539 * @retval None
1540 */
1541 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1542 {
1543 SET_BIT(RCC->APB2RSTR, Periphs);
1544 }
1545
1546 /**
1547 * @brief Release APB2 peripherals reset.
1548 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1549 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1550 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1551 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1552 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1553 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1554 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
1555 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
1556 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
1557 * APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
1558 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1559 * APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
1560 * @param Periphs This parameter can be a combination of the following values:
1561 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1562 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1563 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1564 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1565 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1566 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1567 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1568 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1569 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1570 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1571 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1572 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1573 *
1574 * (*) value not defined in all devices.
1575 * @retval None
1576 */
1577 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1578 {
1579 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1580 }
1581
1582 /**
1583 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes
1584 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
1585 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1586 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1587 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1588 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1589 * APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1590 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1591 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1592 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1593 * APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1594 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
1595 * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
1596 * @param Periphs This parameter can be a combination of the following values:
1597 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1598 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1599 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1600 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1601 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1602 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1603 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1604 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1605 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1606 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1607 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1608 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1609 *
1610 * (*) value not defined in all devices.
1611 * @retval None
1612 */
1613 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
1614 {
1615 __IO uint32_t tmpreg;
1616 SET_BIT(RCC->APB2SMENR, Periphs);
1617 /* Delay after an RCC peripheral clock enabling */
1618 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
1619 (void)tmpreg;
1620 }
1621
1622 /**
1623 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes
1624 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
1625 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1626 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1627 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1628 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1629 * APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1630 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1631 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1632 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1633 * APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1634 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
1635 * APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
1636 * @param Periphs This parameter can be a combination of the following values:
1637 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1638 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1639 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1640 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1641 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1642 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1643 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15
1644 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16
1645 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17
1646 * @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
1647 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1648 * @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
1649 *
1650 * (*) value not defined in all devices.
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
1654 {
1655 CLEAR_BIT(RCC->APB2SMENR, Periphs);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662
1663 /**
1664 * @}
1665 */
1666
1667 /**
1668 * @}
1669 */
1670
1671 #endif /* defined(RCC) */
1672
1673 /**
1674 * @}
1675 */
1676
1677 #ifdef __cplusplus
1678 }
1679 #endif
1680
1681 #endif /* STM32G4xx_LL_BUS_H */
1682
1683 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/