lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_crs.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of CRS LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Define to prevent recursive inclusion -------------------------------------*/
  21 #ifndef __STM32G4xx_LL_CRS_H
  22 #define __STM32G4xx_LL_CRS_H
  23
  24 #ifdef __cplusplus
  25 extern "C" {
  26 #endif
  27
  28 /* Includes ------------------------------------------------------------------*/
  29 #include "stm32g4xx.h"
  30
  31 /** @addtogroup STM32G4xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined(CRS)
  36
  37 /** @defgroup CRS_LL CRS
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45
  46 /* Exported types ------------------------------------------------------------*/
  47 /* Exported constants --------------------------------------------------------*/
  48 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
  49   * @{
  50   */
  51
  52 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
  53   * @brief    Flags defines which can be used with LL_CRS_ReadReg function
  54   * @{
  55   */
  56 #define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF
  57 #define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF
  58 #define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF
  59 #define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF
  60 #define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR
  61 #define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS
  62 #define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF
  63 /**
  64   * @}
  65   */
  66
  67 /** @defgroup CRS_LL_EC_IT IT Defines
  68   * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions
  69   * @{
  70   */
  71 #define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE
  72 #define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE
  73 #define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE
  74 #define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE
  75 /**
  76   * @}
  77   */
  78
  79 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
  80   * @{
  81   */
  82 #define LL_CRS_SYNC_DIV_1                  ((uint32_t)0x00U)                         /*!< Synchro Signal not divided (default) */
  83 #define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */
  84 #define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */
  85 #define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
  86 #define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */
  87 #define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
  88 #define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
  89 #define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
  90 /**
  91   * @}
  92   */
  93
  94 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
  95   * @{
  96   */
  97 #define LL_CRS_SYNC_SOURCE_GPIO            ((uint32_t)0x00U)       /*!< Synchro Signal soucre GPIO */
  98 #define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
  99 #define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
 100 /**
 101   * @}
 102   */
 103
 104 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
 105   * @{
 106   */
 107 #define LL_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00U)     /*!< Synchro Active on rising edge (default) */
 108 #define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
 109 /**
 110   * @}
 111   */
 112
 113 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
 114   * @{
 115   */
 116 #define LL_CRS_FREQ_ERROR_DIR_UP             ((uint32_t)0x00U)         /*!< Upcounting direction, the actual frequency is above the target */
 117 #define LL_CRS_FREQ_ERROR_DIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
 118 /**
 119   * @}
 120   */
 121
 122 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
 123   * @{
 124   */
 125 /**
 126   * @brief Reset value of the RELOAD field
 127   * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
 128   *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)
 129   */
 130 #define LL_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7FU)
 131
 132 /**
 133   * @brief Reset value of Frequency error limit.
 134   */
 135 #define LL_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22U)
 136
 137 /**
 138   * @brief Reset value of the HSI48 Calibration field
 139   * @note The default value is 64, which corresponds to the middle of the trimming interval.
 140   *       The trimming step is specified in the product datasheet.
 141   *       A higher TRIM value corresponds to a higher output frequency
 142   */
 143 #define LL_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x40U)
 144 /**
 145   * @}
 146   */
 147 /**
 148   * @}
 149   */
 150
 151 /* Exported macro ------------------------------------------------------------*/
 152 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
 153   * @{
 154   */
 155
 156 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
 157   * @{
 158   */
 159
 160 /**
 161   * @brief  Write a value in CRS register
 162   * @param  __INSTANCE__ CRS Instance
 163   * @param  __REG__ Register to be written
 164   * @param  __VALUE__ Value to be written in the register
 165   * @retval None
 166   */
 167 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
 168
 169 /**
 170   * @brief  Read a value in CRS register
 171   * @param  __INSTANCE__ CRS Instance
 172   * @param  __REG__ Register to be read
 173   * @retval Register value
 174   */
 175 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
 176 /**
 177   * @}
 178   */
 179
 180 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
 181   * @{
 182   */
 183
 184 /**
 185   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
 186   * @note   The RELOAD value should be selected according to the ratio between
 187   *         the target frequency and the frequency of the synchronization source after
 188   *         prescaling. It is then decreased by one in order to reach the expected
 189   *         synchronization on the zero value. The formula is the following:
 190   *              RELOAD = (fTARGET / fSYNC) -1
 191   * @param  __FTARGET__ Target frequency (value in Hz)
 192   * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
 193   * @retval Reload value (in Hz)
 194   */
 195 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
 196
 197 /**
 198   * @}
 199   */
 200
 201 /**
 202   * @}
 203   */
 204
 205 /* Exported functions --------------------------------------------------------*/
 206 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
 207   * @{
 208   */
 209
 210 /** @defgroup CRS_LL_EF_Configuration Configuration
 211   * @{
 212   */
 213
 214 /**
 215   * @brief  Enable Frequency error counter
 216   * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
 217   * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter
 218   * @retval None
 219   */
 220 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
 221 {
 222   SET_BIT(CRS->CR, CRS_CR_CEN);
 223 }
 224
 225 /**
 226   * @brief  Disable Frequency error counter
 227   * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter
 228   * @retval None
 229   */
 230 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
 231 {
 232   CLEAR_BIT(CRS->CR, CRS_CR_CEN);
 233 }
 234
 235 /**
 236   * @brief  Check if Frequency error counter is enabled or not
 237   * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter
 238   * @retval State of bit (1 or 0).
 239   */
 240 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
 241 {
 242   return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
 243 }
 244
 245 /**
 246   * @brief  Enable Automatic trimming counter
 247   * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming
 248   * @retval None
 249   */
 250 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
 251 {
 252   SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
 253 }
 254
 255 /**
 256   * @brief  Disable Automatic trimming counter
 257   * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming
 258   * @retval None
 259   */
 260 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
 261 {
 262   CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
 263 }
 264
 265 /**
 266   * @brief  Check if Automatic trimming is enabled or not
 267   * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming
 268   * @retval State of bit (1 or 0).
 269   */
 270 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
 271 {
 272   return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
 273 }
 274
 275 /**
 276   * @brief  Set HSI48 oscillator smooth trimming
 277   * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
 278   * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming
 279   * @param  Value a number between Min_Data = 0 and Max_Data = 63
 280   * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
 281   * @retval None
 282   */
 283 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
 284 {
 285   MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
 286 }
 287
 288 /**
 289   * @brief  Get HSI48 oscillator smooth trimming
 290   * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming
 291   * @retval a number between Min_Data = 0 and Max_Data = 63
 292   */
 293 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
 294 {
 295   return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
 296 }
 297
 298 /**
 299   * @brief  Set counter reload value
 300   * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter
 301   * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF
 302   * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
 303   *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
 304   * @retval None
 305   */
 306 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
 307 {
 308   MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
 309 }
 310
 311 /**
 312   * @brief  Get counter reload value
 313   * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter
 314   * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
 315   */
 316 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
 317 {
 318   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
 319 }
 320
 321 /**
 322   * @brief  Set frequency error limit
 323   * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit
 324   * @param  Value a number between Min_Data = 0 and Max_Data = 255
 325   * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
 326   * @retval None
 327   */
 328 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
 329 {
 330   MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
 331 }
 332
 333 /**
 334   * @brief  Get frequency error limit
 335   * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit
 336   * @retval A number between Min_Data = 0 and Max_Data = 255
 337   */
 338 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
 339 {
 340   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
 341 }
 342
 343 /**
 344   * @brief  Set division factor for SYNC signal
 345   * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider
 346   * @param  Divider This parameter can be one of the following values:
 347   *         @arg @ref LL_CRS_SYNC_DIV_1
 348   *         @arg @ref LL_CRS_SYNC_DIV_2
 349   *         @arg @ref LL_CRS_SYNC_DIV_4
 350   *         @arg @ref LL_CRS_SYNC_DIV_8
 351   *         @arg @ref LL_CRS_SYNC_DIV_16
 352   *         @arg @ref LL_CRS_SYNC_DIV_32
 353   *         @arg @ref LL_CRS_SYNC_DIV_64
 354   *         @arg @ref LL_CRS_SYNC_DIV_128
 355   * @retval None
 356   */
 357 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
 358 {
 359   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
 360 }
 361
 362 /**
 363   * @brief  Get division factor for SYNC signal
 364   * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider
 365   * @retval Returned value can be one of the following values:
 366   *         @arg @ref LL_CRS_SYNC_DIV_1
 367   *         @arg @ref LL_CRS_SYNC_DIV_2
 368   *         @arg @ref LL_CRS_SYNC_DIV_4
 369   *         @arg @ref LL_CRS_SYNC_DIV_8
 370   *         @arg @ref LL_CRS_SYNC_DIV_16
 371   *         @arg @ref LL_CRS_SYNC_DIV_32
 372   *         @arg @ref LL_CRS_SYNC_DIV_64
 373   *         @arg @ref LL_CRS_SYNC_DIV_128
 374   */
 375 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
 376 {
 377   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
 378 }
 379
 380 /**
 381   * @brief  Set SYNC signal source
 382   * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource
 383   * @param  Source This parameter can be one of the following values:
 384   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
 385   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
 386   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
 387   * @retval None
 388   */
 389 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
 390 {
 391   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
 392 }
 393
 394 /**
 395   * @brief  Get SYNC signal source
 396   * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource
 397   * @retval Returned value can be one of the following values:
 398   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO
 399   *         @arg @ref LL_CRS_SYNC_SOURCE_LSE
 400   *         @arg @ref LL_CRS_SYNC_SOURCE_USB
 401   */
 402 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
 403 {
 404   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
 405 }
 406
 407 /**
 408   * @brief  Set input polarity for the SYNC signal source
 409   * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity
 410   * @param  Polarity This parameter can be one of the following values:
 411   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
 412   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
 413   * @retval None
 414   */
 415 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
 416 {
 417   MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
 418 }
 419
 420 /**
 421   * @brief  Get input polarity for the SYNC signal source
 422   * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity
 423   * @retval Returned value can be one of the following values:
 424   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING
 425   *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING
 426   */
 427 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
 428 {
 429   return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
 430 }
 431
 432 /**
 433   * @brief  Configure CRS for the synchronization
 434   * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n
 435   *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n
 436   *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n
 437   *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n
 438   *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n
 439   *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization
 440   * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
 441   * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
 442   * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255
 443   * @param  Settings This parameter can be a combination of the following values:
 444   *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
 445   *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
 446   *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
 447   *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
 448   * @retval None
 449   */
 450 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
 451                                                   uint32_t ReloadValue, uint32_t Settings)
 452 {
 453   MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
 454   MODIFY_REG(CRS->CFGR,
 455              CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
 456              ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
 457 }
 458
 459 /**
 460   * @}
 461   */
 462
 463 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
 464   * @{
 465   */
 466
 467 /**
 468   * @brief  Generate software SYNC event
 469   * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC
 470   * @retval None
 471   */
 472 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
 473 {
 474   SET_BIT(CRS->CR, CRS_CR_SWSYNC);
 475 }
 476
 477 /**
 478   * @brief  Get the frequency error direction latched in the time of the last
 479   * SYNC event
 480   * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection
 481   * @retval Returned value can be one of the following values:
 482   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
 483   *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
 484   */
 485 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
 486 {
 487   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
 488 }
 489
 490 /**
 491   * @brief  Get the frequency error counter value latched in the time of the last SYNC event
 492   * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture
 493   * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
 494   */
 495 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
 496 {
 497   return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
 498 }
 499
 500 /**
 501   * @}
 502   */
 503
 504 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
 505   * @{
 506   */
 507
 508 /**
 509   * @brief  Check if SYNC event OK signal occurred or not
 510   * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK
 511   * @retval State of bit (1 or 0).
 512   */
 513 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
 514 {
 515   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
 516 }
 517
 518 /**
 519   * @brief  Check if SYNC warning signal occurred or not
 520   * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN
 521   * @retval State of bit (1 or 0).
 522   */
 523 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
 524 {
 525   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
 526 }
 527
 528 /**
 529   * @brief  Check if Synchronization or trimming error signal occurred or not
 530   * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR
 531   * @retval State of bit (1 or 0).
 532   */
 533 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
 534 {
 535   return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
 536 }
 537
 538 /**
 539   * @brief  Check if Expected SYNC signal occurred or not
 540   * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC
 541   * @retval State of bit (1 or 0).
 542   */
 543 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
 544 {
 545   return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
 546 }
 547
 548 /**
 549   * @brief  Check if SYNC error signal occurred or not
 550   * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR
 551   * @retval State of bit (1 or 0).
 552   */
 553 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
 554 {
 555   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
 556 }
 557
 558 /**
 559   * @brief  Check if SYNC missed error signal occurred or not
 560   * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS
 561   * @retval State of bit (1 or 0).
 562   */
 563 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
 564 {
 565   return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
 566 }
 567
 568 /**
 569   * @brief  Check if Trimming overflow or underflow occurred or not
 570   * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF
 571   * @retval State of bit (1 or 0).
 572   */
 573 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
 574 {
 575   return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
 576 }
 577
 578 /**
 579   * @brief  Clear the SYNC event OK flag
 580   * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK
 581   * @retval None
 582   */
 583 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
 584 {
 585   WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
 586 }
 587
 588 /**
 589   * @brief  Clear the  SYNC warning flag
 590   * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN
 591   * @retval None
 592   */
 593 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
 594 {
 595   WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
 596 }
 597
 598 /**
 599   * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
 600   * the ERR flag
 601   * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR
 602   * @retval None
 603   */
 604 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
 605 {
 606   WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
 607 }
 608
 609 /**
 610   * @brief  Clear Expected SYNC flag
 611   * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC
 612   * @retval None
 613   */
 614 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
 615 {
 616   WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
 617 }
 618
 619 /**
 620   * @}
 621   */
 622
 623 /** @defgroup CRS_LL_EF_IT_Management IT_Management
 624   * @{
 625   */
 626
 627 /**
 628   * @brief  Enable SYNC event OK interrupt
 629   * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK
 630   * @retval None
 631   */
 632 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
 633 {
 634   SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
 635 }
 636
 637 /**
 638   * @brief  Disable SYNC event OK interrupt
 639   * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK
 640   * @retval None
 641   */
 642 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
 643 {
 644   CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
 645 }
 646
 647 /**
 648   * @brief  Check if SYNC event OK interrupt is enabled or not
 649   * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK
 650   * @retval State of bit (1 or 0).
 651   */
 652 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
 653 {
 654   return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
 655 }
 656
 657 /**
 658   * @brief  Enable SYNC warning interrupt
 659   * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN
 660   * @retval None
 661   */
 662 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
 663 {
 664   SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
 665 }
 666
 667 /**
 668   * @brief  Disable SYNC warning interrupt
 669   * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN
 670   * @retval None
 671   */
 672 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
 673 {
 674   CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
 675 }
 676
 677 /**
 678   * @brief  Check if SYNC warning interrupt is enabled or not
 679   * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN
 680   * @retval State of bit (1 or 0).
 681   */
 682 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
 683 {
 684   return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
 685 }
 686
 687 /**
 688   * @brief  Enable Synchronization or trimming error interrupt
 689   * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR
 690   * @retval None
 691   */
 692 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
 693 {
 694   SET_BIT(CRS->CR, CRS_CR_ERRIE);
 695 }
 696
 697 /**
 698   * @brief  Disable Synchronization or trimming error interrupt
 699   * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR
 700   * @retval None
 701   */
 702 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
 703 {
 704   CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
 705 }
 706
 707 /**
 708   * @brief  Check if Synchronization or trimming error interrupt is enabled or not
 709   * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR
 710   * @retval State of bit (1 or 0).
 711   */
 712 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
 713 {
 714   return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
 715 }
 716
 717 /**
 718   * @brief  Enable Expected SYNC interrupt
 719   * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC
 720   * @retval None
 721   */
 722 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
 723 {
 724   SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
 725 }
 726
 727 /**
 728   * @brief  Disable Expected SYNC interrupt
 729   * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC
 730   * @retval None
 731   */
 732 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
 733 {
 734   CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
 735 }
 736
 737 /**
 738   * @brief  Check if Expected SYNC interrupt is enabled or not
 739   * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC
 740   * @retval State of bit (1 or 0).
 741   */
 742 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
 743 {
 744   return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
 745 }
 746
 747 /**
 748   * @}
 749   */
 750
 751 #if defined(USE_FULL_LL_DRIVER)
 752 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
 753   * @{
 754   */
 755
 756 ErrorStatus LL_CRS_DeInit(void);
 757
 758 /**
 759   * @}
 760   */
 761 #endif /* USE_FULL_LL_DRIVER */
 762
 763 /**
 764   * @}
 765   */
 766
 767 /**
 768   * @}
 769   */
 770
 771 #endif /* defined(CRS) */
 772
 773 /**
 774   * @}
 775   */
 776
 777 #ifdef __cplusplus
 778 }
 779 #endif
 780
 781 #endif /* __STM32G4xx_LL_CRS_H */
 782
 783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/