| blob | 4d8f54469d882211aba189db52b5dd0a9de85250 |
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_dac.h
4 * @author MCD Application Team
5 * @brief Header file of DAC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_DAC_H
22 #define STM32G4xx_LL_DAC_H
24 #ifdef __cplusplus
26 #endif
28 /* Includes ------------------------------------------------------------------*/
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
35 #if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
37 /** @defgroup DAC_LL DAC
38 * @{
39 */
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup DAC_LL_Private_Constants DAC Private Constants
46 * @{
47 */
49 /* Internal masks for DAC channels definition */
50 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
51 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR */
52 /* - channel bits position into register SWTRIG */
53 /* - channel bits position into register SWTRIGB */
54 /* - channel register offset of data holding register DHRx */
55 /* - channel register offset of data output register DORx */
56 /* - channel register offset of sample-and-hold sample time register SHSRx */
57 /* - channel register offset of sawtooth register STRx */
59 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
60 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
61 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
65 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
67 #define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
68 #define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
69 #define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
71 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */
72 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
73 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
74 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
75 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
76 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
77 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000U
78 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
79 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U
80 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
83 #define DAC_REG_DOR2_REGOFFSET 0x00000020U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */
84 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
87 #define DAC_REG_SHSR2_REGOFFSET 0x00000040U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */
88 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
91 #define DAC_REG_STR2_REGOFFSET 0x00000080U /* Register offset of STRx channel 1 versus STRx channel 2 (shifted left of 7 bits) */
92 #define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
94 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FU /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
95 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of DORx registers offset when shifted to position 0 */
96 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of SHSRx registers offset when shifted to position 0 */
97 #define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001U /* Mask of STRx registers offset when shifted to position 0 */
99 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28U /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */
100 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20U /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
101 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24U /* Position of bits register offset of DHR8Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
102 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5U /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */
103 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6U /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */
104 #define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7U /* Position of bits register offset of STRx channel 1 or 2 versus STRx channel 1 (shifted left of 7 bits) */
106 /* DAC registers bits positions */
107 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
108 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
109 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
111 /* Miscellaneous data */
112 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
114 /**
115 * @}
116 */
119 /* Private macros ------------------------------------------------------------*/
120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros
121 * @{
122 */
124 /**
125 * @brief Driver macro reserved for internal use: set a pointer to
126 * a register from a register basis from which an offset
127 * is applied.
128 * @param __REG__ Register basis from which the offset is applied.
129 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
130 * @retval Pointer to register address
131 */
132 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
133 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
135 /**
136 * @}
137 */
140 /* Exported types ------------------------------------------------------------*/
141 #if defined(USE_FULL_LL_DRIVER)
142 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
143 * @{
144 */
146 /**
147 * @brief Structure definition of some features of DAC instance.
148 */
150 {
151 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
152 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
154 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource().
155 @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth RESET trigger */
157 uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line).
158 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
160 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource2().
161 @note If waveform automatic generation mode is set to sawtooth, this parameter is used as sawtooth
162 step trigger */
164 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
165 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
167 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */
169 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
170 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
171 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
172 If waveform automatic generation mode is set to sawtooth, this parameter host the sawtooth configuration: polarity, reset data, increment data. Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to
173 set this parameter value.
174 @note If waveform automatic generation mode is disabled, this parameter is discarded.
176 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude(), @ref LL_DAC_SetWaveSawtoothPolarity(), @ref LL_DAC_SetWaveSawtoothResetData() or @ref LL_DAC_SetWaveSawtoothStepData(), depending on the wave automatic generation selected. */
179 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
181 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */
184 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
186 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */
188 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.
189 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
191 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */
195 /**
196 * @}
197 */
200 /* Exported constants --------------------------------------------------------*/
201 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
202 * @{
203 */
205 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags
206 * @brief Flags defines which can be used with LL_DAC_ReadReg function
207 * @{
208 */
209 /* DAC channel 1 flags */
211 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
216 /* DAC channel 2 flags */
218 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
222 /**
223 * @}
224 */
226 /** @defgroup DAC_LL_EC_IT DAC interruptions
227 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
228 * @{
229 */
232 /**
233 * @}
234 */
236 /** @defgroup DAC_LL_EC_CHANNEL DAC channels
237 * @{
238 */
239 #define LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
240 #define LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
241 /**
242 * @}
243 */
245 /** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
246 * @brief High frequency interface mode defines that can be used with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
247 * @{
248 */
249 #define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000U /*!< High frequency interface mode disabled */
250 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
251 #define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
252 /**
253 * @}
254 */
256 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
257 * @{
258 */
261 /**
262 * @}
263 */
265 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
266 * @{
267 */
268 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC (all) channel conversion trigger internal (SW start) */
269 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external IP: TIM1 TRGO. */
270 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external IP: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
271 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: TIM7 TRGO. */
272 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM15 TRGO. */
273 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: TIM2 TRGO. */
274 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM4 TRGO. */
275 #define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
276 #define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
277 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: TIM6 TRGO. */
278 #define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external IP: TIM3 TRGO. */
279 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
280 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
281 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
282 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
283 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
284 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
285 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
286 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
287 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
288 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
289 #define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
290 #define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external IP: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
291 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external IP: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
292 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external IP: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
293 #define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external IP: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 serie, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
294 /**
295 * @}
296 */
298 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
299 * @{
300 */
301 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */
302 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
303 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
304 #define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
305 /**
306 * @}
307 */
309 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
310 * @{
311 */
312 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
324 /**
325 * @}
326 */
328 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
329 * @{
330 */
331 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
332 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
333 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
334 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
335 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
336 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
337 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
338 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
339 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
340 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
341 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
342 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
343 /**
344 * @}
345 */
347 /** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
348 * @{
349 */
350 #define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000U /*!< Sawtooth wave generation, polarity is decrement */
351 #define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
352 /**
353 * @}
354 */
356 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
357 * @{
358 */
359 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */
360 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
361 /**
362 * @}
363 */
365 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
366 * @{
367 */
368 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
369 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
370 /**
371 * @}
372 */
374 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
375 * @{
376 */
377 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */
378 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
379 /**
380 * @}
381 */
383 /** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
384 * @{
385 */
386 #define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000U /*!< The selected DAC channel data format is not signed */
387 #define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
388 /**
389 * @}
390 */
392 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
393 * @{
394 */
397 /**
398 * @}
399 */
401 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
402 * @{
403 */
404 /* List of DAC registers intended to be used (most commonly) with */
405 /* DMA transfer. */
406 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
407 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
408 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
409 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
410 /**
411 * @}
412 */
414 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
415 * @note Only DAC IP HW delays are defined in DAC LL driver driver,
416 * not timeout values.
417 * For details on delays values, refer to descriptions in source code
418 * above each literal definition.
419 * @{
420 */
422 /* Delay for DAC channel voltage settling time from DAC channel startup */
423 /* (transition from disable to enable). */
424 /* Note: DAC channel startup time depends on board application environment: */
425 /* impedance connected to DAC channel output. */
426 /* The delay below is specified under conditions: */
427 /* - voltage maximum transition (lowest to highest value) */
428 /* - until voltage reaches final value +-1LSB */
429 /* - DAC channel output buffer enabled */
430 /* - load impedance of 5kOhm (min), 50pF (max) */
431 /* Literal set to maximum value (refer to device datasheet, */
432 /* parameter "tWAKEUP"). */
433 /* Unit: us */
434 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
437 /* Delay for DAC channel voltage settling time. */
438 /* Note: DAC channel startup time depends on board application environment: */
439 /* impedance connected to DAC channel output. */
440 /* The delay below is specified under conditions: */
441 /* - voltage maximum transition (lowest to highest value) */
442 /* - until voltage reaches final value +-1LSB */
443 /* - DAC channel output buffer enabled */
444 /* - load impedance of 5kOhm min, 50pF max */
445 /* Literal set to maximum value (refer to device datasheet, */
446 /* parameter "tSETTLING"). */
447 /* Unit: us */
450 /**
451 * @}
452 */
454 /**
455 * @}
456 */
458 /* Exported macro ------------------------------------------------------------*/
459 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
460 * @{
461 */
463 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
464 * @{
465 */
467 /**
468 * @brief Write a value in DAC register
469 * @param __INSTANCE__ DAC Instance
470 * @param __REG__ Register to be written
471 * @param __VALUE__ Value to be written in the register
472 * @retval None
473 */
474 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
476 /**
477 * @brief Read a value in DAC register
478 * @param __INSTANCE__ DAC Instance
479 * @param __REG__ Register to be read
480 * @retval Register value
481 */
482 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
484 /**
485 * @}
486 */
488 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
489 * @{
490 */
492 /**
493 * @brief Helper macro to get DAC channel number in decimal format
494 * from literals LL_DAC_CHANNEL_x.
495 * Example:
496 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
497 * will return decimal number "1".
498 * @note The input can be a value from functions where a channel
499 * number is returned.
500 * @param __CHANNEL__ This parameter can be one of the following values:
501 * @arg @ref LL_DAC_CHANNEL_1
502 * @arg @ref LL_DAC_CHANNEL_2 (1)
503 *
504 * (1) On this STM32 serie, parameter not available on all instances.
505 * Refer to device datasheet for channels availability.
506 * @retval 1...2
507 */
508 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
509 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
511 /**
512 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
513 * from number in decimal format.
514 * Example:
515 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
516 * will return a data equivalent to "LL_DAC_CHANNEL_1".
517 * @note If the input parameter does not correspond to a DAC channel,
518 * this macro returns value '0'.
519 * @param __DECIMAL_NB__ 1...2
520 * @retval Returned value can be one of the following values:
521 * @arg @ref LL_DAC_CHANNEL_1
522 * @arg @ref LL_DAC_CHANNEL_2 (1)
523 *
524 * (1) On this STM32 serie, parameter not available on all instances.
525 * Refer to device datasheet for channels availability.
526 */
527 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
528 (((__DECIMAL_NB__) == 1U) \
529 ? ( \
530 LL_DAC_CHANNEL_1 \
531 ) \
532 : \
533 (((__DECIMAL_NB__) == 2U) \
534 ? ( \
535 LL_DAC_CHANNEL_2 \
536 ) \
537 : \
538 ( \
539 0 \
540 ) \
541 ) \
542 )
544 /**
545 * @brief Helper macro to define the DAC conversion data full-scale digital
546 * value corresponding to the selected DAC resolution.
547 * @note DAC conversion data full-scale corresponds to voltage range
548 * determined by analog voltage references Vref+ and Vref-
549 * (refer to reference manual).
550 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
551 * @arg @ref LL_DAC_RESOLUTION_12B
552 * @arg @ref LL_DAC_RESOLUTION_8B
553 * @retval ADC conversion data equivalent voltage value (unit: mVolt)
554 */
555 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
556 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
558 /**
559 * @brief Helper macro to calculate the DAC conversion data (unit: digital
560 * value) corresponding to a voltage (unit: mVolt).
561 * @note This helper macro is intended to provide input data in voltage
562 * rather than digital value,
563 * to be used with LL DAC functions such as
564 * @ref LL_DAC_ConvertData12RightAligned().
565 * @note Analog reference voltage (Vref+) must be either known from
566 * user board environment or can be calculated using ADC measurement
567 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
568 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
569 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
570 * (unit: mVolt).
571 * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
572 * @arg @ref LL_DAC_RESOLUTION_12B
573 * @arg @ref LL_DAC_RESOLUTION_8B
574 * @retval DAC conversion data (unit: digital value)
575 */
576 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
577 __DAC_VOLTAGE__,\
578 __DAC_RESOLUTION__) \
579 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
580 / (__VREFANALOG_VOLTAGE__) \
581 )
583 /**
584 * @brief Helper macro to format sawtooth wave generation configuration
585 * value to be filled into WaveAutoGenerationConfig parameter of @ref LL_DAC_InitTypeDef.
586 * @note This helper will format information to fit in DAC_STRx register.
587 * @param __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
588 * @param __RESET_DATA__ sawtooth reset data.
589 * @param __STEP_DATA__ sawtooth step data
590 * @retval Sawtooth configuration organized in DAC_STRx compatible format.
591 */
592 #define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\
593 __RESET_DATA__,\
594 __STEP_DATA__) \
595 ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
596 | ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
597 | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
598 )
600 /**
601 * @}
602 */
604 /**
605 * @}
606 */
609 /* Exported functions --------------------------------------------------------*/
610 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
611 * @{
612 */
613 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC instance
614 * @{
615 */
616 /**
617 * @brief Set the high frequency interface mode for the selected DAC instance
618 * @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
619 * @param DACx DAC instance
620 * @param HighFreqMode This parameter can be one of the following values:
621 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
622 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
623 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
624 * @retval None
625 */
627 {
629 }
631 /**
632 * @brief Get the high frequency interface mode for the selected DAC instance
633 * @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
634 * @param DACx DAC instance
635 * @retval Returned value can be one of the following values:
636 * @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
637 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
638 * @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
639 */
641 {
643 }
644 /**
645 * @}
646 */
648 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
649 * @{
650 */
652 /**
653 * @brief Set the operating mode for the selected DAC channel:
654 * calibration or normal operating mode.
655 * @rmtoll CR CEN1 LL_DAC_SetMode\n
656 * CR CEN2 LL_DAC_SetMode
657 * @param DACx DAC instance
658 * @param DAC_Channel This parameter can be one of the following values:
659 * @arg @ref LL_DAC_CHANNEL_1
660 * @arg @ref LL_DAC_CHANNEL_2 (1)
661 *
662 * (1) On this STM32 serie, parameter not available on all instances.
663 * Refer to device datasheet for channels availability.
664 * @param ChannelMode This parameter can be one of the following values:
665 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
666 * @arg @ref LL_DAC_MODE_CALIBRATION
667 * @retval None
668 */
669 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
670 {
674 }
676 /**
677 * @brief Get the operating mode for the selected DAC channel:
678 * calibration or normal operating mode.
679 * @rmtoll CR CEN1 LL_DAC_GetMode\n
680 * CR CEN2 LL_DAC_GetMode
681 * @param DACx DAC instance
682 * @param DAC_Channel This parameter can be one of the following values:
683 * @arg @ref LL_DAC_CHANNEL_1
684 * @arg @ref LL_DAC_CHANNEL_2 (1)
685 *
686 * (1) On this STM32 serie, parameter not available on all instances.
687 * Refer to device datasheet for channels availability.
688 * @retval Returned value can be one of the following values:
689 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION
690 * @arg @ref LL_DAC_MODE_CALIBRATION
691 */
693 {
696 );
697 }
699 /**
700 * @brief Set the offset trimming value for the selected DAC channel.
701 * Trimming has an impact when output buffer is enabled
702 * and is intended to replace factory calibration default values.
703 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
704 * CCR OTRIM2 LL_DAC_SetTrimmingValue
705 * @param DACx DAC instance
706 * @param DAC_Channel This parameter can be one of the following values:
707 * @arg @ref LL_DAC_CHANNEL_1
708 * @arg @ref LL_DAC_CHANNEL_2 (1)
709 *
710 * (1) On this STM32 serie, parameter not available on all instances.
711 * Refer to device datasheet for channels availability.
712 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
713 * @retval None
714 */
715 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
716 {
720 }
722 /**
723 * @brief Get the offset trimming value for the selected DAC channel.
724 * Trimming has an impact when output buffer is enabled
725 * and is intended to replace factory calibration default values.
726 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
727 * CCR OTRIM2 LL_DAC_GetTrimmingValue
728 * @param DACx DAC instance
729 * @param DAC_Channel This parameter can be one of the following values:
730 * @arg @ref LL_DAC_CHANNEL_1
731 * @arg @ref LL_DAC_CHANNEL_2 (1)
732 *
733 * (1) On this STM32 serie, parameter not available on all instances.
734 * Refer to device datasheet for channels availability.
735 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
736 */
738 {
739 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
741 );
742 }
744 /**
745 * @brief Set the conversion trigger source for the selected DAC channel.
746 * @note For conversion trigger source to be effective, DAC trigger
747 * must be enabled using function @ref LL_DAC_EnableTrigger().
748 * @note To set conversion trigger source, DAC channel must be disabled.
749 * Otherwise, the setting is discarded.
750 * @note Availability of parameters of trigger sources from timer
751 * depends on timers availability on the selected device.
752 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
753 * CR TSEL2 LL_DAC_SetTriggerSource
754 * @param DACx DAC instance
755 * @param DAC_Channel This parameter can be one of the following values:
756 * @arg @ref LL_DAC_CHANNEL_1
757 * @arg @ref LL_DAC_CHANNEL_2 (1)
758 *
759 * (1) On this STM32 serie, parameter not available on all instances.
760 * Refer to device datasheet for channels availability.
761 * @param TriggerSource This parameter can be one of the following values:
762 * @arg @ref LL_DAC_TRIG_SOFTWARE
763 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
764 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
765 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
766 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
767 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
768 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
769 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
770 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
771 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
772 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
773 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
774 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
775 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
776 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
777 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
778 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
779 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
780 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
781 *
782 * (1) On this STM32 serie, parameter only available on DAC3.
783 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
784 * (3) On this STM32 serie, parameter only available on DAC1&4.
785 * (4) On this STM32 serie, parameter only available on DAC2.
786 * Refer to device datasheet for DACx instances availability.
787 * (5) On this STM32 serie, parameter not available on all devices.
788 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
789 * @retval None
790 */
791 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
792 {
796 }
798 /**
799 * @brief Get the conversion trigger source for the selected DAC channel.
800 * @note For conversion trigger source to be effective, DAC trigger
801 * must be enabled using function @ref LL_DAC_EnableTrigger().
802 * @note Availability of parameters of trigger sources from timer
803 * depends on timers availability on the selected device.
804 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
805 * CR TSEL2 LL_DAC_GetTriggerSource
806 * @param DACx DAC instance
807 * @param DAC_Channel This parameter can be one of the following values:
808 * @arg @ref LL_DAC_CHANNEL_1
809 * @arg @ref LL_DAC_CHANNEL_2 (1)
810 *
811 * (1) On this STM32 serie, parameter not available on all instances.
812 * Refer to device datasheet for channels availability.
813 * @retval Returned value can be one of the following values:
814 * @arg @ref LL_DAC_TRIG_SOFTWARE
815 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
816 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
817 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
818 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
819 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
820 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
821 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
822 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
823 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
824 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
825 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
826 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
827 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
828 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
829 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
830 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
831 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
832 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
833 *
834 * (1) On this STM32 serie, parameter only available on DAC3.
835 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
836 * (3) On this STM32 serie, parameter only available on DAC1&4.
837 * (4) On this STM32 serie, parameter only available on DAC2.
838 * Refer to device datasheet for DACx instances availability.
839 * (5) On this STM32 serie, parameter not available on all devices.
840 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
841 */
843 {
846 );
847 }
849 /**
850 * @brief Set the waveform automatic generation mode
851 * for the selected DAC channel.
852 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
853 * CR WAVE2 LL_DAC_SetWaveAutoGeneration
854 * @param DACx DAC instance
855 * @param DAC_Channel This parameter can be one of the following values:
856 * @arg @ref LL_DAC_CHANNEL_1
857 * @arg @ref LL_DAC_CHANNEL_2 (1)
858 *
859 * (1) On this STM32 serie, parameter not available on all instances.
860 * Refer to device datasheet for channels availability.
861 * @param WaveAutoGeneration This parameter can be one of the following values:
862 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
863 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
864 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
865 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
866 * @retval None
867 */
868 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
869 {
873 }
875 /**
876 * @brief Get the waveform automatic generation mode
877 * for the selected DAC channel.
878 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
879 * CR WAVE2 LL_DAC_GetWaveAutoGeneration
880 * @param DACx DAC instance
881 * @param DAC_Channel This parameter can be one of the following values:
882 * @arg @ref LL_DAC_CHANNEL_1
883 * @arg @ref LL_DAC_CHANNEL_2 (1)
884 *
885 * (1) On this STM32 serie, parameter not available on all instances.
886 * Refer to device datasheet for channels availability.
887 * @retval Returned value can be one of the following values:
888 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
889 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
890 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
891 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
892 */
894 {
897 );
898 }
900 /**
901 * @brief Set the noise waveform generation for the selected DAC channel:
902 * Noise mode and parameters LFSR (linear feedback shift register).
903 * @note For wave generation to be effective, DAC channel
904 * wave generation mode must be enabled using
905 * function @ref LL_DAC_SetWaveAutoGeneration().
906 * @note This setting can be set when the selected DAC channel is disabled
907 * (otherwise, the setting operation is ignored).
908 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
909 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR
910 * @param DACx DAC instance
911 * @param DAC_Channel This parameter can be one of the following values:
912 * @arg @ref LL_DAC_CHANNEL_1
913 * @arg @ref LL_DAC_CHANNEL_2 (1)
914 *
915 * (1) On this STM32 serie, parameter not available on all instances.
916 * Refer to device datasheet for channels availability.
917 * @param NoiseLFSRMask This parameter can be one of the following values:
918 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
919 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
920 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
921 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
922 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
923 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
924 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
925 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
926 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
927 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
928 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
929 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
930 * @retval None
931 */
932 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
933 {
937 }
939 /**
940 * @brief Get the noise waveform generation for the selected DAC channel:
941 * Noise mode and parameters LFSR (linear feedback shift register).
942 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
943 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR
944 * @param DACx DAC instance
945 * @param DAC_Channel This parameter can be one of the following values:
946 * @arg @ref LL_DAC_CHANNEL_1
947 * @arg @ref LL_DAC_CHANNEL_2 (1)
948 *
949 * (1) On this STM32 serie, parameter not available on all instances.
950 * Refer to device datasheet for channels availability.
951 * @retval Returned value can be one of the following values:
952 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
953 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
954 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
955 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
956 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
957 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
958 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
959 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
960 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
961 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
962 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
963 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
964 */
966 {
969 );
970 }
972 /**
973 * @brief Set the triangle waveform generation for the selected DAC channel:
974 * triangle mode and amplitude.
975 * @note For wave generation to be effective, DAC channel
976 * wave generation mode must be enabled using
977 * function @ref LL_DAC_SetWaveAutoGeneration().
978 * @note This setting can be set when the selected DAC channel is disabled
979 * (otherwise, the setting operation is ignored).
980 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
981 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
982 * @param DACx DAC instance
983 * @param DAC_Channel This parameter can be one of the following values:
984 * @arg @ref LL_DAC_CHANNEL_1
985 * @arg @ref LL_DAC_CHANNEL_2 (1)
986 *
987 * (1) On this STM32 serie, parameter not available on all instances.
988 * Refer to device datasheet for channels availability.
989 * @param TriangleAmplitude This parameter can be one of the following values:
990 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
991 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
992 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
993 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
994 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
995 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
996 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
997 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
998 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
999 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1000 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1001 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1002 * @retval None
1003 */
1006 {
1010 }
1012 /**
1013 * @brief Get the triangle waveform generation for the selected DAC channel:
1014 * triangle mode and amplitude.
1015 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
1016 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
1017 * @param DACx DAC instance
1018 * @param DAC_Channel This parameter can be one of the following values:
1019 * @arg @ref LL_DAC_CHANNEL_1
1020 * @arg @ref LL_DAC_CHANNEL_2 (1)
1021 *
1022 * (1) On this STM32 serie, parameter not available on all instances.
1023 * Refer to device datasheet for channels availability.
1024 * @retval Returned value can be one of the following values:
1025 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
1026 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
1027 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
1028 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
1029 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
1030 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
1031 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
1032 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
1033 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
1034 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
1035 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
1036 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
1037 */
1038 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1039 {
1040 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1042 );
1043 }
1045 /**
1046 * @brief Set the swatooth waveform generation polarity.
1047 * @note For wave generation to be effective, DAC channel
1048 * wave generation mode must be enabled using
1049 * function @ref LL_DAC_SetWaveAutoGeneration().
1050 * @note This setting can be set when the selected DAC channel is disabled
1051 * (otherwise, the setting operation is ignored).
1052 * @rmtoll STR1 STDIR1 LL_DAC_SetWaveSawtoothPolarity\n
1053 * STR2 STDIR2 LL_DAC_SetWaveSawtoothPolarity
1054 * @param DACx DAC instance
1055 * @param DAC_Channel This parameter can be one of the following values:
1056 * @arg @ref LL_DAC_CHANNEL_1
1057 * @arg @ref LL_DAC_CHANNEL_2 (1)
1058 *
1059 * (1) On this STM32 serie, parameter not available on all instances.
1060 * Refer to device datasheet for channels availability.
1061 * @param Polarity This parameter can be one of the following values:
1062 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1063 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1064 * @retval None
1065 */
1066 __STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
1067 {
1068 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1071 DAC_STR1_STDIR1,
1072 Polarity);
1073 }
1075 /**
1076 * @brief Get the sawtooth waveform generation polarity.
1077 * @rmtoll STR1 STDIR1 LL_DAC_GetWaveSawtoothPolarity\n
1078 * STR2 STDIR2 LL_DAC_GetWaveSawtoothPolarity
1079 * @param DACx DAC instance
1080 * @param DAC_Channel This parameter can be one of the following values:
1081 * @arg @ref LL_DAC_CHANNEL_1
1082 * @arg @ref LL_DAC_CHANNEL_2 (1)
1083 *
1084 * (1) On this STM32 serie, parameter not available on all instances.
1085 * Refer to device datasheet for channels availability.
1086 * @retval Returned value can be one of the following values:
1087 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
1088 * @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
1089 */
1090 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1091 {
1092 register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1095 }
1097 /**
1098 * @brief Set the swatooth waveform generation reset data.
1099 * @note For wave generation to be effective, DAC channel
1100 * wave generation mode must be enabled using
1101 * function @ref LL_DAC_SetWaveAutoGeneration().
1102 * @note This setting can be set when the selected DAC channel is disabled
1103 * (otherwise, the setting operation is ignored).
1104 * @rmtoll STR1 STRSTDATA1 LL_DAC_SetWaveSawtoothResetData\n
1105 * STR2 STRSTDATA2 LL_DAC_SetWaveSawtoothResetData
1106 * @param DACx DAC instance
1107 * @param DAC_Channel This parameter can be one of the following values:
1108 * @arg @ref LL_DAC_CHANNEL_1
1109 * @arg @ref LL_DAC_CHANNEL_2 (1)
1110 *
1111 * (1) On this STM32 serie, parameter not available on all instances.
1112 * Refer to device datasheet for channels availability.
1113 * @param ResetData This parameter is the sawtooth reset value.
1114 * Range is from 0 to DAC full range 4095 (0xFFF)
1115 * @retval None
1116 */
1117 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
1118 {
1119 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1122 DAC_STR1_STRSTDATA1,
1124 }
1126 /**
1127 * @brief Get the sawtooth waveform generation reset data.
1128 * @rmtoll STR1 STRSTDATA1 LL_DAC_GetWaveSawtoothResetData\n
1129 * STR2 STRSTDATA2 LL_DAC_GetWaveSawtoothResetData
1130 * @param DACx DAC instance
1131 * @param DAC_Channel This parameter can be one of the following values:
1132 * @arg @ref LL_DAC_CHANNEL_1
1133 * @arg @ref LL_DAC_CHANNEL_2 (1)
1134 *
1135 * (1) On this STM32 serie, parameter not available on all instances.
1136 * Refer to device datasheet for channels availability.
1137 * @retval Returned value is the sawtooth reset value.
1138 * Range is from 0 to DAC full range 4095 (0xFFF)
1139 */
1140 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1141 {
1142 register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1145 }
1147 /**
1148 * @brief Set the swatooth waveform generation step data.
1149 * @note For wave generation to be effective, DAC channel
1150 * wave generation mode must be enabled using
1151 * function @ref LL_DAC_SetWaveAutoGeneration().
1152 * @note This setting can be set when the selected DAC channel is disabled
1153 * (otherwise, the setting operation is ignored).
1154 * @rmtoll STR1 STINCDATA1 LL_DAC_SetWaveSawtoothStepData\n
1155 * STR2 STINCDATA2 LL_DAC_SetWaveSawtoothStepData
1156 * @param DACx DAC instance
1157 * @param DAC_Channel This parameter can be one of the following values:
1158 * @arg @ref LL_DAC_CHANNEL_1
1159 * @arg @ref LL_DAC_CHANNEL_2 (1)
1160 *
1161 * (1) On this STM32 serie, parameter not available on all instances.
1162 * Refer to device datasheet for channels availability.
1163 * @param StepData This parameter is the sawtooth step value.
1164 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1165 * Step value step is 1/16 = 0.0625
1166 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1167 * @retval None
1168 */
1169 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
1170 {
1171 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1174 DAC_STR1_STINCDATA1,
1176 }
1178 /**
1179 * @brief Get the sawtooth waveform generation step data.
1180 * @rmtoll STR1 STINCDATA1 LL_DAC_GetWaveSawtoothStepData\n
1181 * STR2 STINCDATA2 LL_DAC_GetWaveSawtoothStepData
1182 * @param DACx DAC instance
1183 * @param DAC_Channel This parameter can be one of the following values:
1184 * @arg @ref LL_DAC_CHANNEL_1
1185 * @arg @ref LL_DAC_CHANNEL_2 (1)
1186 *
1187 * (1) On this STM32 serie, parameter not available on all instances.
1188 * Refer to device datasheet for channels availability.
1189 * @retval Returned value is the sawtooth step value.
1190 * 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
1191 * Step value step is 1/16 = 0.0625
1192 * Step value range is 0.0000 to 4095.9375 (0xFFF.F)
1193 */
1194 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1195 {
1196 register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
1199 }
1201 /**
1202 * @brief Set the swatooth waveform generation reset trigger source.
1203 * @note For wave generation to be effective, DAC channel
1204 * wave generation mode must be enabled using
1205 * function @ref LL_DAC_SetWaveAutoGeneration().
1206 * @note This setting can be set when the selected DAC channel is disabled
1207 * (otherwise, the setting operation is ignored).
1208 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_SetWaveSawtoothResetTriggerSource\n
1209 * STMODR STRSTTRIGSEL2 LL_DAC_SetWaveSawtoothResetTriggerSource
1210 * @param DACx DAC instance
1211 * @param DAC_Channel This parameter can be one of the following values:
1212 * @arg @ref LL_DAC_CHANNEL_1
1213 * @arg @ref LL_DAC_CHANNEL_2 (1)
1214 *
1215 * (1) On this STM32 serie, parameter not available on all instances.
1216 * Refer to device datasheet for channels availability.
1217 * @param TriggerSource This parameter can be one of the following values:
1218 * @arg @ref LL_DAC_TRIG_SOFTWARE
1219 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1220 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1221 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1222 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1223 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1224 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1225 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1226 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1227 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1228 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1229 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1230 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1231 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1232 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1233 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1234 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1235 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1236 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1237 *
1238 * (1) On this STM32 serie, parameter only available on DAC3.
1239 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
1240 * (3) On this STM32 serie, parameter only available on DAC1&4.
1241 * (4) On this STM32 serie, parameter only available on DAC2.
1242 * Refer to device datasheet for DACx instances availability.
1243 * (5) On this STM32 serie, parameter not available on all devices.
1244 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1245 * @retval None
1246 */
1247 __STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1249 {
1252 ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1253 }
1255 /**
1256 * @brief Get the sawtooth waveform generation reset trigger source.
1257 * @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_GetWaveSawtoothResetTriggerSource\n
1258 * STMODR STRSTTRIGSEL2 LL_DAC_GetWaveSawtoothResetTriggerSource
1259 * @param DACx DAC instance
1260 * @param DAC_Channel This parameter can be one of the following values:
1261 * @arg @ref LL_DAC_CHANNEL_1
1262 * @arg @ref LL_DAC_CHANNEL_2 (1)
1263 *
1264 * (1) On this STM32 serie, parameter not available on all instances.
1265 * Refer to device datasheet for channels availability.
1266 * @retval Returned value can be one of the following values:
1267 * @arg @ref LL_DAC_TRIG_SOFTWARE
1268 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1269 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1270 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1271 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1272 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1273 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1274 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
1275 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1276 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1277 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
1278 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
1279 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
1280 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
1281 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
1282 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
1283 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
1284 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
1285 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
1286 *
1287 * (1) On this STM32 serie, parameter only available on DAC3.
1288 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
1289 * (3) On this STM32 serie, parameter only available on DAC1&4.
1290 * (4) On this STM32 serie, parameter only available on DAC2.
1291 * Refer to device datasheet for DACx instances availability.
1292 * (5) On this STM32 serie, parameter not available on all devices.
1293 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1294 */
1295 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1296 {
1299 )
1302 }
1304 /**
1305 * @brief Set the swatooth waveform generation step trigger source.
1306 * @note For wave generation to be effective, DAC channel
1307 * wave generation mode must be enabled using
1308 * function @ref LL_DAC_SetWaveAutoGeneration().
1309 * @note This setting can be set when the selected DAC channel is disabled
1310 * (otherwise, the setting operation is ignored).
1311 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_SetWaveSawtoothStepTriggerSource\n
1312 * STMODR STINCTRIGSEL2 LL_DAC_SetWaveSawtoothStepTriggerSource
1313 * @param DACx DAC instance
1314 * @param DAC_Channel This parameter can be one of the following values:
1315 * @arg @ref LL_DAC_CHANNEL_1
1316 * @arg @ref LL_DAC_CHANNEL_2 (1)
1317 *
1318 * (1) On this STM32 serie, parameter not available on all instances.
1319 * Refer to device datasheet for channels availability.
1320 * @param TriggerSource This parameter can be one of the following values:
1321 * @arg @ref LL_DAC_TRIG_SOFTWARE
1322 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1323 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1324 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1325 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1326 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1327 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1328 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1329 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1330 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1331 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1332 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1333 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1334 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1335 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1336 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1337 *
1338 * (1) On this STM32 serie, parameter only available on DAC3.
1339 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
1340 * Refer to device datasheet for DACx instances availability.
1341 * (3) On this STM32 serie, parameter not available on all devices.
1342 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1343 * @retval None
1344 */
1345 __STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
1347 {
1350 ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1351 }
1353 /**
1354 * @brief Get the sawtooth waveform generation step trigger source.
1355 * @rmtoll STMODR STINCTRIGSEL1 LL_DAC_GetWaveSawtoothStepTriggerSource\n
1356 * STMODR STINCTRIGSEL2 LL_DAC_GetWaveSawtoothStepTriggerSource
1357 * @param DACx DAC instance
1358 * @param DAC_Channel This parameter can be one of the following values:
1359 * @arg @ref LL_DAC_CHANNEL_1
1360 * @arg @ref LL_DAC_CHANNEL_2 (1)
1361 *
1362 * (1) On this STM32 serie, parameter not available on all instances.
1363 * Refer to device datasheet for channels availability.
1364 * @retval Returned value can be one of the following values:
1365 * @arg @ref LL_DAC_TRIG_SOFTWARE
1366 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
1367 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
1368 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
1369 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
1370 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
1371 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
1372 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
1373 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
1374 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
1375 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
1376 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
1377 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
1378 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
1379 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
1380 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
1381 *
1382 * (1) On this STM32 serie, parameter only available on DAC3.
1383 * (2) On this STM32 serie, parameter only available on DAC1/2/4.
1384 * Refer to device datasheet for DACx instances availability.
1385 * (3) On this STM32 serie, parameter not available on all devices.
1386 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
1387 */
1388 __STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1389 {
1392 )
1395 }
1397 /**
1398 * @brief Set the output for the selected DAC channel.
1399 * @note This function set several features:
1400 * - mode normal or sample-and-hold
1401 * - buffer
1402 * - connection to GPIO or internal path.
1403 * These features can also be set individually using
1404 * dedicated functions:
1405 * - @ref LL_DAC_SetOutputBuffer()
1406 * - @ref LL_DAC_SetOutputMode()
1407 * - @ref LL_DAC_SetOutputConnection()
1408 * @note On this STM32 serie, output connection depends on output mode
1409 * (normal or sample and hold) and output buffer state.
1410 * - if output connection is set to internal path and output buffer
1411 * is enabled (whatever output mode):
1412 * output connection is also connected to GPIO pin
1413 * (both connections to GPIO pin and internal path).
1414 * - if output connection is set to GPIO pin, output buffer
1415 * is disabled, output mode set to sample and hold:
1416 * output connection is also connected to internal path
1417 * (both connections to GPIO pin and internal path).
1418 * @note Mode sample-and-hold requires an external capacitor
1419 * to be connected between DAC channel output and ground.
1420 * Capacitor value depends on load on DAC channel output and
1421 * sample-and-hold timings configured.
1422 * As indication, capacitor typical value is 100nF
1423 * (refer to device datasheet, parameter "CSH").
1424 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
1425 * CR MODE2 LL_DAC_ConfigOutput
1426 * @param DACx DAC instance
1427 * @param DAC_Channel This parameter can be one of the following values:
1428 * @arg @ref LL_DAC_CHANNEL_1
1429 * @arg @ref LL_DAC_CHANNEL_2 (1)
1430 *
1431 * (1) On this STM32 serie, parameter not available on all instances.
1432 * Refer to device datasheet for channels availability.
1433 * @param OutputMode This parameter can be one of the following values:
1434 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1435 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1436 * @param OutputBuffer This parameter can be one of the following values:
1437 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1438 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1439 * @param OutputConnection This parameter can be one of the following values:
1440 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1441 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1442 * @retval None
1443 */
1444 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
1446 {
1448 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
1450 }
1452 /**
1453 * @brief Set the output mode normal or sample-and-hold
1454 * for the selected DAC channel.
1455 * @note Mode sample-and-hold requires an external capacitor
1456 * to be connected between DAC channel output and ground.
1457 * Capacitor value depends on load on DAC channel output and
1458 * sample-and-hold timings configured.
1459 * As indication, capacitor typical value is 100nF
1460 * (refer to device datasheet, parameter "CSH").
1461 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
1462 * CR MODE2 LL_DAC_SetOutputMode
1463 * @param DACx DAC instance
1464 * @param DAC_Channel This parameter can be one of the following values:
1465 * @arg @ref LL_DAC_CHANNEL_1
1466 * @arg @ref LL_DAC_CHANNEL_2 (1)
1467 *
1468 * (1) On this STM32 serie, parameter not available on all instances.
1469 * Refer to device datasheet for channels availability.
1470 * @param OutputMode This parameter can be one of the following values:
1471 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1472 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1473 * @retval None
1474 */
1475 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
1476 {
1480 }
1482 /**
1483 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
1484 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
1485 * CR MODE2 LL_DAC_GetOutputMode
1486 * @param DACx DAC instance
1487 * @param DAC_Channel This parameter can be one of the following values:
1488 * @arg @ref LL_DAC_CHANNEL_1
1489 * @arg @ref LL_DAC_CHANNEL_2 (1)
1490 *
1491 * (1) On this STM32 serie, parameter not available on all instances.
1492 * Refer to device datasheet for channels availability.
1493 * @retval Returned value can be one of the following values:
1494 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
1495 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
1496 */
1498 {
1499 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1501 );
1502 }
1504 /**
1505 * @brief Set the output buffer for the selected DAC channel.
1506 * @note On this STM32 serie, when buffer is enabled, its offset can be
1507 * trimmed: factory calibration default values can be
1508 * replaced by user trimming values, using function
1509 * @ref LL_DAC_SetTrimmingValue().
1510 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
1511 * CR MODE2 LL_DAC_SetOutputBuffer
1512 * @param DACx DAC instance
1513 * @param DAC_Channel This parameter can be one of the following values:
1514 * @arg @ref LL_DAC_CHANNEL_1
1515 * @arg @ref LL_DAC_CHANNEL_2 (1)
1516 *
1517 * (1) On this STM32 serie, parameter not available on all instances.
1518 * Refer to device datasheet for channels availability.
1519 * @param OutputBuffer This parameter can be one of the following values:
1520 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1521 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1522 * @retval None
1523 */
1524 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
1525 {
1529 }
1531 /**
1532 * @brief Get the output buffer state for the selected DAC channel.
1533 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
1534 * CR MODE2 LL_DAC_GetOutputBuffer
1535 * @param DACx DAC instance
1536 * @param DAC_Channel This parameter can be one of the following values:
1537 * @arg @ref LL_DAC_CHANNEL_1
1538 * @arg @ref LL_DAC_CHANNEL_2 (1)
1539 *
1540 * (1) On this STM32 serie, parameter not available on all instances.
1541 * Refer to device datasheet for channels availability.
1542 * @retval Returned value can be one of the following values:
1543 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
1544 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
1545 */
1547 {
1548 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1550 );
1551 }
1553 /**
1554 * @brief Set the output connection for the selected DAC channel.
1555 * @note On this STM32 serie, output connection depends on output mode (normal or
1556 * sample and hold) and output buffer state.
1557 * - if output connection is set to internal path and output buffer
1558 * is enabled (whatever output mode):
1559 * output connection is also connected to GPIO pin
1560 * (both connections to GPIO pin and internal path).
1561 * - if output connection is set to GPIO pin, output buffer
1562 * is disabled, output mode set to sample and hold:
1563 * output connection is also connected to internal path
1564 * (both connections to GPIO pin and internal path).
1565 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
1566 * CR MODE2 LL_DAC_SetOutputConnection
1567 * @param DACx DAC instance
1568 * @param DAC_Channel This parameter can be one of the following values:
1569 * @arg @ref LL_DAC_CHANNEL_1
1570 * @arg @ref LL_DAC_CHANNEL_2 (1)
1571 *
1572 * (1) On this STM32 serie, parameter not available on all instances.
1573 * Refer to device datasheet for channels availability.
1574 * @param OutputConnection This parameter can be one of the following values:
1575 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1576 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1577 * @retval None
1578 */
1579 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
1580 {
1584 }
1586 /**
1587 * @brief Get the output connection for the selected DAC channel.
1588 * @note On this STM32 serie, output connection depends on output mode (normal or
1589 * sample and hold) and output buffer state.
1590 * - if output connection is set to internal path and output buffer
1591 * is enabled (whatever output mode):
1592 * output connection is also connected to GPIO pin
1593 * (both connections to GPIO pin and internal path).
1594 * - if output connection is set to GPIO pin, output buffer
1595 * is disabled, output mode set to sample and hold:
1596 * output connection is also connected to internal path
1597 * (both connections to GPIO pin and internal path).
1598 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
1599 * CR MODE2 LL_DAC_GetOutputConnection
1600 * @param DACx DAC instance
1601 * @param DAC_Channel This parameter can be one of the following values:
1602 * @arg @ref LL_DAC_CHANNEL_1
1603 * @arg @ref LL_DAC_CHANNEL_2 (1)
1604 *
1605 * (1) On this STM32 serie, parameter not available on all instances.
1606 * Refer to device datasheet for channels availability.
1607 * @retval Returned value can be one of the following values:
1608 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
1609 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
1610 */
1612 {
1613 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1615 );
1616 }
1618 /**
1619 * @brief Set the sample-and-hold timing for the selected DAC channel:
1620 * sample time
1621 * @note Sample time must be set when DAC channel is disabled
1622 * or during DAC operation when DAC channel flag BWSTx is reset,
1623 * otherwise the setting is ignored.
1624 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
1625 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
1626 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
1627 * @param DACx DAC instance
1628 * @param DAC_Channel This parameter can be one of the following values:
1629 * @arg @ref LL_DAC_CHANNEL_1
1630 * @arg @ref LL_DAC_CHANNEL_2 (1)
1631 *
1632 * (1) On this STM32 serie, parameter not available on all instances.
1633 * Refer to device datasheet for channels availability.
1634 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
1635 * @retval None
1636 */
1637 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
1638 {
1639 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1642 DAC_SHSR1_TSAMPLE1,
1643 SampleTime);
1644 }
1646 /**
1647 * @brief Get the sample-and-hold timing for the selected DAC channel:
1648 * sample time
1649 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
1650 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
1651 * @param DACx DAC instance
1652 * @param DAC_Channel This parameter can be one of the following values:
1653 * @arg @ref LL_DAC_CHANNEL_1
1654 * @arg @ref LL_DAC_CHANNEL_2 (1)
1655 *
1656 * (1) On this STM32 serie, parameter not available on all instances.
1657 * Refer to device datasheet for channels availability.
1658 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1659 */
1660 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1661 {
1662 register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
1665 }
1667 /**
1668 * @brief Set the sample-and-hold timing for the selected DAC channel:
1669 * hold time
1670 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
1671 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
1672 * @param DACx DAC instance
1673 * @param DAC_Channel This parameter can be one of the following values:
1674 * @arg @ref LL_DAC_CHANNEL_1
1675 * @arg @ref LL_DAC_CHANNEL_2 (1)
1676 *
1677 * (1) On this STM32 serie, parameter not available on all instances.
1678 * Refer to device datasheet for channels availability.
1679 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
1680 * @retval None
1681 */
1682 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
1683 {
1687 }
1689 /**
1690 * @brief Get the sample-and-hold timing for the selected DAC channel:
1691 * hold time
1692 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
1693 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
1694 * @param DACx DAC instance
1695 * @param DAC_Channel This parameter can be one of the following values:
1696 * @arg @ref LL_DAC_CHANNEL_1
1697 * @arg @ref LL_DAC_CHANNEL_2 (1)
1698 *
1699 * (1) On this STM32 serie, parameter not available on all instances.
1700 * Refer to device datasheet for channels availability.
1701 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
1702 */
1703 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1704 {
1705 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1707 );
1708 }
1710 /**
1711 * @brief Set the sample-and-hold timing for the selected DAC channel:
1712 * refresh time
1713 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
1714 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
1715 * @param DACx DAC instance
1716 * @param DAC_Channel This parameter can be one of the following values:
1717 * @arg @ref LL_DAC_CHANNEL_1
1718 * @arg @ref LL_DAC_CHANNEL_2 (1)
1719 *
1720 * (1) On this STM32 serie, parameter not available on all instances.
1721 * Refer to device datasheet for channels availability.
1722 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
1723 * @retval None
1724 */
1725 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
1726 {
1730 }
1732 /**
1733 * @brief Get the sample-and-hold timing for the selected DAC channel:
1734 * refresh time
1735 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
1736 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
1737 * @param DACx DAC instance
1738 * @param DAC_Channel This parameter can be one of the following values:
1739 * @arg @ref LL_DAC_CHANNEL_1
1740 * @arg @ref LL_DAC_CHANNEL_2 (1)
1741 *
1742 * (1) On this STM32 serie, parameter not available on all instances.
1743 * Refer to device datasheet for channels availability.
1744 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
1745 */
1746 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1747 {
1748 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1750 );
1751 }
1753 /**
1754 * @brief Set the signed format for the selected DAC channel.
1755 * @note On this STM32 serie, signed format can be used to inject
1756 * Q1.15, Q1.11, Q1.7 signed format data to DAC.
1757 * Ex when using 12bits data format (Q1.11 is used):
1758 * 0x800 will output 0v level
1759 * 0xFFF will output mid-scale level
1760 * 0x000 will output mid-scale level
1761 * 0x7FF will output full-scale level
1762 * @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
1763 * MCR SINFORMAT2 LL_DAC_SetSignedFormat
1764 * @param DACx DAC instance
1765 * @param DAC_Channel This parameter can be one of the following values:
1766 * @arg @ref LL_DAC_CHANNEL_1
1767 * @arg @ref LL_DAC_CHANNEL_2 (1)
1768 *
1769 * (1) On this STM32 serie, parameter not available on all instances.
1770 * Refer to device datasheet for channels availability.
1771 * @param SignedFormat This parameter can be one of the following values:
1772 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1773 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1774 * @retval None
1775 */
1776 __STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
1777 {
1781 }
1783 /**
1784 * @brief Get the signed format state for the selected DAC channel.
1785 * @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
1786 * MCR SINFORMAT2 LL_DAC_GetSignedFormat
1787 * @param DACx DAC instance
1788 * @param DAC_Channel This parameter can be one of the following values:
1789 * @arg @ref LL_DAC_CHANNEL_1
1790 * @arg @ref LL_DAC_CHANNEL_2 (1)
1791 *
1792 * (1) On this STM32 serie, parameter not available on all instances.
1793 * Refer to device datasheet for channels availability.
1794 * @retval Returned value can be one of the following values:
1795 * @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
1796 * @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
1797 */
1799 {
1800 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1802 );
1803 }
1805 /**
1806 * @}
1807 */
1809 /** @defgroup DAC_LL_EF_DMA_Management DMA Management
1810 * @{
1811 */
1813 /**
1814 * @brief Enable DAC DMA transfer request of the selected channel.
1815 * @note To configure DMA source address (peripheral address),
1816 * use function @ref LL_DAC_DMA_GetRegAddr().
1817 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
1818 * CR DMAEN2 LL_DAC_EnableDMAReq
1819 * @param DACx DAC instance
1820 * @param DAC_Channel This parameter can be one of the following values:
1821 * @arg @ref LL_DAC_CHANNEL_1
1822 * @arg @ref LL_DAC_CHANNEL_2 (1)
1823 *
1824 * (1) On this STM32 serie, parameter not available on all instances.
1825 * Refer to device datasheet for channels availability.
1826 * @retval None
1827 */
1829 {
1832 }
1834 /**
1835 * @brief Disable DAC DMA transfer request of the selected channel.
1836 * @note To configure DMA source address (peripheral address),
1837 * use function @ref LL_DAC_DMA_GetRegAddr().
1838 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
1839 * CR DMAEN2 LL_DAC_DisableDMAReq
1840 * @param DACx DAC instance
1841 * @param DAC_Channel This parameter can be one of the following values:
1842 * @arg @ref LL_DAC_CHANNEL_1
1843 * @arg @ref LL_DAC_CHANNEL_2 (1)
1844 *
1845 * (1) On this STM32 serie, parameter not available on all instances.
1846 * Refer to device datasheet for channels availability.
1847 * @retval None
1848 */
1850 {
1853 }
1855 /**
1856 * @brief Get DAC DMA transfer request state of the selected channel.
1857 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
1858 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
1859 * CR DMAEN2 LL_DAC_IsDMAReqEnabled
1860 * @param DACx DAC instance
1861 * @param DAC_Channel This parameter can be one of the following values:
1862 * @arg @ref LL_DAC_CHANNEL_1
1863 * @arg @ref LL_DAC_CHANNEL_2 (1)
1864 *
1865 * (1) On this STM32 serie, parameter not available on all instances.
1866 * Refer to device datasheet for channels availability.
1867 * @retval State of bit (1 or 0).
1868 */
1870 {
1874 }
1876 /**
1877 * @brief Enable DAC DMA Double data mode of the selected channel.
1878 * @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
1879 * MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
1880 * @param DACx DAC instance
1881 * @param DAC_Channel This parameter can be one of the following values:
1882 * @arg @ref LL_DAC_CHANNEL_1
1883 * @arg @ref LL_DAC_CHANNEL_2 (1)
1884 *
1885 * (1) On this STM32 serie, parameter not available on all instances.
1886 * Refer to device datasheet for channels availability.
1887 * @retval None
1888 */
1890 {
1893 }
1895 /**
1896 * @brief Disable DAC DMA Double data mode of the selected channel.
1897 * @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
1898 * MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
1899 * @param DACx DAC instance
1900 * @param DAC_Channel This parameter can be one of the following values:
1901 * @arg @ref LL_DAC_CHANNEL_1
1902 * @arg @ref LL_DAC_CHANNEL_2 (1)
1903 *
1904 * (1) On this STM32 serie, parameter not available on all instances.
1905 * Refer to device datasheet for channels availability.
1906 * @retval None
1907 */
1909 {
1912 }
1914 /**
1915 * @brief Get DAC DMA double data mode state of the selected channel.
1916 * (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
1917 * @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
1918 * MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
1919 * @param DACx DAC instance
1920 * @param DAC_Channel This parameter can be one of the following values:
1921 * @arg @ref LL_DAC_CHANNEL_1
1922 * @arg @ref LL_DAC_CHANNEL_2 (1)
1923 *
1924 * (1) On this STM32 serie, parameter not available on all instances.
1925 * Refer to device datasheet for channels availability.
1926 * @retval State of bit (1 or 0).
1927 */
1928 __STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1929 {
1933 }
1935 /**
1936 * @brief Function to help to configure DMA transfer to DAC: retrieve the
1937 * DAC register address from DAC instance and a list of DAC registers
1938 * intended to be used (most commonly) with DMA transfer.
1939 * @note These DAC registers are data holding registers:
1940 * when DAC conversion is requested, DAC generates a DMA transfer
1941 * request to have data available in DAC data holding registers.
1942 * @note This macro is intended to be used with LL DMA driver, refer to
1943 * function "LL_DMA_ConfigAddresses()".
1944 * Example:
1945 * LL_DMA_ConfigAddresses(DMA1,
1946 * LL_DMA_CHANNEL_1,
1947 * (uint32_t)&< array or variable >,
1948 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
1949 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
1950 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1951 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1952 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
1953 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1954 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
1955 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
1956 * @param DACx DAC instance
1957 * @param DAC_Channel This parameter can be one of the following values:
1958 * @arg @ref LL_DAC_CHANNEL_1
1959 * @arg @ref LL_DAC_CHANNEL_2 (1)
1960 *
1961 * (1) On this STM32 serie, parameter not available on all instances.
1962 * Refer to device datasheet for channels availability.
1963 * @param Register This parameter can be one of the following values:
1964 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
1965 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
1966 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
1967 * @retval DAC register address
1968 */
1969 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
1970 {
1971 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
1972 /* DAC channel selected. */
1975 }
1976 /**
1977 * @}
1978 */
1980 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels
1981 * @{
1982 */
1984 /**
1985 * @brief Enable DAC selected channel.
1986 * @rmtoll CR EN1 LL_DAC_Enable\n
1987 * CR EN2 LL_DAC_Enable
1988 * @note After enable from off state, DAC channel requires a delay
1989 * for output voltage to reach accuracy +/- 1 LSB.
1990 * Refer to device datasheet, parameter "tWAKEUP".
1991 * @param DACx DAC instance
1992 * @param DAC_Channel This parameter can be one of the following values:
1993 * @arg @ref LL_DAC_CHANNEL_1
1994 * @arg @ref LL_DAC_CHANNEL_2 (1)
1995 *
1996 * (1) On this STM32 serie, parameter not available on all instances.
1997 * Refer to device datasheet for channels availability.
1998 * @retval None
1999 */
2001 {
2004 }
2006 /**
2007 * @brief Disable DAC selected channel.
2008 * @rmtoll CR EN1 LL_DAC_Disable\n
2009 * CR EN2 LL_DAC_Disable
2010 * @param DACx DAC instance
2011 * @param DAC_Channel This parameter can be one of the following values:
2012 * @arg @ref LL_DAC_CHANNEL_1
2013 * @arg @ref LL_DAC_CHANNEL_2 (1)
2014 *
2015 * (1) On this STM32 serie, parameter not available on all instances.
2016 * Refer to device datasheet for channels availability.
2017 * @retval None
2018 */
2020 {
2023 }
2025 /**
2026 * @brief Get DAC enable state of the selected channel.
2027 * (0: DAC channel is disabled, 1: DAC channel is enabled)
2028 * @rmtoll CR EN1 LL_DAC_IsEnabled\n
2029 * CR EN2 LL_DAC_IsEnabled
2030 * @param DACx DAC instance
2031 * @param DAC_Channel This parameter can be one of the following values:
2032 * @arg @ref LL_DAC_CHANNEL_1
2033 * @arg @ref LL_DAC_CHANNEL_2 (1)
2034 *
2035 * (1) On this STM32 serie, parameter not available on all instances.
2036 * Refer to device datasheet for channels availability.
2037 * @retval State of bit (1 or 0).
2038 */
2040 {
2044 }
2046 /**
2047 * @brief Get DAC ready for conversion state of the selected channel.
2048 * (0: DAC channel is not ready, 1: DAC channel is ready)
2049 * @rmtoll SR DAC1RDY LL_DAC_IsReady\n
2050 * SR DAC2RDY LL_DAC_IsReady
2051 * @param DACx DAC instance
2052 * @param DAC_Channel This parameter can be one of the following values:
2053 * @arg @ref LL_DAC_CHANNEL_1
2054 * @arg @ref LL_DAC_CHANNEL_2 (1)
2055 *
2056 * (1) On this STM32 serie, parameter not available on all instances.
2057 * Refer to device datasheet for channels availability.
2058 * @retval State of bit (1 or 0).
2059 */
2061 {
2065 }
2067 /**
2068 * @brief Enable DAC trigger of the selected channel.
2069 * @note - If DAC trigger is disabled, DAC conversion is performed
2070 * automatically once the data holding register is updated,
2071 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2072 * @ref LL_DAC_ConvertData12RightAligned(), ...
2073 * - If DAC trigger is enabled, DAC conversion is performed
2074 * only when a hardware of software trigger event is occurring.
2075 * Select trigger source using
2076 * function @ref LL_DAC_SetTriggerSource().
2077 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
2078 * CR TEN2 LL_DAC_EnableTrigger
2079 * @param DACx DAC instance
2080 * @param DAC_Channel This parameter can be one of the following values:
2081 * @arg @ref LL_DAC_CHANNEL_1
2082 * @arg @ref LL_DAC_CHANNEL_2 (1)
2083 *
2084 * (1) On this STM32 serie, parameter not available on all instances.
2085 * Refer to device datasheet for channels availability.
2086 * @retval None
2087 */
2089 {
2092 }
2094 /**
2095 * @brief Disable DAC trigger of the selected channel.
2096 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
2097 * CR TEN2 LL_DAC_DisableTrigger
2098 * @param DACx DAC instance
2099 * @param DAC_Channel This parameter can be one of the following values:
2100 * @arg @ref LL_DAC_CHANNEL_1
2101 * @arg @ref LL_DAC_CHANNEL_2 (1)
2102 *
2103 * (1) On this STM32 serie, parameter not available on all instances.
2104 * Refer to device datasheet for channels availability.
2105 * @retval None
2106 */
2108 {
2111 }
2113 /**
2114 * @brief Get DAC trigger state of the selected channel.
2115 * (0: DAC trigger is disabled, 1: DAC trigger is enabled)
2116 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
2117 * CR TEN2 LL_DAC_IsTriggerEnabled
2118 * @param DACx DAC instance
2119 * @param DAC_Channel This parameter can be one of the following values:
2120 * @arg @ref LL_DAC_CHANNEL_1
2121 * @arg @ref LL_DAC_CHANNEL_2 (1)
2122 *
2123 * (1) On this STM32 serie, parameter not available on all instances.
2124 * Refer to device datasheet for channels availability.
2125 * @retval State of bit (1 or 0).
2126 */
2128 {
2132 }
2134 /**
2135 * @brief Trig DAC conversion by software for the selected DAC channel.
2136 * @note Preliminarily, DAC trigger must be set to software trigger
2137 * using function
2138 * @ref LL_DAC_Init()
2139 * @ref LL_DAC_SetTriggerSource()
2140 * @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
2141 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2142 * and DAC trigger must be enabled using
2143 * function @ref LL_DAC_EnableTrigger().
2144 *
2145 * (1) In case, Sawtooth wave generation has been configured.
2146 * @note For devices featuring DAC with 2 channels: this function
2147 * can perform a SW start of both DAC channels simultaneously.
2148 * Two channels can be selected as parameter.
2149 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2150 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
2151 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
2152 * @param DACx DAC instance
2153 * @param DAC_Channel This parameter can a combination of the following values:
2154 * @arg @ref LL_DAC_CHANNEL_1
2155 * @arg @ref LL_DAC_CHANNEL_2 (1)
2156 *
2157 * (1) On this STM32 serie, parameter not available on all instances.
2158 * Refer to device datasheet for channels availability.
2159 * @retval None
2160 */
2162 {
2165 }
2167 /**
2168 * @brief Trig DAC conversion by secondary software trigger for the selected DAC channel.
2169 * @note Preliminarily, DAC secondary trigger must be set to software trigger
2170 * using function
2171 * @ref LL_DAC_Init()
2172 * @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
2173 * with parameter "LL_DAC_TRIGGER_SOFTWARE".
2174 * and DAC trigger must be enabled using
2175 * function @ref LL_DAC_EnableTrigger().
2176 *
2177 * (1) In case, Sawtooth wave generation has been configured.
2178 * @note For devices featuring DAC with 2 channels: this function
2179 * can perform a SW start of both DAC channels simultaneously.
2180 * Two channels can be selected as parameter.
2181 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
2182 * @rmtoll SWTRIGR SWTRIGB1 LL_DAC_TrigSWConversion2\n
2183 * SWTRIGR SWTRIGB2 LL_DAC_TrigSWConversion2
2184 * @param DACx DAC instance
2185 * @param DAC_Channel This parameter can a combination of the following values:
2186 * @arg @ref LL_DAC_CHANNEL_1
2187 * @arg @ref LL_DAC_CHANNEL_2 (1)
2188 *
2189 * (1) On this STM32 serie, parameter not available on all instances.
2190 * Refer to device datasheet for channels availability.
2191 * @retval None
2192 */
2194 {
2197 }
2199 /**
2200 * @brief Set the data to be loaded in the data holding register
2201 * in format 12 bits left alignment (LSB aligned on bit 0),
2202 * for the selected DAC channel.
2203 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
2204 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
2205 * @param DACx DAC instance
2206 * @param DAC_Channel This parameter can be one of the following values:
2207 * @arg @ref LL_DAC_CHANNEL_1
2208 * @arg @ref LL_DAC_CHANNEL_2 (1)
2209 *
2210 * (1) On this STM32 serie, parameter not available on all instances.
2211 * Refer to device datasheet for channels availability.
2212 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2213 * @retval None
2214 */
2215 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2216 {
2217 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2220 DAC_DHR12R1_DACC1DHR,
2221 Data);
2222 }
2224 /**
2225 * @brief Set the data to be loaded in the data holding register
2226 * in format 12 bits left alignment (MSB aligned on bit 15),
2227 * for the selected DAC channel.
2228 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
2229 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
2230 * @param DACx DAC instance
2231 * @param DAC_Channel This parameter can be one of the following values:
2232 * @arg @ref LL_DAC_CHANNEL_1
2233 * @arg @ref LL_DAC_CHANNEL_2 (1)
2234 *
2235 * (1) On this STM32 serie, parameter not available on all instances.
2236 * Refer to device datasheet for channels availability.
2237 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
2238 * @retval None
2239 */
2240 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2241 {
2242 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2245 DAC_DHR12L1_DACC1DHR,
2246 Data);
2247 }
2249 /**
2250 * @brief Set the data to be loaded in the data holding register
2251 * in format 8 bits left alignment (LSB aligned on bit 0),
2252 * for the selected DAC channel.
2253 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
2254 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
2255 * @param DACx DAC instance
2256 * @param DAC_Channel This parameter can be one of the following values:
2257 * @arg @ref LL_DAC_CHANNEL_1
2258 * @arg @ref LL_DAC_CHANNEL_2 (1)
2259 *
2260 * (1) On this STM32 serie, parameter not available on all instances.
2261 * Refer to device datasheet for channels availability.
2262 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2263 * @retval None
2264 */
2265 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
2266 {
2267 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
2270 DAC_DHR8R1_DACC1DHR,
2271 Data);
2272 }
2275 /**
2276 * @brief Set the data to be loaded in the data holding register
2277 * in format 12 bits left alignment (LSB aligned on bit 0),
2278 * for both DAC channels.
2279 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
2280 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
2281 * @param DACx DAC instance
2282 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2283 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2284 * @retval None
2285 */
2286 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2288 {
2292 }
2294 /**
2295 * @brief Set the data to be loaded in the data holding register
2296 * in format 12 bits left alignment (MSB aligned on bit 15),
2297 * for both DAC channels.
2298 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
2299 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
2300 * @param DACx DAC instance
2301 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
2302 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
2303 * @retval None
2304 */
2305 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2307 {
2308 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
2309 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
2310 /* the 4 LSB must be taken into account for the shift value. */
2314 }
2316 /**
2317 * @brief Set the data to be loaded in the data holding register
2318 * in format 8 bits left alignment (LSB aligned on bit 0),
2319 * for both DAC channels.
2320 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
2321 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
2322 * @param DACx DAC instance
2323 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
2324 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
2325 * @retval None
2326 */
2327 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
2329 {
2333 }
2336 /**
2337 * @brief Retrieve output data currently generated for the selected DAC channel.
2338 * @note Whatever alignment and resolution settings
2339 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
2340 * @ref LL_DAC_ConvertData12RightAligned(), ...),
2341 * output data format is 12 bits right aligned (LSB aligned on bit 0).
2342 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
2343 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData
2344 * @param DACx DAC instance
2345 * @param DAC_Channel This parameter can be one of the following values:
2346 * @arg @ref LL_DAC_CHANNEL_1
2347 * @arg @ref LL_DAC_CHANNEL_2 (1)
2348 *
2349 * (1) On this STM32 serie, parameter not available on all instances.
2350 * Refer to device datasheet for channels availability.
2351 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2352 */
2354 {
2355 register uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
2358 }
2360 /**
2361 * @}
2362 */
2364 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
2365 * @{
2366 */
2367 /**
2368 * @brief Get DAC calibration offset flag for DAC channel 1
2369 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
2370 * @param DACx DAC instance
2371 * @retval State of bit (1 or 0).
2372 */
2374 {
2376 }
2379 /**
2380 * @brief Get DAC calibration offset flag for DAC channel 2
2381 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
2382 * @param DACx DAC instance
2383 * @retval State of bit (1 or 0).
2384 */
2386 {
2388 }
2391 /**
2392 * @brief Get DAC busy writing sample time flag for DAC channel 1
2393 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
2394 * @param DACx DAC instance
2395 * @retval State of bit (1 or 0).
2396 */
2398 {
2400 }
2403 /**
2404 * @brief Get DAC busy writing sample time flag for DAC channel 2
2405 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
2406 * @param DACx DAC instance
2407 * @retval State of bit (1 or 0).
2408 */
2410 {
2412 }
2415 /**
2416 * @brief Get DAC ready status flag for DAC channel 1
2417 * @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
2418 * @param DACx DAC instance
2419 * @retval State of bit (1 or 0).
2420 */
2422 {
2424 }
2427 /**
2428 * @brief Get DAC ready status flag for DAC channel 2
2429 * @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
2430 * @param DACx DAC instance
2431 * @retval State of bit (1 or 0).
2432 */
2434 {
2436 }
2439 /**
2440 * @brief Get DAC output register status flag for DAC channel 1
2441 * @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
2442 * @param DACx DAC instance
2443 * @retval State of bit (1 or 0).
2444 */
2446 {
2448 }
2451 /**
2452 * @brief Get DAC output register status flag for DAC channel 2
2453 * @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
2454 * @param DACx DAC instance
2455 * @retval State of bit (1 or 0).
2456 */
2458 {
2460 }
2463 /**
2464 * @brief Get DAC underrun flag for DAC channel 1
2465 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
2466 * @param DACx DAC instance
2467 * @retval State of bit (1 or 0).
2468 */
2470 {
2472 }
2475 /**
2476 * @brief Get DAC underrun flag for DAC channel 2
2477 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
2478 * @param DACx DAC instance
2479 * @retval State of bit (1 or 0).
2480 */
2482 {
2484 }
2487 /**
2488 * @brief Clear DAC underrun flag for DAC channel 1
2489 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
2490 * @param DACx DAC instance
2491 * @retval None
2492 */
2494 {
2496 }
2499 /**
2500 * @brief Clear DAC underrun flag for DAC channel 2
2501 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
2502 * @param DACx DAC instance
2503 * @retval None
2504 */
2506 {
2508 }
2511 /**
2512 * @}
2513 */
2515 /** @defgroup DAC_LL_EF_IT_Management IT management
2516 * @{
2517 */
2519 /**
2520 * @brief Enable DMA underrun interrupt for DAC channel 1
2521 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
2522 * @param DACx DAC instance
2523 * @retval None
2524 */
2526 {
2528 }
2531 /**
2532 * @brief Enable DMA underrun interrupt for DAC channel 2
2533 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
2534 * @param DACx DAC instance
2535 * @retval None
2536 */
2538 {
2540 }
2543 /**
2544 * @brief Disable DMA underrun interrupt for DAC channel 1
2545 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
2546 * @param DACx DAC instance
2547 * @retval None
2548 */
2550 {
2552 }
2555 /**
2556 * @brief Disable DMA underrun interrupt for DAC channel 2
2557 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
2558 * @param DACx DAC instance
2559 * @retval None
2560 */
2562 {
2564 }
2567 /**
2568 * @brief Get DMA underrun interrupt for DAC channel 1
2569 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
2570 * @param DACx DAC instance
2571 * @retval State of bit (1 or 0).
2572 */
2574 {
2576 }
2579 /**
2580 * @brief Get DMA underrun interrupt for DAC channel 2
2581 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
2582 * @param DACx DAC instance
2583 * @retval State of bit (1 or 0).
2584 */
2586 {
2588 }
2591 /**
2592 * @}
2593 */
2595 #if defined(USE_FULL_LL_DRIVER)
2596 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
2597 * @{
2598 */
2601 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
2604 /**
2605 * @}
2606 */
2609 /**
2610 * @}
2611 */
2613 /**
2614 * @}
2615 */
2619 /**
2620 * @}
2621 */
2623 #ifdef __cplusplus
2624 }
2625 #endif
2629 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/