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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_fmc.h
blob6fb800760261805d72332d90a5b5fdd9c84e956a
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_fmc.h
4 * @author MCD Application Team
5 * @brief Header file of FMC HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_FMC_H
22 #define STM32G4xx_LL_FMC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx_hal_def.h"
30
31 /** @addtogroup STM32G4xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup FMC_LL
36 * @{
37 */
38
39 /** @addtogroup FMC_LL_Private_Macros
40 * @{
41 */
42 #if defined(FMC_BANK1)
43
44 #define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
45 ((__BANK__) == FMC_NORSRAM_BANK2) || \
46 ((__BANK__) == FMC_NORSRAM_BANK3) || \
47 ((__BANK__) == FMC_NORSRAM_BANK4))
48 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
49 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
50 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
51 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
52 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
53 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
55 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
56 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
57 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
58 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
59 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
60 ((__SIZE__) == FMC_PAGE_SIZE_1024))
61 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
62 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
63 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
64 ((__MODE__) == FMC_ACCESS_MODE_B) || \
65 ((__MODE__) == FMC_ACCESS_MODE_C) || \
66 ((__MODE__) == FMC_ACCESS_MODE_D))
67 #define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
68 ((__NBL__) == FMC_NBL_SETUPTIME_1) || \
69 ((__NBL__) == FMC_NBL_SETUPTIME_2) || \
70 ((__NBL__) == FMC_NBL_SETUPTIME_3))
71 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
72 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
73 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
74 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
75 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
76 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
77 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
78 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
79 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
80 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
81 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
82 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
83 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
84 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
85 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
86 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
87 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
88 #define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
89 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
90 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
91 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
92 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
93 #define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
94 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
95 #define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
96 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
97 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
98 #define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U))
99
100 #endif /* FMC_BANK1 */
101 #if defined(FMC_BANK3)
102
103 #define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
104 #define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
105 ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
106 #define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
107 ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
108 #define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
109 ((__STATE__) == FMC_NAND_ECC_ENABLE))
110
111 #define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
112 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
113 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
114 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
116 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
117 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
118 #define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
119 #define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
120 #define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
121 #define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
122 #define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
123 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
124
125 #endif /* FMC_BANK3 */
126
127 /**
128 * @}
129 */
130
131 /* Exported typedef ----------------------------------------------------------*/
132
133 /** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
134 * @{
135 */
136
137 #if defined(FMC_BANK1)
138 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
139 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
140 #endif /* FMC_BANK1 */
141 #if defined(FMC_BANK3)
142 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
143 #endif /* FMC_BANK3 */
144
145 #if defined(FMC_BANK1)
146 #define FMC_NORSRAM_DEVICE FMC_Bank1_R
147 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
148 #endif /* FMC_BANK1 */
149 #if defined(FMC_BANK3)
150 #define FMC_NAND_DEVICE FMC_Bank3_R
151 #endif /* FMC_BANK3 */
152
153 #if defined(FMC_BANK1)
154 /**
155 * @brief FMC NORSRAM Configuration Structure definition
156 */
157 typedef struct
158 {
159 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
160 This parameter can be a value of @ref FMC_NORSRAM_Bank */
161
162 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
163 multiplexed on the data bus or not.
164 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
165
166 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
167 the corresponding memory device.
168 This parameter can be a value of @ref FMC_Memory_Type */
169
170 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
171 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
172
173 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
174 valid only with synchronous burst Flash memories.
175 This parameter can be a value of @ref FMC_Burst_Access_Mode */
176
177 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
178 the Flash memory in burst mode.
179 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
180
181 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
182 clock cycle before the wait state or during the wait state,
183 valid only when accessing memories in burst mode.
184 This parameter can be a value of @ref FMC_Wait_Timing */
185
186 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
187 This parameter can be a value of @ref FMC_Write_Operation */
188
189 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
190 signal, valid for Flash memory access in burst mode.
191 This parameter can be a value of @ref FMC_Wait_Signal */
192
193 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
194 This parameter can be a value of @ref FMC_Extended_Mode */
195
196 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
197 valid only with asynchronous Flash memories.
198 This parameter can be a value of @ref FMC_AsynchronousWait */
199
200 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
201 This parameter can be a value of @ref FMC_Write_Burst */
202
203 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
204 This parameter is only enabled through the FMC_BCR1 register, and don't care
205 through FMC_BCR2..4 registers.
206 This parameter can be a value of @ref FMC_Continous_Clock */
207
208 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
209 This parameter is only enabled through the FMC_BCR1 register, and don't care
210 through FMC_BCR2..4 registers.
211 This parameter can be a value of @ref FMC_Write_FIFO */
212
213 uint32_t PageSize; /*!< Specifies the memory page size.
214 This parameter can be a value of @ref FMC_Page_Size */
215
216 uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
217 This parameter can be a value of @ref FMC_Byte_Lane */
218
219 FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank
220 for PSRAM refresh.
221 This parameter can be set to ENABLE or DISABLE */
222
223 uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous
224 accesses and in HCLK cycles for asynchronous accesses,
225 valid only if MaxChipSelectPulse is ENABLE.
226 This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
227 @note: This parameter is common to all NSBank. */
228
229 }FMC_NORSRAM_InitTypeDef;
230
231 /**
232 * @brief FMC NORSRAM Timing parameters structure definition
233 */
234 typedef struct
235 {
236 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
237 the duration of the address setup time.
238 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
239 @note This parameter is not used with synchronous NOR Flash memories. */
240
241 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
242 the duration of the address hold time.
243 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
244 @note This parameter is not used with synchronous NOR Flash memories. */
245
246 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
247 the duration of the data setup time.
248 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
249 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
250 NOR Flash memories. */
251
252 uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
253 the duration of the data hold time.
254 This parameter can be a value between Min_Data = 0 and Max_Data = 3.
255 @note This parameter is used for used in asynchronous accesses. */
256
257 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
258 the duration of the bus turnaround.
259 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
260 @note This parameter is only used for multiplexed NOR Flash memories. */
261
262 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
263 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
264 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
265 accesses. */
266
267 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
268 to the memory before getting the first data.
269 The parameter value depends on the memory type as shown below:
270 - It must be set to 0 in case of a CRAM
271 - It is don't care in asynchronous NOR, SRAM or ROM accesses
272 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
273 with synchronous burst mode enable */
274
275 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
276 This parameter can be a value of @ref FMC_Access_Mode */
277 }FMC_NORSRAM_TimingTypeDef;
278 #endif /* FMC_BANK1 */
279
280 #if defined(FMC_BANK3)
281 /**
282 * @brief FMC NAND Configuration Structure definition
283 */
284 typedef struct
285 {
286 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
287 This parameter can be a value of @ref FMC_NAND_Bank */
288
289 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
290 This parameter can be any value of @ref FMC_Wait_feature */
291
292 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
293 This parameter can be any value of @ref FMC_NAND_Data_Width */
294
295 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
296 This parameter can be any value of @ref FMC_ECC */
297
298 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
299 This parameter can be any value of @ref FMC_ECC_Page_Size */
300
301 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
302 delay between CLE low and RE low.
303 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
304
305 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
306 delay between ALE low and RE low.
307 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
308 }FMC_NAND_InitTypeDef;
309
310 /**
311 * @brief FMC NAND Timing parameters structure definition
312 */
313 typedef struct
314 {
315 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
316 the command assertion for NAND-Flash read or write access
317 to common/Attribute or I/O memory space (depending on
318 the memory space timing to be configured).
319 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
320
321 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
322 command for NAND-Flash read or write access to
323 common/Attribute or I/O memory space (depending on the
324 memory space timing to be configured).
325 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
326
327 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
328 (and data for write access) after the command de-assertion
329 for NAND-Flash read or write access to common/Attribute
330 or I/O memory space (depending on the memory space timing
331 to be configured).
332 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
333
334 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
335 data bus is kept in HiZ after the start of a NAND-Flash
336 write access to common/Attribute or I/O memory space (depending
337 on the memory space timing to be configured).
338 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
339 }FMC_NAND_PCC_TimingTypeDef;
340 #endif /* FMC_BANK3 */
341
342 /**
343 * @}
344 */
345
346 /* Exported constants --------------------------------------------------------*/
347 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
348 * @{
349 */
350 #if defined(FMC_BANK1)
351
352 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
353 * @{
354 */
355
356 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
357 * @{
358 */
359 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
360 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
361 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
362 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
363 /**
364 * @}
365 */
366
367 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
368 * @{
369 */
370 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
371 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
372 /**
373 * @}
374 */
375
376 /** @defgroup FMC_Memory_Type FMC Memory Type
377 * @{
378 */
379 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
380 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
381 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
382 /**
383 * @}
384 */
385
386 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
387 * @{
388 */
389 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
390 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
391 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
392 /**
393 * @}
394 */
395
396 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
397 * @{
398 */
399 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
400 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
401 /**
402 * @}
403 */
404
405 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
406 * @{
407 */
408 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
409 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
410 /**
411 * @}
412 */
413
414 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
415 * @{
416 */
417 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
418 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
419 /**
420 * @}
421 */
422
423 /** @defgroup FMC_Wait_Timing FMC Wait Timing
424 * @{
425 */
426 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
427 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
428 /**
429 * @}
430 */
431
432 /** @defgroup FMC_Write_Operation FMC Write Operation
433 * @{
434 */
435 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
436 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
437 /**
438 * @}
439 */
440
441 /** @defgroup FMC_Wait_Signal FMC Wait Signal
442 * @{
443 */
444 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
445 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
446 /**
447 * @}
448 */
449
450 /** @defgroup FMC_Extended_Mode FMC Extended Mode
451 * @{
452 */
453 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
454 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
455 /**
456 * @}
457 */
458
459 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
460 * @{
461 */
462 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
463 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
464 /**
465 * @}
466 */
467
468 /** @defgroup FMC_Page_Size FMC Page Size
469 * @{
470 */
471 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
472 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCRx_CPSIZE_0)
473 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCRx_CPSIZE_1)
474 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))
475 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCRx_CPSIZE_2)
476 /**
477 * @}
478 */
479
480 /** @defgroup FMC_Write_Burst FMC Write Burst
481 * @{
482 */
483 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
484 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
485 /**
486 * @}
487 */
488
489 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
490 * @{
491 */
492 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
493 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
494 /**
495 * @}
496 */
497
498 /** @defgroup FMC_Write_FIFO FMC Write FIFO
499 * @{
500 */
501 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
502 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
503 /**
504 * @}
505 */
506
507 /** @defgroup FMC_Access_Mode FMC Access Mode
508 * @{
509 */
510 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
511 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
512 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
513 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
514 /**
515 * @}
516 */
517
518 /** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
519 * @{
520 */
521 #define FMC_NBL_SETUPTIME_0 ((uint32_t)0x00000000U)
522 #define FMC_NBL_SETUPTIME_1 ((uint32_t)0x00400000U)
523 #define FMC_NBL_SETUPTIME_2 ((uint32_t)0x00800000U)
524 #define FMC_NBL_SETUPTIME_3 ((uint32_t)0x00C00000U)
525 /**
526 * @}
527 */
528
529 /**
530 * @}
531 */
532 #endif /* FMC_BANK1 */
533
534 #if defined(FMC_BANK3)
535
536 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
537 * @{
538 */
539 /** @defgroup FMC_NAND_Bank FMC NAND Bank
540 * @{
541 */
542 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
543 /**
544 * @}
545 */
546
547 /** @defgroup FMC_Wait_feature FMC Wait feature
548 * @{
549 */
550 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
551 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
552 /**
553 * @}
554 */
555
556 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
557 * @{
558 */
559 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
560 /**
561 * @}
562 */
563
564 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
565 * @{
566 */
567 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
568 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
569 /**
570 * @}
571 */
572
573 /** @defgroup FMC_ECC FMC ECC
574 * @{
575 */
576 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
577 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
578 /**
579 * @}
580 */
581
582 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
583 * @{
584 */
585 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
586 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
587 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
588 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
589 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
590 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
591 /**
592 * @}
593 */
594
595 /**
596 * @}
597 */
598 #endif /* FMC_BANK3 */
599
600
601 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
602 * @{
603 */
604 #if defined(FMC_BANK3)
605 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
606 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
607 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
608 #endif /* FMC_BANK3 */
609 /**
610 * @}
611 */
612
613 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
614 * @{
615 */
616 #if defined(FMC_BANK3)
617 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
618 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
619 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
620 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
621 #endif /* FMC_BANK3 */
622 /**
623 * @}
624 */
625 /**
626 * @}
627 */
628
629 /**
630 * @}
631 */
632
633 /* Private macro -------------------------------------------------------------*/
634 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
635 * @{
636 */
637 #if defined(FMC_BANK1)
638 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
639 * @brief macros to handle NOR device enable/disable and read/write operations
640 * @{
641 */
642
643 /**
644 * @brief Enable the NORSRAM device access.
645 * @param __INSTANCE__ FMC_NORSRAM Instance
646 * @param __BANK__ FMC_NORSRAM Bank
647 * @retval None
648 */
649 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)
650
651 /**
652 * @brief Disable the NORSRAM device access.
653 * @param __INSTANCE__ FMC_NORSRAM Instance
654 * @param __BANK__ FMC_NORSRAM Bank
655 * @retval None
656 */
657 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)
658
659 /**
660 * @}
661 */
662 #endif /* FMC_BANK1 */
663
664 #if defined(FMC_BANK3)
665 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
666 * @brief macros to handle NAND device enable/disable
667 * @{
668 */
669
670 /**
671 * @brief Enable the NAND device access.
672 * @param __INSTANCE__ FMC_NAND Instance
673 * @retval None
674 */
675 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
676
677 /**
678 * @brief Disable the NAND device access.
679 * @param __INSTANCE__ FMC_NAND Instance
680 * @param __BANK__ FMC_NAND Bank
681 * @retval None
682 */
683 #define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
684
685 /**
686 * @}
687 */
688
689 /** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
690 * @brief macros to handle NAND interrupts
691 * @{
692 */
693
694 /**
695 * @brief Enable the NAND device interrupt.
696 * @param __INSTANCE__ FMC_NAND instance
697 * @param __INTERRUPT__ FMC_NAND interrupt
698 * This parameter can be any combination of the following values:
699 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
700 * @arg FMC_IT_LEVEL: Interrupt level.
701 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
702 * @retval None
703 */
704 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
705
706 /**
707 * @brief Disable the NAND device interrupt.
708 * @param __INSTANCE__ FMC_NAND Instance
709 * @param __INTERRUPT__ FMC_NAND interrupt
710 * This parameter can be any combination of the following values:
711 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
712 * @arg FMC_IT_LEVEL: Interrupt level.
713 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
714 * @retval None
715 */
716 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
717
718 /**
719 * @brief Get flag status of the NAND device.
720 * @param __INSTANCE__ FMC_NAND Instance
721 * @param __BANK__ FMC_NAND Bank
722 * @param __FLAG__ FMC_NAND flag
723 * This parameter can be any combination of the following values:
724 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
725 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
726 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
727 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
728 * @retval The state of FLAG (SET or RESET).
729 */
730 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
731
732 /**
733 * @brief Clear flag status of the NAND device.
734 * @param __INSTANCE__ FMC_NAND Instance
735 * @param __FLAG__ FMC_NAND flag
736 * This parameter can be any combination of the following values:
737 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
738 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
739 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
740 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
741 * @retval None
742 */
743 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
744
745 /**
746 * @}
747 */
748 #endif /* FMC_BANK3 */
749
750 /**
751 * @}
752 */
753
754 /**
755 * @}
756 */
757
758 /* Private functions ---------------------------------------------------------*/
759 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
760 * @{
761 */
762
763 #if defined(FMC_BANK1)
764 /** @defgroup FMC_LL_NORSRAM NOR SRAM
765 * @{
766 */
767 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
768 * @{
769 */
770 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
771 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
772 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
773 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
774 /**
775 * @}
776 */
777
778 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
779 * @{
780 */
781 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
782 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
783 /**
784 * @}
785 */
786 /**
787 * @}
788 */
789 #endif /* FMC_BANK1 */
790
791 #if defined(FMC_BANK3)
792 /** @defgroup FMC_LL_NAND NAND
793 * @{
794 */
795 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
796 * @{
797 */
798 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
799 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
800 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
801 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
802 /**
803 * @}
804 */
805
806 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
807 * @{
808 */
809 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
810 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
811 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
812 /**
813 * @}
814 */
815 /**
816 * @}
817 */
818 #endif /* FMC_BANK3 */
819
820
821
822 /**
823 * @}
824 */
825
826 /**
827 * @}
828 */
829
830 /**
831 * @}
832 */
833
834 #ifdef __cplusplus
835 }
836 #endif
837
838 #endif /* STM32G4xx_LL_FMC_H */
839
840 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/