[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_hrtim.h
| blob | cbd291db9feb24de9fd917a8ff05076cab81bd3f |
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_HRTIM_H
22 #define STM32G4xx_LL_HRTIM_H
24 #ifdef __cplusplus
26 #endif
28 /* Includes ------------------------------------------------------------------*/
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
35 #if defined (HRTIM1)
37 /** @defgroup HRTIM_LL HRTIM
38 * @{
39 */
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
44 * @{
45 */
47 {
55 };
58 {
69 };
72 {
83 };
86 {
97 };
100 {
111 };
114 {
125 };
128 {
139 };
142 {
153 };
156 {
169 };
172 {
185 };
188 {
199 };
202 {
209 };
212 {
221 };
224 {
232 };
235 {
246 };
249 {
256 HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
257 };
260 {
268 };
271 {
284 };
287 {
300 };
303 {
310 };
313 {
320 };
323 {
330 };
333 {
341 };
344 {
352 };
355 {
362 };
365 {
372 };
374 /**
375 * @}
376 */
379 /* Private constants ---------------------------------------------------------*/
380 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
381 * @{
382 */
383 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
384 HRTIM_CR1_TAUDIS |\
385 HRTIM_CR1_TBUDIS |\
386 HRTIM_CR1_TCUDIS |\
387 HRTIM_CR1_TDUDIS |\
388 HRTIM_CR1_TEUDIS |\
389 HRTIM_CR1_TFUDIS))
391 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
392 HRTIM_CR2_TASWU |\
393 HRTIM_CR2_TBSWU |\
394 HRTIM_CR2_TCSWU |\
395 HRTIM_CR2_TDSWU |\
396 HRTIM_CR2_TESWU |\
397 HRTIM_CR2_TFSWU))
399 #define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
400 HRTIM_CR2_SWPB |\
401 HRTIM_CR2_SWPC |\
402 HRTIM_CR2_SWPD |\
403 HRTIM_CR2_SWPE |\
404 HRTIM_CR2_SWPF))
406 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
407 HRTIM_CR2_TARST |\
408 HRTIM_CR2_TBRST |\
409 HRTIM_CR2_TCRST |\
410 HRTIM_CR2_TDRST |\
411 HRTIM_CR2_TERST |\
412 HRTIM_CR2_TFRST))
414 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
415 HRTIM_OENR_TA2OEN |\
416 HRTIM_OENR_TB1OEN |\
417 HRTIM_OENR_TB2OEN |\
418 HRTIM_OENR_TC1OEN |\
419 HRTIM_OENR_TC2OEN |\
420 HRTIM_OENR_TD1OEN |\
421 HRTIM_OENR_TD2OEN |\
422 HRTIM_OENR_TE1OEN |\
423 HRTIM_OENR_TE2OEN |\
424 HRTIM_OENR_TF1OEN |\
425 HRTIM_OENR_TF2OEN))
427 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
428 HRTIM_ODISR_TA2ODIS |\
429 HRTIM_ODISR_TB1ODIS |\
430 HRTIM_ODISR_TB2ODIS |\
431 HRTIM_ODISR_TC1ODIS |\
432 HRTIM_ODISR_TC2ODIS |\
433 HRTIM_ODISR_TD1ODIS |\
434 HRTIM_ODISR_TD2ODIS |\
435 HRTIM_ODISR_TE1ODIS |\
436 HRTIM_ODISR_TE2ODIS |\
437 HRTIM_ODISR_TF1ODIS |\
438 HRTIM_ODISR_TF2ODIS))
440 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
441 HRTIM_OUTR_IDLM1 |\
442 HRTIM_OUTR_IDLES1 |\
443 HRTIM_OUTR_FAULT1 |\
444 HRTIM_OUTR_CHP1 |\
445 HRTIM_OUTR_DIDL1))
447 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
448 HRTIM_EECR1_EE1POL |\
449 HRTIM_EECR1_EE1SNS |\
450 HRTIM_EECR1_EE1FAST))
452 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
453 HRTIM_FLTINR1_FLT1SRC_0 ))
455 #define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
456 HRTIM_FLTINR2_FLT5SRC_1 |\
457 HRTIM_FLTINR2_FLT4SRC_1 |\
458 HRTIM_FLTINR2_FLT3SRC_1 |\
459 HRTIM_FLTINR2_FLT2SRC_1 |\
460 HRTIM_FLTINR2_FLT1SRC_1))
462 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
463 HRTIM_BMCR_BMCLK |\
464 HRTIM_BMCR_BMOM))
466 /**
467 * @}
468 */
471 /* Private macros ------------------------------------------------------------*/
472 /* Exported types ------------------------------------------------------------*/
473 #if defined(USE_FULL_LL_DRIVER)
474 /** @defgroup HRTIM_LL_ES_INIT HRTIM Exported Init structure
475 * @{
476 */
477 /* TO BE COMPLETED */
478 /**
479 * @}
480 */
483 /* Exported constants --------------------------------------------------------*/
484 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
485 * @{
486 */
488 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
489 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function
490 * @{
491 */
492 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
493 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
494 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
495 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
496 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
497 #define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
498 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
499 #define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
500 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
502 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
503 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
504 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
505 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
506 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
507 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
508 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
510 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
511 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
512 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
513 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
514 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
515 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
516 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
517 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
518 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
519 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
520 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
521 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
522 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
523 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
524 /**
525 * @}
526 */
528 /** @defgroup HRTIM_LL_EC_IT IT Defines
529 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
530 * @{
531 */
532 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
533 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
534 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
535 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
536 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
537 #define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
538 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
539 #define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
540 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
542 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
543 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
544 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
545 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
546 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
547 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
548 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
550 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
551 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
552 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
553 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
554 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
555 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
556 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
557 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
558 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
559 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
560 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
561 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
562 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
563 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
564 /**
565 * @}
566 */
568 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
569 * @{
570 * @brief Constants defining defining the synchronization input source.
571 */
572 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
573 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
574 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
575 /**
576 * @}
577 */
579 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
580 * @{
581 * @brief Constants defining the source and event to be sent on the synchronization output.
582 */
583 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
584 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
585 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
586 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
587 /**
588 * @}
589 */
591 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
592 * @{
593 * @brief Constants defining the routing and conditioning of the synchronization output event.
594 */
596 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
597 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
598 /**
599 * @}
600 */
602 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID
603 * @{
604 * @brief Constants identifying a timing unit.
605 */
615 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
616 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
617 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
618 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
620 /**
621 * @}
622 */
624 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
625 * @{
626 * @brief Constants identifying an HRTIM output.
627 */
640 /**
641 * @}
642 */
644 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
645 * @{
646 * @brief Constants identifying a compare unit.
647 */
650 /**
651 * @}
652 */
654 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
655 * @{
656 * @brief Constants identifying a capture unit.
657 */
660 /**
661 * @}
662 */
664 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID
665 * @{
666 * @brief Constants identifying a fault channel.
667 */
674 /**
675 * @}
676 */
678 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
679 * @{
680 * @brief Constants identifying an external event channel.
681 */
692 /**
693 * @}
694 */
696 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
697 * @{
698 * @brief Constants defining the state of an HRTIM output.
699 */
700 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
701 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
702 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
703 /**
704 * @}
705 */
707 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
708 * @{
709 * @brief Constants identifying an ADC trigger.
710 */
721 /**
722 * @}
723 */
725 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
726 * @{
727 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
728 */
729 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
730 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
731 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
732 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
733 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
734 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
735 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
736 /**
737 * @}
738 */
740 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
741 * @{
742 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
743 */
755 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
756 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
757 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
758 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
759 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
760 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
761 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
762 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
763 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
764 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
765 #define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
766 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
767 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
768 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
769 #define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
770 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
771 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
772 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
773 #define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
774 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
775 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
776 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
777 /**
778 * @}
779 */
781 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
782 * @{
783 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
784 */
795 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
796 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
797 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
798 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
799 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
800 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
801 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
802 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
803 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
804 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
805 #define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
806 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
807 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
808 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
809 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
810 #define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
811 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
812 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
813 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
814 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
815 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
816 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
817 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
818 /**
819 * @}
820 */
822 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
823 * @{
824 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
825 */
826 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
827 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
828 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
829 #define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
830 #define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
831 #define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
832 #define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
833 #define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
834 #define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
835 #define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
836 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
837 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
838 #define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
839 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
840 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
841 #define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
842 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
843 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
844 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
845 #define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
846 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
847 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
848 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
849 #define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
850 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
851 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
852 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
853 #define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
854 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
855 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
856 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
857 #define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
858 /**
859 * @}
860 */
862 /** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
863 * @{
864 * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
865 */
866 #define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
867 #define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
868 #define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
869 #define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
870 #define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
871 #define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
872 #define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
873 #define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
874 #define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
875 #define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
876 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
877 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
878 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
879 #define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
880 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
881 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
882 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
883 #define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
884 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
885 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
886 #define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
887 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
888 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
889 #define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
890 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
891 #define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
892 #define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
893 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
894 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
895 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
896 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
897 #define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
898 /**
899 * @}
900 */
902 /** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
903 * @{
904 * @brief Constants defining the DLL calibration mode.
905 */
906 #define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is perfomed only once */
907 #define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
908 /**
909 * @}
910 */
912 /** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
913 * @{
914 * @brief Constants defining the DLL calibration periods (in micro seconds).
915 */
916 #define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
917 #define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
918 #define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
919 #define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
920 /**
921 * @}
922 */
924 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
925 * @{
926 * @brief Constants defining timer high-resolution clock prescaler ratio.
927 */
928 #define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
929 #define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
930 #define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
931 #define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
932 #define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
933 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
934 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
935 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
936 /**
937 * @}
938 */
940 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
941 * @{
942 * @brief Constants defining timer counter operating mode.
943 */
944 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
945 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
946 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
947 /**
948 * @}
949 */
951 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
952 * @{
953 * @brief Constants defining on which output the DAC synchronization event is sent.
954 */
956 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
957 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
958 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
959 /**
960 * @}
961 */
963 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
964 * @{
965 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
966 */
968 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
969 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
970 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
971 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
972 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
973 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
974 #define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
975 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
976 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
977 /**
978 * @}
979 */
981 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
982 * @{
983 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
984 */
985 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
986 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
987 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
988 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
989 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
990 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
991 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
992 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
993 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
994 /**
995 * @}
996 */
998 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
999 * @{
1000 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
1001 */
1003 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
1004 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
1005 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
1006 /**
1007 * @}
1008 */
1010 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
1011 * @{
1012 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
1013 */
1015 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
1016 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
1017 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
1018 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
1019 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
1020 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
1021 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
1022 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
1023 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
1024 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
1025 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
1026 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
1027 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
1028 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
1029 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
1030 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
1031 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
1032 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
1033 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1034 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1035 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1036 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1037 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1038 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1039 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1040 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1041 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1042 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1043 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1044 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1045 #define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
1046 #define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
1047 #define LL_HRTIM_RESETTRIG_OTHER5_CMP4 HRTIM_RSTR_TIMFCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
1048 /**
1049 * @}
1050 */
1052 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
1053 * @{
1054 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
1055 */
1057 #define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
1058 #define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
1059 #define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
1060 #define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
1061 #define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
1062 #define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
1063 #define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
1064 #define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
1065 #define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
1066 #define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
1067 #define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
1068 #define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
1069 #define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
1070 #define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
1071 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
1072 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
1073 #define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
1074 #define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
1075 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
1076 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
1077 #define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
1078 #define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
1079 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
1080 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
1081 #define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
1082 #define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
1083 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
1084 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
1085 #define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
1086 #define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
1087 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
1088 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
1089 #define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
1090 #define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
1091 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
1092 #define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
1093 /**
1094 * @}
1095 */
1097 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
1098 * @{
1099 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
1100 */
1101 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
1102 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
1103 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
1104 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
1105 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
1106 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
1107 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
1108 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
1110 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
1111 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
1112 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
1113 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
1114 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
1115 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
1116 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
1117 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
1118 /**
1119 * @}
1120 */
1122 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
1123 * @{
1124 * @brief Constants defining how the timer behaves during a burst mode operation.
1125 */
1126 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
1127 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
1128 /**
1129 * @}
1130 */
1132 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
1133 * @{
1134 * @brief Constants defining the registers that can be written during a burst DMA operation.
1135 */
1136 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
1137 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
1138 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
1139 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
1140 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
1141 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
1142 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
1143 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
1144 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
1145 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
1146 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
1147 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
1148 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
1149 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
1150 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
1151 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
1152 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
1153 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
1154 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
1155 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
1156 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
1157 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
1158 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
1159 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
1160 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
1161 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
1162 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
1163 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
1164 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
1165 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
1166 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
1167 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
1168 #define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
1169 #define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
1170 /**
1171 * @}
1172 */
1174 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
1175 * @{
1176 * @brief Constants defining on which output the signal is currently applied in push-pull mode.
1177 */
1178 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
1179 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
1180 /**
1181 * @}
1182 */
1184 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
1185 * @{
1186 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
1187 */
1188 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1189 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1190 /**
1191 * @}
1192 */
1194 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
1195 * @{
1196 * @brief Constants defining the event filtering applied to external events by a timer.
1197 */
1198 #define LL_HRTIM_EEFLTR_NONE (0x00000000U)
1199 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
1200 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
1201 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
1202 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
1203 /* Blanking Filter for TIMER A */
1204 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1205 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1206 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1207 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1208 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1209 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1210 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1211 #define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1212 /* Blanking Filter for TIMER B */
1213 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1214 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1215 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1216 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1217 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1218 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1219 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1220 #define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1221 /* Blanking Filter for TIMER C */
1222 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1223 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1224 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1225 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1226 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1227 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1228 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1229 #define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1230 /* Blanking Filter for TIMER D */
1231 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1232 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1233 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1234 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1235 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1236 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1237 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1238 #define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1239 /* Blanking Filter for TIMER E */
1240 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1241 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1242 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1243 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1244 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1245 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1246 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1247 #define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1248 /* Blanking Filter for TIMER F */
1249 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1250 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1251 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1252 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1253 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1254 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1255 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1256 #define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1258 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
1259 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
1260 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
1262 /**
1263 * @}
1264 */
1266 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
1267 * @{
1268 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
1269 */
1270 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
1271 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1272 /**
1273 * @}
1274 */
1276 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
1277 * @{
1278 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
1279 */
1283 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1285 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
1286 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
1287 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
1288 /**
1289 * @}
1290 */
1292 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
1293 * @{
1294 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
1295 */
1298 /**
1299 * @}
1300 */
1302 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
1303 * @{
1304 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
1305 */
1307 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1308 /**
1309 * @}
1310 */
1312 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
1313 * @{
1314 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
1315 */
1319 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1321 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1322 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1323 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1325 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1326 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1327 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1328 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1329 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1330 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1331 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1332 /**
1333 * @}
1334 */
1336 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
1337 * @{
1338 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
1339 */
1341 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
1342 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
1343 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
1344 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
1345 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
1346 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
1347 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
1348 /**
1349 * @}
1350 */
1352 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
1353 * @{
1354 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
1355 */
1359 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1361 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1362 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1363 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1365 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1366 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1367 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1368 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1369 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1370 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1371 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1372 /**
1373 * @}
1374 */
1376 /** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
1377 * @{
1378 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
1379 */
1381 #define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */
1382 #define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transision */
1383 #define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transision */
1384 #define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transision */
1385 #define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transision */
1386 #define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transision */
1387 #define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transision */
1388 #define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transision */
1389 #define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transision */
1390 #define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transision */
1391 #define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transision */
1393 /* Timer Events mapping for Timer A */
1394 #define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its ictive state */
1395 #define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1396 #define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1397 #define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1398 #define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1399 #define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1400 #define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1401 #define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1402 #define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1403 /* Timer Events mapping for Timer B */
1404 #define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1405 #define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1406 #define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1407 #define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1408 #define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1409 #define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1410 #define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1411 #define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1412 #define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1413 /* Timer Events mapping for Timer C */
1414 #define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1415 #define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1416 #define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1417 #define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1418 #define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1419 #define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1420 #define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1421 #define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1422 #define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1423 /* Timer Events mapping for Timer D */
1424 #define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1425 #define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1426 #define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1427 #define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1428 #define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1429 #define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1430 #define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1431 #define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1432 #define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1433 /* Timer Events mapping for Timer E */
1434 #define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1435 #define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1436 #define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1437 #define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1438 #define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1439 #define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1440 #define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1441 #define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1442 #define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1443 /* Timer Events mapping for Timer F */
1444 #define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
1445 #define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
1446 #define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
1447 #define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
1448 #define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
1449 #define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
1450 #define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
1451 #define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
1452 #define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
1453 #define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transision */
1454 #define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transision */
1455 #define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transision */
1456 #define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transision */
1457 #define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transision */
1458 #define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transision */
1459 #define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transision */
1460 #define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transision */
1461 #define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transision */
1462 #define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transision */
1463 #define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transision */
1464 /**
1465 * @}
1466 */
1468 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
1469 * @{
1470 * @brief Constants defining the events that can be selected to configure the
1471 * set crossbar of a timer output
1472 */
1474 #define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
1475 #define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
1476 #define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
1477 #define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
1478 #define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
1479 #define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
1480 #define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
1481 #define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
1482 #define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
1483 #define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
1484 #define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
1485 /* Timer Events mapping for Timer A */
1486 #define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1487 #define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1488 #define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1489 #define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1490 #define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1491 #define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1492 #define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1493 #define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1494 #define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1495 /* Timer Events mapping for Timer B */
1496 #define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1497 #define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1498 #define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1499 #define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1500 #define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1501 #define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1502 #define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1503 #define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1504 #define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1505 /* Timer Events mapping for Timer C */
1506 #define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1507 #define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1508 #define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1509 #define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1510 #define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1511 #define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1512 #define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1513 #define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1514 #define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1515 /* Timer Events mapping for Timer D */
1516 #define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1517 #define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1518 #define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1519 #define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1520 #define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1521 #define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1522 #define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1523 #define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1524 #define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1525 /* Timer Events mapping for Timer E */
1526 #define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1527 #define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1528 #define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1529 #define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1530 #define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1531 #define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1532 #define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1533 #define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1534 #define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1535 /* Timer Events mapping for Timer F */
1536 #define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
1537 #define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
1538 #define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
1539 #define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
1540 #define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
1541 #define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
1542 #define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
1543 #define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
1544 #define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
1545 #define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
1546 #define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
1547 #define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
1548 #define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
1549 #define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
1550 #define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
1551 #define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
1552 #define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
1553 #define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
1554 #define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
1555 #define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
1556 /**
1557 * @}
1558 */
1560 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
1561 * @{
1562 * @brief Constants defining the polarity of a timer output.
1563 */
1566 /**
1567 * @}
1568 */
1570 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
1571 * @{
1572 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
1573 */
1574 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
1575 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
1576 /**
1577 * @}
1578 */
1580 /** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
1581 * @{
1582 * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
1583 */
1586 #define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
1587 #define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
1588 /**
1589 * @}
1590 */
1591 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
1592 * @{
1593 * @brief Constants defining the half mode of an HRTIM Timer instance.
1594 */
1597 /**
1598 * @}
1599 */
1601 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
1602 * @{
1603 * @brief Constants defining the output level when output is in IDLE state
1604 */
1605 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
1606 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
1607 /**
1608 * @}
1609 */
1611 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
1612 * @{
1613 * @brief Constants defining the output level when output is in FAULT state.
1614 */
1615 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
1616 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
1617 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
1618 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
1619 /**
1620 * @}
1621 */
1623 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
1624 * @{
1625 * @brief Constants defining whether or not chopper mode is enabled for a timer output.
1626 */
1628 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1629 /**
1630 * @}
1631 */
1633 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
1634 * @{
1635 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
1636 during a programmable period before the output takes its idle state.
1637 */
1638 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1639 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1640 /**
1641 * @}
1642 */
1643 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
1644 * @{
1645 * @brief Constants defining the level of a timer output.
1646 */
1647 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
1648 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
1649 /**
1650 * @}
1651 */
1653 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
1654 * @{
1655 * @brief Constants defining available sources associated to external events.
1656 */
1666 #define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
1667 #define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
1668 #define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
1669 #define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
1670 #define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
1671 #define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
1672 #define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
1673 #define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
1674 #define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
1675 #define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
1676 #define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
1677 #define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
1678 #define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
1679 #define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
1680 #define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
1681 #define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
1682 #define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
1683 #define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
1684 #define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
1685 #define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
1686 #define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
1687 #define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
1688 #define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
1689 #define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
1690 #define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
1691 #define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
1692 #define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
1693 #define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
1694 #define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
1695 #define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
1696 #define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
1697 /**
1698 * @}
1699 */
1700 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
1701 * @{
1702 * @brief Constants defining the polarity of an external event.
1703 */
1706 /**
1707 * @}
1708 */
1710 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
1711 * @{
1712 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
1713 */
1715 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1716 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1717 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1718 /**
1719 * @}
1720 */
1722 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
1723 * @{
1724 * @brief Constants defining whether or not an external event is programmed in fast mode.
1725 */
1726 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1727 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1728 /**
1729 * @}
1730 */
1732 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
1733 * @{
1734 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
1735 */
1739 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
1741 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
1742 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
1743 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
1745 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
1746 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
1747 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
1748 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
1749 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
1750 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
1751 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
1752 /**
1753 * @}
1754 */
1756 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
1757 * @{
1758 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
1759 */
1763 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
1764 /**
1765 * @}
1766 */
1768 /** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
1769 * @{
1770 * @brief Constants defining the external event counter.
1771 */
1774 /**
1775 * @}
1776 */
1778 /** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
1779 * @{
1780 * @brief Constants defining the external event reset mode.
1781 */
1782 #define LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
1783 #define LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
1784 /**
1785 * @}
1786 */
1788 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
1789 * @{
1790 * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
1791 */
1793 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1794 #define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
1795 /**
1796 * @}
1797 */
1799 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
1800 * @{
1801 * @brief Constants defining the polarity of a fault event.
1802 */
1805 /**
1806 * @}
1807 */
1809 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
1810 * @{
1811 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
1812 */
1816 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
1818 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
1819 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
1820 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
1822 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
1823 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
1824 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
1825 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
1826 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
1827 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
1828 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
1829 /**
1830 * @}
1831 */
1833 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
1834 * @{
1835 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
1836 */
1840 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
1841 /**
1842 * @}
1843 */
1845 /** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
1846 * @{
1847 * @brief Constants defining the Blanking Source of a fault event.
1848 */
1849 #define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
1850 #define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
1851 /**
1852 * @}
1853 */
1855 /** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
1856 * @{
1857 * @brief Constants defining the Counter RESet Mode of a fault event.
1858 */
1859 #define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
1860 #define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
1861 period. */
1862 /**
1863 * @}
1864 */
1866 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
1867 * @{
1868 * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
1869 */
1870 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
1871 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1872 /**
1873 * @}
1874 */
1876 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
1877 * @{
1878 * @brief Constants defining the clock source for the burst mode counter.
1879 */
1880 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1881 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1882 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1883 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1884 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1885 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1886 #define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
1887 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1888 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1889 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1890 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1891 /**
1892 * @}
1893 */
1895 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
1896 * @{
1897 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
1898 */
1902 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
1904 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
1905 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
1906 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
1908 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
1909 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
1910 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
1911 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
1912 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
1913 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
1914 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
1915 /**
1916 * @}
1917 */
1919 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
1920 * @{
1921 * @brief Constants defining the events that can be used to trig the burst mode operation.
1922 */
1924 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
1925 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
1926 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
1927 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
1928 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
1929 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
1930 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
1931 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
1932 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
1933 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
1934 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
1935 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
1936 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
1937 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
1938 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
1939 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
1940 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
1941 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */
1942 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
1943 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
1944 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */
1945 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
1946 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */
1947 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
1948 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
1949 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
1950 #define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
1951 #define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
1952 #define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
1953 #define LL_HRTIM_BM_TRIG_TIMF_CMP2 (HRTIM_BMTRGR_TFCMP2) /*!< Timer F compare 2 event is starting the burst mode operation */
1954 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
1955 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
1956 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
1957 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
1958 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
1959 /**
1960 * @}
1961 */
1963 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
1964 * @{
1965 * @brief Constants defining the operating state of the burst mode controller.
1966 */
1969 /**
1970 * @}
1971 */
1973 /** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
1974 * @{
1975 * @brief Constants defining the Counter Up Down Mode.
1976 */
1978 #define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
1979 /**
1980 * @}
1981 */
1983 /** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
1984 * @{
1985 * @brief Constants defining the Roll-Over counter Mode.
1986 */
1987 #define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
1988 #define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
1989 #define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
1990 /**
1991 * @}
1992 */
1994 /** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
1995 * @{
1996 * @brief Constants defining how the timer counter operates.
1997 */
1998 #define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
1999 #define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
2000 /**
2001 * @}
2002 */
2004 /** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
2005 * @{
2006 * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
2007 */
2008 #define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
2009 #define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
2010 #define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
2011 #define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
2012 /**
2013 * @}
2014 */
2016 /** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
2017 * @{
2018 * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
2019 */
2020 #define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2021 #define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
2022 /**
2023 * @}
2024 */
2026 /** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
2027 * @{
2028 * @brief Constants defining the Dual Channel DAC Reset trigger.
2029 */
2030 #define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
2031 #define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
2032 /**
2033 * @}
2034 */
2036 /** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
2037 * @{
2038 * @brief Constants defining the Dual Channel DAC Step trigger.
2039 */
2041 #define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
2042 /**
2043 * @}
2044 */
2046 /**
2047 * @}
2048 */
2050 /* Exported macro ------------------------------------------------------------*/
2051 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
2052 * @{
2053 */
2055 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
2056 * @{
2057 */
2059 /**
2060 * @brief Write a value in HRTIM register
2061 * @param __INSTANCE__ HRTIM Instance
2062 * @param __REG__ Register to be written
2063 * @param __VALUE__ Value to be written in the register
2064 * @retval None
2065 */
2066 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2068 /**
2069 * @brief Read a value in HRTIM register
2070 * @param __INSTANCE__ HRTIM Instance
2071 * @param __REG__ Register to be read
2072 * @retval Register value
2073 */
2074 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2075 /**
2076 * @}
2077 */
2079 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
2080 * @{
2081 */
2082 /**
2083 * @brief HELPER macro returning the output state from output enable/disable status
2084 * @param __OUTPUT_STATUS_EN__ output enable status
2085 * @param __OUTPUT_STATUS_DIS__ output Disable status
2086 * @retval Returned value can be one of the following values:
2087 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
2088 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
2089 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
2090 */
2091 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
2092 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
2093 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
2094 /**
2095 * @}
2096 */
2098 /**
2099 * @}
2100 */
2102 /* Exported functions --------------------------------------------------------*/
2103 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
2104 * @{
2105 */
2106 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
2107 * @{
2108 */
2110 /**
2111 * @brief Select the HRTIM synchronization input source.
2112 * @note This function must not be called when the concerned timer(s) is (are) enabled .
2113 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2114 * @param HRTIMx High Resolution Timer instance
2115 * @param SyncInSrc This parameter can be one of the following values:
2116 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2117 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2118 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2119 * @retval None
2120 */
2122 {
2124 }
2126 /**
2127 * @brief Get actual HRTIM synchronization input source.
2128 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
2129 * @param HRTIMx High Resolution Timer instance
2130 * @retval SyncInSrc Returned value can be one of the following values:
2131 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
2132 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
2133 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
2134 */
2136 {
2138 }
2140 /**
2141 * @brief Configure the HRTIM synchronization output.
2142 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
2143 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut
2144 * @param HRTIMx High Resolution Timer instance
2145 * @param Config This parameter can be one of the following values:
2146 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2147 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2148 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2149 * @param Src This parameter can be one of the following values:
2150 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2151 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2152 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2153 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2154 * @retval None
2155 */
2156 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
2157 {
2158 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
2159 }
2161 /**
2162 * @brief Set the routing and conditioning of the synchronization output event.
2163 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
2164 * @note This function can be called only when the master timer is enabled.
2165 * @param HRTIMx High Resolution Timer instance
2166 * @param SyncOutConfig This parameter can be one of the following values:
2167 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2168 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2169 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2170 * @retval None
2171 */
2173 {
2175 }
2177 /**
2178 * @brief Get actual routing and conditioning of the synchronization output event.
2179 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
2180 * @param HRTIMx High Resolution Timer instance
2181 * @retval SyncOutConfig Returned value can be one of the following values:
2182 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED
2183 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
2184 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
2185 */
2187 {
2189 }
2191 /**
2192 * @brief Set the source and event to be sent on the HRTIM synchronization output.
2193 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
2194 * @param HRTIMx High Resolution Timer instance
2195 * @param SyncOutSrc This parameter can be one of the following values:
2196 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2197 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2198 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2199 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2200 * @retval None
2201 */
2203 {
2205 }
2207 /**
2208 * @brief Get actual source and event sent on the HRTIM synchronization output.
2209 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
2210 * @param HRTIMx High Resolution Timer instance
2211 * @retval SyncOutSrc Returned value can be one of the following values:
2212 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
2213 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
2214 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
2215 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
2216 */
2218 {
2220 }
2222 /**
2223 * @brief Disable (temporarily) update event generation.
2224 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
2225 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
2226 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
2227 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
2228 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
2229 * CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
2230 * CR1 TFUDIS LL_HRTIM_SuspendUpdate
2231 * @note Allow to temporarily disable the transfer from preload to active
2232 * registers, whatever the selected update event. This allows to modify
2233 * several registers in multiple timers.
2234 * @param HRTIMx High Resolution Timer instance
2235 * @param Timers This parameter can be a combination of the following values:
2236 * @arg @ref LL_HRTIM_TIMER_MASTER
2237 * @arg @ref LL_HRTIM_TIMER_A
2238 * @arg @ref LL_HRTIM_TIMER_B
2239 * @arg @ref LL_HRTIM_TIMER_C
2240 * @arg @ref LL_HRTIM_TIMER_D
2241 * @arg @ref LL_HRTIM_TIMER_E
2242 * @arg @ref LL_HRTIM_TIMER_F
2243 * @retval None
2244 */
2246 {
2247 /* clear register before applying the new value */
2248 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
2250 }
2252 /**
2253 * @brief Enable update event generation.
2254 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
2255 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
2256 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
2257 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
2258 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
2259 * CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
2260 * CR1 TFUDIS LL_HRTIM_ResumeUpdate
2261 * @note The regular update event takes place.
2262 * @param HRTIMx High Resolution Timer instance
2263 * @param Timers This parameter can be a combination of the following values:
2264 * @arg @ref LL_HRTIM_TIMER_MASTER
2265 * @arg @ref LL_HRTIM_TIMER_A
2266 * @arg @ref LL_HRTIM_TIMER_B
2267 * @arg @ref LL_HRTIM_TIMER_C
2268 * @arg @ref LL_HRTIM_TIMER_D
2269 * @arg @ref LL_HRTIM_TIMER_E
2270 * @arg @ref LL_HRTIM_TIMER_F
2271 * @retval None
2272 */
2274 {
2276 }
2278 /**
2279 * @brief Force an immediate transfer from the preload to the active register .
2280 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
2281 * CR2 TASWU LL_HRTIM_ForceUpdate\n
2282 * CR2 TBSWU LL_HRTIM_ForceUpdate\n
2283 * CR2 TCSWU LL_HRTIM_ForceUpdate\n
2284 * CR2 TDSWU LL_HRTIM_ForceUpdate\n
2285 * CR2 TESWU LL_HRTIM_ForceUpdate\n
2286 * CR2 TFSWU LL_HRTIM_ForceUpdate
2287 * @note Any pending update request is cancelled.
2288 * @param HRTIMx High Resolution Timer instance
2289 * @param Timers This parameter can be a combination of the following values:
2290 * @arg @ref LL_HRTIM_TIMER_MASTER
2291 * @arg @ref LL_HRTIM_TIMER_A
2292 * @arg @ref LL_HRTIM_TIMER_B
2293 * @arg @ref LL_HRTIM_TIMER_C
2294 * @arg @ref LL_HRTIM_TIMER_D
2295 * @arg @ref LL_HRTIM_TIMER_E
2296 * @arg @ref LL_HRTIM_TIMER_F
2297 * @retval None
2298 */
2300 {
2302 }
2304 /**
2305 * @brief Reset the HRTIM timer(s) counter.
2306 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
2307 * CR2 TARST LL_HRTIM_CounterReset\n
2308 * CR2 TBRST LL_HRTIM_CounterReset\n
2309 * CR2 TCRST LL_HRTIM_CounterReset\n
2310 * CR2 TDRST LL_HRTIM_CounterReset\n
2311 * CR2 TERST LL_HRTIM_CounterReset\n
2312 * CR2 TFRST LL_HRTIM_CounterReset
2313 * @param HRTIMx High Resolution Timer instance
2314 * @param Timers This parameter can be a combination of the following values:
2315 * @arg @ref LL_HRTIM_TIMER_MASTER
2316 * @arg @ref LL_HRTIM_TIMER_A
2317 * @arg @ref LL_HRTIM_TIMER_B
2318 * @arg @ref LL_HRTIM_TIMER_C
2319 * @arg @ref LL_HRTIM_TIMER_D
2320 * @arg @ref LL_HRTIM_TIMER_E
2321 * @arg @ref LL_HRTIM_TIMER_F
2322 * @retval None
2323 */
2325 {
2326 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
2327 }
2329 /**
2330 * @brief enable the swap of the Timer Output.
2331 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2332 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2333 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2334 * @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
2335 * CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
2336 * CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
2337 * CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
2338 * CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
2339 * CR2 SWPF LL_HRTIM_EnableSwapOutputs
2340 * @param HRTIMx High Resolution Timer instance
2341 * @param Timer This parameter can be one of the following values:
2342 * @arg @ref LL_HRTIM_TIMER_A
2343 * @arg @ref LL_HRTIM_TIMER_B
2344 * @arg @ref LL_HRTIM_TIMER_C
2345 * @arg @ref LL_HRTIM_TIMER_D
2346 * @arg @ref LL_HRTIM_TIMER_E
2347 * @arg @ref LL_HRTIM_TIMER_F
2348 * @retval None
2349 */
2351 {
2355 }
2357 /**
2358 * @brief disable the swap of the Timer Output.
2359 * @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2360 * and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2361 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2362 * @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
2363 * CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
2364 * CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
2365 * CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
2366 * CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
2367 * CR2 SWPF LL_HRTIM_DisableSwapOutputs
2368 * @param HRTIMx High Resolution Timer instance
2369 * @param Timer This parameter can be one of the following values:
2370 * @arg @ref LL_HRTIM_TIMER_A
2371 * @arg @ref LL_HRTIM_TIMER_B
2372 * @arg @ref LL_HRTIM_TIMER_C
2373 * @arg @ref LL_HRTIM_TIMER_D
2374 * @arg @ref LL_HRTIM_TIMER_E
2375 * @arg @ref LL_HRTIM_TIMER_F
2376 * @retval None
2377 */
2379 {
2383 }
2385 /**
2386 * @brief reports the Timer Outputs swap position.
2387 * @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
2388 * @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
2389 * CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
2390 * CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
2391 * CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
2392 * CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
2393 * CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
2394 * @param HRTIMx High Resolution Timer instance
2395 * @param Timer This parameter can be one of the following values:
2396 * @arg @ref LL_HRTIM_TIMER_A
2397 * @arg @ref LL_HRTIM_TIMER_B
2398 * @arg @ref LL_HRTIM_TIMER_C
2399 * @arg @ref LL_HRTIM_TIMER_D
2400 * @arg @ref LL_HRTIM_TIMER_E
2401 * @arg @ref LL_HRTIM_TIMER_F
2402 * @retval
2403 * 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
2404 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
2405 * 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
2406 * HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
2407 */
2409 {
2412 return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
2413 }
2415 /**
2416 * @brief Enable the HRTIM timer(s) output(s) .
2417 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
2418 * OENR TA2OEN LL_HRTIM_EnableOutput\n
2419 * OENR TB1OEN LL_HRTIM_EnableOutput\n
2420 * OENR TB2OEN LL_HRTIM_EnableOutput\n
2421 * OENR TC1OEN LL_HRTIM_EnableOutput\n
2422 * OENR TC2OEN LL_HRTIM_EnableOutput\n
2423 * OENR TD1OEN LL_HRTIM_EnableOutput\n
2424 * OENR TD2OEN LL_HRTIM_EnableOutput\n
2425 * OENR TE1OEN LL_HRTIM_EnableOutput\n
2426 * OENR TE2OEN LL_HRTIM_EnableOutput\n
2427 * OENR TF1OEN LL_HRTIM_EnableOutput\n
2428 * OENR TF2OEN LL_HRTIM_EnableOutput
2429 * @param HRTIMx High Resolution Timer instance
2430 * @param Outputs This parameter can be a combination of the following values:
2431 * @arg @ref LL_HRTIM_OUTPUT_TA1
2432 * @arg @ref LL_HRTIM_OUTPUT_TA2
2433 * @arg @ref LL_HRTIM_OUTPUT_TB1
2434 * @arg @ref LL_HRTIM_OUTPUT_TB2
2435 * @arg @ref LL_HRTIM_OUTPUT_TC1
2436 * @arg @ref LL_HRTIM_OUTPUT_TC2
2437 * @arg @ref LL_HRTIM_OUTPUT_TD1
2438 * @arg @ref LL_HRTIM_OUTPUT_TD2
2439 * @arg @ref LL_HRTIM_OUTPUT_TE1
2440 * @arg @ref LL_HRTIM_OUTPUT_TE2
2441 * @arg @ref LL_HRTIM_OUTPUT_TF1
2442 * @arg @ref LL_HRTIM_OUTPUT_TF2
2443 * @retval None
2444 */
2446 {
2448 }
2450 /**
2451 * @brief Disable the HRTIM timer(s) output(s) .
2452 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
2453 * OENR TA2OEN LL_HRTIM_DisableOutput\n
2454 * OENR TB1OEN LL_HRTIM_DisableOutput\n
2455 * OENR TB2OEN LL_HRTIM_DisableOutput\n
2456 * OENR TC1OEN LL_HRTIM_DisableOutput\n
2457 * OENR TC2OEN LL_HRTIM_DisableOutput\n
2458 * OENR TD1OEN LL_HRTIM_DisableOutput\n
2459 * OENR TD2OEN LL_HRTIM_DisableOutput\n
2460 * OENR TE1OEN LL_HRTIM_DisableOutput\n
2461 * OENR TE2OEN LL_HRTIM_DisableOutput\n
2462 * OENR TF1OEN LL_HRTIM_DisableOutput\n
2463 * OENR TF2OEN LL_HRTIM_DisableOutput
2464 * @param HRTIMx High Resolution Timer instance
2465 * @param Outputs This parameter can be a combination of the following values:
2466 * @arg @ref LL_HRTIM_OUTPUT_TA1
2467 * @arg @ref LL_HRTIM_OUTPUT_TA2
2468 * @arg @ref LL_HRTIM_OUTPUT_TB1
2469 * @arg @ref LL_HRTIM_OUTPUT_TB2
2470 * @arg @ref LL_HRTIM_OUTPUT_TC1
2471 * @arg @ref LL_HRTIM_OUTPUT_TC2
2472 * @arg @ref LL_HRTIM_OUTPUT_TD1
2473 * @arg @ref LL_HRTIM_OUTPUT_TD2
2474 * @arg @ref LL_HRTIM_OUTPUT_TE1
2475 * @arg @ref LL_HRTIM_OUTPUT_TE2
2476 * @arg @ref LL_HRTIM_OUTPUT_TF1
2477 * @arg @ref LL_HRTIM_OUTPUT_TF2
2478 * @retval None
2479 */
2481 {
2483 }
2485 /**
2486 * @brief Indicates whether the HRTIM timer output is enabled.
2487 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
2488 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
2489 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
2490 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
2491 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
2492 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
2493 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
2494 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
2495 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
2496 * OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
2497 * OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
2498 * OENR TF2OEN LL_HRTIM_IsEnabledOutput
2499 * @param HRTIMx High Resolution Timer instance
2500 * @param Output This parameter can be one of the following values:
2501 * @arg @ref LL_HRTIM_OUTPUT_TA1
2502 * @arg @ref LL_HRTIM_OUTPUT_TA2
2503 * @arg @ref LL_HRTIM_OUTPUT_TB1
2504 * @arg @ref LL_HRTIM_OUTPUT_TB2
2505 * @arg @ref LL_HRTIM_OUTPUT_TC1
2506 * @arg @ref LL_HRTIM_OUTPUT_TC2
2507 * @arg @ref LL_HRTIM_OUTPUT_TD1
2508 * @arg @ref LL_HRTIM_OUTPUT_TD2
2509 * @arg @ref LL_HRTIM_OUTPUT_TE1
2510 * @arg @ref LL_HRTIM_OUTPUT_TE2
2511 * @arg @ref LL_HRTIM_OUTPUT_TF1
2512 * @arg @ref LL_HRTIM_OUTPUT_TF2
2513 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
2514 */
2516 {
2518 }
2520 /**
2521 * @brief Indicates whether the HRTIM timer output is disabled.
2522 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
2523 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
2524 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
2525 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
2526 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
2527 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
2528 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
2529 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
2530 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
2531 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
2532 * ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
2533 * ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
2534 * @param HRTIMx High Resolution Timer instance
2535 * @param Output This parameter can be one of the following values:
2536 * @arg @ref LL_HRTIM_OUTPUT_TA1
2537 * @arg @ref LL_HRTIM_OUTPUT_TA2
2538 * @arg @ref LL_HRTIM_OUTPUT_TB1
2539 * @arg @ref LL_HRTIM_OUTPUT_TB2
2540 * @arg @ref LL_HRTIM_OUTPUT_TC1
2541 * @arg @ref LL_HRTIM_OUTPUT_TC2
2542 * @arg @ref LL_HRTIM_OUTPUT_TD1
2543 * @arg @ref LL_HRTIM_OUTPUT_TD2
2544 * @arg @ref LL_HRTIM_OUTPUT_TE1
2545 * @arg @ref LL_HRTIM_OUTPUT_TE2
2546 * @arg @ref LL_HRTIM_OUTPUT_TF1
2547 * @arg @ref LL_HRTIM_OUTPUT_TF2
2548 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
2549 */
2551 {
2553 }
2555 /**
2556 * @brief Configure an ADC trigger.
2557 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
2558 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
2559 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
2560 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
2561 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
2562 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
2563 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
2564 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
2565 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
2566 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
2567 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
2568 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
2569 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
2570 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
2571 * ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
2572 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
2573 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
2574 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
2575 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
2576 * ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
2577 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
2578 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
2579 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
2580 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
2581 * ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
2582 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
2583 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
2584 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
2585 * ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
2586 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
2587 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
2588 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
2589 * ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
2590 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
2591 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
2592 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
2593 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
2594 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
2595 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
2596 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
2597 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
2598 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
2599 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
2600 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
2601 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
2602 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
2603 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
2604 * ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
2605 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
2606 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
2607 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
2608 * ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
2609 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
2610 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
2611 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
2612 * ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
2613 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
2614 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
2615 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
2616 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
2617 * ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
2618 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
2619 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
2620 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
2621 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
2622 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
2623 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
2624 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
2625 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
2626 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
2627 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
2628 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
2629 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
2630 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
2631 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
2632 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
2633 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
2634 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
2635 * ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
2636 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
2637 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
2638 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
2639 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
2640 * ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
2641 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
2642 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
2643 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
2644 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
2645 * ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
2646 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
2647 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
2648 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
2649 * ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
2650 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
2651 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
2652 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
2653 * ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
2654 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
2655 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
2656 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
2657 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
2658 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
2659 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
2660 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
2661 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
2662 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
2663 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
2664 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
2665 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
2666 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
2667 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
2668 * ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
2669 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
2670 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
2671 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
2672 * ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
2673 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
2674 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
2675 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
2676 * ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
2677 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
2678 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
2679 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
2680 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
2681 * ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
2682 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
2683 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
2684 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
2685 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
2686 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
2687 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
2688 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
2689 * @param HRTIMx High Resolution Timer instance
2690 * @param ADCTrig This parameter can be one of the following values:
2691 * @arg @ref LL_HRTIM_ADCTRIG_1
2692 * @arg @ref LL_HRTIM_ADCTRIG_2
2693 * @arg @ref LL_HRTIM_ADCTRIG_3
2694 * @arg @ref LL_HRTIM_ADCTRIG_4
2695 * @param Update This parameter can be one of the following values:
2696 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2697 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2698 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2699 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2700 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2701 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2702 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2703 * @param Src This parameter can be a combination of the following values:
2704 *
2705 * For ADC trigger 1 and ADC trigger 3:
2706 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
2707 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
2708 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
2709 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
2710 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
2711 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
2712 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
2713 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
2714 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
2715 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
2716 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
2717 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
2718 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
2719 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
2720 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
2721 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
2722 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
2723 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
2724 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
2725 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
2726 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
2727 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
2728 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
2729 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
2730 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
2731 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
2732 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
2733 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
2734 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
2735 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
2736 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
2737 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
2738 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
2739 *
2740 * For ADC trigger 2 and ADC trigger 4:
2741 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
2742 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
2743 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
2744 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
2745 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
2746 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
2747 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
2748 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
2749 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
2750 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
2751 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
2752 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
2753 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
2754 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
2755 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
2756 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
2757 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
2758 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
2759 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
2760 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
2761 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
2762 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
2763 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
2764 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
2765 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
2766 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
2767 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
2768 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
2769 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
2770 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
2771 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
2772 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
2773 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
2774 *
2775 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
2776 * can be one of the following values:
2777 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
2778 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
2779 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
2780 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
2781 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
2782 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
2783 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
2784 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
2785 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
2786 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
2787 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
2788 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
2789 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
2790 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
2791 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
2792 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
2793 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
2794 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
2795 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
2796 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
2797 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
2798 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
2799 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
2800 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
2801 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
2802 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
2803 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
2804 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
2805 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
2806 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
2807 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
2808 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
2809 *
2810 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
2811 * can be one of the following values:
2812 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
2813 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
2814 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
2815 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
2816 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
2817 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
2818 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
2819 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
2820 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
2821 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
2822 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
2823 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
2824 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
2825 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
2826 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
2827 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
2828 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
2829 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
2830 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
2831 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
2832 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
2833 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
2834 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
2835 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
2836 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
2837 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
2838 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
2839 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
2840 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
2841 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
2842 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
2843 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
2844 * @retval None
2845 */
2846 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
2847 {
2848 register __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2850 register __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
2854 }
2856 /**
2857 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
2858 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
2859 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
2860 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
2861 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
2862 * ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
2863 * ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
2864 * ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
2865 * ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
2866 * ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
2867 * ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
2868 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
2869 * registers are not preloaded either: a write access will result in an
2870 * immediate update of the trigger source.
2871 * @param HRTIMx High Resolution Timer instance
2872 * @param ADCTrig This parameter can be one of the following values:
2873 * @arg @ref LL_HRTIM_ADCTRIG_1
2874 * @arg @ref LL_HRTIM_ADCTRIG_2
2875 * @arg @ref LL_HRTIM_ADCTRIG_3
2876 * @arg @ref LL_HRTIM_ADCTRIG_4
2877 * @arg @ref LL_HRTIM_ADCTRIG_5
2878 * @arg @ref LL_HRTIM_ADCTRIG_6
2879 * @arg @ref LL_HRTIM_ADCTRIG_7
2880 * @arg @ref LL_HRTIM_ADCTRIG_8
2881 * @arg @ref LL_HRTIM_ADCTRIG_9
2882 * @arg @ref LL_HRTIM_ADCTRIG_10
2883 * @param Update This parameter can be one of the following values:
2884 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2885 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2886 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2887 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2888 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2889 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2890 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2891 * @retval None
2892 */
2893 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
2894 {
2895 register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2898 }
2900 /**
2901 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
2902 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
2903 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
2904 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
2905 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
2906 * ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
2907 * ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
2908 * ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
2909 * ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
2910 * ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
2911 * ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
2912 * @param HRTIMx High Resolution Timer instance
2913 * @param ADCTrig This parameter can be one of the following values:
2914 * @arg @ref LL_HRTIM_ADCTRIG_1
2915 * @arg @ref LL_HRTIM_ADCTRIG_2
2916 * @arg @ref LL_HRTIM_ADCTRIG_3
2917 * @arg @ref LL_HRTIM_ADCTRIG_4
2918 * @arg @ref LL_HRTIM_ADCTRIG_5
2919 * @arg @ref LL_HRTIM_ADCTRIG_6
2920 * @arg @ref LL_HRTIM_ADCTRIG_7
2921 * @arg @ref LL_HRTIM_ADCTRIG_8
2922 * @arg @ref LL_HRTIM_ADCTRIG_9
2923 * @arg @ref LL_HRTIM_ADCTRIG_10
2924 * @retval Update Returned value can be one of the following values:
2925 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
2926 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
2927 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
2928 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
2929 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
2930 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
2931 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
2932 */
2934 {
2935 register const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
2938 }
2940 /**
2941 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
2942 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
2943 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
2944 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
2945 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
2946 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
2947 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
2948 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
2949 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
2950 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
2951 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
2952 * ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
2953 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
2954 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
2955 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
2956 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
2957 * ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
2958 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
2959 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
2960 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
2961 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
2962 * ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
2963 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
2964 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
2965 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
2966 * ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
2967 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
2968 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
2969 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
2970 * ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
2971 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
2972 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
2973 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
2974 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
2975 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
2976 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
2977 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
2978 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
2979 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
2980 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
2981 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
2982 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
2983 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
2984 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
2985 * ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
2986 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
2987 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
2988 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
2989 * ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
2990 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
2991 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
2992 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
2993 * ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
2994 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
2995 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
2996 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
2997 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
2998 * ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
2999 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
3000 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
3001 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
3002 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
3003 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
3004 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
3005 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
3006 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
3007 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
3008 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
3009 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
3010 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
3011 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
3012 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
3013 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
3014 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
3015 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
3016 * ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
3017 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
3018 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
3019 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
3020 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
3021 * ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
3022 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
3023 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
3024 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
3025 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
3026 * ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
3027 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
3028 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
3029 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
3030 * ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
3031 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
3032 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
3033 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
3034 * ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
3035 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
3036 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
3037 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
3038 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
3039 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
3040 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
3041 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
3042 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
3043 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
3044 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
3045 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
3046 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
3047 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
3048 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
3049 * ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
3050 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
3051 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
3052 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
3053 * ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
3054 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
3055 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
3056 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
3057 * ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
3058 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
3059 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
3060 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
3061 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
3062 * ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
3063 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
3064 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
3065 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
3066 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
3067 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
3068 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
3069 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
3070 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3071 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3072 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3073 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3074 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3075 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3076 * @param HRTIMx High Resolution Timer instance
3077 * @param ADCTrig This parameter can be one of the following values:
3078 * @arg @ref LL_HRTIM_ADCTRIG_1
3079 * @arg @ref LL_HRTIM_ADCTRIG_2
3080 * @arg @ref LL_HRTIM_ADCTRIG_3
3081 * @arg @ref LL_HRTIM_ADCTRIG_4
3082 * @arg @ref LL_HRTIM_ADCTRIG_5
3083 * @arg @ref LL_HRTIM_ADCTRIG_6
3084 * @arg @ref LL_HRTIM_ADCTRIG_7
3085 * @arg @ref LL_HRTIM_ADCTRIG_8
3086 * @arg @ref LL_HRTIM_ADCTRIG_9
3087 * @arg @ref LL_HRTIM_ADCTRIG_10
3088 * @param Src
3089 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3090 * combination of the following values:
3091 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3092 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3093 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3094 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3095 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3096 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3097 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3098 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3099 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3100 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3101 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3102 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3103 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3104 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3105 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3106 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3107 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3108 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3109 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3110 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3111 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3112 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3113 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3114 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3115 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3116 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3117 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3118 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3119 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3120 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3121 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3122 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3123 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3124 *
3125 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3126 * combination of the following values:
3127 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3128 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3129 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3130 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3131 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3132 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3133 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3134 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3135 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3136 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3137 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3138 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3139 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3140 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3141 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3142 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3143 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3144 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3145 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3146 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3147 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3148 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3149 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3150 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3151 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3152 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3153 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3154 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3155 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3156 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3157 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3158 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3159 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3160 *
3161 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3162 * can be one of the following values:
3163 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3164 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3165 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3166 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3167 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3168 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3169 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3170 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3171 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3172 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3173 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3174 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3175 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3176 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3177 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3178 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3179 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3180 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3181 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3182 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3183 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3184 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3185 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3186 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3187 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3188 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3189 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3190 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3191 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3192 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3193 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3194 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3195 *
3196 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3197 * can be one of the following values:
3198 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3199 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3200 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3201 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3202 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3203 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3204 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3205 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3206 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3207 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3208 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3209 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3210 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3211 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3212 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3213 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3214 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3215 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3216 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3217 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3218 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3219 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3220 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3221 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3222 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3223 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3224 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3225 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3226 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3227 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3228 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3229 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3230 * @retval None
3231 */
3232 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
3233 {
3234 register __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3237 }
3239 /**
3240 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
3241 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
3242 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
3243 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
3244 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
3245 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
3246 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
3247 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
3248 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
3249 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
3250 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
3251 * ADC1R ADC1TFC2 LL_HRTIM_GetADCTrigSrc\n
3252 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
3253 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
3254 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
3255 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
3256 * ADC1R ADC1TFC3 LL_HRTIM_GetADCTrigSrc\n
3257 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
3258 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
3259 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
3260 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
3261 * ADC1R ADC1TFC4 LL_HRTIM_GetADCTrigSrc\n
3262 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
3263 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
3264 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
3265 * ADC1R ADC1TFPER LL_HRTIM_GetADCTrigSrc\n
3266 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
3267 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
3268 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
3269 * ADC1R ADC1TFRST LL_HRTIM_GetADCTrigSrc\n
3270 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
3271 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
3272 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
3273 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
3274 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
3275 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
3276 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
3277 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
3278 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
3279 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
3280 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
3281 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
3282 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
3283 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
3284 * ADC2R ADC2TFC2 LL_HRTIM_GetADCTrigSrc\n
3285 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
3286 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
3287 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
3288 * ADC2R ADC2TFC3 LL_HRTIM_GetADCTrigSrc\n
3289 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
3290 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
3291 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
3292 * ADC2R ADC2TFC4 LL_HRTIM_GetADCTrigSrc\n
3293 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
3294 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
3295 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
3296 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
3297 * ADC2R ADC2TFPER LL_HRTIM_GetADCTrigSrc\n
3298 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
3299 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
3300 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
3301 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
3302 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
3303 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
3304 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
3305 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
3306 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
3307 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
3308 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
3309 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
3310 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
3311 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
3312 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
3313 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
3314 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
3315 * ADC3R ADC3TFC2 LL_HRTIM_GetADCTrigSrc\n
3316 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
3317 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
3318 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
3319 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
3320 * ADC3R ADC3TFC3 LL_HRTIM_GetADCTrigSrc\n
3321 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
3322 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
3323 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
3324 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
3325 * ADC3R ADC3TFC4 LL_HRTIM_GetADCTrigSrc\n
3326 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
3327 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
3328 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
3329 * ADC3R ADC3TFPER LL_HRTIM_GetADCTrigSrc\n
3330 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
3331 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
3332 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
3333 * ADC3R ADC3TFRST LL_HRTIM_GetADCTrigSrc\n
3334 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
3335 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
3336 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
3337 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
3338 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
3339 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
3340 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
3341 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
3342 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
3343 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
3344 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
3345 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
3346 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
3347 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
3348 * ADC4R ADC4TFC2 LL_HRTIM_GetADCTrigSrc\n
3349 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
3350 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
3351 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
3352 * ADC4R ADC4TFC3 LL_HRTIM_GetADCTrigSrc\n
3353 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
3354 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
3355 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
3356 * ADC4R ADC4TFC4 LL_HRTIM_GetADCTrigSrc\n
3357 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
3358 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
3359 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
3360 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
3361 * ADC4R ADC4TFPER LL_HRTIM_GetADCTrigSrc\n
3362 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
3363 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
3364 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
3365 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
3366 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
3367 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
3368 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
3369 * ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
3370 * ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
3371 * ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
3372 * ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
3373 * ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
3374 * ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
3375 * @param HRTIMx High Resolution Timer instance
3376 * @param HRTIMx High Resolution Timer instance
3377 * @param ADCTrig This parameter can be one of the following values:
3378 * @arg @ref LL_HRTIM_ADCTRIG_1
3379 * @arg @ref LL_HRTIM_ADCTRIG_2
3380 * @arg @ref LL_HRTIM_ADCTRIG_3
3381 * @arg @ref LL_HRTIM_ADCTRIG_4
3382 * @arg @ref LL_HRTIM_ADCTRIG_5
3383 * @arg @ref LL_HRTIM_ADCTRIG_6
3384 * @arg @ref LL_HRTIM_ADCTRIG_7
3385 * @arg @ref LL_HRTIM_ADCTRIG_8
3386 * @arg @ref LL_HRTIM_ADCTRIG_9
3387 * @arg @ref LL_HRTIM_ADCTRIG_10
3388 * @retval Src This parameter can be a combination of the following values:
3389 *
3390 * For ADC trigger 1 and ADC trigger 3 this parameter can be a
3391 * combination of the following values:
3392 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
3393 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
3394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
3395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
3396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
3397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
3398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
3399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
3400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
3401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
3402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
3403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
3404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
3405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
3406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
3407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
3408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
3409 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
3410 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
3411 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
3412 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
3413 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
3414 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
3415 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
3416 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
3417 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
3418 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
3419 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
3420 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
3421 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
3422 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
3423 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
3424 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
3425 *
3426 * For ADC trigger 2 and ADC trigger 4 this parameter can be a
3427 * combination of the following values:
3428 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
3429 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
3430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
3431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
3432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
3433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
3434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
3435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
3436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
3437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
3438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
3439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
3440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
3441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
3442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
3443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
3444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
3445 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
3446 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
3447 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
3448 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
3449 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
3450 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
3451 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
3452 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
3453 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
3454 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
3455 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
3456 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
3457 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
3458 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
3459 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
3460 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
3461 *
3462 * For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
3463 * can be one of the following values:
3464 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
3465 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
3466 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
3467 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
3468 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
3469 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
3470 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
3471 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
3472 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
3473 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
3474 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
3475 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
3476 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
3477 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
3478 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
3479 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
3480 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
3481 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
3482 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
3483 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
3484 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
3485 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
3486 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
3487 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
3488 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
3489 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
3490 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
3491 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
3492 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
3493 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
3494 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
3495 * @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
3496 *
3497 * For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
3498 * can be one of the following values:
3499 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
3500 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
3501 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
3502 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
3503 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
3504 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
3505 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
3506 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
3507 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
3508 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
3509 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
3510 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
3511 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
3512 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
3513 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
3514 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
3515 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
3516 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
3517 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
3518 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
3519 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
3520 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
3521 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
3522 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
3523 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
3524 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
3525 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
3526 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
3527 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
3528 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
3529 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
3530 * @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
3531 */
3533 {
3534 register const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
3538 }
3541 /**
3542 * @brief Select the ADC post scaler.
3543 * @note This function allows to adjust each ADC trigger rate individually.
3544 * @note In center-aligned mode, the ADC trigger rate is also dependent on
3545 * ADROM[1:0] bitfield, programmed in the source timer
3546 * (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
3547 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_SetADCPostScaler\n
3548 * ADCPS2 ADC9PSC LL_HRTIM_SetADCPostScaler\n
3549 * ADCPS2 ADC8PSC LL_HRTIM_SetADCPostScaler\n
3550 * ADCPS2 ADC7PSC LL_HRTIM_SetADCPostScaler\n
3551 * ADCPS2 ADC6PSC LL_HRTIM_SetADCPostScaler\n
3552 * ADCPS1 ADC5PSC LL_HRTIM_SetADCPostScaler\n
3553 * ADCPS1 ADC4PSC LL_HRTIM_SetADCPostScaler\n
3554 * ADCPS1 ADC3PSC LL_HRTIM_SetADCPostScaler\n
3555 * ADCPS1 ADC2PSC LL_HRTIM_SetADCPostScaler\n
3556 * ADCPS1 ADC1PSC LL_HRTIM_SetADCPostScaler
3557 * @param HRTIMx High Resolution Timer instance
3558 * @param ADCTrig This parameter can be one of the following values:
3559 * @arg @ref LL_HRTIM_ADCTRIG_1
3560 * @arg @ref LL_HRTIM_ADCTRIG_2
3561 * @arg @ref LL_HRTIM_ADCTRIG_3
3562 * @arg @ref LL_HRTIM_ADCTRIG_4
3563 * @arg @ref LL_HRTIM_ADCTRIG_5
3564 * @arg @ref LL_HRTIM_ADCTRIG_6
3565 * @arg @ref LL_HRTIM_ADCTRIG_7
3566 * @arg @ref LL_HRTIM_ADCTRIG_8
3567 * @arg @ref LL_HRTIM_ADCTRIG_9
3568 * @arg @ref LL_HRTIM_ADCTRIG_10
3569 * @param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3570 * @retval None
3571 */
3572 __STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
3573 {
3581 }
3583 /**
3584 * @brief Get the selected ADC post scaler.
3585 * @rmtoll ADCPS2 ADC10PSC LL_HRTIM_GetADCPostScaler\n
3586 * ADCPS2 ADC9PSC LL_HRTIM_GetADCPostScaler\n
3587 * ADCPS2 ADC8PSC LL_HRTIM_GetADCPostScaler\n
3588 * ADCPS2 ADC7PSC LL_HRTIM_GetADCPostScaler\n
3589 * ADCPS2 ADC6PSC LL_HRTIM_GetADCPostScaler\n
3590 * ADCPS1 ADC5PSC LL_HRTIM_GetADCPostScaler\n
3591 * ADCPS1 ADC4PSC LL_HRTIM_GetADCPostScaler\n
3592 * ADCPS1 ADC3PSC LL_HRTIM_GetADCPostScaler\n
3593 * ADCPS1 ADC2PSC LL_HRTIM_GetADCPostScaler\n
3594 * ADCPS1 ADC1PSC LL_HRTIM_GetADCPostScaler
3595 * @param HRTIMx High Resolution Timer instance
3596 * @param ADCTrig This parameter can be one of the following values:
3597 * @arg @ref LL_HRTIM_ADCTRIG_1
3598 * @arg @ref LL_HRTIM_ADCTRIG_2
3599 * @arg @ref LL_HRTIM_ADCTRIG_3
3600 * @arg @ref LL_HRTIM_ADCTRIG_4
3601 * @arg @ref LL_HRTIM_ADCTRIG_5
3602 * @arg @ref LL_HRTIM_ADCTRIG_6
3603 * @arg @ref LL_HRTIM_ADCTRIG_7
3604 * @arg @ref LL_HRTIM_ADCTRIG_8
3605 * @arg @ref LL_HRTIM_ADCTRIG_9
3606 * @arg @ref LL_HRTIM_ADCTRIG_10
3607 * @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
3608 */
3610 {
3620 }
3622 /**
3623 * @brief Configure the DLL calibration mode.
3624 * @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
3625 * DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
3626 * @param HRTIMx High Resolution Timer instance
3627 * @param Mode This parameter can be one of the following values:
3628 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
3629 * @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
3630 * @param Period This parameter can be one of the following values:
3631 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
3632 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
3633 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
3634 * @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
3635 * @retval None
3636 */
3637 __STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
3638 {
3639 MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
3640 }
3642 /**
3643 * @brief Launch DLL calibration
3644 * @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
3645 * @param HRTIMx High Resolution Timer instance
3646 * @retval None
3647 */
3649 {
3651 }
3653 /**
3654 * @}
3655 */
3657 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
3658 * @{
3659 */
3661 /**
3662 * @brief Enable timer(s) counter.
3663 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterEnable\n
3664 * MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
3665 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
3666 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
3667 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
3668 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
3669 * MDIER MCEN LL_HRTIM_TIM_CounterEnable
3670 * @param HRTIMx High Resolution Timer instance
3671 * @param Timers This parameter can be a combination of the following values:
3672 * @arg @ref LL_HRTIM_TIMER_MASTER
3673 * @arg @ref LL_HRTIM_TIMER_A
3674 * @arg @ref LL_HRTIM_TIMER_B
3675 * @arg @ref LL_HRTIM_TIMER_C
3676 * @arg @ref LL_HRTIM_TIMER_D
3677 * @arg @ref LL_HRTIM_TIMER_E
3678 * @arg @ref LL_HRTIM_TIMER_F
3679 * @retval None
3680 */
3682 {
3684 }
3686 /**
3687 * @brief Disable timer(s) counter.
3688 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterDisable\n
3689 * MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
3690 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
3691 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
3692 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
3693 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
3694 * MDIER MCEN LL_HRTIM_TIM_CounterDisable
3695 * @param HRTIMx High Resolution Timer instance
3696 * @param Timers This parameter can be a combination of the following values:
3697 * @arg @ref LL_HRTIM_TIMER_MASTER
3698 * @arg @ref LL_HRTIM_TIMER_A
3699 * @arg @ref LL_HRTIM_TIMER_B
3700 * @arg @ref LL_HRTIM_TIMER_C
3701 * @arg @ref LL_HRTIM_TIMER_D
3702 * @arg @ref LL_HRTIM_TIMER_E
3703 * @arg @ref LL_HRTIM_TIMER_F
3704 * @retval None
3705 */
3707 {
3709 }
3711 /**
3712 * @brief Indicate whether the timer counter is enabled.
3713 * @rmtoll MDIER TFCEN LL_HRTIM_TIM_IsCounterEnabled\n
3714 * MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
3715 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
3716 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
3717 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
3718 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
3719 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
3720 * @param HRTIMx High Resolution Timer instance
3721 * @param Timer This parameter can be one of the following values:
3722 * @arg @ref LL_HRTIM_TIMER_MASTER
3723 * @arg @ref LL_HRTIM_TIMER_A
3724 * @arg @ref LL_HRTIM_TIMER_B
3725 * @arg @ref LL_HRTIM_TIMER_C
3726 * @arg @ref LL_HRTIM_TIMER_D
3727 * @arg @ref LL_HRTIM_TIMER_E
3728 * @arg @ref LL_HRTIM_TIMER_F
3729 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
3730 */
3732 {
3734 }
3736 /**
3737 * @brief Set the timer clock prescaler ratio.
3738 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
3739 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
3740 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
3741 * @note The prescaling ratio cannot be modified once the timer counter is enabled.
3742 * @param HRTIMx High Resolution Timer instance
3743 * @param Timer This parameter can be one of the following values:
3744 * @arg @ref LL_HRTIM_TIMER_MASTER
3745 * @arg @ref LL_HRTIM_TIMER_A
3746 * @arg @ref LL_HRTIM_TIMER_B
3747 * @arg @ref LL_HRTIM_TIMER_C
3748 * @arg @ref LL_HRTIM_TIMER_D
3749 * @arg @ref LL_HRTIM_TIMER_E
3750 * @arg @ref LL_HRTIM_TIMER_F
3751 * @param Prescaler This parameter can be one of the following values:
3752 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3753 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3754 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3755 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3756 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3757 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3758 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3759 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3760 * @retval None
3761 */
3762 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
3763 {
3765 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3767 }
3769 /**
3770 * @brief Get the timer clock prescaler ratio
3771 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
3772 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
3773 * @param HRTIMx High Resolution Timer instance
3774 * @param Timer This parameter can be one of the following values:
3775 * @arg @ref LL_HRTIM_TIMER_MASTER
3776 * @arg @ref LL_HRTIM_TIMER_A
3777 * @arg @ref LL_HRTIM_TIMER_B
3778 * @arg @ref LL_HRTIM_TIMER_C
3779 * @arg @ref LL_HRTIM_TIMER_D
3780 * @arg @ref LL_HRTIM_TIMER_E
3781 * @arg @ref LL_HRTIM_TIMER_F
3782 * @retval Prescaler Returned value can be one of the following values:
3783 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
3784 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
3785 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
3786 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
3787 * @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
3788 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
3789 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
3790 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
3791 */
3793 {
3795 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3797 }
3799 /**
3800 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
3801 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
3802 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
3803 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
3804 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
3805 * @param HRTIMx High Resolution Timer instance
3806 * @param Timer This parameter can be one of the following values:
3807 * @arg @ref LL_HRTIM_TIMER_MASTER
3808 * @arg @ref LL_HRTIM_TIMER_A
3809 * @arg @ref LL_HRTIM_TIMER_B
3810 * @arg @ref LL_HRTIM_TIMER_C
3811 * @arg @ref LL_HRTIM_TIMER_D
3812 * @arg @ref LL_HRTIM_TIMER_E
3813 * @arg @ref LL_HRTIM_TIMER_F
3814 * @param Mode This parameter can be one of the following values:
3815 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3816 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3817 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3818 * @retval None
3819 */
3820 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
3821 {
3823 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3825 }
3827 /**
3828 * @brief Get the counter operating mode mode
3829 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
3830 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
3831 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
3832 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
3833 * @param HRTIMx High Resolution Timer instance
3834 * @param Timer This parameter can be one of the following values:
3835 * @arg @ref LL_HRTIM_TIMER_MASTER
3836 * @arg @ref LL_HRTIM_TIMER_A
3837 * @arg @ref LL_HRTIM_TIMER_B
3838 * @arg @ref LL_HRTIM_TIMER_C
3839 * @arg @ref LL_HRTIM_TIMER_D
3840 * @arg @ref LL_HRTIM_TIMER_E
3841 * @arg @ref LL_HRTIM_TIMER_F
3842 * @retval Mode Returned value can be one of the following values:
3843 * @arg @ref LL_HRTIM_MODE_CONTINUOUS
3844 * @arg @ref LL_HRTIM_MODE_SINGLESHOT
3845 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
3846 */
3848 {
3850 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3852 }
3854 /**
3855 * @brief Enable the half duty-cycle mode.
3856 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
3857 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
3858 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
3859 * active register is automatically updated with HRTIM_MPER/2
3860 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
3861 * @param HRTIMx High Resolution Timer instance
3862 * @param Timer This parameter can be one of the following values:
3863 * @arg @ref LL_HRTIM_TIMER_MASTER
3864 * @arg @ref LL_HRTIM_TIMER_A
3865 * @arg @ref LL_HRTIM_TIMER_B
3866 * @arg @ref LL_HRTIM_TIMER_C
3867 * @arg @ref LL_HRTIM_TIMER_D
3868 * @arg @ref LL_HRTIM_TIMER_E
3869 * @arg @ref LL_HRTIM_TIMER_F
3870 * @retval None
3871 */
3873 {
3875 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3877 }
3879 /**
3880 * @brief Disable the half duty-cycle mode.
3881 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
3882 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
3883 * @param HRTIMx High Resolution Timer instance
3884 * @param Timer This parameter can be one of the following values:
3885 * @arg @ref LL_HRTIM_TIMER_MASTER
3886 * @arg @ref LL_HRTIM_TIMER_A
3887 * @arg @ref LL_HRTIM_TIMER_B
3888 * @arg @ref LL_HRTIM_TIMER_C
3889 * @arg @ref LL_HRTIM_TIMER_D
3890 * @arg @ref LL_HRTIM_TIMER_E
3891 * @arg @ref LL_HRTIM_TIMER_F
3892 * @retval None
3893 */
3895 {
3897 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3900 }
3902 /**
3903 * @brief Indicate whether half duty-cycle mode is enabled for a given timer.
3904 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
3905 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
3906 * @param HRTIMx High Resolution Timer instance
3907 * @param Timer This parameter can be one of the following values:
3908 * @arg @ref LL_HRTIM_TIMER_MASTER
3909 * @arg @ref LL_HRTIM_TIMER_A
3910 * @arg @ref LL_HRTIM_TIMER_B
3911 * @arg @ref LL_HRTIM_TIMER_C
3912 * @arg @ref LL_HRTIM_TIMER_D
3913 * @arg @ref LL_HRTIM_TIMER_E
3914 * @arg @ref LL_HRTIM_TIMER_F
3915 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
3916 */
3918 {
3920 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
3923 }
3925 /**
3926 * @brief Enable the Re-Syncronisation Update.
3927 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3928 * or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
3929 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_EnableResyncUpdate
3930 * @param HRTIMx High Resolution Timer instance
3931 * @param Timer This parameter can be one of the following values:
3932 * @arg @ref LL_HRTIM_TIMER_A
3933 * @arg @ref LL_HRTIM_TIMER_B
3934 * @arg @ref LL_HRTIM_TIMER_C
3935 * @arg @ref LL_HRTIM_TIMER_D
3936 * @arg @ref LL_HRTIM_TIMER_E
3937 * @arg @ref LL_HRTIM_TIMER_F
3938 * @retval None
3939 */
3941 {
3943 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3946 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3947 }
3949 /**
3950 * @brief Disable the Re-Syncronisation Update.
3951 * @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
3952 * or from a software update (TxSWU bit) is taken into account immediately.
3953 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_DisableResyncUpdate
3954 * @param HRTIMx High Resolution Timer instance
3955 * @param Timer This parameter can be one of the following values:
3956 * @arg @ref LL_HRTIM_TIMER_A
3957 * @arg @ref LL_HRTIM_TIMER_B
3958 * @arg @ref LL_HRTIM_TIMER_C
3959 * @arg @ref LL_HRTIM_TIMER_D
3960 * @arg @ref LL_HRTIM_TIMER_E
3961 * @arg @ref LL_HRTIM_TIMER_F
3962 * @retval None
3963 */
3965 {
3967 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3971 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3972 }
3974 /**
3975 * @brief Indicate whether the Re-Syncronisation Update is enabled.
3976 * @note This bit specifies whether update source coming outside
3977 * from the timing unit must be synchronized
3978 * @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_IsEnabledResyncUpdate
3979 * @param HRTIMx High Resolution Timer instance
3980 * @param Timer This parameter can be one of the following values:
3981 * @arg @ref LL_HRTIM_TIMER_A
3982 * @arg @ref LL_HRTIM_TIMER_B
3983 * @arg @ref LL_HRTIM_TIMER_C
3984 * @arg @ref LL_HRTIM_TIMER_D
3985 * @arg @ref LL_HRTIM_TIMER_E
3986 * @arg @ref LL_HRTIM_TIMER_F
3987 * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
3988 */
3989 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
3990 {
3992 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
3996 /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
3997 }
3999 /**
4000 * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
4001 * @note When interleaved mode is enabled, the content of the compare registers is overridden.
4002 * @rmtoll MCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
4003 * MCR INTLVD LL_HRTIM_TIM_SetInterleavedMode\n
4004 * TIMxCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
4005 * TIMxCR INTLVD LL_HRTIM_TIM_SetInterleavedMode
4006 * @param HRTIMx High Resolution Timer instance
4007 * @param Timer This parameter can be one of the following values:
4008 * @arg @ref LL_HRTIM_TIMER_MASTER
4009 * @arg @ref LL_HRTIM_TIMER_A
4010 * @arg @ref LL_HRTIM_TIMER_B
4011 * @arg @ref LL_HRTIM_TIMER_C
4012 * @arg @ref LL_HRTIM_TIMER_D
4013 * @arg @ref LL_HRTIM_TIMER_E
4014 * @arg @ref LL_HRTIM_TIMER_F
4015 * @param Mode This parameter can be one of the following values:
4016 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4017 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4018 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4019 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4020 * @retval None
4021 */
4022 __STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
4023 {
4025 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4029 }
4031 /**
4032 * @brief get the Interleaved configuration.
4033 * @rmtoll MCR INTLVD LL_HRTIM_TIM_GetInterleavedMode\n
4034 * TIMxCR INTLVD LL_HRTIM_TIM_GetInterleavedMode
4035 * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
4036 * the interleaved Mode is dual if HALF bit is set,
4038 * HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
4039 * with HRTIM_MPER/2 or HRTIM_MPER/4
4040 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
4042 * @param HRTIMx High Resolution Timer instance
4043 * @param Timer This parameter can be one of the following values:
4044 * @arg @ref LL_HRTIM_TIMER_MASTER
4045 * @arg @ref LL_HRTIM_TIMER_A
4046 * @arg @ref LL_HRTIM_TIMER_B
4047 * @arg @ref LL_HRTIM_TIMER_C
4048 * @arg @ref LL_HRTIM_TIMER_D
4049 * @arg @ref LL_HRTIM_TIMER_E
4050 * @arg @ref LL_HRTIM_TIMER_F
4051 * @retval This parameter can be one of the following values:
4052 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
4053 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
4054 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
4055 * @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
4056 */
4057 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4058 {
4060 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4063 return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD));
4064 }
4066 /**
4067 * @brief Enable the timer start when receiving a synchronization input event.
4068 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
4069 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
4070 * @param HRTIMx High Resolution Timer instance
4071 * @param Timer This parameter can be one of the following values:
4072 * @arg @ref LL_HRTIM_TIMER_MASTER
4073 * @arg @ref LL_HRTIM_TIMER_A
4074 * @arg @ref LL_HRTIM_TIMER_B
4075 * @arg @ref LL_HRTIM_TIMER_C
4076 * @arg @ref LL_HRTIM_TIMER_D
4077 * @arg @ref LL_HRTIM_TIMER_E
4078 * @arg @ref LL_HRTIM_TIMER_F
4079 * @retval None
4080 */
4082 {
4084 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4086 }
4088 /**
4089 * @brief Disable the timer start when receiving a synchronization input event.
4090 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
4091 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
4092 * @param HRTIMx High Resolution Timer instance
4093 * @param Timer This parameter can be one of the following values:
4094 * @arg @ref LL_HRTIM_TIMER_MASTER
4095 * @arg @ref LL_HRTIM_TIMER_A
4096 * @arg @ref LL_HRTIM_TIMER_B
4097 * @arg @ref LL_HRTIM_TIMER_C
4098 * @arg @ref LL_HRTIM_TIMER_D
4099 * @arg @ref LL_HRTIM_TIMER_E
4100 * @arg @ref LL_HRTIM_TIMER_F
4101 * @retval None
4102 */
4104 {
4106 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4108 }
4110 /**
4111 * @brief Indicate whether the timer start when receiving a synchronization input event.
4112 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
4113 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
4114 * @param HRTIMx High Resolution Timer instance
4115 * @param Timer This parameter can be one of the following values:
4116 * @arg @ref LL_HRTIM_TIMER_MASTER
4117 * @arg @ref LL_HRTIM_TIMER_A
4118 * @arg @ref LL_HRTIM_TIMER_B
4119 * @arg @ref LL_HRTIM_TIMER_C
4120 * @arg @ref LL_HRTIM_TIMER_D
4121 * @arg @ref LL_HRTIM_TIMER_E
4122 * @arg @ref LL_HRTIM_TIMER_F
4123 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4124 */
4125 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4126 {
4128 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4131 }
4133 /**
4134 * @brief Enable the timer reset when receiving a synchronization input event.
4135 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
4136 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
4137 * @param HRTIMx High Resolution Timer instance
4138 * @param Timer This parameter can be one of the following values:
4139 * @arg @ref LL_HRTIM_TIMER_MASTER
4140 * @arg @ref LL_HRTIM_TIMER_A
4141 * @arg @ref LL_HRTIM_TIMER_B
4142 * @arg @ref LL_HRTIM_TIMER_C
4143 * @arg @ref LL_HRTIM_TIMER_D
4144 * @arg @ref LL_HRTIM_TIMER_E
4145 * @arg @ref LL_HRTIM_TIMER_F
4146 * @retval None
4147 */
4149 {
4151 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4153 }
4155 /**
4156 * @brief Disable the timer reset when receiving a synchronization input event.
4157 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
4158 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
4159 * @param HRTIMx High Resolution Timer instance
4160 * @param Timer This parameter can be one of the following values:
4161 * @arg @ref LL_HRTIM_TIMER_MASTER
4162 * @arg @ref LL_HRTIM_TIMER_A
4163 * @arg @ref LL_HRTIM_TIMER_B
4164 * @arg @ref LL_HRTIM_TIMER_C
4165 * @arg @ref LL_HRTIM_TIMER_D
4166 * @arg @ref LL_HRTIM_TIMER_E
4167 * @arg @ref LL_HRTIM_TIMER_F
4168 * @retval None
4169 */
4171 {
4173 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4175 }
4177 /**
4178 * @brief Indicate whether the timer reset when receiving a synchronization input event.
4179 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
4180 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
4181 * @param HRTIMx High Resolution Timer instance
4182 * @param Timer This parameter can be one of the following values:
4183 * @arg @ref LL_HRTIM_TIMER_MASTER
4184 * @arg @ref LL_HRTIM_TIMER_A
4185 * @arg @ref LL_HRTIM_TIMER_B
4186 * @arg @ref LL_HRTIM_TIMER_C
4187 * @arg @ref LL_HRTIM_TIMER_D
4188 * @arg @ref LL_HRTIM_TIMER_E
4189 * @arg @ref LL_HRTIM_TIMER_F
4190 * @retval None
4191 */
4192 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4193 {
4195 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4198 }
4200 /**
4201 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4202 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
4203 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
4204 * @param HRTIMx High Resolution Timer instance
4205 * @param Timer This parameter can be one of the following values:
4206 * @arg @ref LL_HRTIM_TIMER_MASTER
4207 * @arg @ref LL_HRTIM_TIMER_A
4208 * @arg @ref LL_HRTIM_TIMER_B
4209 * @arg @ref LL_HRTIM_TIMER_C
4210 * @arg @ref LL_HRTIM_TIMER_D
4211 * @arg @ref LL_HRTIM_TIMER_E
4212 * @arg @ref LL_HRTIM_TIMER_F
4213 * @param DACTrig This parameter can be one of the following values:
4214 * @arg @ref LL_HRTIM_DACTRIG_NONE
4215 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4216 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4217 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4218 * @retval None
4219 */
4220 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
4221 {
4223 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4225 }
4227 /**
4228 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
4229 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
4230 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
4231 * @param HRTIMx High Resolution Timer instance
4232 * @param Timer This parameter can be one of the following values:
4233 * @arg @ref LL_HRTIM_TIMER_MASTER
4234 * @arg @ref LL_HRTIM_TIMER_A
4235 * @arg @ref LL_HRTIM_TIMER_B
4236 * @arg @ref LL_HRTIM_TIMER_C
4237 * @arg @ref LL_HRTIM_TIMER_D
4238 * @arg @ref LL_HRTIM_TIMER_E
4239 * @arg @ref LL_HRTIM_TIMER_F
4240 * @retval DACTrig Returned value can be one of the following values:
4241 * @arg @ref LL_HRTIM_DACTRIG_NONE
4242 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
4243 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
4244 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
4245 */
4247 {
4249 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4251 }
4253 /**
4254 * @brief Enable the timer registers preload mechanism.
4255 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
4256 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
4257 * @note When the preload mode is enabled, accessed registers are shadow registers.
4258 * Their content is transferred into the active register after an update request,
4259 * either software or synchronized with an event.
4260 * @param HRTIMx High Resolution Timer instance
4261 * @param Timer This parameter can be one of the following values:
4262 * @arg @ref LL_HRTIM_TIMER_MASTER
4263 * @arg @ref LL_HRTIM_TIMER_A
4264 * @arg @ref LL_HRTIM_TIMER_B
4265 * @arg @ref LL_HRTIM_TIMER_C
4266 * @arg @ref LL_HRTIM_TIMER_D
4267 * @arg @ref LL_HRTIM_TIMER_E
4268 * @arg @ref LL_HRTIM_TIMER_F
4269 * @retval None
4270 */
4272 {
4274 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4276 }
4278 /**
4279 * @brief Disable the timer registers preload mechanism.
4280 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
4281 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
4282 * @param HRTIMx High Resolution Timer instance
4283 * @param Timer This parameter can be one of the following values:
4284 * @arg @ref LL_HRTIM_TIMER_MASTER
4285 * @arg @ref LL_HRTIM_TIMER_A
4286 * @arg @ref LL_HRTIM_TIMER_B
4287 * @arg @ref LL_HRTIM_TIMER_C
4288 * @arg @ref LL_HRTIM_TIMER_D
4289 * @arg @ref LL_HRTIM_TIMER_E
4290 * @arg @ref LL_HRTIM_TIMER_F
4291 * @retval None
4292 */
4294 {
4296 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4298 }
4300 /**
4301 * @brief Indicate whether the timer registers preload mechanism is enabled.
4302 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
4303 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
4304 * @param HRTIMx High Resolution Timer instance
4305 * @param Timer This parameter can be one of the following values:
4306 * @arg @ref LL_HRTIM_TIMER_MASTER
4307 * @arg @ref LL_HRTIM_TIMER_A
4308 * @arg @ref LL_HRTIM_TIMER_B
4309 * @arg @ref LL_HRTIM_TIMER_C
4310 * @arg @ref LL_HRTIM_TIMER_D
4311 * @arg @ref LL_HRTIM_TIMER_E
4312 * @arg @ref LL_HRTIM_TIMER_F
4313 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
4314 */
4316 {
4318 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4321 }
4323 /**
4324 * @brief Set the timer register update trigger.
4325 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
4326 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
4327 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
4328 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
4329 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
4330 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
4331 * TIMxCR TFU LL_HRTIM_TIM_SetUpdateTrig\n
4332 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
4333 * @param HRTIMx High Resolution Timer instance
4334 * @param Timer This parameter can be one of the following values:
4335 * @arg @ref LL_HRTIM_TIMER_MASTER
4336 * @arg @ref LL_HRTIM_TIMER_A
4337 * @arg @ref LL_HRTIM_TIMER_B
4338 * @arg @ref LL_HRTIM_TIMER_C
4339 * @arg @ref LL_HRTIM_TIMER_D
4340 * @arg @ref LL_HRTIM_TIMER_E
4341 * @arg @ref LL_HRTIM_TIMER_F
4342 * @param UpdateTrig This parameter can be one of the following values:
4343 *
4344 * For the master timer this parameter can be one of the following values:
4345 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4346 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4347 *
4348 * For timer A..F this parameter can be:
4349 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4350 * or a combination of the following values:
4351 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4352 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4353 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4354 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4355 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4356 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4357 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4358 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4359 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4360 * @retval None
4361 */
4362 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
4363 {
4365 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4366 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
4367 }
4369 /**
4370 * @brief Get the timer register update trigger.
4371 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
4372 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
4373 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
4374 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
4375 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
4376 * TIMxCR TFU LL_HRTIM_TIM_GetUpdateTrig\n
4377 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
4378 * @param HRTIMx High Resolution Timer instance
4379 * @param Timer This parameter can be one of the following values:
4380 * @arg @ref LL_HRTIM_TIMER_MASTER
4381 * @arg @ref LL_HRTIM_TIMER_A
4382 * @arg @ref LL_HRTIM_TIMER_B
4383 * @arg @ref LL_HRTIM_TIMER_C
4384 * @arg @ref LL_HRTIM_TIMER_D
4385 * @arg @ref LL_HRTIM_TIMER_E
4386 * @arg @ref LL_HRTIM_TIMER_F
4387 * @retval UpdateTrig Returned value can be one of the following values:
4388 *
4389 * For the master timer this parameter can be one of the following values:
4390 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4391 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4392 *
4393 * For timer A..F this parameter can be:
4394 * @arg @ref LL_HRTIM_UPDATETRIG_NONE
4395 * or a combination of the following values:
4396 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER
4397 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
4398 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
4399 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
4400 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
4401 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
4402 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
4403 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
4404 * @arg @ref LL_HRTIM_UPDATETRIG_RESET
4405 */
4407 {
4409 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4411 }
4413 /**
4414 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
4415 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
4416 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
4417 * @param HRTIMx High Resolution Timer instance
4418 * @param Timer This parameter can be one of the following values:
4419 * @arg @ref LL_HRTIM_TIMER_MASTER
4420 * @arg @ref LL_HRTIM_TIMER_A
4421 * @arg @ref LL_HRTIM_TIMER_B
4422 * @arg @ref LL_HRTIM_TIMER_C
4423 * @arg @ref LL_HRTIM_TIMER_D
4424 * @arg @ref LL_HRTIM_TIMER_E
4425 * @arg @ref LL_HRTIM_TIMER_F
4426 * @param UpdateGating This parameter can be one of the following values:
4427 *
4428 * For the master timer this parameter can be one of the following values:
4429 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4430 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4431 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4432 *
4433 * For the timer A..F this parameter can be one of the following values:
4434 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4435 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4436 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4437 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4438 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4439 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4440 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4441 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4442 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4443 * @retval None
4444 */
4445 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
4446 {
4448 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4449 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
4450 }
4452 /**
4453 * @brief Get the timer registers update condition.
4454 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
4455 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
4456 * @param HRTIMx High Resolution Timer instance
4457 * @param Timer This parameter can be one of the following values:
4458 * @arg @ref LL_HRTIM_TIMER_MASTER
4459 * @arg @ref LL_HRTIM_TIMER_A
4460 * @arg @ref LL_HRTIM_TIMER_B
4461 * @arg @ref LL_HRTIM_TIMER_C
4462 * @arg @ref LL_HRTIM_TIMER_D
4463 * @arg @ref LL_HRTIM_TIMER_E
4464 * @arg @ref LL_HRTIM_TIMER_F
4465 * @retval UpdateGating Returned value can be one of the following values:
4466 *
4467 * For the master timer this parameter can be one of the following values:
4468 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4469 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4470 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4471 *
4472 * For the timer A..F this parameter can be one of the following values:
4473 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
4474 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
4475 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
4476 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
4477 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
4478 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
4479 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
4480 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
4481 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
4482 */
4484 {
4486 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
4487 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
4488 }
4490 /**
4491 * @brief Enable the push-pull mode.
4492 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
4493 * @param HRTIMx High Resolution Timer instance
4494 * @param Timer This parameter can be one of the following values:
4495 * @arg @ref LL_HRTIM_TIMER_A
4496 * @arg @ref LL_HRTIM_TIMER_B
4497 * @arg @ref LL_HRTIM_TIMER_C
4498 * @arg @ref LL_HRTIM_TIMER_D
4499 * @arg @ref LL_HRTIM_TIMER_E
4500 * @arg @ref LL_HRTIM_TIMER_F
4501 * @retval None
4502 */
4504 {
4506 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4509 }
4511 /**
4512 * @brief Disable the push-pull mode.
4513 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
4514 * @param HRTIMx High Resolution Timer instance
4515 * @param Timer This parameter can be one of the following values:
4516 * @arg @ref LL_HRTIM_TIMER_A
4517 * @arg @ref LL_HRTIM_TIMER_B
4518 * @arg @ref LL_HRTIM_TIMER_C
4519 * @arg @ref LL_HRTIM_TIMER_D
4520 * @arg @ref LL_HRTIM_TIMER_E
4521 * @arg @ref LL_HRTIM_TIMER_F
4522 * @retval None
4523 */
4525 {
4527 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4530 }
4532 /**
4533 * @brief Indicate whether the push-pull mode is enabled.
4534 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
4535 * @param HRTIMx High Resolution Timer instance
4536 * @param Timer This parameter can be one of the following values:
4537 * @arg @ref LL_HRTIM_TIMER_A
4538 * @arg @ref LL_HRTIM_TIMER_B
4539 * @arg @ref LL_HRTIM_TIMER_C
4540 * @arg @ref LL_HRTIM_TIMER_D
4541 * @arg @ref LL_HRTIM_TIMER_E
4542 * @arg @ref LL_HRTIM_TIMER_F
4543 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
4544 */
4545 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
4546 {
4548 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4551 }
4553 /**
4554 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
4555 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
4556 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
4557 * @note In auto-delayed mode the compare match occurs independently from the timer counter value.
4558 * @param HRTIMx High Resolution Timer instance
4559 * @param Timer This parameter can be one of the following values:
4560 * @arg @ref LL_HRTIM_TIMER_A
4561 * @arg @ref LL_HRTIM_TIMER_B
4562 * @arg @ref LL_HRTIM_TIMER_C
4563 * @arg @ref LL_HRTIM_TIMER_D
4564 * @arg @ref LL_HRTIM_TIMER_E
4565 * @arg @ref LL_HRTIM_TIMER_F
4566 * @param CompareUnit This parameter can be one of the following values:
4567 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4568 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4569 * @param Mode This parameter can be one of the following values:
4570 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4571 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4572 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4573 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4574 * @retval None
4575 */
4576 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
4578 {
4580 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4582 register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4584 }
4586 /**
4587 * @brief Get the functioning mode of the compare unit.
4588 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
4589 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
4590 * @param HRTIMx High Resolution Timer instance
4591 * @param Timer This parameter can be one of the following values:
4592 * @arg @ref LL_HRTIM_TIMER_A
4593 * @arg @ref LL_HRTIM_TIMER_B
4594 * @arg @ref LL_HRTIM_TIMER_C
4595 * @arg @ref LL_HRTIM_TIMER_D
4596 * @arg @ref LL_HRTIM_TIMER_E
4597 * @arg @ref LL_HRTIM_TIMER_F
4598 * @param CompareUnit This parameter can be one of the following values:
4599 * @arg @ref LL_HRTIM_COMPAREUNIT_2
4600 * @arg @ref LL_HRTIM_COMPAREUNIT_4
4601 * @retval Mode Returned value can be one of the following values:
4602 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
4603 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
4604 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
4605 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
4606 */
4607 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
4608 {
4610 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
4612 register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
4614 }
4616 /**
4617 * @brief Set the timer counter value.
4618 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
4619 * CNTxR CNTx LL_HRTIM_TIM_SetCounter
4620 * @note This function can only be called when the timer is stopped.
4621 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
4622 * significant bits of the counter are not significant. They cannot be
4623 * written and return 0 when read.
4624 * @note The timer behavior is not guaranteed if the counter value is set above
4625 * the period.
4626 * @param HRTIMx High Resolution Timer instance
4627 * @param Timer This parameter can be one of the following values:
4628 * @arg @ref LL_HRTIM_TIMER_MASTER
4629 * @arg @ref LL_HRTIM_TIMER_A
4630 * @arg @ref LL_HRTIM_TIMER_B
4631 * @arg @ref LL_HRTIM_TIMER_C
4632 * @arg @ref LL_HRTIM_TIMER_D
4633 * @arg @ref LL_HRTIM_TIMER_E
4634 * @arg @ref LL_HRTIM_TIMER_F
4635 * @param Counter Value between 0 and 0xFFFF
4636 * @retval None
4637 */
4638 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
4639 {
4641 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4644 }
4646 /**
4647 * @brief Get actual timer counter value.
4648 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
4649 * CNTxR CNTx LL_HRTIM_TIM_GetCounter
4650 * @param HRTIMx High Resolution Timer instance
4651 * @param Timer This parameter can be one of the following values:
4652 * @arg @ref LL_HRTIM_TIMER_MASTER
4653 * @arg @ref LL_HRTIM_TIMER_A
4654 * @arg @ref LL_HRTIM_TIMER_B
4655 * @arg @ref LL_HRTIM_TIMER_C
4656 * @arg @ref LL_HRTIM_TIMER_D
4657 * @arg @ref LL_HRTIM_TIMER_E
4658 * @arg @ref LL_HRTIM_TIMER_F
4659 * @retval Counter Value between 0 and 0xFFFF
4660 */
4662 {
4664 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
4667 }
4669 /**
4670 * @brief Set the timer period value.
4671 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
4672 * PERxR PERx LL_HRTIM_TIM_SetPeriod
4673 * @param HRTIMx High Resolution Timer instance
4674 * @param Timer This parameter can be one of the following values:
4675 * @arg @ref LL_HRTIM_TIMER_MASTER
4676 * @arg @ref LL_HRTIM_TIMER_A
4677 * @arg @ref LL_HRTIM_TIMER_B
4678 * @arg @ref LL_HRTIM_TIMER_C
4679 * @arg @ref LL_HRTIM_TIMER_D
4680 * @arg @ref LL_HRTIM_TIMER_E
4681 * @arg @ref LL_HRTIM_TIMER_F
4682 * @param Period Value between 0 and 0xFFFF
4683 * @retval None
4684 */
4685 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
4686 {
4688 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4691 }
4693 /**
4694 * @brief Get actual timer period value.
4695 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
4696 * PERxR PERx LL_HRTIM_TIM_GetPeriod
4697 * @param HRTIMx High Resolution Timer instance
4698 * @param Timer This parameter can be one of the following values:
4699 * @arg @ref LL_HRTIM_TIMER_MASTER
4700 * @arg @ref LL_HRTIM_TIMER_A
4701 * @arg @ref LL_HRTIM_TIMER_B
4702 * @arg @ref LL_HRTIM_TIMER_C
4703 * @arg @ref LL_HRTIM_TIMER_D
4704 * @arg @ref LL_HRTIM_TIMER_E
4705 * @arg @ref LL_HRTIM_TIMER_F
4706 * @retval Period Value between 0 and 0xFFFF
4707 */
4709 {
4711 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
4714 }
4716 /**
4717 * @brief Set the timer repetition period value.
4718 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
4719 * REPxR REPx LL_HRTIM_TIM_SetRepetition
4720 * @param HRTIMx High Resolution Timer instance
4721 * @param Timer This parameter can be one of the following values:
4722 * @arg @ref LL_HRTIM_TIMER_MASTER
4723 * @arg @ref LL_HRTIM_TIMER_A
4724 * @arg @ref LL_HRTIM_TIMER_B
4725 * @arg @ref LL_HRTIM_TIMER_C
4726 * @arg @ref LL_HRTIM_TIMER_D
4727 * @arg @ref LL_HRTIM_TIMER_E
4728 * @arg @ref LL_HRTIM_TIMER_F
4729 * @param Repetition Value between 0 and 0xFF
4730 * @retval None
4731 */
4732 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
4733 {
4735 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4738 }
4740 /**
4741 * @brief Get actual timer repetition period value.
4742 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
4743 * REPxR REPx LL_HRTIM_TIM_GetRepetition
4744 * @param HRTIMx High Resolution Timer instance
4745 * @param Timer This parameter can be one of the following values:
4746 * @arg @ref LL_HRTIM_TIMER_MASTER
4747 * @arg @ref LL_HRTIM_TIMER_A
4748 * @arg @ref LL_HRTIM_TIMER_B
4749 * @arg @ref LL_HRTIM_TIMER_C
4750 * @arg @ref LL_HRTIM_TIMER_D
4751 * @arg @ref LL_HRTIM_TIMER_E
4752 * @arg @ref LL_HRTIM_TIMER_F
4753 * @retval Repetition Value between 0 and 0xFF
4754 */
4756 {
4758 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
4761 }
4763 /**
4764 * @brief Set the compare value of the compare unit 1.
4765 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
4766 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
4767 * @param HRTIMx High Resolution Timer instance
4768 * @param Timer This parameter can be one of the following values:
4769 * @arg @ref LL_HRTIM_TIMER_MASTER
4770 * @arg @ref LL_HRTIM_TIMER_A
4771 * @arg @ref LL_HRTIM_TIMER_B
4772 * @arg @ref LL_HRTIM_TIMER_C
4773 * @arg @ref LL_HRTIM_TIMER_D
4774 * @arg @ref LL_HRTIM_TIMER_E
4775 * @arg @ref LL_HRTIM_TIMER_F
4776 * @param CompareValue Compare value must be above or equal to 3
4777 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4778 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4779 * @retval None
4780 */
4781 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4782 {
4784 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4787 }
4789 /**
4790 * @brief Get actual compare value of the compare unit 1.
4791 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
4792 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
4793 * @param HRTIMx High Resolution Timer instance
4794 * @param Timer This parameter can be one of the following values:
4795 * @arg @ref LL_HRTIM_TIMER_MASTER
4796 * @arg @ref LL_HRTIM_TIMER_A
4797 * @arg @ref LL_HRTIM_TIMER_B
4798 * @arg @ref LL_HRTIM_TIMER_C
4799 * @arg @ref LL_HRTIM_TIMER_D
4800 * @arg @ref LL_HRTIM_TIMER_E
4801 * @arg @ref LL_HRTIM_TIMER_F
4802 * @retval CompareValue Compare value must be above or equal to 3
4803 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4804 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4805 */
4807 {
4809 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
4812 }
4814 /**
4815 * @brief Set the compare value of the compare unit 2.
4816 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
4817 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
4818 * @param HRTIMx High Resolution Timer instance
4819 * @param Timer This parameter can be one of the following values:
4820 * @arg @ref LL_HRTIM_TIMER_MASTER
4821 * @arg @ref LL_HRTIM_TIMER_A
4822 * @arg @ref LL_HRTIM_TIMER_B
4823 * @arg @ref LL_HRTIM_TIMER_C
4824 * @arg @ref LL_HRTIM_TIMER_D
4825 * @arg @ref LL_HRTIM_TIMER_E
4826 * @arg @ref LL_HRTIM_TIMER_F
4827 * @param CompareValue Compare value must be above or equal to 3
4828 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4829 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4830 * @retval None
4831 */
4832 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4833 {
4835 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4838 }
4840 /**
4841 * @brief Get actual compare value of the compare unit 2.
4842 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
4843 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
4844 * @param HRTIMx High Resolution Timer instance
4845 * @param Timer This parameter can be one of the following values:
4846 * @arg @ref LL_HRTIM_TIMER_MASTER
4847 * @arg @ref LL_HRTIM_TIMER_A
4848 * @arg @ref LL_HRTIM_TIMER_B
4849 * @arg @ref LL_HRTIM_TIMER_C
4850 * @arg @ref LL_HRTIM_TIMER_D
4851 * @arg @ref LL_HRTIM_TIMER_E
4852 * @arg @ref LL_HRTIM_TIMER_F
4853 * @retval CompareValue Compare value must be above or equal to 3
4854 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4855 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4856 */
4858 {
4860 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
4863 }
4865 /**
4866 * @brief Set the compare value of the compare unit 3.
4867 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
4868 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
4869 * @param HRTIMx High Resolution Timer instance
4870 * @param Timer This parameter can be one of the following values:
4871 * @arg @ref LL_HRTIM_TIMER_MASTER
4872 * @arg @ref LL_HRTIM_TIMER_A
4873 * @arg @ref LL_HRTIM_TIMER_B
4874 * @arg @ref LL_HRTIM_TIMER_C
4875 * @arg @ref LL_HRTIM_TIMER_D
4876 * @arg @ref LL_HRTIM_TIMER_E
4877 * @arg @ref LL_HRTIM_TIMER_F
4878 * @param CompareValue Compare value must be above or equal to 3
4879 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4880 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4881 * @retval None
4882 */
4883 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4884 {
4886 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4889 }
4891 /**
4892 * @brief Get actual compare value of the compare unit 3.
4893 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
4894 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
4895 * @param HRTIMx High Resolution Timer instance
4896 * @param Timer This parameter can be one of the following values:
4897 * @arg @ref LL_HRTIM_TIMER_MASTER
4898 * @arg @ref LL_HRTIM_TIMER_A
4899 * @arg @ref LL_HRTIM_TIMER_B
4900 * @arg @ref LL_HRTIM_TIMER_C
4901 * @arg @ref LL_HRTIM_TIMER_D
4902 * @arg @ref LL_HRTIM_TIMER_E
4903 * @arg @ref LL_HRTIM_TIMER_F
4904 * @retval CompareValue Compare value must be above or equal to 3
4905 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4906 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4907 */
4909 {
4911 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
4914 }
4916 /**
4917 * @brief Set the compare value of the compare unit 4.
4918 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
4919 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
4920 * @param HRTIMx High Resolution Timer instance
4921 * @param Timer This parameter can be one of the following values:
4922 * @arg @ref LL_HRTIM_TIMER_MASTER
4923 * @arg @ref LL_HRTIM_TIMER_A
4924 * @arg @ref LL_HRTIM_TIMER_B
4925 * @arg @ref LL_HRTIM_TIMER_C
4926 * @arg @ref LL_HRTIM_TIMER_D
4927 * @arg @ref LL_HRTIM_TIMER_E
4928 * @arg @ref LL_HRTIM_TIMER_F
4929 * @param CompareValue Compare value must be above or equal to 3
4930 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4931 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4932 * @retval None
4933 */
4934 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
4935 {
4937 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4940 }
4942 /**
4943 * @brief Get actual compare value of the compare unit 4.
4944 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
4945 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
4946 * @param HRTIMx High Resolution Timer instance
4947 * @param Timer This parameter can be one of the following values:
4948 * @arg @ref LL_HRTIM_TIMER_MASTER
4949 * @arg @ref LL_HRTIM_TIMER_A
4950 * @arg @ref LL_HRTIM_TIMER_B
4951 * @arg @ref LL_HRTIM_TIMER_C
4952 * @arg @ref LL_HRTIM_TIMER_D
4953 * @arg @ref LL_HRTIM_TIMER_E
4954 * @arg @ref LL_HRTIM_TIMER_F
4955 * @retval CompareValue Compare value must be above or equal to 3
4956 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
4957 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
4958 */
4960 {
4962 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
4965 }
4967 /**
4968 * @brief Set the reset trigger of a timer counter.
4969 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
4970 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
4971 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
4972 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
4973 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
4974 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
4975 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
4976 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
4977 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
4978 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
4979 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
4980 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
4981 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
4982 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
4983 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
4984 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
4985 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
4986 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
4987 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
4988 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
4989 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
4990 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
4991 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
4992 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
4993 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
4994 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
4995 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
4996 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
4997 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
4998 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig\n
4999 * RSTxR TIMFCMP1 LL_HRTIM_TIM_SetResetTrig\n
5000 * RSTxR TIMFCMP2 LL_HRTIM_TIM_SetResetTrig
5001 * @note The reset of the timer counter can be triggered by up to 30 events
5002 * that can be selected among the following sources:
5003 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
5004 * @arg The master timer: Reset and Compare 1..4 (5 events).
5005 * @arg The external events EXTEVNT1..10 (10 events).
5006 * @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
5007 * @param HRTIMx High Resolution Timer instance
5008 * @param Timer This parameter can be one of the following values:
5009 * @arg @ref LL_HRTIM_TIMER_A
5010 * @arg @ref LL_HRTIM_TIMER_B
5011 * @arg @ref LL_HRTIM_TIMER_C
5012 * @arg @ref LL_HRTIM_TIMER_D
5013 * @arg @ref LL_HRTIM_TIMER_E
5014 * @arg @ref LL_HRTIM_TIMER_F
5015 * @param ResetTrig This parameter can be a combination of the following values:
5016 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5017 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5018 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5019 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5020 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5021 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5022 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5023 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5024 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5025 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5026 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5027 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5028 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5029 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5030 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5031 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5032 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5033 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5034 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5035 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5036 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5037 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5038 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5039 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5040 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5041 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5042 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5043 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5044 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5045 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5046 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5047 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5048 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5049 * @retval None
5050 */
5051 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
5052 {
5054 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5057 }
5059 /**
5060 * @brief Get actual reset trigger of a timer counter.
5061 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
5062 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
5063 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
5064 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
5065 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
5066 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
5067 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
5068 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
5069 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
5070 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
5071 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
5072 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
5073 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
5074 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
5075 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
5076 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
5077 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
5078 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
5079 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
5080 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
5081 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
5082 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
5083 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
5084 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
5085 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
5086 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
5087 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
5088 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
5089 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
5090 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig\n
5091 * RSTxR TIMFCMP1 LL_HRTIM_TIM_GetResetTrig\n
5092 * RSTxR TIMFCMP2 LL_HRTIM_TIM_GetResetTrig
5093 * @param HRTIMx High Resolution Timer instance
5094 * @param Timer This parameter can be one of the following values:
5095 * @arg @ref LL_HRTIM_TIMER_A
5096 * @arg @ref LL_HRTIM_TIMER_B
5097 * @arg @ref LL_HRTIM_TIMER_C
5098 * @arg @ref LL_HRTIM_TIMER_D
5099 * @arg @ref LL_HRTIM_TIMER_E
5100 * @arg @ref LL_HRTIM_TIMER_F
5101 * @retval ResetTrig Returned value can be one of the following values:
5102 * @arg @ref LL_HRTIM_RESETTRIG_NONE
5103 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE
5104 * @arg @ref LL_HRTIM_RESETTRIG_CMP2
5105 * @arg @ref LL_HRTIM_RESETTRIG_CMP4
5106 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
5107 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
5108 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
5109 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
5110 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
5111 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1
5112 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2
5113 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3
5114 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4
5115 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5
5116 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6
5117 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7
5118 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8
5119 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9
5120 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10
5121 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
5122 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
5123 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
5124 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
5125 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
5126 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
5127 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
5128 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
5129 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
5130 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
5131 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
5132 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
5133 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
5134 * @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
5135 */
5137 {
5139 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
5142 }
5144 /**
5145 * @brief Get captured value for capture unit 1.
5146 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
5147 * @param HRTIMx High Resolution Timer instance
5148 * @param Timer This parameter can be one of the following values:
5149 * @arg @ref LL_HRTIM_TIMER_A
5150 * @arg @ref LL_HRTIM_TIMER_B
5151 * @arg @ref LL_HRTIM_TIMER_C
5152 * @arg @ref LL_HRTIM_TIMER_D
5153 * @arg @ref LL_HRTIM_TIMER_E
5154 * @arg @ref LL_HRTIM_TIMER_F
5155 * @retval Captured value
5156 */
5158 {
5160 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5163 }
5165 /**
5166 * @brief Get the counting direction when capture 1 event occurred.
5167 * @rmtoll CPT1xR DIR LL_HRTIM_TIM_GetCapture1Direction
5168 * @param HRTIMx High Resolution Timer instance
5169 * @param Timer This parameter can be one of the following values:
5170 * @arg @ref LL_HRTIM_TIMER_A
5171 * @arg @ref LL_HRTIM_TIMER_B
5172 * @arg @ref LL_HRTIM_TIMER_C
5173 * @arg @ref LL_HRTIM_TIMER_D
5174 * @arg @ref LL_HRTIM_TIMER_E
5175 * @arg @ref LL_HRTIM_TIMER_F
5176 * @retval Filter This parameter can be one of the following values:
5177 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5178 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5179 */
5180 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5181 {
5183 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
5186 }
5188 /**
5189 * @brief Get captured value for capture unit 2.
5190 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
5191 * @param HRTIMx High Resolution Timer instance
5192 * @param Timer This parameter can be one of the following values:
5193 * @arg @ref LL_HRTIM_TIMER_A
5194 * @arg @ref LL_HRTIM_TIMER_B
5195 * @arg @ref LL_HRTIM_TIMER_C
5196 * @arg @ref LL_HRTIM_TIMER_D
5197 * @arg @ref LL_HRTIM_TIMER_E
5198 * @arg @ref LL_HRTIM_TIMER_F
5199 * @retval Captured value
5200 */
5202 {
5204 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5207 }
5209 /**
5210 * @brief Get the counting direction when capture 2 event occurred.
5211 * @rmtoll CPT2xR DIR LL_HRTIM_TIM_GetCapture2Direction
5212 * @param HRTIMx High Resolution Timer instance
5213 * @param Timer This parameter can be one of the following values:
5214 * @arg @ref LL_HRTIM_TIMER_A
5215 * @arg @ref LL_HRTIM_TIMER_B
5216 * @arg @ref LL_HRTIM_TIMER_C
5217 * @arg @ref LL_HRTIM_TIMER_D
5218 * @arg @ref LL_HRTIM_TIMER_E
5219 * @arg @ref LL_HRTIM_TIMER_F
5220 * @retval Filter This parameter can be one of the following values:
5221 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
5222 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
5223 */
5224 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5225 {
5227 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
5230 }
5232 /**
5233 * @brief Set the trigger of a capture unit for a given timer.
5234 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
5235 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
5236 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
5237 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
5238 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
5239 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
5240 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
5241 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
5242 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
5243 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
5244 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
5245 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
5246 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
5247 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
5248 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5249 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5250 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
5251 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
5252 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5253 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5254 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
5255 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
5256 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5257 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5258 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
5259 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
5260 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5261 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5262 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
5263 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
5264 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5265 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig\n
5266 * CPT1xCR TF1SET LL_HRTIM_TIM_SetCaptureTrig\n
5267 * CPT1xCR TF1RST LL_HRTIM_TIM_SetCaptureTrig\n
5268 * CPT1xCR TFCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
5269 * CPT1xCR TFCMP2 LL_HRTIM_TIM_SetCaptureTrig
5270 * @param HRTIMx High Resolution Timer instance
5271 * @param Timer This parameter can be one of the following values:
5272 * @arg @ref LL_HRTIM_TIMER_A
5273 * @arg @ref LL_HRTIM_TIMER_B
5274 * @arg @ref LL_HRTIM_TIMER_C
5275 * @arg @ref LL_HRTIM_TIMER_D
5276 * @arg @ref LL_HRTIM_TIMER_E
5277 * @arg @ref LL_HRTIM_TIMER_F
5278 * @param CaptureUnit This parameter can be one of the following values:
5279 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5280 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5281 * @param CaptureTrig This parameter can be a combination of the following values:
5282 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5283 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5284 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5285 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5286 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5287 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5288 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5289 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5290 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5291 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5292 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5293 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5294 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5295 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5296 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5297 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5298 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5299 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5300 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5301 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5302 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5303 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5304 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5305 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5306 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5307 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5308 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5309 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5310 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5311 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5312 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5313 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5314 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5315 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5316 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5317 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5318 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5319 * @retval None
5320 */
5321 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
5323 {
5325 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5331 cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
5335 }
5337 /**
5338 * @brief Get actual trigger of a capture unit for a given timer.
5339 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
5340 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
5341 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
5342 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
5343 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
5344 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
5345 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
5346 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
5347 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
5348 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
5349 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
5350 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
5351 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
5352 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
5353 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5354 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5355 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
5356 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
5357 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5358 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5359 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
5360 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
5361 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5362 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5363 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
5364 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
5365 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5366 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5367 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
5368 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
5369 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5370 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig\n
5371 * CPT1xCR TF1SET LL_HRTIM_TIM_GetCaptureTrig\n
5372 * CPT1xCR TF1RST LL_HRTIM_TIM_GetCaptureTrig\n
5373 * CPT1xCR TFCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
5374 * CPT1xCR TFCMP2 LL_HRTIM_TIM_GetCaptureTrig
5375 * @param HRTIMx High Resolution Timer instance
5376 * @param Timer This parameter can be one of the following values:
5377 * @arg @ref LL_HRTIM_TIMER_A
5378 * @arg @ref LL_HRTIM_TIMER_B
5379 * @arg @ref LL_HRTIM_TIMER_C
5380 * @arg @ref LL_HRTIM_TIMER_D
5381 * @arg @ref LL_HRTIM_TIMER_E
5382 * @arg @ref LL_HRTIM_TIMER_F
5383 * @param CaptureUnit This parameter can be one of the following values:
5384 * @arg @ref LL_HRTIM_CAPTUREUNIT_1
5385 * @arg @ref LL_HRTIM_CAPTUREUNIT_2
5386 * @retval CaptureTrig This parameter can be a combination of the following values:
5387 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE
5388 * @arg @ref LL_HRTIM_CAPTURETRIG_SW
5389 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
5390 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
5391 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
5392 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
5393 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
5394 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
5395 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
5396 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
5397 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
5398 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
5399 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
5400 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
5401 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
5402 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
5403 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
5404 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
5405 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
5406 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
5407 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
5408 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
5409 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
5410 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
5411 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
5412 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
5413 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
5414 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
5415 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
5416 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
5417 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
5418 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
5419 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
5420 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
5421 * @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
5422 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
5423 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
5424 */
5425 __STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
5426 {
5428 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
5434 cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
5436 return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
5437 }
5439 /**
5440 * @brief Enable deadtime insertion for a given timer.
5441 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
5442 * @param HRTIMx High Resolution Timer instance
5443 * @param Timer This parameter can be one of the following values:
5444 * @arg @ref LL_HRTIM_TIMER_A
5445 * @arg @ref LL_HRTIM_TIMER_B
5446 * @arg @ref LL_HRTIM_TIMER_C
5447 * @arg @ref LL_HRTIM_TIMER_D
5448 * @arg @ref LL_HRTIM_TIMER_E
5449 * @arg @ref LL_HRTIM_TIMER_F
5450 * @retval None
5451 */
5453 {
5455 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5458 }
5460 /**
5461 * @brief Disable deadtime insertion for a given timer.
5462 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
5463 * @param HRTIMx High Resolution Timer instance
5464 * @param Timer This parameter can be one of the following values:
5465 * @arg @ref LL_HRTIM_TIMER_A
5466 * @arg @ref LL_HRTIM_TIMER_B
5467 * @arg @ref LL_HRTIM_TIMER_C
5468 * @arg @ref LL_HRTIM_TIMER_D
5469 * @arg @ref LL_HRTIM_TIMER_E
5470 * @arg @ref LL_HRTIM_TIMER_F
5471 * @retval None
5472 */
5474 {
5476 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5479 }
5481 /**
5482 * @brief Indicate whether deadtime insertion is enabled for a given timer.
5483 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
5484 * @param HRTIMx High Resolution Timer instance
5485 * @param Timer This parameter can be one of the following values:
5486 * @arg @ref LL_HRTIM_TIMER_A
5487 * @arg @ref LL_HRTIM_TIMER_B
5488 * @arg @ref LL_HRTIM_TIMER_C
5489 * @arg @ref LL_HRTIM_TIMER_D
5490 * @arg @ref LL_HRTIM_TIMER_E
5491 * @arg @ref LL_HRTIM_TIMER_F
5492 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
5493 */
5495 {
5497 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5501 }
5503 /**
5504 * @brief Set the delayed protection (DLYPRT) mode.
5505 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
5506 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
5507 * @note This function must be called prior enabling the delayed protection
5508 * @note Balanced Idle mode is only available in push-pull mode
5509 * @param HRTIMx High Resolution Timer instance
5510 * @param Timer This parameter can be one of the following values:
5511 * @arg @ref LL_HRTIM_TIMER_A
5512 * @arg @ref LL_HRTIM_TIMER_B
5513 * @arg @ref LL_HRTIM_TIMER_C
5514 * @arg @ref LL_HRTIM_TIMER_D
5515 * @arg @ref LL_HRTIM_TIMER_E
5516 * @arg @ref LL_HRTIM_TIMER_F
5517 * @param DLYPRTMode Delayed protection (DLYPRT) mode
5518 *
5519 * For timers A, B and C this parameter can be one of the following values:
5520 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5521 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5522 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5523 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5524 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5525 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5526 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5527 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5528 *
5529 * For timers D, E and F this parameter can be one of the following values:
5530 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5531 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5532 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5533 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5534 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5535 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5536 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5537 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5538 * @retval None
5539 */
5540 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
5541 {
5543 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5546 }
5548 /**
5549 * @brief Get the delayed protection (DLYPRT) mode.
5550 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
5551 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
5552 * @param HRTIMx High Resolution Timer instance
5553 * @param Timer This parameter can be one of the following values:
5554 * @arg @ref LL_HRTIM_TIMER_A
5555 * @arg @ref LL_HRTIM_TIMER_B
5556 * @arg @ref LL_HRTIM_TIMER_C
5557 * @arg @ref LL_HRTIM_TIMER_D
5558 * @arg @ref LL_HRTIM_TIMER_E
5559 * @arg @ref LL_HRTIM_TIMER_F
5560 * @retval DLYPRTMode Delayed protection (DLYPRT) mode
5561 *
5562 * For timers A, B and C this parameter can be one of the following values:
5563 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
5564 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
5565 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
5566 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
5567 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
5568 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
5569 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
5570 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
5571 *
5572 * For timers D, E and F this parameter can be one of the following values:
5573 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
5574 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
5575 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
5576 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
5577 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
5578 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
5579 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
5580 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
5581 */
5583 {
5585 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5588 }
5590 /**
5591 * @brief Enable delayed protection (DLYPRT) for a given timer.
5592 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
5593 * @note This function must not be called once the concerned timer is enabled
5594 * @param HRTIMx High Resolution Timer instance
5595 * @param Timer This parameter can be one of the following values:
5596 * @arg @ref LL_HRTIM_TIMER_A
5597 * @arg @ref LL_HRTIM_TIMER_B
5598 * @arg @ref LL_HRTIM_TIMER_C
5599 * @arg @ref LL_HRTIM_TIMER_D
5600 * @arg @ref LL_HRTIM_TIMER_E
5601 * @arg @ref LL_HRTIM_TIMER_F
5602 * @retval None
5603 */
5605 {
5607 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5610 }
5612 /**
5613 * @brief Disable delayed protection (DLYPRT) for a given timer.
5614 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
5615 * @note This function must not be called once the concerned timer is enabled
5616 * @param HRTIMx High Resolution Timer instance
5617 * @param Timer This parameter can be one of the following values:
5618 * @arg @ref LL_HRTIM_TIMER_A
5619 * @arg @ref LL_HRTIM_TIMER_B
5620 * @arg @ref LL_HRTIM_TIMER_C
5621 * @arg @ref LL_HRTIM_TIMER_D
5622 * @arg @ref LL_HRTIM_TIMER_E
5623 * @arg @ref LL_HRTIM_TIMER_F
5624 * @retval None
5625 */
5627 {
5629 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5632 }
5634 /**
5635 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
5636 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
5637 * @param HRTIMx High Resolution Timer instance
5638 * @param Timer This parameter can be one of the following values:
5639 * @arg @ref LL_HRTIM_TIMER_A
5640 * @arg @ref LL_HRTIM_TIMER_B
5641 * @arg @ref LL_HRTIM_TIMER_C
5642 * @arg @ref LL_HRTIM_TIMER_D
5643 * @arg @ref LL_HRTIM_TIMER_E
5644 * @arg @ref LL_HRTIM_TIMER_F
5645 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5646 */
5648 {
5650 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5653 }
5655 /**
5656 * @brief Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5657 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_EnableBIAR
5658 * @note This function must not be called once the concerned timer is enabled
5659 * @param HRTIMx High Resolution Timer instance
5660 * @param Timer This parameter can be one of the following values:
5661 * @arg @ref LL_HRTIM_TIMER_A
5662 * @arg @ref LL_HRTIM_TIMER_B
5663 * @arg @ref LL_HRTIM_TIMER_C
5664 * @arg @ref LL_HRTIM_TIMER_D
5665 * @arg @ref LL_HRTIM_TIMER_E
5666 * @arg @ref LL_HRTIM_TIMER_F
5667 * @retval None
5668 */
5670 {
5672 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5675 }
5677 /**
5678 * @brief Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
5679 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_DisableBIAR
5680 * @note This function must not be called once the concerned timer is enabled
5681 * @param HRTIMx High Resolution Timer instance
5682 * @param Timer This parameter can be one of the following values:
5683 * @arg @ref LL_HRTIM_TIMER_A
5684 * @arg @ref LL_HRTIM_TIMER_B
5685 * @arg @ref LL_HRTIM_TIMER_C
5686 * @arg @ref LL_HRTIM_TIMER_D
5687 * @arg @ref LL_HRTIM_TIMER_E
5688 * @arg @ref LL_HRTIM_TIMER_F
5689 * @retval None
5690 */
5692 {
5694 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
5697 }
5699 /**
5700 * @brief Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
5701 * @rmtoll OUTxR BIAR LL_HRTIM_TIM_IsEnabledBIAR
5702 * @param HRTIMx High Resolution Timer instance
5703 * @param Timer This parameter can be one of the following values:
5704 * @arg @ref LL_HRTIM_TIMER_A
5705 * @arg @ref LL_HRTIM_TIMER_B
5706 * @arg @ref LL_HRTIM_TIMER_C
5707 * @arg @ref LL_HRTIM_TIMER_D
5708 * @arg @ref LL_HRTIM_TIMER_E
5709 * @arg @ref LL_HRTIM_TIMER_F
5710 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
5711 */
5713 {
5715 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
5719 }
5721 /**
5722 * @brief Enable the fault channel(s) for a given timer.
5723 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
5724 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
5725 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
5726 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
5727 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault\n
5728 * FLTxR FLT6EN LL_HRTIM_TIM_EnableFault
5729 * @param HRTIMx High Resolution Timer instance
5730 * @param Timer This parameter can be one of the following values:
5731 * @arg @ref LL_HRTIM_TIMER_A
5732 * @arg @ref LL_HRTIM_TIMER_B
5733 * @arg @ref LL_HRTIM_TIMER_C
5734 * @arg @ref LL_HRTIM_TIMER_D
5735 * @arg @ref LL_HRTIM_TIMER_E
5736 * @arg @ref LL_HRTIM_TIMER_F
5737 * @param Faults This parameter can be a combination of the following values:
5738 * @arg @ref LL_HRTIM_FAULT_1
5739 * @arg @ref LL_HRTIM_FAULT_2
5740 * @arg @ref LL_HRTIM_FAULT_3
5741 * @arg @ref LL_HRTIM_FAULT_4
5742 * @arg @ref LL_HRTIM_FAULT_5
5743 * @arg @ref LL_HRTIM_FAULT_6
5744 * @retval None
5745 */
5746 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5747 {
5749 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5752 }
5754 /**
5755 * @brief Disable the fault channel(s) for a given timer.
5756 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
5757 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
5758 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
5759 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
5760 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault\n
5761 * FLTxR FLT6EN LL_HRTIM_TIM_DisableFault
5762 * @param HRTIMx High Resolution Timer instance
5763 * @param Timer This parameter can be one of the following values:
5764 * @arg @ref LL_HRTIM_TIMER_A
5765 * @arg @ref LL_HRTIM_TIMER_B
5766 * @arg @ref LL_HRTIM_TIMER_C
5767 * @arg @ref LL_HRTIM_TIMER_D
5768 * @arg @ref LL_HRTIM_TIMER_E
5769 * @arg @ref LL_HRTIM_TIMER_F
5770 * @param Faults This parameter can be a combination of the following values:
5771 * @arg @ref LL_HRTIM_FAULT_1
5772 * @arg @ref LL_HRTIM_FAULT_2
5773 * @arg @ref LL_HRTIM_FAULT_3
5774 * @arg @ref LL_HRTIM_FAULT_4
5775 * @arg @ref LL_HRTIM_FAULT_5
5776 * @arg @ref LL_HRTIM_FAULT_6
5777 * @retval None
5778 */
5779 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
5780 {
5782 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5785 }
5787 /**
5788 * @brief Indicate whether the fault channel is enabled for a given timer.
5789 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
5790 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
5791 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
5792 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
5793 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault\n
5794 * FLTxR FLT6EN LL_HRTIM_TIM_IsEnabledFault
5795 * @param HRTIMx High Resolution Timer instance
5796 * @param Timer This parameter can be one of the following values:
5797 * @arg @ref LL_HRTIM_TIMER_A
5798 * @arg @ref LL_HRTIM_TIMER_B
5799 * @arg @ref LL_HRTIM_TIMER_C
5800 * @arg @ref LL_HRTIM_TIMER_D
5801 * @arg @ref LL_HRTIM_TIMER_E
5802 * @arg @ref LL_HRTIM_TIMER_F
5803 * @param Fault This parameter can be one of the following values:
5804 * @arg @ref LL_HRTIM_FAULT_1
5805 * @arg @ref LL_HRTIM_FAULT_2
5806 * @arg @ref LL_HRTIM_FAULT_3
5807 * @arg @ref LL_HRTIM_FAULT_4
5808 * @arg @ref LL_HRTIM_FAULT_5
5809 * @arg @ref LL_HRTIM_FAULT_6
5810 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
5811 */
5812 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
5813 {
5815 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5819 }
5821 /**
5822 * @brief Lock the fault conditioning set-up for a given timer.
5823 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
5824 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
5825 * @param HRTIMx High Resolution Timer instance
5826 * @param Timer This parameter can be one of the following values:
5827 * @arg @ref LL_HRTIM_TIMER_A
5828 * @arg @ref LL_HRTIM_TIMER_B
5829 * @arg @ref LL_HRTIM_TIMER_C
5830 * @arg @ref LL_HRTIM_TIMER_D
5831 * @arg @ref LL_HRTIM_TIMER_E
5832 * @arg @ref LL_HRTIM_TIMER_F
5833 * @retval None
5834 */
5836 {
5838 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
5841 }
5843 /**
5844 * @brief Define how the timer behaves during a burst mode operation.
5845 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
5846 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
5847 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
5848 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
5849 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
5850 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption\n
5851 * BMCR TFBM LL_HRTIM_TIM_SetBurstModeOption
5852 * @note This function must not be called when the burst mode is enabled
5853 * @param HRTIMx High Resolution Timer instance
5854 * @param Timer This parameter can be one of the following values:
5855 * @arg @ref LL_HRTIM_TIMER_MASTER
5856 * @arg @ref LL_HRTIM_TIMER_A
5857 * @arg @ref LL_HRTIM_TIMER_B
5858 * @arg @ref LL_HRTIM_TIMER_C
5859 * @arg @ref LL_HRTIM_TIMER_D
5860 * @arg @ref LL_HRTIM_TIMER_E
5861 * @arg @ref LL_HRTIM_TIMER_F
5862 * @param BurtsModeOption This parameter can be one of the following values:
5863 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5864 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5865 * @retval None
5866 */
5867 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
5868 {
5871 }
5873 /**
5874 * @brief Retrieve how the timer behaves during a burst mode operation.
5875 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
5876 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
5877 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
5878 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
5879 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
5880 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption\n
5881 * BMCR TFBM LL_HRTIM_TIM_GetBurstModeOption
5882 * @param HRTIMx High Resolution Timer instance
5883 * @param Timer This parameter can be one of the following values:
5884 * @arg @ref LL_HRTIM_TIMER_MASTER
5885 * @arg @ref LL_HRTIM_TIMER_A
5886 * @arg @ref LL_HRTIM_TIMER_B
5887 * @arg @ref LL_HRTIM_TIMER_C
5888 * @arg @ref LL_HRTIM_TIMER_D
5889 * @arg @ref LL_HRTIM_TIMER_E
5890 * @arg @ref LL_HRTIM_TIMER_F
5891 * @retval BurtsMode This parameter can be one of the following values:
5892 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
5893 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
5894 */
5895 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
5896 {
5899 }
5901 /**
5902 * @brief Program which registers are to be written by Burst DMA transfers.
5903 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
5904 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
5905 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5906 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5907 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
5908 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
5909 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5910 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5911 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5912 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5913 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
5914 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
5915 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
5916 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
5917 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
5918 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
5919 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
5920 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
5921 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
5922 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
5923 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
5924 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
5925 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
5926 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
5927 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
5928 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
5929 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
5930 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
5931 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
5932 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
5933 * @param HRTIMx High Resolution Timer instance
5934 * @param Timer This parameter can be one of the following values:
5935 * @arg @ref LL_HRTIM_TIMER_MASTER
5936 * @arg @ref LL_HRTIM_TIMER_A
5937 * @arg @ref LL_HRTIM_TIMER_B
5938 * @arg @ref LL_HRTIM_TIMER_C
5939 * @arg @ref LL_HRTIM_TIMER_D
5940 * @arg @ref LL_HRTIM_TIMER_E
5941 * @arg @ref LL_HRTIM_TIMER_F
5942 * @param Registers Registers to be updated by the DMA request
5943 *
5944 * For Master timer this parameter can be can be a combination of the following values:
5945 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5946 * @arg @ref LL_HRTIM_BURSTDMA_MCR
5947 * @arg @ref LL_HRTIM_BURSTDMA_MICR
5948 * @arg @ref LL_HRTIM_BURSTDMA_MDIER
5949 * @arg @ref LL_HRTIM_BURSTDMA_MCNT
5950 * @arg @ref LL_HRTIM_BURSTDMA_MPER
5951 * @arg @ref LL_HRTIM_BURSTDMA_MREP
5952 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1
5953 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2
5954 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3
5955 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4
5956 *
5957 * For Timers A..F this parameter can be can be a combination of the following values:
5958 * @arg @ref LL_HRTIM_BURSTDMA_NONE
5959 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
5960 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR
5961 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
5962 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
5963 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER
5964 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP
5965 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
5966 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
5967 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
5968 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
5969 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
5970 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
5971 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
5972 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
5973 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
5974 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
5975 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
5976 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
5977 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
5978 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
5979 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
5980 * @arg @ref LL_HRTIM_BURSTDMA_CR2
5981 * @arg @ref LL_HRTIM_BURSTDMA_EEFR3
5982 * @retval None
5983 */
5984 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
5985 {
5987 {
5995 };
5998 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
6000 }
6002 /**
6003 * @brief Indicate on which output the signal is currently applied.
6004 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
6005 * @note Only significant when the timer operates in push-pull mode.
6006 * @param HRTIMx High Resolution Timer instance
6007 * @param Timer This parameter can be one of the following values:
6008 * @arg @ref LL_HRTIM_TIMER_A
6009 * @arg @ref LL_HRTIM_TIMER_B
6010 * @arg @ref LL_HRTIM_TIMER_C
6011 * @arg @ref LL_HRTIM_TIMER_D
6012 * @arg @ref LL_HRTIM_TIMER_E
6013 * @arg @ref LL_HRTIM_TIMER_F
6014 * @retval CPPSTAT This parameter can be one of the following values:
6015 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
6016 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
6017 */
6018 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6019 {
6021 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6024 }
6026 /**
6027 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
6028 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
6029 * @param HRTIMx High Resolution Timer instance
6030 * @param Timer This parameter can be one of the following values:
6031 * @arg @ref LL_HRTIM_TIMER_A
6032 * @arg @ref LL_HRTIM_TIMER_B
6033 * @arg @ref LL_HRTIM_TIMER_C
6034 * @arg @ref LL_HRTIM_TIMER_D
6035 * @arg @ref LL_HRTIM_TIMER_E
6036 * @arg @ref LL_HRTIM_TIMER_F
6037 * @retval IPPSTAT This parameter can be one of the following values:
6038 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
6039 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
6040 */
6041 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6042 {
6044 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
6047 }
6049 /**
6050 * @brief Set the event filter for a given timer.
6051 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
6052 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
6053 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
6054 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
6055 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
6056 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
6057 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
6058 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
6059 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
6060 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
6061 * @note This function must not be called when the timer counter is enabled.
6062 * @param HRTIMx High Resolution Timer instance
6063 * @param Timer This parameter can be one of the following values:
6064 * @arg @ref LL_HRTIM_TIMER_A
6065 * @arg @ref LL_HRTIM_TIMER_B
6066 * @arg @ref LL_HRTIM_TIMER_C
6067 * @arg @ref LL_HRTIM_TIMER_D
6068 * @arg @ref LL_HRTIM_TIMER_E
6069 * @arg @ref LL_HRTIM_TIMER_F
6070 * @param Event This parameter can be one of the following values:
6071 * @arg @ref LL_HRTIM_EVENT_1
6072 * @arg @ref LL_HRTIM_EVENT_2
6073 * @arg @ref LL_HRTIM_EVENT_3
6074 * @arg @ref LL_HRTIM_EVENT_4
6075 * @arg @ref LL_HRTIM_EVENT_5
6076 * @arg @ref LL_HRTIM_EVENT_6
6077 * @arg @ref LL_HRTIM_EVENT_7
6078 * @arg @ref LL_HRTIM_EVENT_8
6079 * @arg @ref LL_HRTIM_EVENT_9
6080 * @arg @ref LL_HRTIM_EVENT_10
6081 * @param Filter This parameter can be one of the following values:
6082 * @arg @ref LL_HRTIM_EEFLTR_NONE
6083 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6084 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6085 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6086 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6087 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6088 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6089 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6090 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6091 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6092 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6093 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6094 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6095 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6096 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6097 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6098 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6099 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6100 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6101 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6102 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6103 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6104 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6105 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6106 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6107 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6108 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6109 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6110 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6111 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6112 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6113 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6114 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6115 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6116 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6117 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6118 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6119 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6120 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6121 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6122 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6123 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6124 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6125 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6126 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6127 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6128 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6129 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6130 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6131 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6132 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6133 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6134 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6135 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6136 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6137 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6139 * @retval None
6140 */
6141 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
6142 {
6145 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6147 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
6148 }
6150 /**
6151 * @brief Get actual event filter settings for a given timer.
6152 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
6153 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
6154 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
6155 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
6156 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
6157 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
6158 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
6159 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
6160 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
6161 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
6162 * @param HRTIMx High Resolution Timer instance
6163 * @param Timer This parameter can be one of the following values:
6164 * @arg @ref LL_HRTIM_TIMER_A
6165 * @arg @ref LL_HRTIM_TIMER_B
6166 * @arg @ref LL_HRTIM_TIMER_C
6167 * @arg @ref LL_HRTIM_TIMER_D
6168 * @arg @ref LL_HRTIM_TIMER_E
6169 * @arg @ref LL_HRTIM_TIMER_F
6170 * @param Event This parameter can be one of the following values:
6171 * @arg @ref LL_HRTIM_EVENT_1
6172 * @arg @ref LL_HRTIM_EVENT_2
6173 * @arg @ref LL_HRTIM_EVENT_3
6174 * @arg @ref LL_HRTIM_EVENT_4
6175 * @arg @ref LL_HRTIM_EVENT_5
6176 * @arg @ref LL_HRTIM_EVENT_6
6177 * @arg @ref LL_HRTIM_EVENT_7
6178 * @arg @ref LL_HRTIM_EVENT_8
6179 * @arg @ref LL_HRTIM_EVENT_9
6180 * @arg @ref LL_HRTIM_EVENT_10
6181 * @retval Filter This parameter can be one of the following values:
6182 * @arg @ref LL_HRTIM_EEFLTR_NONE
6183 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
6184 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
6185 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
6186 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
6187 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
6188 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
6189 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
6190 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
6191 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
6192 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
6193 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
6194 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
6195 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
6196 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
6197 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
6198 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
6199 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
6200 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
6201 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
6202 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
6203 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
6204 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
6205 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
6206 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
6207 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
6208 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
6209 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
6210 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
6211 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
6212 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
6213 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
6214 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
6215 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
6216 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
6217 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
6218 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
6219 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
6220 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
6221 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
6222 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
6223 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
6224 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
6225 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
6226 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
6227 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
6228 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
6229 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
6230 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
6231 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
6232 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
6233 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
6234 * @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
6235 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
6236 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
6237 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
6238 */
6239 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6240 {
6243 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6245 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6246 }
6248 /**
6249 * @brief Enable or disable event latch mechanism for a given timer.
6250 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6251 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6252 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6253 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6254 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6255 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6256 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6257 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6258 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
6259 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
6260 * @note This function must not be called when the timer counter is enabled.
6261 * @param HRTIMx High Resolution Timer instance
6262 * @param Timer This parameter can be one of the following values:
6263 * @arg @ref LL_HRTIM_TIMER_A
6264 * @arg @ref LL_HRTIM_TIMER_B
6265 * @arg @ref LL_HRTIM_TIMER_C
6266 * @arg @ref LL_HRTIM_TIMER_D
6267 * @arg @ref LL_HRTIM_TIMER_E
6268 * @arg @ref LL_HRTIM_TIMER_F
6269 * @param Event This parameter can be one of the following values:
6270 * @arg @ref LL_HRTIM_EVENT_1
6271 * @arg @ref LL_HRTIM_EVENT_2
6272 * @arg @ref LL_HRTIM_EVENT_3
6273 * @arg @ref LL_HRTIM_EVENT_4
6274 * @arg @ref LL_HRTIM_EVENT_5
6275 * @arg @ref LL_HRTIM_EVENT_6
6276 * @arg @ref LL_HRTIM_EVENT_7
6277 * @arg @ref LL_HRTIM_EVENT_8
6278 * @arg @ref LL_HRTIM_EVENT_9
6279 * @arg @ref LL_HRTIM_EVENT_10
6280 * @param LatchStatus This parameter can be one of the following values:
6281 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6282 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6283 * @retval None
6284 */
6285 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
6287 {
6290 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6292 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
6293 }
6295 /**
6296 * @brief Get actual event latch status for a given timer.
6297 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6298 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6299 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6300 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6301 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6302 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6303 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6304 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6305 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
6306 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
6307 * @param HRTIMx High Resolution Timer instance
6308 * @param Timer This parameter can be one of the following values:
6309 * @arg @ref LL_HRTIM_TIMER_A
6310 * @arg @ref LL_HRTIM_TIMER_B
6311 * @arg @ref LL_HRTIM_TIMER_C
6312 * @arg @ref LL_HRTIM_TIMER_D
6313 * @arg @ref LL_HRTIM_TIMER_E
6314 * @arg @ref LL_HRTIM_TIMER_F
6315 * @param Event This parameter can be one of the following values:
6316 * @arg @ref LL_HRTIM_EVENT_1
6317 * @arg @ref LL_HRTIM_EVENT_2
6318 * @arg @ref LL_HRTIM_EVENT_3
6319 * @arg @ref LL_HRTIM_EVENT_4
6320 * @arg @ref LL_HRTIM_EVENT_5
6321 * @arg @ref LL_HRTIM_EVENT_6
6322 * @arg @ref LL_HRTIM_EVENT_7
6323 * @arg @ref LL_HRTIM_EVENT_8
6324 * @arg @ref LL_HRTIM_EVENT_9
6325 * @arg @ref LL_HRTIM_EVENT_10
6326 * @retval LatchStatus This parameter can be one of the following values:
6327 * @arg @ref LL_HRTIM_EELATCH_DISABLED
6328 * @arg @ref LL_HRTIM_EELATCH_ENABLED
6329 */
6330 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
6331 {
6334 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
6336 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
6337 }
6339 /**
6340 * @brief Select the Trigger-Half operating mode for a given timer.
6341 * @note This bitfield defines whether the compare 2 register
6342 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6343 * @note or in triggered-half mode
6344 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_SetTriggeredHalfMode
6345 * @param HRTIMx High Resolution Timer instance
6346 * @param Timer This parameter can be one of the following values:
6347 * @arg @ref LL_HRTIM_TIMER_A
6348 * @arg @ref LL_HRTIM_TIMER_B
6349 * @arg @ref LL_HRTIM_TIMER_C
6350 * @arg @ref LL_HRTIM_TIMER_D
6351 * @arg @ref LL_HRTIM_TIMER_E
6352 * @arg @ref LL_HRTIM_TIMER_F
6353 * @param Mode This parameter can be one of the following values:
6354 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6355 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6356 * @retval None
6357 */
6358 __STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6359 {
6361 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6364 }
6366 /**
6367 * @brief Get the Trigger-Half operating mode for a given timer.
6368 * @note This bitfield reports whether the compare 2 register
6369 * @note is behaving in standard mode (compare match issued as soon as counter equal compare)
6370 * @note or in triggered-half mode
6371 * @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_GetTriggeredHalfMode
6372 * @param HRTIMx High Resolution Timer instance
6373 * @param Timer This parameter can be one of the following values:
6374 * @arg @ref LL_HRTIM_TIMER_A
6375 * @arg @ref LL_HRTIM_TIMER_B
6376 * @arg @ref LL_HRTIM_TIMER_C
6377 * @arg @ref LL_HRTIM_TIMER_D
6378 * @arg @ref LL_HRTIM_TIMER_E
6379 * @arg @ref LL_HRTIM_TIMER_F
6380 * @retval Mode This parameter can be one of the following values:
6381 * @arg @ref LL_HRTIM_TRIGHALF_ENABLED
6382 * @arg @ref LL_HRTIM_TRIGHALF_DISABLED
6383 */
6384 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6385 {
6387 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6390 }
6392 /**
6393 * @brief Select the compare 1 operating mode.
6394 * @note This bit defines the compare 1 operating mode:
6395 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6396 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6397 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_SetComp1Mode
6398 * @param HRTIMx High Resolution Timer instance
6399 * @param Timer This parameter can be one of the following values:
6400 * @arg @ref LL_HRTIM_TIMER_A
6401 * @arg @ref LL_HRTIM_TIMER_B
6402 * @arg @ref LL_HRTIM_TIMER_C
6403 * @arg @ref LL_HRTIM_TIMER_D
6404 * @arg @ref LL_HRTIM_TIMER_E
6405 * @arg @ref LL_HRTIM_TIMER_F
6406 * @param Mode This parameter can be one of the following values:
6407 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6408 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6409 * @retval None
6410 */
6411 __STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6412 {
6414 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6417 }
6419 /**
6420 * @brief Get the selected compare 1 operating mode.
6421 * @note This bit reports the compare 1 operating mode:
6422 * @note 0: the compare 1 event is generated when the counter is equal to the compare value
6423 * @note 1: the compare 1 event is generated when the counter is greater than the compare value
6424 * @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_GetComp1Mode
6425 * @param HRTIMx High Resolution Timer instance
6426 * @param Timer This parameter can be one of the following values:
6427 * @arg @ref LL_HRTIM_TIMER_A
6428 * @arg @ref LL_HRTIM_TIMER_B
6429 * @arg @ref LL_HRTIM_TIMER_C
6430 * @arg @ref LL_HRTIM_TIMER_D
6431 * @arg @ref LL_HRTIM_TIMER_E
6432 * @arg @ref LL_HRTIM_TIMER_F
6433 * @retval Mode This parameter can be one of the following values:
6434 * @arg @ref LL_HRTIM_GTCMP1_EQUAL
6435 * @arg @ref LL_HRTIM_GTCMP1_GREATER
6436 */
6438 {
6440 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6443 }
6445 /**
6446 * @brief Select the compare 3 operating mode.
6447 * @note This bit defines the compare 3 operating mode:
6448 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6449 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6450 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_SetComp3Mode
6451 * @param HRTIMx High Resolution Timer instance
6452 * @param Timer This parameter can be one of the following values:
6453 * @arg @ref LL_HRTIM_TIMER_A
6454 * @arg @ref LL_HRTIM_TIMER_B
6455 * @arg @ref LL_HRTIM_TIMER_C
6456 * @arg @ref LL_HRTIM_TIMER_D
6457 * @arg @ref LL_HRTIM_TIMER_E
6458 * @arg @ref LL_HRTIM_TIMER_F
6459 * @param Mode This parameter can be one of the following values:
6460 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6461 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6462 * @retval None
6463 */
6464 __STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6465 {
6467 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6470 }
6472 /**
6473 * @brief Get the selected compare 3 operating mode.
6474 * @note This bit reports the compare 3 operating mode:
6475 * @note 0: the compare 3 event is generated when the counter is equal to the compare value
6476 * @note 1: the compare 3 event is generated when the counter is greater than the compare value
6477 * @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_GetComp1Mode
6478 * @param HRTIMx High Resolution Timer instance
6479 * @param Timer This parameter can be one of the following values:
6480 * @arg @ref LL_HRTIM_TIMER_A
6481 * @arg @ref LL_HRTIM_TIMER_B
6482 * @arg @ref LL_HRTIM_TIMER_C
6483 * @arg @ref LL_HRTIM_TIMER_D
6484 * @arg @ref LL_HRTIM_TIMER_E
6485 * @arg @ref LL_HRTIM_TIMER_F
6486 * @retval Mode This parameter can be one of the following values:
6487 * @arg @ref LL_HRTIM_GTCMP3_EQUAL
6488 * @arg @ref LL_HRTIM_GTCMP3_GREATER
6489 */
6491 {
6493 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
6496 }
6498 /**
6499 * @brief Select the roll-over mode.
6500 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6501 * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
6502 * and DMA requests, repetition counter decrement and External Event filtering.
6503 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_SetRollOverMode
6504 * @param HRTIMx High Resolution Timer instance
6505 * @param Timer This parameter can be one of the following values:
6506 * @arg @ref LL_HRTIM_TIMER_A
6507 * @arg @ref LL_HRTIM_TIMER_B
6508 * @arg @ref LL_HRTIM_TIMER_C
6509 * @arg @ref LL_HRTIM_TIMER_D
6510 * @arg @ref LL_HRTIM_TIMER_E
6511 * @arg @ref LL_HRTIM_TIMER_F
6512 * @param Mode This parameter can be one of the following values:
6513 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6514 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6515 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6516 * @retval None
6517 */
6518 __STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6519 {
6521 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6524 }
6526 /**
6527 * @brief Get selected the roll-over mode.
6528 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetRollOverMode
6529 * @param HRTIMx High Resolution Timer instance
6530 * @param Timer This parameter can be one of the following values:
6531 * @arg @ref LL_HRTIM_TIMER_A
6532 * @arg @ref LL_HRTIM_TIMER_B
6533 * @arg @ref LL_HRTIM_TIMER_C
6534 * @arg @ref LL_HRTIM_TIMER_D
6535 * @arg @ref LL_HRTIM_TIMER_E
6536 * @arg @ref LL_HRTIM_TIMER_F
6537 * @retval Mode returned value can be one of the following values:
6538 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6539 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6540 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6541 */
6543 {
6545 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6548 }
6550 /**
6551 * @brief Select Fault and Event roll-over mode.
6552 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6553 * @note only concerns the Roll-over event used by the Fault and Event counters.
6554 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_SetFaultEventRollOverMode
6555 * @param HRTIMx High Resolution Timer instance
6556 * @param Timer This parameter can be one of the following values:
6557 * @arg @ref LL_HRTIM_TIMER_A
6558 * @arg @ref LL_HRTIM_TIMER_B
6559 * @arg @ref LL_HRTIM_TIMER_C
6560 * @arg @ref LL_HRTIM_TIMER_D
6561 * @arg @ref LL_HRTIM_TIMER_E
6562 * @arg @ref LL_HRTIM_TIMER_F
6563 * @param Mode This parameter can be one of the following values:
6564 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6565 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6566 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6567 * @retval None
6568 */
6569 __STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6570 {
6572 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6575 }
6577 /**
6578 * @brief Get selected Fault and Event role-over mode.
6579 * @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_GetFaultEventRollOverMode
6580 * @param HRTIMx High Resolution Timer instance
6581 * @param Timer This parameter can be one of the following values:
6582 * @arg @ref LL_HRTIM_TIMER_A
6583 * @arg @ref LL_HRTIM_TIMER_B
6584 * @arg @ref LL_HRTIM_TIMER_C
6585 * @arg @ref LL_HRTIM_TIMER_D
6586 * @arg @ref LL_HRTIM_TIMER_E
6587 * @arg @ref LL_HRTIM_TIMER_F
6588 * @retval Mode returned value can be one of the following values:
6589 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6590 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6591 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6592 */
6593 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6594 {
6596 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6599 }
6601 /**
6602 * @brief Select the Burst mode roll-over mode.
6603 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6604 * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
6605 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetBMRollOverMode
6606 * @param HRTIMx High Resolution Timer instance
6607 * @param Timer This parameter can be one of the following values:
6608 * @arg @ref LL_HRTIM_TIMER_A
6609 * @arg @ref LL_HRTIM_TIMER_B
6610 * @arg @ref LL_HRTIM_TIMER_C
6611 * @arg @ref LL_HRTIM_TIMER_D
6612 * @arg @ref LL_HRTIM_TIMER_E
6613 * @arg @ref LL_HRTIM_TIMER_F
6614 * @param Mode This parameter can be one of the following values:
6615 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6616 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6617 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6618 * @retval None
6619 */
6620 __STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6621 {
6623 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6626 }
6628 /**
6629 * @brief Get selected Burst mode roll-over mode.
6630 * @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetBMRollOverMode
6631 * @param HRTIMx High Resolution Timer instance
6632 * @param Timer This parameter can be one of the following values:
6633 * @arg @ref LL_HRTIM_TIMER_A
6634 * @arg @ref LL_HRTIM_TIMER_B
6635 * @arg @ref LL_HRTIM_TIMER_C
6636 * @arg @ref LL_HRTIM_TIMER_D
6637 * @arg @ref LL_HRTIM_TIMER_E
6638 * @arg @ref LL_HRTIM_TIMER_F
6639 * @retval Mode returned value can be one of the following values:
6640 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6641 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6642 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6643 */
6645 {
6647 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6650 }
6652 /**
6653 * @brief Select the ADC roll-over mode.
6654 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6655 * @note Only concerns the Roll-over event used to trigger the ADC.
6656 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetADCRollOverMode
6657 * @param HRTIMx High Resolution Timer instance
6658 * @param Timer This parameter can be one of the following values:
6659 * @arg @ref LL_HRTIM_TIMER_A
6660 * @arg @ref LL_HRTIM_TIMER_B
6661 * @arg @ref LL_HRTIM_TIMER_C
6662 * @arg @ref LL_HRTIM_TIMER_D
6663 * @arg @ref LL_HRTIM_TIMER_E
6664 * @arg @ref LL_HRTIM_TIMER_F
6665 * @param Mode This parameter can be one of the following values:
6666 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6667 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6668 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6669 * @retval None
6670 */
6671 __STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6672 {
6674 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6677 }
6679 /**
6680 * @brief Get selected ADC roll-over mode.
6681 * @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_GetADCRollOverMode
6682 * @param HRTIMx High Resolution Timer instance
6683 * @param Timer This parameter can be one of the following values:
6684 * @arg @ref LL_HRTIM_TIMER_A
6685 * @arg @ref LL_HRTIM_TIMER_B
6686 * @arg @ref LL_HRTIM_TIMER_C
6687 * @arg @ref LL_HRTIM_TIMER_D
6688 * @arg @ref LL_HRTIM_TIMER_E
6689 * @arg @ref LL_HRTIM_TIMER_F
6690 * @retval Mode returned value can be one of the following values:
6691 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6692 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6693 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6694 */
6695 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6696 {
6698 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6701 }
6703 /**
6704 * @brief Select the ADC roll-over mode.
6705 * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
6706 * @note Only concerns concerns the Roll-over event which sets and/or resets the ouputs,
6707 * as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
6708 * and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
6709 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode
6710 * @param HRTIMx High Resolution Timer instance
6711 * @param Timer This parameter can be one of the following values:
6712 * @arg @ref LL_HRTIM_TIMER_A
6713 * @arg @ref LL_HRTIM_TIMER_B
6714 * @arg @ref LL_HRTIM_TIMER_C
6715 * @arg @ref LL_HRTIM_TIMER_D
6716 * @arg @ref LL_HRTIM_TIMER_E
6717 * @arg @ref LL_HRTIM_TIMER_F
6718 * @param Mode This parameter can be one of the following values:
6719 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6720 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6721 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6722 * @retval None
6723 */
6724 __STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6725 {
6727 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6730 }
6732 /**
6733 * @brief Get selected ADC roll-over mode.
6734 * @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_GetOutputRollOverMode
6735 * @param HRTIMx High Resolution Timer instance
6736 * @param Timer This parameter can be one of the following values:
6737 * @arg @ref LL_HRTIM_TIMER_A
6738 * @arg @ref LL_HRTIM_TIMER_B
6739 * @arg @ref LL_HRTIM_TIMER_C
6740 * @arg @ref LL_HRTIM_TIMER_D
6741 * @arg @ref LL_HRTIM_TIMER_E
6742 * @arg @ref LL_HRTIM_TIMER_F
6743 * @retval Mode returned value can be one of the following values:
6744 * @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
6745 * @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
6746 * @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
6747 */
6748 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6749 {
6751 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6754 }
6756 /**
6757 * @brief Select the counting mode.
6758 * @note The up-down counting mode is available for both continuous and single-shot
6759 * (retriggerable and nonretriggerable) operating modes
6760 * (see function @ref LL_HRTIM_TIM_SetCounterMode()).
6761 * @note The counter roll-over event is defined differently in-up-down counting mode to
6762 * support various operating condition.
6763 * See @ref LL_HRTIM_TIM_SetCounterMode()
6764 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_SetCountingMode
6765 * @param HRTIMx High Resolution Timer instance
6766 * @param Timer This parameter can be one of the following values:
6767 * @arg @ref LL_HRTIM_TIMER_A
6768 * @arg @ref LL_HRTIM_TIMER_B
6769 * @arg @ref LL_HRTIM_TIMER_C
6770 * @arg @ref LL_HRTIM_TIMER_D
6771 * @arg @ref LL_HRTIM_TIMER_E
6772 * @arg @ref LL_HRTIM_TIMER_F
6773 * @param Mode This parameter can be one of the following values:
6774 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6775 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6776 * @retval None
6777 */
6778 __STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6779 {
6781 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6784 }
6786 /**
6787 * @brief Get selected counting mode.
6788 * @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_GetCountingMode
6789 * @param HRTIMx High Resolution Timer instance
6790 * @param Timer This parameter can be one of the following values:
6791 * @arg @ref LL_HRTIM_TIMER_A
6792 * @arg @ref LL_HRTIM_TIMER_B
6793 * @arg @ref LL_HRTIM_TIMER_C
6794 * @arg @ref LL_HRTIM_TIMER_D
6795 * @arg @ref LL_HRTIM_TIMER_E
6796 * @arg @ref LL_HRTIM_TIMER_F
6797 * @retval Mode returned value can be one of the following values:
6798 * @arg @ref LL_HRTIM_COUNTING_MODE_UP
6799 * @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
6800 * @retval None
6801 */
6803 {
6805 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6808 }
6810 /**
6811 * @brief Select Dual Channel DAC Reset trigger.
6812 * @note Significant only when Dual channel DAC trigger is enabled
6813 * (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
6814 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_SetDualDacResetTrigger
6815 * @param HRTIMx High Resolution Timer instance
6816 * @param Timer This parameter can be one of the following values:
6817 * @arg @ref LL_HRTIM_TIMER_A
6818 * @arg @ref LL_HRTIM_TIMER_B
6819 * @arg @ref LL_HRTIM_TIMER_C
6820 * @arg @ref LL_HRTIM_TIMER_D
6821 * @arg @ref LL_HRTIM_TIMER_E
6822 * @arg @ref LL_HRTIM_TIMER_F
6823 * @param Mode This parameter can be one of the following values:
6824 * @arg @ref LL_HRTIM_DCDR_COUNTER
6825 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6826 * @retval None
6827 */
6828 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6829 {
6831 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6834 }
6836 /**
6837 * @brief Get selected Dual Channel DAC Reset trigger.
6838 * @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_GetDualDacResetTrigger
6839 * @param HRTIMx High Resolution Timer instance
6840 * @param Timer This parameter can be one of the following values:
6841 * @arg @ref LL_HRTIM_TIMER_A
6842 * @arg @ref LL_HRTIM_TIMER_B
6843 * @arg @ref LL_HRTIM_TIMER_C
6844 * @arg @ref LL_HRTIM_TIMER_D
6845 * @arg @ref LL_HRTIM_TIMER_E
6846 * @arg @ref LL_HRTIM_TIMER_F
6847 * @retval Trigger returned value can be one of the following values:
6848 * @arg @ref LL_HRTIM_DCDR_COUNTER
6849 * @arg @ref LL_HRTIM_DCDR_OUT1SET
6850 */
6851 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6852 {
6854 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6857 }
6859 /**
6860 * @brief Select Dual Channel DAC Reset trigger.
6861 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_SetDualDacStepTrigger
6862 * @param HRTIMx High Resolution Timer instance
6863 * @param Timer This parameter can be one of the following values:
6864 * @arg @ref LL_HRTIM_TIMER_A
6865 * @arg @ref LL_HRTIM_TIMER_B
6866 * @arg @ref LL_HRTIM_TIMER_C
6867 * @arg @ref LL_HRTIM_TIMER_D
6868 * @arg @ref LL_HRTIM_TIMER_E
6869 * @arg @ref LL_HRTIM_TIMER_F
6870 * @param Mode This parameter can be one of the following values:
6871 * @arg @ref LL_HRTIM_DCDS_CMP2
6872 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6873 * @retval None
6874 */
6875 __STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
6876 {
6878 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6881 }
6883 /**
6884 * @brief Get selected Dual Channel DAC Reset trigger.
6885 * @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_GetDualDacStepTrigger
6886 * @param HRTIMx High Resolution Timer instance
6887 * @param Timer This parameter can be one of the following values:
6888 * @arg @ref LL_HRTIM_TIMER_A
6889 * @arg @ref LL_HRTIM_TIMER_B
6890 * @arg @ref LL_HRTIM_TIMER_C
6891 * @arg @ref LL_HRTIM_TIMER_D
6892 * @arg @ref LL_HRTIM_TIMER_E
6893 * @arg @ref LL_HRTIM_TIMER_F
6894 * @retval Trigger returned value can be one of the following values:
6895 * @arg @ref LL_HRTIM_DCDS_CMP2
6896 * @arg @ref LL_HRTIM_DCDS_OUT1RST
6897 */
6898 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6899 {
6901 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6904 }
6906 /**
6907 * @brief Enable Dual Channel DAC trigger.
6908 * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
6909 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_EnableDualDacTrigger
6910 * @param HRTIMx High Resolution Timer instance
6911 * @param Timer This parameter can be one of the following values:
6912 * @arg @ref LL_HRTIM_TIMER_A
6913 * @arg @ref LL_HRTIM_TIMER_B
6914 * @arg @ref LL_HRTIM_TIMER_C
6915 * @arg @ref LL_HRTIM_TIMER_D
6916 * @arg @ref LL_HRTIM_TIMER_E
6917 * @arg @ref LL_HRTIM_TIMER_F
6918 * @retval None
6919 */
6921 {
6923 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6926 }
6928 /**
6929 * @brief Disable Dual Channel DAC trigger.
6930 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_DisableDualDacTrigger
6931 * @param HRTIMx High Resolution Timer instance
6932 * @param Timer This parameter can be one of the following values:
6933 * @arg @ref LL_HRTIM_TIMER_A
6934 * @arg @ref LL_HRTIM_TIMER_B
6935 * @arg @ref LL_HRTIM_TIMER_C
6936 * @arg @ref LL_HRTIM_TIMER_D
6937 * @arg @ref LL_HRTIM_TIMER_E
6938 * @arg @ref LL_HRTIM_TIMER_F
6939 * @retval None
6940 */
6942 {
6944 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6947 }
6949 /**
6950 * @brief Indicate whether Dual Channel DAC trigger is enabled for a given timer.
6951 * @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_IsEnabledDualDacTrigger
6952 * @param HRTIMx High Resolution Timer instance
6953 * @param Timer This parameter can be one of the following values:
6954 * @arg @ref LL_HRTIM_TIMER_A
6955 * @arg @ref LL_HRTIM_TIMER_B
6956 * @arg @ref LL_HRTIM_TIMER_C
6957 * @arg @ref LL_HRTIM_TIMER_D
6958 * @arg @ref LL_HRTIM_TIMER_E
6959 * @arg @ref LL_HRTIM_TIMER_F
6960 * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
6961 */
6962 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
6963 {
6965 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
6969 }
6972 /**
6973 * @brief Set the external event counter threshold.
6974 * @note The external event is propagated to the timer only if the number
6975 * of active edges is greater than the external event counter threshold.
6976 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_SetEventCounterThreshold\n
6977 * EEFxR3 EEVACNT LL_HRTIM_TIM_SetEventCounterThreshold
6978 * @param HRTIMx High Resolution Timer instance
6979 * @param Timer This parameter can be one of the following values:
6980 * @arg @ref LL_HRTIM_TIMER_A
6981 * @arg @ref LL_HRTIM_TIMER_B
6982 * @arg @ref LL_HRTIM_TIMER_C
6983 * @arg @ref LL_HRTIM_TIMER_D
6984 * @arg @ref LL_HRTIM_TIMER_E
6985 * @arg @ref LL_HRTIM_TIMER_F
6986 * @param EventCounter This parameter can be one of the following values:
6987 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
6988 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
6989 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
6990 * @retval None
6991 */
6992 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
6994 {
6996 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
6998 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
6999 }
7001 /**
7002 * @brief Get the programmed external event counter threshold.
7003 * @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_GetEventCounterThreshold\n
7004 * EEFxR3 EEVACNT LL_HRTIM_TIM_GetEventCounterThreshold
7005 * @param HRTIMx High Resolution Timer instance
7006 * @param Timer This parameter can be one of the following values:
7007 * @arg @ref LL_HRTIM_TIMER_A
7008 * @arg @ref LL_HRTIM_TIMER_B
7009 * @arg @ref LL_HRTIM_TIMER_C
7010 * @arg @ref LL_HRTIM_TIMER_D
7011 * @arg @ref LL_HRTIM_TIMER_E
7012 * @arg @ref LL_HRTIM_TIMER_F
7013 * @param EventCounter This parameter can be one of the following values:
7014 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7015 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7016 * @retval Threshold Value between Min_Data=0 and Max_Data=63
7017 */
7018 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7020 {
7022 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7024 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ;
7025 }
7027 /**
7028 * @brief Select the external event counter source.
7029 * @note External event counting is only valid for edge-sensitive
7030 * external events (See function LL_HRTIM_EE_Config() and function
7031 * LL_HRTIM_EE_SetSensitivity()).
7032 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_SetEventCounterSource\n
7033 * EEFxR3 EEVASEL LL_HRTIM_TIM_SetEventCounterSource
7034 * @param HRTIMx High Resolution Timer instance
7035 * @param Timer This parameter can be one of the following values:
7036 * @arg @ref LL_HRTIM_TIMER_A
7037 * @arg @ref LL_HRTIM_TIMER_B
7038 * @arg @ref LL_HRTIM_TIMER_C
7039 * @arg @ref LL_HRTIM_TIMER_D
7040 * @arg @ref LL_HRTIM_TIMER_E
7041 * @arg @ref LL_HRTIM_TIMER_F
7042 * @param EventCounter This parameter can be one of the following values:
7043 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7044 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7045 * @param Event This parameter can be one of the following values:
7046 * @arg @ref LL_HRTIM_EVENT_1
7047 * @arg @ref LL_HRTIM_EVENT_2
7048 * @arg @ref LL_HRTIM_EVENT_3
7049 * @arg @ref LL_HRTIM_EVENT_4
7050 * @arg @ref LL_HRTIM_EVENT_5
7051 * @arg @ref LL_HRTIM_EVENT_6
7052 * @arg @ref LL_HRTIM_EVENT_7
7053 * @arg @ref LL_HRTIM_EVENT_8
7054 * @arg @ref LL_HRTIM_EVENT_9
7055 * @arg @ref LL_HRTIM_EVENT_10
7056 * @retval None
7057 */
7058 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7060 {
7062 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7065 /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
7066 and 9 if LL_HRTIM_EVENT_10 */
7067 MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7068 }
7070 /**
7071 * @brief get the selected external event counter source.
7072 * LL_HRTIM_EE_SetSensitivity()).
7073 * @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_GetEventCounterSource\n
7074 * EEFxR3 EEVASEL LL_HRTIM_TIM_GetEventCounterSource
7075 * @param HRTIMx High Resolution Timer instance
7076 * @param Timer This parameter can be one of the following values:
7077 * @arg @ref LL_HRTIM_TIMER_A
7078 * @arg @ref LL_HRTIM_TIMER_B
7079 * @arg @ref LL_HRTIM_TIMER_C
7080 * @arg @ref LL_HRTIM_TIMER_D
7081 * @arg @ref LL_HRTIM_TIMER_E
7082 * @arg @ref LL_HRTIM_TIMER_F
7083 * @param EventCounter This parameter can be one of the following values:
7084 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7085 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7086 * @retval Event This parameter can be one of the following values:
7087 * @arg @ref LL_HRTIM_EVENT_1
7088 * @arg @ref LL_HRTIM_EVENT_2
7089 * @arg @ref LL_HRTIM_EVENT_3
7090 * @arg @ref LL_HRTIM_EVENT_4
7091 * @arg @ref LL_HRTIM_EVENT_5
7092 * @arg @ref LL_HRTIM_EVENT_6
7093 * @arg @ref LL_HRTIM_EVENT_7
7094 * @arg @ref LL_HRTIM_EVENT_8
7095 * @arg @ref LL_HRTIM_EVENT_9
7096 * @arg @ref LL_HRTIM_EVENT_10
7097 */
7098 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7100 {
7102 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7104 register uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
7106 /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
7107 and 9 if SEL is LL_HRTIM_EVENT_10 */
7109 }
7111 /**
7112 * @brief Select the external event counter reset mode.
7113 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_SetEventCounterResetMode\n
7114 * EEFxR3 EEVARSTM LL_HRTIM_TIM_SetEventCounterResetMode
7115 * @param HRTIMx High Resolution Timer instance
7116 * @param Timer This parameter can be one of the following values:
7117 * @arg @ref LL_HRTIM_TIMER_A
7118 * @arg @ref LL_HRTIM_TIMER_B
7119 * @arg @ref LL_HRTIM_TIMER_C
7120 * @arg @ref LL_HRTIM_TIMER_D
7121 * @arg @ref LL_HRTIM_TIMER_E
7122 * @arg @ref LL_HRTIM_TIMER_F
7123 * @param EventCounter This parameter can be one of the following values:
7124 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7125 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7126 * @param Mode This parameter can be one of the following values:
7127 * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL
7128 * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL
7129 * @retval None
7130 */
7131 __STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
7133 {
7135 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7138 }
7140 /**
7141 * @brief Get selected external event counter reset mode.
7142 * @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_GetEventCounterResetMode\n
7143 * EEFxR3 EEVARSTM LL_HRTIM_TIM_GetEventCounterResetMode
7144 * @param HRTIMx High Resolution Timer instance
7145 * @param Timer This parameter can be one of the following values:
7146 * @arg @ref LL_HRTIM_TIMER_A
7147 * @arg @ref LL_HRTIM_TIMER_B
7148 * @arg @ref LL_HRTIM_TIMER_C
7149 * @arg @ref LL_HRTIM_TIMER_D
7150 * @arg @ref LL_HRTIM_TIMER_E
7151 * @arg @ref LL_HRTIM_TIMER_F
7152 * @param EventCounter This parameter can be one of the following values:
7153 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7154 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7155 * @retval Mode This parameter can be one of the following values:
7156 * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_UNCONDITIONAL
7157 * @arg @ref LL_HRTIM_EVENT_COUNTERRSTMODE_CONDITIONAL
7158 */
7159 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7161 {
7163 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7165 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ;
7166 }
7168 /**
7169 * @brief Reset the external event counter.
7170 * @rmtoll EEFxR3 EEVACRES LL_HRTIM_TIM_ResetEventCounter\n
7171 * EEFxR3 EEVBCRES LL_HRTIM_TIM_ResetEventCounter
7172 * @param HRTIMx High Resolution Timer instance
7173 * @param Timer This parameter can be one of the following values:
7174 * @arg @ref LL_HRTIM_TIMER_A
7175 * @arg @ref LL_HRTIM_TIMER_B
7176 * @arg @ref LL_HRTIM_TIMER_C
7177 * @arg @ref LL_HRTIM_TIMER_D
7178 * @arg @ref LL_HRTIM_TIMER_E
7179 * @arg @ref LL_HRTIM_TIMER_F
7180 * @param EventCounter This parameter can be one of the following values:
7181 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7182 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7183 * @retval None
7184 */
7185 __STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7186 {
7188 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7191 }
7193 /**
7194 * @brief Enable the external event counter.
7195 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_EnableEventCounter\n
7196 * EEFxR3 EEVBCE LL_HRTIM_TIM_EnableEventCounter
7197 * @param HRTIMx High Resolution Timer instance
7198 * @param Timer This parameter can be one of the following values:
7199 * @arg @ref LL_HRTIM_TIMER_A
7200 * @arg @ref LL_HRTIM_TIMER_B
7201 * @arg @ref LL_HRTIM_TIMER_C
7202 * @arg @ref LL_HRTIM_TIMER_D
7203 * @arg @ref LL_HRTIM_TIMER_E
7204 * @arg @ref LL_HRTIM_TIMER_F
7205 * @param EventCounter This parameter can be one of the following values:
7206 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7207 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7208 * @retval None
7209 */
7210 __STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7211 {
7213 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7216 }
7218 /**
7219 * @brief Disable the external event counter.
7220 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_DisableEventCounter\n
7221 * EEFxR3 EEVBCE LL_HRTIM_TIM_DisableEventCounter
7222 * @param HRTIMx High Resolution Timer instance
7223 * @param Timer This parameter can be one of the following values:
7224 * @arg @ref LL_HRTIM_TIMER_A
7225 * @arg @ref LL_HRTIM_TIMER_B
7226 * @arg @ref LL_HRTIM_TIMER_C
7227 * @arg @ref LL_HRTIM_TIMER_D
7228 * @arg @ref LL_HRTIM_TIMER_E
7229 * @arg @ref LL_HRTIM_TIMER_F
7230 * @param EventCounter This parameter can be one of the following values:
7231 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7232 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7233 * @retval None
7234 */
7235 __STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
7236 {
7238 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7241 }
7244 /**
7245 * @brief Indicate whether the external event counter is enabled for a given timer.
7246 * @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_IsEnabledEventCounter\n
7247 * EEFxR3 EEVBCE LL_HRTIM_TIM_IsEnabledEventCounter
7248 * @param HRTIMx High Resolution Timer instance
7249 * @param Timer This parameter can be one of the following values:
7250 * @arg @ref LL_HRTIM_TIMER_A
7251 * @arg @ref LL_HRTIM_TIMER_B
7252 * @arg @ref LL_HRTIM_TIMER_C
7253 * @arg @ref LL_HRTIM_TIMER_D
7254 * @arg @ref LL_HRTIM_TIMER_E
7255 * @arg @ref LL_HRTIM_TIMER_F
7256 * @param EventCounter This parameter can be one of the following values:
7257 * @arg @ref LL_HRTIM_EVENT_COUNTER_A
7258 * @arg @ref LL_HRTIM_EVENT_COUNTER_B
7259 * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
7260 */
7261 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
7263 {
7265 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
7271 }
7273 /**
7274 * @}
7275 */
7277 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
7278 * @{
7279 */
7281 /**
7282 * @brief Configure the dead time insertion feature for a given timer.
7283 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
7284 * DTxR SDTF LL_HRTIM_DT_Config\n
7285 * DTxR SDRT LL_HRTIM_DT_Config
7286 * @param HRTIMx High Resolution Timer instance
7287 * @param Timer This parameter can be one of the following values:
7288 * @arg @ref LL_HRTIM_TIMER_A
7289 * @arg @ref LL_HRTIM_TIMER_B
7290 * @arg @ref LL_HRTIM_TIMER_C
7291 * @arg @ref LL_HRTIM_TIMER_D
7292 * @arg @ref LL_HRTIM_TIMER_E
7293 * @arg @ref LL_HRTIM_TIMER_F
7294 * @param Configuration This parameter must be a combination of all the following values:
7295 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
7296 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
7297 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
7298 * @retval None
7299 */
7300 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7301 {
7303 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7306 }
7308 /**
7309 * @brief Set the deadtime prescaler value.
7310 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
7311 * @param HRTIMx High Resolution Timer instance
7312 * @param Timer This parameter can be one of the following values:
7313 * @arg @ref LL_HRTIM_TIMER_A
7314 * @arg @ref LL_HRTIM_TIMER_B
7315 * @arg @ref LL_HRTIM_TIMER_C
7316 * @arg @ref LL_HRTIM_TIMER_D
7317 * @arg @ref LL_HRTIM_TIMER_E
7318 * @arg @ref LL_HRTIM_TIMER_F
7319 * @param Prescaler This parameter can be one of the following values:
7320 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7321 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7322 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7323 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7324 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7325 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7326 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7327 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7328 * @retval None
7329 */
7330 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7331 {
7333 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7336 }
7338 /**
7339 * @brief Get actual deadtime prescaler value.
7340 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
7341 * @param HRTIMx High Resolution Timer instance
7342 * @param Timer This parameter can be one of the following values:
7343 * @arg @ref LL_HRTIM_TIMER_A
7344 * @arg @ref LL_HRTIM_TIMER_B
7345 * @arg @ref LL_HRTIM_TIMER_C
7346 * @arg @ref LL_HRTIM_TIMER_D
7347 * @arg @ref LL_HRTIM_TIMER_E
7348 * @arg @ref LL_HRTIM_TIMER_F
7349 * @retval Prescaler This parameter can be one of the following values:
7350 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
7351 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
7352 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
7353 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
7354 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
7355 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
7356 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
7357 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
7358 */
7360 {
7362 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7365 }
7367 /**
7368 * @brief Set the deadtime rising value.
7369 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
7370 * @param HRTIMx High Resolution Timer instance
7371 * @param Timer This parameter can be one of the following values:
7372 * @arg @ref LL_HRTIM_TIMER_A
7373 * @arg @ref LL_HRTIM_TIMER_B
7374 * @arg @ref LL_HRTIM_TIMER_C
7375 * @arg @ref LL_HRTIM_TIMER_D
7376 * @arg @ref LL_HRTIM_TIMER_E
7377 * @arg @ref LL_HRTIM_TIMER_F
7378 * @param RisingValue Value between 0 and 0x1FF
7379 * @retval None
7380 */
7381 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
7382 {
7384 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7387 }
7389 /**
7390 * @brief Get actual deadtime rising value.
7391 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
7392 * @param HRTIMx High Resolution Timer instance
7393 * @param Timer This parameter can be one of the following values:
7394 * @arg @ref LL_HRTIM_TIMER_A
7395 * @arg @ref LL_HRTIM_TIMER_B
7396 * @arg @ref LL_HRTIM_TIMER_C
7397 * @arg @ref LL_HRTIM_TIMER_D
7398 * @arg @ref LL_HRTIM_TIMER_E
7399 * @arg @ref LL_HRTIM_TIMER_F
7400 * @retval RisingValue Value between 0 and 0x1FF
7401 */
7403 {
7405 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7408 }
7410 /**
7411 * @brief Set the deadtime sign on rising edge.
7412 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
7413 * @param HRTIMx High Resolution Timer instance
7414 * @param Timer This parameter can be one of the following values:
7415 * @arg @ref LL_HRTIM_TIMER_A
7416 * @arg @ref LL_HRTIM_TIMER_B
7417 * @arg @ref LL_HRTIM_TIMER_C
7418 * @arg @ref LL_HRTIM_TIMER_D
7419 * @arg @ref LL_HRTIM_TIMER_E
7420 * @arg @ref LL_HRTIM_TIMER_F
7421 * @param RisingSign This parameter can be one of the following values:
7422 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7423 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7424 * @retval None
7425 */
7426 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
7427 {
7429 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7432 }
7434 /**
7435 * @brief Get actual deadtime sign on rising edge.
7436 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
7437 * @param HRTIMx High Resolution Timer instance
7438 * @param Timer This parameter can be one of the following values:
7439 * @arg @ref LL_HRTIM_TIMER_A
7440 * @arg @ref LL_HRTIM_TIMER_B
7441 * @arg @ref LL_HRTIM_TIMER_C
7442 * @arg @ref LL_HRTIM_TIMER_D
7443 * @arg @ref LL_HRTIM_TIMER_E
7444 * @arg @ref LL_HRTIM_TIMER_F
7445 * @retval RisingSign This parameter can be one of the following values:
7446 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE
7447 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
7448 */
7450 {
7452 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7455 }
7457 /**
7458 * @brief Set the deadime falling value.
7459 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
7460 * @param HRTIMx High Resolution Timer instance
7461 * @param Timer This parameter can be one of the following values:
7462 * @arg @ref LL_HRTIM_TIMER_A
7463 * @arg @ref LL_HRTIM_TIMER_B
7464 * @arg @ref LL_HRTIM_TIMER_C
7465 * @arg @ref LL_HRTIM_TIMER_D
7466 * @arg @ref LL_HRTIM_TIMER_E
7467 * @arg @ref LL_HRTIM_TIMER_F
7468 * @param FallingValue Value between 0 and 0x1FF
7469 * @retval None
7470 */
7471 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
7472 {
7474 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7477 }
7479 /**
7480 * @brief Get actual deadtime falling value
7481 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
7482 * @param HRTIMx High Resolution Timer instance
7483 * @param Timer This parameter can be one of the following values:
7484 * @arg @ref LL_HRTIM_TIMER_A
7485 * @arg @ref LL_HRTIM_TIMER_B
7486 * @arg @ref LL_HRTIM_TIMER_C
7487 * @arg @ref LL_HRTIM_TIMER_D
7488 * @arg @ref LL_HRTIM_TIMER_E
7489 * @arg @ref LL_HRTIM_TIMER_F
7490 * @retval FallingValue Value between 0 and 0x1FF
7491 */
7493 {
7495 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7498 }
7500 /**
7501 * @brief Set the deadtime sign on falling edge.
7502 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
7503 * @param HRTIMx High Resolution Timer instance
7504 * @param Timer This parameter can be one of the following values:
7505 * @arg @ref LL_HRTIM_TIMER_A
7506 * @arg @ref LL_HRTIM_TIMER_B
7507 * @arg @ref LL_HRTIM_TIMER_C
7508 * @arg @ref LL_HRTIM_TIMER_D
7509 * @arg @ref LL_HRTIM_TIMER_E
7510 * @arg @ref LL_HRTIM_TIMER_F
7511 * @param FallingSign This parameter can be one of the following values:
7512 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7513 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7514 * @retval None
7515 */
7516 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
7517 {
7519 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7522 }
7524 /**
7525 * @brief Get actual deadtime sign on falling edge.
7526 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
7527 * @param HRTIMx High Resolution Timer instance
7528 * @param Timer This parameter can be one of the following values:
7529 * @arg @ref LL_HRTIM_TIMER_A
7530 * @arg @ref LL_HRTIM_TIMER_B
7531 * @arg @ref LL_HRTIM_TIMER_C
7532 * @arg @ref LL_HRTIM_TIMER_D
7533 * @arg @ref LL_HRTIM_TIMER_E
7534 * @arg @ref LL_HRTIM_TIMER_F
7535 * @retval FallingSign This parameter can be one of the following values:
7536 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
7537 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
7538 */
7540 {
7542 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7545 }
7547 /**
7548 * @brief Lock the deadtime value and sign on rising edge.
7549 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
7550 * @param HRTIMx High Resolution Timer instance
7551 * @param Timer This parameter can be one of the following values:
7552 * @arg @ref LL_HRTIM_TIMER_A
7553 * @arg @ref LL_HRTIM_TIMER_B
7554 * @arg @ref LL_HRTIM_TIMER_C
7555 * @arg @ref LL_HRTIM_TIMER_D
7556 * @arg @ref LL_HRTIM_TIMER_E
7557 * @arg @ref LL_HRTIM_TIMER_F
7558 * @retval None
7559 */
7561 {
7563 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7566 }
7568 /**
7569 * @brief Lock the deadtime sign on rising edge.
7570 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
7571 * @param HRTIMx High Resolution Timer instance
7572 * @param Timer This parameter can be one of the following values:
7573 * @arg @ref LL_HRTIM_TIMER_A
7574 * @arg @ref LL_HRTIM_TIMER_B
7575 * @arg @ref LL_HRTIM_TIMER_C
7576 * @arg @ref LL_HRTIM_TIMER_D
7577 * @arg @ref LL_HRTIM_TIMER_E
7578 * @arg @ref LL_HRTIM_TIMER_F
7579 * @retval None
7580 */
7582 {
7584 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7587 }
7589 /**
7590 * @brief Lock the deadtime value and sign on falling edge.
7591 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
7592 * @param HRTIMx High Resolution Timer instance
7593 * @param Timer This parameter can be one of the following values:
7594 * @arg @ref LL_HRTIM_TIMER_A
7595 * @arg @ref LL_HRTIM_TIMER_B
7596 * @arg @ref LL_HRTIM_TIMER_C
7597 * @arg @ref LL_HRTIM_TIMER_D
7598 * @arg @ref LL_HRTIM_TIMER_E
7599 * @arg @ref LL_HRTIM_TIMER_F
7600 * @retval None
7601 */
7603 {
7605 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7608 }
7610 /**
7611 * @brief Lock the deadtime sign on falling edge.
7612 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
7613 * @param HRTIMx High Resolution Timer instance
7614 * @param Timer This parameter can be one of the following values:
7615 * @arg @ref LL_HRTIM_TIMER_A
7616 * @arg @ref LL_HRTIM_TIMER_B
7617 * @arg @ref LL_HRTIM_TIMER_C
7618 * @arg @ref LL_HRTIM_TIMER_D
7619 * @arg @ref LL_HRTIM_TIMER_E
7620 * @arg @ref LL_HRTIM_TIMER_F
7621 * @retval None
7622 */
7624 {
7626 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
7629 }
7631 /**
7632 * @}
7633 */
7635 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
7636 * @{
7637 */
7639 /**
7640 * @brief Configure the chopper stage for a given timer.
7641 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
7642 * CHPxR CARDTY LL_HRTIM_CHP_Config\n
7643 * CHPxR STRTPW LL_HRTIM_CHP_Config
7644 * @note This function must not be called if the chopper mode is already
7645 * enabled for one of the timer outputs.
7646 * @param HRTIMx High Resolution Timer instance
7647 * @param Timer This parameter can be one of the following values:
7648 * @arg @ref LL_HRTIM_TIMER_A
7649 * @arg @ref LL_HRTIM_TIMER_B
7650 * @arg @ref LL_HRTIM_TIMER_C
7651 * @arg @ref LL_HRTIM_TIMER_D
7652 * @arg @ref LL_HRTIM_TIMER_E
7653 * @arg @ref LL_HRTIM_TIMER_F
7654 * @param Configuration This parameter must be a combination of all the following values:
7655 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
7656 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
7657 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
7658 * @retval None
7659 */
7660 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
7661 {
7663 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7666 }
7668 /**
7669 * @brief Set prescaler determining the carrier frequency to be added on top
7670 * of the timer output signals when chopper mode is enabled.
7671 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
7672 * @note This function must not be called if the chopper mode is already
7673 * enabled for one of the timer outputs.
7674 * @param HRTIMx High Resolution Timer instance
7675 * @param Timer This parameter can be one of the following values:
7676 * @arg @ref LL_HRTIM_TIMER_A
7677 * @arg @ref LL_HRTIM_TIMER_B
7678 * @arg @ref LL_HRTIM_TIMER_C
7679 * @arg @ref LL_HRTIM_TIMER_D
7680 * @arg @ref LL_HRTIM_TIMER_E
7681 * @arg @ref LL_HRTIM_TIMER_F
7682 * @param Prescaler This parameter can be one of the following values:
7683 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7684 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7685 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7686 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7687 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7688 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7689 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7690 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7691 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7692 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7693 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7694 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7695 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7696 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7697 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7698 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7699 * @retval None
7700 */
7701 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
7702 {
7704 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7707 }
7709 /**
7710 * @brief Get actual chopper stage prescaler value.
7711 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
7712 * @param HRTIMx High Resolution Timer instance
7713 * @param Timer This parameter can be one of the following values:
7714 * @arg @ref LL_HRTIM_TIMER_A
7715 * @arg @ref LL_HRTIM_TIMER_B
7716 * @arg @ref LL_HRTIM_TIMER_C
7717 * @arg @ref LL_HRTIM_TIMER_D
7718 * @arg @ref LL_HRTIM_TIMER_E
7719 * @arg @ref LL_HRTIM_TIMER_F
7720 * @retval Prescaler This parameter can be one of the following values:
7721 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
7722 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
7723 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
7724 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
7725 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
7726 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
7727 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
7728 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
7729 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
7730 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
7731 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
7732 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
7733 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
7734 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
7735 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
7736 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
7737 */
7739 {
7741 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7744 }
7746 /**
7747 * @brief Set the chopper duty cycle.
7748 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
7749 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
7750 * @note This function must not be called if the chopper mode is already
7751 * enabled for one of the timer outputs.
7752 * @param HRTIMx High Resolution Timer instance
7753 * @param Timer This parameter can be one of the following values:
7754 * @arg @ref LL_HRTIM_TIMER_A
7755 * @arg @ref LL_HRTIM_TIMER_B
7756 * @arg @ref LL_HRTIM_TIMER_C
7757 * @arg @ref LL_HRTIM_TIMER_D
7758 * @arg @ref LL_HRTIM_TIMER_E
7759 * @arg @ref LL_HRTIM_TIMER_F
7760 * @param DutyCycle This parameter can be one of the following values:
7761 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7762 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7763 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7764 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7765 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7766 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7767 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7768 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7769 * @retval None
7770 */
7771 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
7772 {
7774 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7777 }
7779 /**
7780 * @brief Get actual chopper duty cycle.
7781 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
7782 * @param HRTIMx High Resolution Timer instance
7783 * @param Timer This parameter can be one of the following values:
7784 * @arg @ref LL_HRTIM_TIMER_A
7785 * @arg @ref LL_HRTIM_TIMER_B
7786 * @arg @ref LL_HRTIM_TIMER_C
7787 * @arg @ref LL_HRTIM_TIMER_D
7788 * @arg @ref LL_HRTIM_TIMER_E
7789 * @arg @ref LL_HRTIM_TIMER_F
7790 * @retval DutyCycle This parameter can be one of the following values:
7791 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
7792 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
7793 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
7794 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
7795 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
7796 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
7797 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
7798 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
7799 */
7801 {
7803 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7806 }
7808 /**
7809 * @brief Set the start pulse width.
7810 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
7811 * @note This function must not be called if the chopper mode is already
7812 * enabled for one of the timer outputs.
7813 * @param HRTIMx High Resolution Timer instance
7814 * @param Timer This parameter can be one of the following values:
7815 * @arg @ref LL_HRTIM_TIMER_A
7816 * @arg @ref LL_HRTIM_TIMER_B
7817 * @arg @ref LL_HRTIM_TIMER_C
7818 * @arg @ref LL_HRTIM_TIMER_D
7819 * @arg @ref LL_HRTIM_TIMER_E
7820 * @arg @ref LL_HRTIM_TIMER_F
7821 * @param PulseWidth This parameter can be one of the following values:
7822 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7823 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7824 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7825 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7826 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7827 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7828 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7829 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7830 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7831 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7832 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7833 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7834 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7835 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7836 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7837 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7838 * @retval None
7839 */
7840 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
7841 {
7843 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7846 }
7848 /**
7849 * @brief Get actual start pulse width.
7850 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
7851 * @param HRTIMx High Resolution Timer instance
7852 * @param Timer This parameter can be one of the following values:
7853 * @arg @ref LL_HRTIM_TIMER_A
7854 * @arg @ref LL_HRTIM_TIMER_B
7855 * @arg @ref LL_HRTIM_TIMER_C
7856 * @arg @ref LL_HRTIM_TIMER_D
7857 * @arg @ref LL_HRTIM_TIMER_E
7858 * @arg @ref LL_HRTIM_TIMER_F
7859 * @retval PulseWidth This parameter can be one of the following values:
7860 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
7861 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
7862 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
7863 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
7864 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
7865 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
7866 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
7867 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
7868 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
7869 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
7870 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
7871 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
7872 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
7873 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
7874 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
7875 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
7876 */
7878 {
7880 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
7883 }
7885 /**
7886 * @}
7887 */
7889 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management
7890 * @{
7891 */
7893 /**
7894 * @brief Set the timer output set source.
7895 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7896 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7897 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7898 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7899 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7900 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7901 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7902 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7903 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7904 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7905 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7906 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7907 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7908 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7909 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7910 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7911 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7912 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7913 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7914 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7915 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7916 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7917 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7918 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7919 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7920 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7921 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7922 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7923 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7924 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7925 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7926 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
7927 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
7928 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
7929 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
7930 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7931 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7932 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7933 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7934 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
7935 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
7936 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
7937 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
7938 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
7939 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7940 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7941 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7942 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7943 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7944 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7945 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7946 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7947 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7948 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
7949 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
7950 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
7951 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
7952 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
7953 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
7954 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
7955 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
7956 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
7957 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
7958 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
7959 * @param HRTIMx High Resolution Timer instance
7960 * @param Output This parameter can be one of the following values:
7961 * @arg @ref LL_HRTIM_OUTPUT_TA1
7962 * @arg @ref LL_HRTIM_OUTPUT_TA2
7963 * @arg @ref LL_HRTIM_OUTPUT_TB1
7964 * @arg @ref LL_HRTIM_OUTPUT_TB2
7965 * @arg @ref LL_HRTIM_OUTPUT_TC1
7966 * @arg @ref LL_HRTIM_OUTPUT_TC2
7967 * @arg @ref LL_HRTIM_OUTPUT_TD1
7968 * @arg @ref LL_HRTIM_OUTPUT_TD2
7969 * @arg @ref LL_HRTIM_OUTPUT_TE1
7970 * @arg @ref LL_HRTIM_OUTPUT_TE2
7971 * @arg @ref LL_HRTIM_OUTPUT_TF1
7972 * @arg @ref LL_HRTIM_OUTPUT_TF2
7973 * @param SetSrc This parameter can be a combination of the following values:
7974 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
7975 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
7976 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
7977 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
7978 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
7979 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
7980 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
7981 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
7982 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
7983 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
7984 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
7985 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
7986 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
7987 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
7988 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4
7989 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
7990 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
7991 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
7992 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
7993 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
7994 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
7995 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
7996 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
7997 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3
7998 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3
7999 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4
8000 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3
8001 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4
8002 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1
8003 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2
8004 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8005 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8006 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8007 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8008 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8009 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8010 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2
8011 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3
8012 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4
8013 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8014 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8015 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8016 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8017 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1
8018 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3
8019 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4
8020 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1
8021 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4
8022 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3
8023 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4
8024 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3
8025 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4
8026 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1
8027 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2
8028 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1
8029 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2
8030 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8031 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8032 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8033 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8034 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8035 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8036 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8037 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8038 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8039 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8040 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8041 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8042 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8043 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8044 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8045 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8046 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8047 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8048 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8049 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8050 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8051 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8052 * @retval None
8053 */
8054 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
8055 {
8056 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8057 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8060 }
8062 /**
8063 * @brief Get the timer output set source.
8064 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8065 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8066 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8067 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8068 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8069 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8070 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8071 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8072 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8073 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8074 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8075 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8076 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8077 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8078 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8079 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8080 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8081 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8082 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8083 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8084 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8085 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8086 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8087 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8088 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8089 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8090 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8091 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8092 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8093 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8094 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8095 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
8096 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
8097 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
8098 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
8099 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8100 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8101 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8102 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8103 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
8104 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
8105 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
8106 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
8107 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
8108 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8109 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8110 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8111 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8112 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8113 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8114 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8115 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8116 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8117 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
8118 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
8119 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
8120 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
8121 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
8122 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
8123 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
8124 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
8125 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
8126 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
8127 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
8128 * @param HRTIMx High Resolution Timer instance
8129 * @param Output This parameter can be one of the following values:
8130 * @arg @ref LL_HRTIM_OUTPUT_TA1
8131 * @arg @ref LL_HRTIM_OUTPUT_TA2
8132 * @arg @ref LL_HRTIM_OUTPUT_TB1
8133 * @arg @ref LL_HRTIM_OUTPUT_TB2
8134 * @arg @ref LL_HRTIM_OUTPUT_TC1
8135 * @arg @ref LL_HRTIM_OUTPUT_TC2
8136 * @arg @ref LL_HRTIM_OUTPUT_TD1
8137 * @arg @ref LL_HRTIM_OUTPUT_TD2
8138 * @arg @ref LL_HRTIM_OUTPUT_TE1
8139 * @arg @ref LL_HRTIM_OUTPUT_TE2
8140 * @arg @ref LL_HRTIM_OUTPUT_TF1
8141 * @arg @ref LL_HRTIM_OUTPUT_TF2
8142 * @retval SetSrc This parameter can be a combination of the following values:
8143 * @arg @ref LL_HRTIM_OUTPUTSET_NONE
8144 * @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
8145 * @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
8146 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
8147 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
8148 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
8149 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
8150 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
8151 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
8152 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
8153 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
8154 * @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
8155 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
8156 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
8157 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMFCMP4
8158 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP2
8159 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMCCMP3
8160 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP1
8161 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMDCMP2
8162 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP3
8163 * @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMECMP4
8164 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
8165 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
8166 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMFCMP3
8167 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP3
8168 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMCCMP4
8169 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP3
8170 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMDCMP4
8171 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP1
8172 * @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMECMP2
8173 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
8174 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
8175 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
8176 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
8177 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
8178 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
8179 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMFCMP2
8180 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP3
8181 * @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMECMP4
8182 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
8183 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
8184 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
8185 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
8186 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMFCMP1
8187 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMFCMP3
8188 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMCCMP4
8189 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMECMP1
8190 * @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMECMP4
8191 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMFCMP3
8192 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMACMP4
8193 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP3
8194 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMBCMP4
8195 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP1
8196 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMCCMP2
8197 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP1
8198 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMDCMP2
8199 * @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
8200 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
8201 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
8202 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
8203 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
8204 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
8205 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
8206 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
8207 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
8208 * @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
8209 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
8210 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
8211 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
8212 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
8213 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
8214 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
8215 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
8216 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
8217 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
8218 * @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
8219 * @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
8220 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8221 */
8223 {
8224 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8225 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
8228 }
8230 /**
8231 * @brief Set the timer output reset source.
8232 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8233 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8234 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8235 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8236 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8237 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8238 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8239 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8240 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8241 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8242 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8243 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8244 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8245 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8246 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8247 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8248 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8249 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8250 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8251 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8252 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8253 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8254 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8255 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8256 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8257 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8258 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8259 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8260 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8261 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8262 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8263 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
8264 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
8265 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
8266 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
8267 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8268 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8269 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8270 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8271 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
8272 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
8273 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
8274 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
8275 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
8276 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8277 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8278 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8279 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8280 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8281 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8282 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8283 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8284 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8285 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
8286 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
8287 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
8288 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
8289 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
8290 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
8291 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
8292 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
8293 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
8294 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
8295 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
8296 * @param HRTIMx High Resolution Timer instance
8297 * @param Output This parameter can be one of the following values:
8298 * @arg @ref LL_HRTIM_OUTPUT_TA1
8299 * @arg @ref LL_HRTIM_OUTPUT_TA2
8300 * @arg @ref LL_HRTIM_OUTPUT_TB1
8301 * @arg @ref LL_HRTIM_OUTPUT_TB2
8302 * @arg @ref LL_HRTIM_OUTPUT_TC1
8303 * @arg @ref LL_HRTIM_OUTPUT_TC2
8304 * @arg @ref LL_HRTIM_OUTPUT_TD1
8305 * @arg @ref LL_HRTIM_OUTPUT_TD2
8306 * @arg @ref LL_HRTIM_OUTPUT_TE1
8307 * @arg @ref LL_HRTIM_OUTPUT_TE2
8308 * @arg @ref LL_HRTIM_OUTPUT_TF1
8309 * @arg @ref LL_HRTIM_OUTPUT_TF2
8310 * @param ResetSrc This parameter can be a combination of the following values:
8311 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8312 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8313 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8314 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8315 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8316 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8317 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8318 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8319 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8320 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8321 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8322 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8323 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8324 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8325 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4
8326 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
8327 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
8328 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
8329 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
8330 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
8331 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
8332 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8333 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8334 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3
8335 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3
8336 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4
8337 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3
8338 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4
8339 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1
8340 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2
8341 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8342 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8343 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8344 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8345 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8346 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8347 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2
8348 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3
8349 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4
8350 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8351 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8352 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8353 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8354 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1
8355 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3
8356 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4
8357 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1
8358 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4
8359 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3
8360 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4
8361 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3
8362 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4
8363 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1
8364 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2
8365 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1
8366 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2
8367 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8368 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8369 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8370 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8371 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8372 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8373 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8374 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8375 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8376 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8377 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8378 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8379 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8380 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8381 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8382 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8383 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8384 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8385 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8386 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8387 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8388 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8389 * @retval None
8390 */
8391 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
8392 {
8393 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8394 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8397 }
8399 /**
8400 * @brief Get the timer output set source.
8401 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8402 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8403 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8404 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8405 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8406 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8407 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8408 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8409 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8410 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8411 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8412 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8413 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8414 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8415 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8416 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8417 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8418 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8419 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8420 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8421 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8422 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8423 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8424 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8425 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8426 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8427 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8428 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8429 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8430 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8431 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8432 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
8433 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
8434 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
8435 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
8436 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8437 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8438 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8439 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8440 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
8441 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
8442 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
8443 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
8444 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
8445 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8446 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8447 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8448 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8449 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8450 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8451 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8452 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8453 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8454 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
8455 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
8456 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
8457 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
8458 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
8459 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
8460 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
8461 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
8462 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
8463 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
8464 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
8465 * @param HRTIMx High Resolution Timer instance
8466 * @param Output This parameter can be one of the following values:
8467 * @arg @ref LL_HRTIM_OUTPUT_TA1
8468 * @arg @ref LL_HRTIM_OUTPUT_TA2
8469 * @arg @ref LL_HRTIM_OUTPUT_TB1
8470 * @arg @ref LL_HRTIM_OUTPUT_TB2
8471 * @arg @ref LL_HRTIM_OUTPUT_TC1
8472 * @arg @ref LL_HRTIM_OUTPUT_TC2
8473 * @arg @ref LL_HRTIM_OUTPUT_TD1
8474 * @arg @ref LL_HRTIM_OUTPUT_TD2
8475 * @arg @ref LL_HRTIM_OUTPUT_TE1
8476 * @arg @ref LL_HRTIM_OUTPUT_TE2
8477 * @arg @ref LL_HRTIM_OUTPUT_TF1
8478 * @arg @ref LL_HRTIM_OUTPUT_TF2
8479 * @retval ResetSrc This parameter can be a combination of the following values:
8480 * @arg @ref LL_HRTIM_OUTPUTRESET_NONE
8481 * @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
8482 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
8483 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
8484 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
8485 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
8486 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
8487 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
8488 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
8489 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
8490 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
8491 * @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
8492 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
8493 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
8494 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMFCMP4
8495 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP2
8496 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMCCMP3
8497 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP1
8498 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMDCMP2
8499 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP3
8500 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMECMP4
8501 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
8502 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
8503 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMFCMP3
8504 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP3
8505 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMCCMP4
8506 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP3
8507 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMDCMP4
8508 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP1
8509 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMECMP2
8510 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
8511 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
8512 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
8513 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
8514 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
8515 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
8516 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMFCMP2
8517 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP3
8518 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMECMP4
8519 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
8520 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
8521 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
8522 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
8523 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMFCMP1
8524 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMFCMP3
8525 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMCCMP4
8526 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMECMP1
8527 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMECMP4
8528 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMFCMP3
8529 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMACMP4
8530 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP3
8531 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMBCMP4
8532 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP1
8533 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMCCMP2
8534 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP1
8535 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMDCMP2
8536 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
8537 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
8538 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
8539 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
8540 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
8541 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
8542 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
8543 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
8544 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
8545 * @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
8546 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
8547 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
8548 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
8549 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
8550 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
8551 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
8552 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
8553 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
8554 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
8555 * @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
8556 * @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
8557 * (source = TIMy and destination = TIMx, Compare Unit = CMPz).
8558 */
8559 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
8560 {
8561 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8562 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
8565 }
8567 /**
8568 * @brief Configure a timer output.
8569 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
8570 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
8571 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n
8572 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n
8573 * OUTxR CHP1 LL_HRTIM_OUT_Config\n
8574 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n
8575 * OUTxR POL2 LL_HRTIM_OUT_Config\n
8576 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
8577 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n
8578 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n
8579 * OUTxR CHP2 LL_HRTIM_OUT_Config\n
8580 * OUTxR DIDL2 LL_HRTIM_OUT_Config
8581 * @param HRTIMx High Resolution Timer instance
8582 * @param Output This parameter can be one of the following values:
8583 * @arg @ref LL_HRTIM_OUTPUT_TA1
8584 * @arg @ref LL_HRTIM_OUTPUT_TA2
8585 * @arg @ref LL_HRTIM_OUTPUT_TB1
8586 * @arg @ref LL_HRTIM_OUTPUT_TB2
8587 * @arg @ref LL_HRTIM_OUTPUT_TC1
8588 * @arg @ref LL_HRTIM_OUTPUT_TC2
8589 * @arg @ref LL_HRTIM_OUTPUT_TD1
8590 * @arg @ref LL_HRTIM_OUTPUT_TD2
8591 * @arg @ref LL_HRTIM_OUTPUT_TE1
8592 * @arg @ref LL_HRTIM_OUTPUT_TE2
8593 * @arg @ref LL_HRTIM_OUTPUT_TF1
8594 * @arg @ref LL_HRTIM_OUTPUT_TF2
8595 * @param Configuration This parameter must be a combination of all the following values:
8596 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8597 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8598 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8599 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8600 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8601 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8602 * @retval None
8603 */
8604 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
8605 {
8606 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8607 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8611 }
8613 /**
8614 * @brief Set the polarity of a timer output.
8615 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
8616 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity
8617 * @param HRTIMx High Resolution Timer instance
8618 * @param Output This parameter can be one of the following values:
8619 * @arg @ref LL_HRTIM_OUTPUT_TA1
8620 * @arg @ref LL_HRTIM_OUTPUT_TA2
8621 * @arg @ref LL_HRTIM_OUTPUT_TB1
8622 * @arg @ref LL_HRTIM_OUTPUT_TB2
8623 * @arg @ref LL_HRTIM_OUTPUT_TC1
8624 * @arg @ref LL_HRTIM_OUTPUT_TC2
8625 * @arg @ref LL_HRTIM_OUTPUT_TD1
8626 * @arg @ref LL_HRTIM_OUTPUT_TD2
8627 * @arg @ref LL_HRTIM_OUTPUT_TE1
8628 * @arg @ref LL_HRTIM_OUTPUT_TE2
8629 * @arg @ref LL_HRTIM_OUTPUT_TF1
8630 * @arg @ref LL_HRTIM_OUTPUT_TF2
8631 * @param Polarity This parameter can be one of the following values:
8632 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8633 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8634 * @retval None
8635 */
8636 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
8637 {
8638 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8639 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8641 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
8642 }
8644 /**
8645 * @brief Get actual polarity of the timer output.
8646 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
8647 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity
8648 * @param HRTIMx High Resolution Timer instance
8649 * @param Output This parameter can be one of the following values:
8650 * @arg @ref LL_HRTIM_OUTPUT_TA1
8651 * @arg @ref LL_HRTIM_OUTPUT_TA2
8652 * @arg @ref LL_HRTIM_OUTPUT_TB1
8653 * @arg @ref LL_HRTIM_OUTPUT_TB2
8654 * @arg @ref LL_HRTIM_OUTPUT_TC1
8655 * @arg @ref LL_HRTIM_OUTPUT_TC2
8656 * @arg @ref LL_HRTIM_OUTPUT_TD1
8657 * @arg @ref LL_HRTIM_OUTPUT_TD2
8658 * @arg @ref LL_HRTIM_OUTPUT_TE1
8659 * @arg @ref LL_HRTIM_OUTPUT_TE2
8660 * @arg @ref LL_HRTIM_OUTPUT_TF1
8661 * @arg @ref LL_HRTIM_OUTPUT_TF2
8662 * @retval Polarity This parameter can be one of the following values:
8663 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
8664 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
8665 */
8667 {
8668 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8669 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8671 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8672 }
8674 /**
8675 * @brief Set the output IDLE mode.
8676 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
8677 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
8678 * @note This function must not be called when the burst mode is active
8679 * @param HRTIMx High Resolution Timer instance
8680 * @param Output This parameter can be one of the following values:
8681 * @arg @ref LL_HRTIM_OUTPUT_TA1
8682 * @arg @ref LL_HRTIM_OUTPUT_TA2
8683 * @arg @ref LL_HRTIM_OUTPUT_TB1
8684 * @arg @ref LL_HRTIM_OUTPUT_TB2
8685 * @arg @ref LL_HRTIM_OUTPUT_TC1
8686 * @arg @ref LL_HRTIM_OUTPUT_TC2
8687 * @arg @ref LL_HRTIM_OUTPUT_TD1
8688 * @arg @ref LL_HRTIM_OUTPUT_TD2
8689 * @arg @ref LL_HRTIM_OUTPUT_TE1
8690 * @arg @ref LL_HRTIM_OUTPUT_TE2
8691 * @arg @ref LL_HRTIM_OUTPUT_TF1
8692 * @arg @ref LL_HRTIM_OUTPUT_TF2
8693 * @param IdleMode This parameter can be one of the following values:
8694 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8695 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8696 * @retval None
8697 */
8698 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
8699 {
8700 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8701 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8703 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
8704 }
8706 /**
8707 * @brief Get actual output IDLE mode.
8708 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
8709 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
8710 * @param HRTIMx High Resolution Timer instance
8711 * @param Output This parameter can be one of the following values:
8712 * @arg @ref LL_HRTIM_OUTPUT_TA1
8713 * @arg @ref LL_HRTIM_OUTPUT_TA2
8714 * @arg @ref LL_HRTIM_OUTPUT_TB1
8715 * @arg @ref LL_HRTIM_OUTPUT_TB2
8716 * @arg @ref LL_HRTIM_OUTPUT_TC1
8717 * @arg @ref LL_HRTIM_OUTPUT_TC2
8718 * @arg @ref LL_HRTIM_OUTPUT_TD1
8719 * @arg @ref LL_HRTIM_OUTPUT_TD2
8720 * @arg @ref LL_HRTIM_OUTPUT_TE1
8721 * @arg @ref LL_HRTIM_OUTPUT_TE2
8722 * @arg @ref LL_HRTIM_OUTPUT_TF1
8723 * @arg @ref LL_HRTIM_OUTPUT_TF2
8724 * @retval IdleMode This parameter can be one of the following values:
8725 * @arg @ref LL_HRTIM_OUT_NO_IDLE
8726 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
8727 */
8729 {
8730 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8731 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8733 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8734 }
8736 /**
8737 * @brief Set the output IDLE level.
8738 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
8739 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
8740 * @note This function must be called prior enabling the timer.
8741 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
8742 * @param HRTIMx High Resolution Timer instance
8743 * @param Output This parameter can be one of the following values:
8744 * @arg @ref LL_HRTIM_OUTPUT_TA1
8745 * @arg @ref LL_HRTIM_OUTPUT_TA2
8746 * @arg @ref LL_HRTIM_OUTPUT_TB1
8747 * @arg @ref LL_HRTIM_OUTPUT_TB2
8748 * @arg @ref LL_HRTIM_OUTPUT_TC1
8749 * @arg @ref LL_HRTIM_OUTPUT_TC2
8750 * @arg @ref LL_HRTIM_OUTPUT_TD1
8751 * @arg @ref LL_HRTIM_OUTPUT_TD2
8752 * @arg @ref LL_HRTIM_OUTPUT_TE1
8753 * @arg @ref LL_HRTIM_OUTPUT_TE2
8754 * @arg @ref LL_HRTIM_OUTPUT_TF1
8755 * @arg @ref LL_HRTIM_OUTPUT_TF2
8756 * @param IdleLevel This parameter can be one of the following values:
8757 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8758 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8759 * @retval None
8760 */
8761 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
8762 {
8763 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8764 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8766 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
8767 }
8769 /**
8770 * @brief Get actual output IDLE level.
8771 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
8772 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
8773 * @param HRTIMx High Resolution Timer instance
8774 * @param Output This parameter can be one of the following values:
8775 * @arg @ref LL_HRTIM_OUTPUT_TA1
8776 * @arg @ref LL_HRTIM_OUTPUT_TA2
8777 * @arg @ref LL_HRTIM_OUTPUT_TB1
8778 * @arg @ref LL_HRTIM_OUTPUT_TB2
8779 * @arg @ref LL_HRTIM_OUTPUT_TC1
8780 * @arg @ref LL_HRTIM_OUTPUT_TC2
8781 * @arg @ref LL_HRTIM_OUTPUT_TD1
8782 * @arg @ref LL_HRTIM_OUTPUT_TD2
8783 * @arg @ref LL_HRTIM_OUTPUT_TE1
8784 * @arg @ref LL_HRTIM_OUTPUT_TE2
8785 * @arg @ref LL_HRTIM_OUTPUT_TF1
8786 * @arg @ref LL_HRTIM_OUTPUT_TF2
8787 * @retval IdleLevel This parameter can be one of the following values:
8788 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
8789 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
8790 */
8792 {
8793 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8794 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8796 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8797 }
8799 /**
8800 * @brief Set the output FAULT state.
8801 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
8802 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
8803 * @note This function must not called when the timer is enabled and a fault
8804 * channel is enabled at timer level.
8805 * @param HRTIMx High Resolution Timer instance
8806 * @param Output This parameter can be one of the following values:
8807 * @arg @ref LL_HRTIM_OUTPUT_TA1
8808 * @arg @ref LL_HRTIM_OUTPUT_TA2
8809 * @arg @ref LL_HRTIM_OUTPUT_TB1
8810 * @arg @ref LL_HRTIM_OUTPUT_TB2
8811 * @arg @ref LL_HRTIM_OUTPUT_TC1
8812 * @arg @ref LL_HRTIM_OUTPUT_TC2
8813 * @arg @ref LL_HRTIM_OUTPUT_TD1
8814 * @arg @ref LL_HRTIM_OUTPUT_TD2
8815 * @arg @ref LL_HRTIM_OUTPUT_TE1
8816 * @arg @ref LL_HRTIM_OUTPUT_TE2
8817 * @arg @ref LL_HRTIM_OUTPUT_TF1
8818 * @arg @ref LL_HRTIM_OUTPUT_TF2
8819 * @param FaultState This parameter can be one of the following values:
8820 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8821 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8822 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8823 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8824 * @retval None
8825 */
8826 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
8827 {
8828 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8829 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8831 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
8832 }
8834 /**
8835 * @brief Get actual FAULT state.
8836 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
8837 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
8838 * @param HRTIMx High Resolution Timer instance
8839 * @param Output This parameter can be one of the following values:
8840 * @arg @ref LL_HRTIM_OUTPUT_TA1
8841 * @arg @ref LL_HRTIM_OUTPUT_TA2
8842 * @arg @ref LL_HRTIM_OUTPUT_TB1
8843 * @arg @ref LL_HRTIM_OUTPUT_TB2
8844 * @arg @ref LL_HRTIM_OUTPUT_TC1
8845 * @arg @ref LL_HRTIM_OUTPUT_TC2
8846 * @arg @ref LL_HRTIM_OUTPUT_TD1
8847 * @arg @ref LL_HRTIM_OUTPUT_TD2
8848 * @arg @ref LL_HRTIM_OUTPUT_TE1
8849 * @arg @ref LL_HRTIM_OUTPUT_TE2
8850 * @arg @ref LL_HRTIM_OUTPUT_TF1
8851 * @arg @ref LL_HRTIM_OUTPUT_TF2
8852 * @retval FaultState This parameter can be one of the following values:
8853 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
8854 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
8855 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
8856 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
8857 */
8859 {
8860 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8861 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8863 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8864 }
8866 /**
8867 * @brief Set the output chopper mode.
8868 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
8869 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
8870 * @note This function must not called when the timer is enabled.
8871 * @param HRTIMx High Resolution Timer instance
8872 * @param Output This parameter can be one of the following values:
8873 * @arg @ref LL_HRTIM_OUTPUT_TA1
8874 * @arg @ref LL_HRTIM_OUTPUT_TA2
8875 * @arg @ref LL_HRTIM_OUTPUT_TB1
8876 * @arg @ref LL_HRTIM_OUTPUT_TB2
8877 * @arg @ref LL_HRTIM_OUTPUT_TC1
8878 * @arg @ref LL_HRTIM_OUTPUT_TC2
8879 * @arg @ref LL_HRTIM_OUTPUT_TD1
8880 * @arg @ref LL_HRTIM_OUTPUT_TD2
8881 * @arg @ref LL_HRTIM_OUTPUT_TE1
8882 * @arg @ref LL_HRTIM_OUTPUT_TE2
8883 * @arg @ref LL_HRTIM_OUTPUT_TF1
8884 * @arg @ref LL_HRTIM_OUTPUT_TF2
8885 * @param ChopperMode This parameter can be one of the following values:
8886 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8887 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8888 * @retval None
8889 */
8890 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
8891 {
8892 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8893 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8895 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8896 }
8898 /**
8899 * @brief Get actual output chopper mode
8900 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
8901 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
8902 * @param HRTIMx High Resolution Timer instance
8903 * @param Output This parameter can be one of the following values:
8904 * @arg @ref LL_HRTIM_OUTPUT_TA1
8905 * @arg @ref LL_HRTIM_OUTPUT_TA2
8906 * @arg @ref LL_HRTIM_OUTPUT_TB1
8907 * @arg @ref LL_HRTIM_OUTPUT_TB2
8908 * @arg @ref LL_HRTIM_OUTPUT_TC1
8909 * @arg @ref LL_HRTIM_OUTPUT_TC2
8910 * @arg @ref LL_HRTIM_OUTPUT_TD1
8911 * @arg @ref LL_HRTIM_OUTPUT_TD2
8912 * @arg @ref LL_HRTIM_OUTPUT_TE1
8913 * @arg @ref LL_HRTIM_OUTPUT_TE2
8914 * @arg @ref LL_HRTIM_OUTPUT_TF1
8915 * @arg @ref LL_HRTIM_OUTPUT_TF2
8916 * @retval ChopperMode This parameter can be one of the following values:
8917 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
8918 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
8919 */
8921 {
8922 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8923 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8925 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8926 }
8928 /**
8929 * @brief Set the output burst mode entry mode.
8930 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
8931 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
8932 * @note This function must not called when the timer is enabled.
8933 * @param HRTIMx High Resolution Timer instance
8934 * @param Output This parameter can be one of the following values:
8935 * @arg @ref LL_HRTIM_OUTPUT_TA1
8936 * @arg @ref LL_HRTIM_OUTPUT_TA2
8937 * @arg @ref LL_HRTIM_OUTPUT_TB1
8938 * @arg @ref LL_HRTIM_OUTPUT_TB2
8939 * @arg @ref LL_HRTIM_OUTPUT_TC1
8940 * @arg @ref LL_HRTIM_OUTPUT_TC2
8941 * @arg @ref LL_HRTIM_OUTPUT_TD1
8942 * @arg @ref LL_HRTIM_OUTPUT_TD2
8943 * @arg @ref LL_HRTIM_OUTPUT_TE1
8944 * @arg @ref LL_HRTIM_OUTPUT_TE2
8945 * @arg @ref LL_HRTIM_OUTPUT_TF1
8946 * @arg @ref LL_HRTIM_OUTPUT_TF2
8947 * @param BMEntryMode This parameter can be one of the following values:
8948 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8949 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8950 * @retval None
8951 */
8952 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
8953 {
8954 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8955 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8957 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
8958 }
8960 /**
8961 * @brief Get actual output burst mode entry mode.
8962 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
8963 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
8964 * @param HRTIMx High Resolution Timer instance
8965 * @param Output This parameter can be one of the following values:
8966 * @arg @ref LL_HRTIM_OUTPUT_TA1
8967 * @arg @ref LL_HRTIM_OUTPUT_TA2
8968 * @arg @ref LL_HRTIM_OUTPUT_TB1
8969 * @arg @ref LL_HRTIM_OUTPUT_TB2
8970 * @arg @ref LL_HRTIM_OUTPUT_TC1
8971 * @arg @ref LL_HRTIM_OUTPUT_TC2
8972 * @arg @ref LL_HRTIM_OUTPUT_TD1
8973 * @arg @ref LL_HRTIM_OUTPUT_TD2
8974 * @arg @ref LL_HRTIM_OUTPUT_TE1
8975 * @arg @ref LL_HRTIM_OUTPUT_TE2
8976 * @arg @ref LL_HRTIM_OUTPUT_TF1
8977 * @arg @ref LL_HRTIM_OUTPUT_TF2
8978 * @retval BMEntryMode This parameter can be one of the following values:
8979 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
8980 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
8981 */
8983 {
8984 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
8985 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
8987 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
8988 }
8990 /**
8991 * @brief Get the level (active or inactive) of the designated output when the
8992 * delayed protection was triggered.
8993 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
8994 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
8995 * @param HRTIMx High Resolution Timer instance
8996 * @param Output This parameter can be one of the following values:
8997 * @arg @ref LL_HRTIM_OUTPUT_TA1
8998 * @arg @ref LL_HRTIM_OUTPUT_TA2
8999 * @arg @ref LL_HRTIM_OUTPUT_TB1
9000 * @arg @ref LL_HRTIM_OUTPUT_TB2
9001 * @arg @ref LL_HRTIM_OUTPUT_TC1
9002 * @arg @ref LL_HRTIM_OUTPUT_TC2
9003 * @arg @ref LL_HRTIM_OUTPUT_TD1
9004 * @arg @ref LL_HRTIM_OUTPUT_TD2
9005 * @arg @ref LL_HRTIM_OUTPUT_TE1
9006 * @arg @ref LL_HRTIM_OUTPUT_TE2
9007 * @arg @ref LL_HRTIM_OUTPUT_TF1
9008 * @arg @ref LL_HRTIM_OUTPUT_TF2
9009 * @retval OutputLevel This parameter can be one of the following values:
9010 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9011 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9012 */
9013 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
9014 {
9015 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9016 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9018 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9019 HRTIM_TIMISR_O1STAT_Pos);
9020 }
9022 /**
9023 * @brief Force the timer output to its active or inactive level.
9024 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
9025 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
9026 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n
9027 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel
9028 * @param HRTIMx High Resolution Timer instance
9029 * @param Output This parameter can be one of the following values:
9030 * @arg @ref LL_HRTIM_OUTPUT_TA1
9031 * @arg @ref LL_HRTIM_OUTPUT_TA2
9032 * @arg @ref LL_HRTIM_OUTPUT_TB1
9033 * @arg @ref LL_HRTIM_OUTPUT_TB2
9034 * @arg @ref LL_HRTIM_OUTPUT_TC1
9035 * @arg @ref LL_HRTIM_OUTPUT_TC2
9036 * @arg @ref LL_HRTIM_OUTPUT_TD1
9037 * @arg @ref LL_HRTIM_OUTPUT_TD2
9038 * @arg @ref LL_HRTIM_OUTPUT_TE1
9039 * @arg @ref LL_HRTIM_OUTPUT_TE2
9040 * @arg @ref LL_HRTIM_OUTPUT_TF1
9041 * @arg @ref LL_HRTIM_OUTPUT_TF2
9042 * @param OutputLevel This parameter can be one of the following values:
9043 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9044 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9045 * @retval None
9046 */
9047 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
9048 {
9050 {
9053 };
9055 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9056 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
9059 }
9061 /**
9062 * @brief Get actual output level, before the output stage (chopper, polarity).
9063 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
9064 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
9065 * @param HRTIMx High Resolution Timer instance
9066 * @param Output This parameter can be one of the following values:
9067 * @arg @ref LL_HRTIM_OUTPUT_TA1
9068 * @arg @ref LL_HRTIM_OUTPUT_TA2
9069 * @arg @ref LL_HRTIM_OUTPUT_TB1
9070 * @arg @ref LL_HRTIM_OUTPUT_TB2
9071 * @arg @ref LL_HRTIM_OUTPUT_TC1
9072 * @arg @ref LL_HRTIM_OUTPUT_TC2
9073 * @arg @ref LL_HRTIM_OUTPUT_TD1
9074 * @arg @ref LL_HRTIM_OUTPUT_TD2
9075 * @arg @ref LL_HRTIM_OUTPUT_TE1
9076 * @arg @ref LL_HRTIM_OUTPUT_TE2
9077 * @arg @ref LL_HRTIM_OUTPUT_TF1
9078 * @arg @ref LL_HRTIM_OUTPUT_TF2
9079 * @retval OutputLevel This parameter can be one of the following values:
9080 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
9081 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
9082 */
9084 {
9085 register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
9086 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
9088 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
9089 HRTIM_TIMISR_O1CPY_Pos);
9090 }
9092 /**
9093 * @}
9094 */
9096 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
9097 * @{
9098 */
9100 /**
9101 * @brief Configure external event conditioning.
9102 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
9103 * EECR1 EE1POL LL_HRTIM_EE_Config\n
9104 * EECR1 EE1SNS LL_HRTIM_EE_Config\n
9105 * EECR1 EE1FAST LL_HRTIM_EE_Config\n
9106 * EECR1 EE2SRC LL_HRTIM_EE_Config\n
9107 * EECR1 EE2POL LL_HRTIM_EE_Config\n
9108 * EECR1 EE2SNS LL_HRTIM_EE_Config\n
9109 * EECR1 EE2FAST LL_HRTIM_EE_Config\n
9110 * EECR1 EE3SRC LL_HRTIM_EE_Config\n
9111 * EECR1 EE3POL LL_HRTIM_EE_Config\n
9112 * EECR1 EE3SNS LL_HRTIM_EE_Config\n
9113 * EECR1 EE3FAST LL_HRTIM_EE_Config\n
9114 * EECR1 EE4SRC LL_HRTIM_EE_Config\n
9115 * EECR1 EE4POL LL_HRTIM_EE_Config\n
9116 * EECR1 EE4SNS LL_HRTIM_EE_Config\n
9117 * EECR1 EE4FAST LL_HRTIM_EE_Config\n
9118 * EECR1 EE5SRC LL_HRTIM_EE_Config\n
9119 * EECR1 EE5POL LL_HRTIM_EE_Config\n
9120 * EECR1 EE5SNS LL_HRTIM_EE_Config\n
9121 * EECR1 EE5FAST LL_HRTIM_EE_Config\n
9122 * EECR2 EE6SRC LL_HRTIM_EE_Config\n
9123 * EECR2 EE6POL LL_HRTIM_EE_Config\n
9124 * EECR2 EE6SNS LL_HRTIM_EE_Config\n
9125 * EECR2 EE6FAST LL_HRTIM_EE_Config\n
9126 * EECR2 EE7SRC LL_HRTIM_EE_Config\n
9127 * EECR2 EE7POL LL_HRTIM_EE_Config\n
9128 * EECR2 EE7SNS LL_HRTIM_EE_Config\n
9129 * EECR2 EE7FAST LL_HRTIM_EE_Config\n
9130 * EECR2 EE8SRC LL_HRTIM_EE_Config\n
9131 * EECR2 EE8POL LL_HRTIM_EE_Config\n
9132 * EECR2 EE8SNS LL_HRTIM_EE_Config\n
9133 * EECR2 EE8FAST LL_HRTIM_EE_Config\n
9134 * EECR2 EE9SRC LL_HRTIM_EE_Config\n
9135 * EECR2 EE9POL LL_HRTIM_EE_Config\n
9136 * EECR2 EE9SNS LL_HRTIM_EE_Config\n
9137 * EECR2 EE9FAST LL_HRTIM_EE_Config\n
9138 * EECR2 EE10SRC LL_HRTIM_EE_Config\n
9139 * EECR2 EE10POL LL_HRTIM_EE_Config\n
9140 * EECR2 EE10SNS LL_HRTIM_EE_Config\n
9141 * EECR2 EE10FAST LL_HRTIM_EE_Config
9142 * @note This function must not be called when the timer counter is enabled.
9143 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
9144 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
9145 * @param HRTIMx High Resolution Timer instance
9146 * @param Event This parameter can be one of the following values:
9147 * @arg @ref LL_HRTIM_EVENT_1
9148 * @arg @ref LL_HRTIM_EVENT_2
9149 * @arg @ref LL_HRTIM_EVENT_3
9150 * @arg @ref LL_HRTIM_EVENT_4
9151 * @arg @ref LL_HRTIM_EVENT_5
9152 * @arg @ref LL_HRTIM_EVENT_6
9153 * @arg @ref LL_HRTIM_EVENT_7
9154 * @arg @ref LL_HRTIM_EVENT_8
9155 * @arg @ref LL_HRTIM_EVENT_9
9156 * @arg @ref LL_HRTIM_EVENT_10
9157 * @param Configuration This parameter must be a combination of all the following values:
9158 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
9159 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
9160 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9161 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
9162 * @retval None
9163 */
9164 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
9165 {
9167 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9171 }
9173 /**
9174 * @brief Set the external event source.
9175 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
9176 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
9177 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
9178 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
9179 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
9180 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
9181 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
9182 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
9183 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
9184 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc
9185 * @param HRTIMx High Resolution Timer instance
9186 * @param Event This parameter can be one of the following values:
9187 * @arg @ref LL_HRTIM_EVENT_1
9188 * @arg @ref LL_HRTIM_EVENT_2
9189 * @arg @ref LL_HRTIM_EVENT_3
9190 * @arg @ref LL_HRTIM_EVENT_4
9191 * @arg @ref LL_HRTIM_EVENT_5
9192 * @arg @ref LL_HRTIM_EVENT_6
9193 * @arg @ref LL_HRTIM_EVENT_7
9194 * @arg @ref LL_HRTIM_EVENT_8
9195 * @arg @ref LL_HRTIM_EVENT_9
9196 * @arg @ref LL_HRTIM_EVENT_10
9197 * @param Src This parameter can be one of the following values:
9198 * @arg External event source 1
9199 * @arg External event source 2
9200 * @arg External event source 3
9201 * @arg External event source 4
9202 * @retval None
9203 */
9205 {
9207 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9209 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
9210 }
9212 /**
9213 * @brief Get actual external event source.
9214 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
9215 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
9216 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
9217 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
9218 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
9219 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
9220 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
9221 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
9222 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
9223 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc
9224 * @param HRTIMx High Resolution Timer instance
9225 * @param Event This parameter can be one of the following values:
9226 * @arg @ref LL_HRTIM_EVENT_1
9227 * @arg @ref LL_HRTIM_EVENT_2
9228 * @arg @ref LL_HRTIM_EVENT_3
9229 * @arg @ref LL_HRTIM_EVENT_4
9230 * @arg @ref LL_HRTIM_EVENT_5
9231 * @arg @ref LL_HRTIM_EVENT_6
9232 * @arg @ref LL_HRTIM_EVENT_7
9233 * @arg @ref LL_HRTIM_EVENT_8
9234 * @arg @ref LL_HRTIM_EVENT_9
9235 * @arg @ref LL_HRTIM_EVENT_10
9236 * @retval EventSrc This parameter can be one of the following values:
9237 * @arg External event source 1
9238 * @arg External event source 2
9239 * @arg External event source 3
9240 * @arg External event source 4
9241 */
9243 {
9245 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9247 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9248 }
9250 /**
9251 * @brief Set the polarity of an external event.
9252 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
9253 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
9254 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
9255 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
9256 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
9257 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
9258 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
9259 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
9260 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
9261 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity
9262 * @note This function must not be called when the timer counter is enabled.
9263 * @note Event polarity is only significant when event detection is level-sensitive.
9264 * @param HRTIMx High Resolution Timer instance
9265 * @param Event This parameter can be one of the following values:
9266 * @arg @ref LL_HRTIM_EVENT_1
9267 * @arg @ref LL_HRTIM_EVENT_2
9268 * @arg @ref LL_HRTIM_EVENT_3
9269 * @arg @ref LL_HRTIM_EVENT_4
9270 * @arg @ref LL_HRTIM_EVENT_5
9271 * @arg @ref LL_HRTIM_EVENT_6
9272 * @arg @ref LL_HRTIM_EVENT_7
9273 * @arg @ref LL_HRTIM_EVENT_8
9274 * @arg @ref LL_HRTIM_EVENT_9
9275 * @arg @ref LL_HRTIM_EVENT_10
9276 * @param Polarity This parameter can be one of the following values:
9277 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9278 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9279 * @retval None
9280 */
9281 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
9282 {
9284 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9286 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
9287 }
9289 /**
9290 * @brief Get actual polarity setting of an external event.
9291 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
9292 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
9293 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
9294 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
9295 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
9296 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
9297 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
9298 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
9299 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
9300 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity
9301 * @param HRTIMx High Resolution Timer instance
9302 * @param Event This parameter can be one of the following values:
9303 * @arg @ref LL_HRTIM_EVENT_1
9304 * @arg @ref LL_HRTIM_EVENT_2
9305 * @arg @ref LL_HRTIM_EVENT_3
9306 * @arg @ref LL_HRTIM_EVENT_4
9307 * @arg @ref LL_HRTIM_EVENT_5
9308 * @arg @ref LL_HRTIM_EVENT_6
9309 * @arg @ref LL_HRTIM_EVENT_7
9310 * @arg @ref LL_HRTIM_EVENT_8
9311 * @arg @ref LL_HRTIM_EVENT_9
9312 * @arg @ref LL_HRTIM_EVENT_10
9313 * @retval Polarity This parameter can be one of the following values:
9314 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH
9315 * @arg @ref LL_HRTIM_EE_POLARITY_LOW
9316 */
9318 {
9320 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9322 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9323 }
9325 /**
9326 * @brief Set the sensitivity of an external event.
9327 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
9328 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
9329 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
9330 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
9331 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
9332 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
9333 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
9334 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
9335 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
9336 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
9337 * @param HRTIMx High Resolution Timer instance
9338 * @param Event This parameter can be one of the following values:
9339 * @arg @ref LL_HRTIM_EVENT_1
9340 * @arg @ref LL_HRTIM_EVENT_2
9341 * @arg @ref LL_HRTIM_EVENT_3
9342 * @arg @ref LL_HRTIM_EVENT_4
9343 * @arg @ref LL_HRTIM_EVENT_5
9344 * @arg @ref LL_HRTIM_EVENT_6
9345 * @arg @ref LL_HRTIM_EVENT_7
9346 * @arg @ref LL_HRTIM_EVENT_8
9347 * @arg @ref LL_HRTIM_EVENT_9
9348 * @arg @ref LL_HRTIM_EVENT_10
9349 * @param Sensitivity This parameter can be one of the following values:
9350 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9351 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9352 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9353 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9354 * @retval None
9355 */
9357 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
9358 {
9360 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9362 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
9363 }
9365 /**
9366 * @brief Get actual sensitivity setting of an external event.
9367 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
9368 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
9369 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
9370 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
9371 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
9372 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
9373 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
9374 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
9375 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
9376 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
9377 * @param HRTIMx High Resolution Timer instance
9378 * @param Event This parameter can be one of the following values:
9379 * @arg @ref LL_HRTIM_EVENT_1
9380 * @arg @ref LL_HRTIM_EVENT_2
9381 * @arg @ref LL_HRTIM_EVENT_3
9382 * @arg @ref LL_HRTIM_EVENT_4
9383 * @arg @ref LL_HRTIM_EVENT_5
9384 * @arg @ref LL_HRTIM_EVENT_6
9385 * @arg @ref LL_HRTIM_EVENT_7
9386 * @arg @ref LL_HRTIM_EVENT_8
9387 * @arg @ref LL_HRTIM_EVENT_9
9388 * @arg @ref LL_HRTIM_EVENT_10
9389 * @retval Polarity This parameter can be one of the following values:
9390 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
9391 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
9392 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
9393 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
9394 */
9396 {
9398 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9400 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9401 }
9403 /**
9404 * @brief Set the fast mode of an external event.
9405 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
9406 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
9407 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
9408 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
9409 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
9410 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
9411 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
9412 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
9413 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
9414 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
9415 * @note This function must not be called when the timer counter is enabled.
9416 * @param HRTIMx High Resolution Timer instance
9417 * @param Event This parameter can be one of the following values:
9418 * @arg @ref LL_HRTIM_EVENT_1
9419 * @arg @ref LL_HRTIM_EVENT_2
9420 * @arg @ref LL_HRTIM_EVENT_3
9421 * @arg @ref LL_HRTIM_EVENT_4
9422 * @arg @ref LL_HRTIM_EVENT_5
9423 * @param FastMode This parameter can be one of the following values:
9424 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9425 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9426 * @retval None
9427 */
9428 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
9429 {
9431 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9433 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
9434 }
9436 /**
9437 * @brief Get actual fast mode setting of an external event.
9438 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
9439 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
9440 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
9441 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
9442 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
9443 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
9444 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
9445 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
9446 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
9447 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
9448 * @param HRTIMx High Resolution Timer instance
9449 * @param Event This parameter can be one of the following values:
9450 * @arg @ref LL_HRTIM_EVENT_1
9451 * @arg @ref LL_HRTIM_EVENT_2
9452 * @arg @ref LL_HRTIM_EVENT_3
9453 * @arg @ref LL_HRTIM_EVENT_4
9454 * @arg @ref LL_HRTIM_EVENT_5
9455 * @retval FastMode This parameter can be one of the following values:
9456 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
9457 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
9458 */
9460 {
9462 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
9464 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9465 }
9467 /**
9468 * @brief Set the digital noise filter of a external event.
9469 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
9470 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n
9471 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n
9472 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n
9473 * EECR3 EE10F LL_HRTIM_EE_SetFilter
9474 * @param HRTIMx High Resolution Timer instance
9475 * @param Event This parameter can be one of the following values:
9476 * @arg @ref LL_HRTIM_EVENT_6
9477 * @arg @ref LL_HRTIM_EVENT_7
9478 * @arg @ref LL_HRTIM_EVENT_8
9479 * @arg @ref LL_HRTIM_EVENT_9
9480 * @arg @ref LL_HRTIM_EVENT_10
9481 * @param Filter This parameter can be one of the following values:
9482 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9483 * @arg @ref LL_HRTIM_EE_FILTER_1
9484 * @arg @ref LL_HRTIM_EE_FILTER_2
9485 * @arg @ref LL_HRTIM_EE_FILTER_3
9486 * @arg @ref LL_HRTIM_EE_FILTER_4
9487 * @arg @ref LL_HRTIM_EE_FILTER_5
9488 * @arg @ref LL_HRTIM_EE_FILTER_6
9489 * @arg @ref LL_HRTIM_EE_FILTER_7
9490 * @arg @ref LL_HRTIM_EE_FILTER_8
9491 * @arg @ref LL_HRTIM_EE_FILTER_9
9492 * @arg @ref LL_HRTIM_EE_FILTER_10
9493 * @arg @ref LL_HRTIM_EE_FILTER_11
9494 * @arg @ref LL_HRTIM_EE_FILTER_12
9495 * @arg @ref LL_HRTIM_EE_FILTER_13
9496 * @arg @ref LL_HRTIM_EE_FILTER_14
9497 * @arg @ref LL_HRTIM_EE_FILTER_15
9498 * @retval None
9499 */
9500 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
9501 {
9505 }
9507 /**
9508 * @brief Get actual digital noise filter setting of a external event.
9509 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
9510 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n
9511 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n
9512 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n
9513 * EECR3 EE10F LL_HRTIM_EE_GetFilter
9514 * @param HRTIMx High Resolution Timer instance
9515 * @param Event This parameter can be one of the following values:
9516 * @arg @ref LL_HRTIM_EVENT_6
9517 * @arg @ref LL_HRTIM_EVENT_7
9518 * @arg @ref LL_HRTIM_EVENT_8
9519 * @arg @ref LL_HRTIM_EVENT_9
9520 * @arg @ref LL_HRTIM_EVENT_10
9521 * @retval Filter This parameter can be one of the following values:
9522 * @arg @ref LL_HRTIM_EE_FILTER_NONE
9523 * @arg @ref LL_HRTIM_EE_FILTER_1
9524 * @arg @ref LL_HRTIM_EE_FILTER_2
9525 * @arg @ref LL_HRTIM_EE_FILTER_3
9526 * @arg @ref LL_HRTIM_EE_FILTER_4
9527 * @arg @ref LL_HRTIM_EE_FILTER_5
9528 * @arg @ref LL_HRTIM_EE_FILTER_6
9529 * @arg @ref LL_HRTIM_EE_FILTER_7
9530 * @arg @ref LL_HRTIM_EE_FILTER_8
9531 * @arg @ref LL_HRTIM_EE_FILTER_9
9532 * @arg @ref LL_HRTIM_EE_FILTER_10
9533 * @arg @ref LL_HRTIM_EE_FILTER_11
9534 * @arg @ref LL_HRTIM_EE_FILTER_12
9535 * @arg @ref LL_HRTIM_EE_FILTER_13
9536 * @arg @ref LL_HRTIM_EE_FILTER_14
9537 * @arg @ref LL_HRTIM_EE_FILTER_15
9538 */
9540 {
9543 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
9544 }
9546 /**
9547 * @brief Set the external event prescaler.
9548 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
9549 * @param HRTIMx High Resolution Timer instance
9550 * @param Prescaler This parameter can be one of the following values:
9551 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9552 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9553 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9554 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9555 * @retval None
9556 */
9559 {
9561 }
9563 /**
9564 * @brief Get actual external event prescaler setting.
9565 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
9566 * @param HRTIMx High Resolution Timer instance
9567 * @retval Prescaler This parameter can be one of the following values:
9568 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
9569 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
9570 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
9571 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
9572 */
9575 {
9577 }
9579 /**
9580 * @}
9581 */
9583 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management
9584 * @{
9585 */
9586 /**
9587 * @brief Configure fault signal conditioning Polarity and Source.
9588 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
9589 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
9590 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
9591 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
9592 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
9593 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
9594 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
9595 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
9596 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
9597 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config\n
9598 * FLTINR2 FLT6P LL_HRTIM_FLT_Config\n
9599 * FLTINR2 FLT6SRC LL_HRTIM_FLT_Config
9600 * @note This function must not be called when the fault channel is enabled.
9601 * @param HRTIMx High Resolution Timer instance
9602 * @param Fault This parameter can be one of the following values:
9603 * @arg @ref LL_HRTIM_FAULT_1
9604 * @arg @ref LL_HRTIM_FAULT_2
9605 * @arg @ref LL_HRTIM_FAULT_3
9606 * @arg @ref LL_HRTIM_FAULT_4
9607 * @arg @ref LL_HRTIM_FAULT_5
9608 * @arg @ref LL_HRTIM_FAULT_6
9609 * @param Configuration This parameter must be a combination of all the following values:
9610 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
9611 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
9612 * @retval None
9613 */
9614 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
9615 {
9617 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9618 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9623 cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9624 (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9626 mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9632 }
9634 /**
9635 * @brief Set the source of a fault signal.
9636 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
9637 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
9638 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
9639 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
9640 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc\n
9641 * FLTINR2 FLT6SRC LL_HRTIM_FLT_SetSrc
9642 * @note This function must not be called when the fault channel is enabled.
9643 * @param HRTIMx High Resolution Timer instance
9644 * @param Fault This parameter can be one of the following values:
9645 * @arg @ref LL_HRTIM_FAULT_1
9646 * @arg @ref LL_HRTIM_FAULT_2
9647 * @arg @ref LL_HRTIM_FAULT_3
9648 * @arg @ref LL_HRTIM_FAULT_4
9649 * @arg @ref LL_HRTIM_FAULT_5
9650 * @arg @ref LL_HRTIM_FAULT_6
9651 * @param Src This parameter can be one of the following values:
9652 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9653 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9654 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9655 * @retval None
9656 */
9658 {
9660 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9661 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9663 uint64_t cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
9664 (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
9665 uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
9670 }
9672 /**
9673 * @brief Get actual source of a fault signal.
9674 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
9675 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
9676 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
9677 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
9678 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc\n
9679 * FLTINR2 FLT6SRC LL_HRTIM_FLT_GetSrc
9680 * @param HRTIMx High Resolution Timer instance
9681 * @param Fault This parameter can be one of the following values:
9682 * @arg @ref LL_HRTIM_FAULT_1
9683 * @arg @ref LL_HRTIM_FAULT_2
9684 * @arg @ref LL_HRTIM_FAULT_3
9685 * @arg @ref LL_HRTIM_FAULT_4
9686 * @arg @ref LL_HRTIM_FAULT_5
9687 * @arg @ref LL_HRTIM_FAULT_6
9688 * @retval Source This parameter can be one of the following values:
9689 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
9690 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
9691 * @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
9692 */
9694 {
9696 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9697 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9703 /* this for SouRCe bit 1 */
9706 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
9708 /* this for SouRCe bit 0 */
9714 }
9716 /**
9717 * @brief Set the polarity of a fault signal.
9718 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
9719 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
9720 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
9721 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
9722 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity\n
9723 * FLTINR2 FLT6P LL_HRTIM_FLT_SetPolarity
9724 * @note This function must not be called when the fault channel is enabled.
9725 * @param HRTIMx High Resolution Timer instance
9726 * @param Fault This parameter can be one of the following values:
9727 * @arg @ref LL_HRTIM_FAULT_1
9728 * @arg @ref LL_HRTIM_FAULT_2
9729 * @arg @ref LL_HRTIM_FAULT_3
9730 * @arg @ref LL_HRTIM_FAULT_4
9731 * @arg @ref LL_HRTIM_FAULT_5
9732 * @arg @ref LL_HRTIM_FAULT_6
9733 * @param Polarity This parameter can be one of the following values:
9734 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9735 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9736 * @retval None
9737 */
9738 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
9739 {
9741 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9742 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9744 uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9745 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9747 /* for Polarity bit */
9750 }
9752 /**
9753 * @brief Get actual polarity of a fault signal.
9754 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
9755 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
9756 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
9757 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
9758 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity\n
9759 * FLTINR2 FLT6P LL_HRTIM_FLT_GetPolarity
9760 * @param HRTIMx High Resolution Timer instance
9761 * @param Fault This parameter can be one of the following values:
9762 * @arg @ref LL_HRTIM_FAULT_1
9763 * @arg @ref LL_HRTIM_FAULT_2
9764 * @arg @ref LL_HRTIM_FAULT_3
9765 * @arg @ref LL_HRTIM_FAULT_4
9766 * @arg @ref LL_HRTIM_FAULT_5
9767 * @arg @ref LL_HRTIM_FAULT_6
9768 * @retval Polarity This parameter can be one of the following values:
9769 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW
9770 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
9771 */
9773 {
9775 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9776 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9781 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
9789 }
9791 /**
9792 * @brief Set the digital noise filter of a fault signal.
9793 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
9794 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
9795 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
9796 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
9797 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter\n
9798 * FLTINR2 FLT6F LL_HRTIM_FLT_SetFilter
9799 * @note This function must not be called when the fault channel is enabled.
9800 * @param HRTIMx High Resolution Timer instance
9801 * @param Fault This parameter can be one of the following values:
9802 * @arg @ref LL_HRTIM_FAULT_1
9803 * @arg @ref LL_HRTIM_FAULT_2
9804 * @arg @ref LL_HRTIM_FAULT_3
9805 * @arg @ref LL_HRTIM_FAULT_4
9806 * @arg @ref LL_HRTIM_FAULT_5
9807 * @arg @ref LL_HRTIM_FAULT_6
9808 * @param Filter This parameter can be one of the following values:
9809 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9810 * @arg @ref LL_HRTIM_FLT_FILTER_1
9811 * @arg @ref LL_HRTIM_FLT_FILTER_2
9812 * @arg @ref LL_HRTIM_FLT_FILTER_3
9813 * @arg @ref LL_HRTIM_FLT_FILTER_4
9814 * @arg @ref LL_HRTIM_FLT_FILTER_5
9815 * @arg @ref LL_HRTIM_FLT_FILTER_6
9816 * @arg @ref LL_HRTIM_FLT_FILTER_7
9817 * @arg @ref LL_HRTIM_FLT_FILTER_8
9818 * @arg @ref LL_HRTIM_FLT_FILTER_9
9819 * @arg @ref LL_HRTIM_FLT_FILTER_10
9820 * @arg @ref LL_HRTIM_FLT_FILTER_11
9821 * @arg @ref LL_HRTIM_FLT_FILTER_12
9822 * @arg @ref LL_HRTIM_FLT_FILTER_13
9823 * @arg @ref LL_HRTIM_FLT_FILTER_14
9824 * @arg @ref LL_HRTIM_FLT_FILTER_15
9825 * @retval None
9826 */
9827 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
9828 {
9830 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9831 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9833 uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */
9834 uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
9838 }
9840 /**
9841 * @brief Get actual digital noise filter setting of a fault signal.
9842 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
9843 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
9844 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
9845 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
9846 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter\n
9847 * FLTINR2 FLT6F LL_HRTIM_FLT_GetFilter
9848 * @param HRTIMx High Resolution Timer instance
9849 * @param Fault This parameter can be one of the following values:
9850 * @arg @ref LL_HRTIM_FAULT_1
9851 * @arg @ref LL_HRTIM_FAULT_2
9852 * @arg @ref LL_HRTIM_FAULT_3
9853 * @arg @ref LL_HRTIM_FAULT_4
9854 * @arg @ref LL_HRTIM_FAULT_5
9855 * @arg @ref LL_HRTIM_FAULT_6
9856 * @retval Filter This parameter can be one of the following values:
9857 * @arg @ref LL_HRTIM_FLT_FILTER_NONE
9858 * @arg @ref LL_HRTIM_FLT_FILTER_1
9859 * @arg @ref LL_HRTIM_FLT_FILTER_2
9860 * @arg @ref LL_HRTIM_FLT_FILTER_3
9861 * @arg @ref LL_HRTIM_FLT_FILTER_4
9862 * @arg @ref LL_HRTIM_FLT_FILTER_5
9863 * @arg @ref LL_HRTIM_FLT_FILTER_6
9864 * @arg @ref LL_HRTIM_FLT_FILTER_7
9865 * @arg @ref LL_HRTIM_FLT_FILTER_8
9866 * @arg @ref LL_HRTIM_FLT_FILTER_9
9867 * @arg @ref LL_HRTIM_FLT_FILTER_10
9868 * @arg @ref LL_HRTIM_FLT_FILTER_11
9869 * @arg @ref LL_HRTIM_FLT_FILTER_12
9870 * @arg @ref LL_HRTIM_FLT_FILTER_13
9871 * @arg @ref LL_HRTIM_FLT_FILTER_14
9872 * @arg @ref LL_HRTIM_FLT_FILTER_15
9873 */
9875 {
9877 register __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
9878 register __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
9882 temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
9890 }
9892 /**
9893 * @brief Set the fault circuitry prescaler.
9894 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
9895 * @param HRTIMx High Resolution Timer instance
9896 * @param Prescaler This parameter can be one of the following values:
9897 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9898 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9899 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9900 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9901 * @retval None
9902 */
9904 {
9906 }
9908 /**
9909 * @brief Get actual fault circuitry prescaler setting.
9910 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
9911 * @param HRTIMx High Resolution Timer instance
9912 * @retval Prescaler This parameter can be one of the following values:
9913 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
9914 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
9915 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
9916 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
9917 */
9919 {
9921 }
9923 /**
9924 * @brief Lock the fault signal conditioning settings.
9925 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
9926 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
9927 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
9928 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
9929 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock\n
9930 * FLTINR2 FLT6LCK LL_HRTIM_FLT_Lock
9931 * @param HRTIMx High Resolution Timer instance
9932 * @param Fault This parameter can be one of the following values:
9933 * @arg @ref LL_HRTIM_FAULT_1
9934 * @arg @ref LL_HRTIM_FAULT_2
9935 * @arg @ref LL_HRTIM_FAULT_3
9936 * @arg @ref LL_HRTIM_FAULT_4
9937 * @arg @ref LL_HRTIM_FAULT_5
9938 * @arg @ref LL_HRTIM_FAULT_6
9939 * @retval None
9940 */
9942 {
9944 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9947 }
9949 /**
9950 * @brief Enable the fault circuitry for the designated fault input.
9951 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
9952 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
9953 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
9954 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
9955 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable\n
9956 * FLTINR2 FLT6E LL_HRTIM_FLT_Enable
9957 * @param HRTIMx High Resolution Timer instance
9958 * @param Fault This parameter can be one of the following values:
9959 * @arg @ref LL_HRTIM_FAULT_1
9960 * @arg @ref LL_HRTIM_FAULT_2
9961 * @arg @ref LL_HRTIM_FAULT_3
9962 * @arg @ref LL_HRTIM_FAULT_4
9963 * @arg @ref LL_HRTIM_FAULT_5
9964 * @arg @ref LL_HRTIM_FAULT_6
9965 * @retval None
9966 */
9968 {
9970 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
9973 }
9975 /**
9976 * @brief Disable the fault circuitry for for the designated fault input.
9977 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
9978 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
9979 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
9980 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
9981 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable\n
9982 * FLTINR2 FLT6E LL_HRTIM_FLT_Disable
9983 * @param HRTIMx High Resolution Timer instance
9984 * @param Fault This parameter can be one of the following values:
9985 * @arg @ref LL_HRTIM_FAULT_1
9986 * @arg @ref LL_HRTIM_FAULT_2
9987 * @arg @ref LL_HRTIM_FAULT_3
9988 * @arg @ref LL_HRTIM_FAULT_4
9989 * @arg @ref LL_HRTIM_FAULT_5
9990 * @arg @ref LL_HRTIM_FAULT_6
9991 * @retval None
9992 */
9994 {
9996 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10000 }
10002 /**
10003 * @brief Indicate whether the fault circuitry is enabled for a given fault input.
10004 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
10005 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
10006 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
10007 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
10008 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled\n
10009 * FLTINR2 FLT6E LL_HRTIM_FLT_IsEnabled
10010 * @param HRTIMx High Resolution Timer instance
10011 * @param Fault This parameter can be one of the following values:
10012 * @arg @ref LL_HRTIM_FAULT_1
10013 * @arg @ref LL_HRTIM_FAULT_2
10014 * @arg @ref LL_HRTIM_FAULT_3
10015 * @arg @ref LL_HRTIM_FAULT_4
10016 * @arg @ref LL_HRTIM_FAULT_5
10017 * @arg @ref LL_HRTIM_FAULT_6
10018 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
10019 */
10021 {
10023 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
10025 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
10027 }
10029 /**
10030 * @brief Enable the Blanking of the fault circuitry for the designated fault input.
10031 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_EnableBlanking\n
10032 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_EnableBlanking\n
10033 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_EnableBlanking\n
10034 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_EnableBlanking\n
10035 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_EnableBlanking\n
10036 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_EnableBlanking
10037 * @param HRTIMx High Resolution Timer instance
10038 * @param Fault This parameter can be one of the following values:
10039 * @arg @ref LL_HRTIM_FAULT_1
10040 * @arg @ref LL_HRTIM_FAULT_2
10041 * @arg @ref LL_HRTIM_FAULT_3
10042 * @arg @ref LL_HRTIM_FAULT_4
10043 * @arg @ref LL_HRTIM_FAULT_5
10044 * @arg @ref LL_HRTIM_FAULT_6
10045 * @retval None
10046 */
10048 {
10050 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10053 }
10055 /**
10056 * @brief Disable the Blanking of the fault circuitry for the designated fault input.
10057 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_DisableBlanking\n
10058 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_DisableBlanking\n
10059 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_DisableBlanking\n
10060 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_DisableBlanking\n
10061 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_DisableBlanking\n
10062 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_DisableBlanking
10063 * @param HRTIMx High Resolution Timer instance
10064 * @param Fault This parameter can be one of the following values:
10065 * @arg @ref LL_HRTIM_FAULT_1
10066 * @arg @ref LL_HRTIM_FAULT_2
10067 * @arg @ref LL_HRTIM_FAULT_3
10068 * @arg @ref LL_HRTIM_FAULT_4
10069 * @arg @ref LL_HRTIM_FAULT_5
10070 * @arg @ref LL_HRTIM_FAULT_6
10071 * @retval None
10072 */
10074 {
10076 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10079 }
10081 /**
10082 * @brief Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
10083 * @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10084 * FLTINR1 FLT2BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10085 * FLTINR1 FLT3BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10086 * FLTINR1 FLT4BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10087 * FLTINR2 FLT5BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
10088 * FLTINR2 FLT6BLKE LL_HRTIM_FLT_IsEnabledBlanking
10089 * @param HRTIMx High Resolution Timer instance
10090 * @param Fault This parameter can be one of the following values:
10091 * @arg @ref LL_HRTIM_FAULT_1
10092 * @arg @ref LL_HRTIM_FAULT_2
10093 * @arg @ref LL_HRTIM_FAULT_3
10094 * @arg @ref LL_HRTIM_FAULT_4
10095 * @arg @ref LL_HRTIM_FAULT_5
10096 * @arg @ref LL_HRTIM_FAULT_6
10097 * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
10098 */
10099 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10100 {
10102 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10105 temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
10108 }
10110 /**
10111 * @brief Set the Blanking Source of the fault circuitry for a given fault input.
10112 * @note Fault inputs can be temporary disabled to blank spurious fault events.
10113 * @note This function allows for selection amongst 2 possible blanking sources.
10114 * @note Events triggering blanking window start and blanking window end depend
10115 * on both the selected blanking source and the fault input.
10116 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10117 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10118 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10119 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10120 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_SetBlankingSrc\n
10121 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_SetBlankingSrc
10122 * @param HRTIMx High Resolution Timer instance
10123 * @param Fault This parameter can be one of the following values:
10124 * @arg @ref LL_HRTIM_FAULT_1
10125 * @arg @ref LL_HRTIM_FAULT_2
10126 * @arg @ref LL_HRTIM_FAULT_3
10127 * @arg @ref LL_HRTIM_FAULT_4
10128 * @arg @ref LL_HRTIM_FAULT_5
10129 * @arg @ref LL_HRTIM_FAULT_6
10130 * @param Source parameter can be one of the following values:
10131 * @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
10132 * @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
10133 * @retval None
10134 */
10135 __STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
10136 {
10138 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10140 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
10142 }
10144 /**
10145 * @brief Get the Blanking Source of the fault circuitry is enabled for a given fault input.
10146 * @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10147 * FLTINR3 FLT2BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10148 * FLTINR3 FLT3BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10149 * FLTINR3 FLT4BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10150 * FLTINR4 FLT5BLKS LL_HRTIM_FLT_GetBlankingSrc\n
10151 * FLTINR4 FLT6BLKS LL_HRTIM_FLT_GetBlankingSrc
10152 * @param HRTIMx High Resolution Timer instance
10153 * @param Fault This parameter can be one of the following values:
10154 * @arg @ref LL_HRTIM_FAULT_1
10155 * @arg @ref LL_HRTIM_FAULT_2
10156 * @arg @ref LL_HRTIM_FAULT_3
10157 * @arg @ref LL_HRTIM_FAULT_4
10158 * @arg @ref LL_HRTIM_FAULT_5
10159 * @arg @ref LL_HRTIM_FAULT_6
10160 */
10162 {
10164 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10166 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
10167 }
10169 /**
10170 * @brief Set the Counter threshold value of a fault counter.
10171 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_SetCounterThreshold\n
10172 * FLTINR3 FLT2CNT LL_HRTIM_FLT_SetCounterThreshold\n
10173 * FLTINR3 FLT3CNT LL_HRTIM_FLT_SetCounterThreshold\n
10174 * FLTINR3 FLT4CNT LL_HRTIM_FLT_SetCounterThreshold\n
10175 * FLTINR4 FLT5CNT LL_HRTIM_FLT_SetCounterThreshold\n
10176 * FLTINR4 FLT6CNT LL_HRTIM_FLT_SetCounterThreshold
10177 * @note This function must not be called when the fault channel is enabled.
10178 * @param HRTIMx High Resolution Timer instance
10179 * @param Fault This parameter can be one of the following values:
10180 * @arg @ref LL_HRTIM_FAULT_1
10181 * @arg @ref LL_HRTIM_FAULT_2
10182 * @arg @ref LL_HRTIM_FAULT_3
10183 * @arg @ref LL_HRTIM_FAULT_4
10184 * @arg @ref LL_HRTIM_FAULT_5
10185 * @arg @ref LL_HRTIM_FAULT_6
10186 * @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10187 * @retval None
10188 */
10189 __STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
10190 {
10192 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10194 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault]));
10195 }
10197 /**
10198 * @brief Get actual the Counter threshold value of a fault counter.
10199 * @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_GetCounterThreshold\n
10200 * FLTINR3 FLT2CNT LL_HRTIM_FLT_GetCounterThreshold\n
10201 * FLTINR3 FLT3CNT LL_HRTIM_FLT_GetCounterThreshold\n
10202 * FLTINR3 FLT4CNT LL_HRTIM_FLT_GetCounterThreshold\n
10203 * FLTINR4 FLT5CNT LL_HRTIM_FLT_GetCounterThreshold\n
10204 * FLTINR4 FLT6CNT LL_HRTIM_FLT_GetCounterThreshold
10205 * @param HRTIMx High Resolution Timer instance
10206 * @param Fault This parameter can be one of the following values:
10207 * @arg @ref LL_HRTIM_FAULT_1
10208 * @arg @ref LL_HRTIM_FAULT_2
10209 * @arg @ref LL_HRTIM_FAULT_3
10210 * @arg @ref LL_HRTIM_FAULT_4
10211 * @arg @ref LL_HRTIM_FAULT_5
10212 * @arg @ref LL_HRTIM_FAULT_6
10213 * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
10214 */
10215 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
10216 {
10218 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10220 return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
10221 }
10223 /**
10224 * @brief Set the mode of reset of a fault counter to 'always reset'.
10225 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_SetResetMode\n
10226 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_SetResetMode\n
10227 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_SetResetMode\n
10228 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_SetResetMode\n
10229 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_SetResetMode\n
10230 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_SetResetMode
10231 * @param HRTIMx High Resolution Timer instance
10232 * @param Fault This parameter can be one of the following values:
10233 * @arg @ref LL_HRTIM_FAULT_1
10234 * @arg @ref LL_HRTIM_FAULT_2
10235 * @arg @ref LL_HRTIM_FAULT_3
10236 * @arg @ref LL_HRTIM_FAULT_4
10237 * @arg @ref LL_HRTIM_FAULT_5
10238 * @arg @ref LL_HRTIM_FAULT_6
10239 * @param Mode This parameter can be one of the following values:
10240 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10241 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10242 * @retval None
10243 */
10244 __STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
10245 {
10247 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10249 MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
10251 }
10253 /**
10254 * @brief Get the mode of reset of a fault counter to 'reset on event'.
10255 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_GetResetMode\n
10256 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_GetResetMode\n
10257 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_GetResetMode\n
10258 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_GetResetMode\n
10259 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_GetResetMode\n
10260 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_GetResetMode
10261 * @param HRTIMx High Resolution Timer instance
10262 * @param Fault This parameter can be one of the following values:
10263 * @arg @ref LL_HRTIM_FAULT_1
10264 * @arg @ref LL_HRTIM_FAULT_2
10265 * @arg @ref LL_HRTIM_FAULT_3
10266 * @arg @ref LL_HRTIM_FAULT_4
10267 * @arg @ref LL_HRTIM_FAULT_5
10268 * @arg @ref LL_HRTIM_FAULT_6
10269 * @retval Mode This parameter can be one of the following values:
10270 * @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
10271 * @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
10272 */
10274 {
10276 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10279 }
10281 /**
10282 * @brief Reset the fault counter for a fault circuitry
10283 * @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_ResetCounter\n
10284 * FLTINR3 FLT2RSTM LL_HRTIM_FLT_ResetCounter\n
10285 * FLTINR3 FLT3RSTM LL_HRTIM_FLT_ResetCounter\n
10286 * FLTINR3 FLT4RSTM LL_HRTIM_FLT_ResetCounter\n
10287 * FLTINR4 FLT5RSTM LL_HRTIM_FLT_ResetCounter\n
10288 * FLTINR4 FLT6RSTM LL_HRTIM_FLT_ResetCounter
10289 * @param HRTIMx High Resolution Timer instance
10290 * @param Fault This parameter can be one of the following values:
10291 * @arg @ref LL_HRTIM_FAULT_1
10292 * @arg @ref LL_HRTIM_FAULT_2
10293 * @arg @ref LL_HRTIM_FAULT_3
10294 * @arg @ref LL_HRTIM_FAULT_4
10295 * @arg @ref LL_HRTIM_FAULT_5
10296 * @arg @ref LL_HRTIM_FAULT_6
10297 * @retval None
10298 */
10300 {
10302 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
10306 }
10308 /**
10309 * @}
10310 */
10312 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
10313 * @{
10314 */
10316 /**
10317 * @brief Configure the burst mode controller.
10318 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
10319 * BMCR BMCLK LL_HRTIM_BM_Config\n
10320 * BMCR BMPRSC LL_HRTIM_BM_Config
10321 * @param HRTIMx High Resolution Timer instance
10322 * @param Configuration This parameter must be a combination of all the following values:
10323 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
10324 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10325 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
10326 * @retval None
10327 */
10329 {
10331 }
10333 /**
10334 * @brief Set the burst mode controller operating mode.
10335 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
10336 * @param HRTIMx High Resolution Timer instance
10337 * @param Mode This parameter can be one of the following values:
10338 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10339 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10340 * @retval None
10341 */
10343 {
10345 }
10347 /**
10348 * @brief Get actual burst mode controller operating mode.
10349 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
10350 * @param HRTIMx High Resolution Timer instance
10351 * @retval Mode This parameter can be one of the following values:
10352 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
10353 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
10354 */
10356 {
10358 }
10360 /**
10361 * @brief Set the burst mode controller clock source.
10362 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
10363 * @param HRTIMx High Resolution Timer instance
10364 * @param ClockSrc This parameter can be one of the following values:
10365 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10366 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10367 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10368 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10369 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10370 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10371 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10372 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10373 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10374 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10375 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10376 * @retval None
10377 */
10379 {
10381 }
10383 /**
10384 * @brief Get actual burst mode controller clock source.
10385 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
10386 * @param HRTIMx High Resolution Timer instance
10387 * @retval ClockSrc This parameter can be one of the following values:
10388 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10389 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10390 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10391 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10392 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10393 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10394 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10395 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10396 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10397 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10398 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
10399 * @retval ClockSrc This parameter can be one of the following values:
10400 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
10401 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
10402 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
10403 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
10404 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
10405 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
10406 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
10407 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
10408 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
10409 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
10410 */
10412 {
10414 }
10416 /**
10417 * @brief Set the burst mode controller prescaler.
10418 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
10419 * @param HRTIMx High Resolution Timer instance
10420 * @param Prescaler This parameter can be one of the following values:
10421 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10422 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10423 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10424 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10425 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10426 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10427 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10428 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10429 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10430 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10431 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10432 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10433 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10434 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10435 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10436 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10437 * @retval None
10438 */
10440 {
10442 }
10444 /**
10445 * @brief Get actual burst mode controller prescaler setting.
10446 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
10447 * @param HRTIMx High Resolution Timer instance
10448 * @retval Prescaler This parameter can be one of the following values:
10449 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
10450 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
10451 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
10452 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
10453 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
10454 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
10455 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
10456 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
10457 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
10458 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
10459 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
10460 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
10461 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
10462 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
10463 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
10464 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
10465 */
10467 {
10469 }
10471 /**
10472 * @brief Enable burst mode compare and period registers preload.
10473 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
10474 * @param HRTIMx High Resolution Timer instance
10475 * @retval None
10476 */
10478 {
10480 }
10482 /**
10483 * @brief Disable burst mode compare and period registers preload.
10484 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
10485 * @param HRTIMx High Resolution Timer instance
10486 * @retval None
10487 */
10489 {
10491 }
10493 /**
10494 * @brief Indicate whether burst mode compare and period registers are preloaded.
10495 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
10496 * @param HRTIMx High Resolution Timer instance
10497 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
10498 */
10500 {
10505 }
10507 /**
10508 * @brief Set the burst mode controller trigger
10509 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
10510 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
10511 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
10512 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
10513 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
10514 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
10515 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
10516 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n
10517 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
10518 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
10519 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
10520 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
10521 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
10522 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
10523 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
10524 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
10525 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
10526 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
10527 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
10528 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
10529 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
10530 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
10531 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
10532 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
10533 * BMTRGR TFREP LL_HRTIM_BM_SetTrig\n
10534 * BMTRGR TFRST LL_HRTIM_BM_SetTrig\n
10535 * BMTRGR TFCMP1 LL_HRTIM_BM_SetTrig\n
10536 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
10537 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
10538 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
10539 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
10540 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
10541 * @param HRTIMx High Resolution Timer instance
10542 * @param Trig This parameter can be a combination of the following values:
10543 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10544 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10545 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10546 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10547 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10548 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10549 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10550 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10551 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10552 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10553 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10554 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10555 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10556 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10557 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10558 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10559 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10560 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10561 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10562 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10563 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10564 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10565 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10566 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10567 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10568 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10569 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10570 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10571 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10572 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10573 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10574 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10575 * @retval None
10576 */
10578 {
10580 }
10582 /**
10583 * @brief Get actual burst mode controller trigger.
10584 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
10585 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
10586 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
10587 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
10588 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
10589 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
10590 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
10591 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n
10592 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
10593 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
10594 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
10595 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
10596 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
10597 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
10598 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
10599 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
10600 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
10601 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
10602 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
10603 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
10604 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
10605 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
10606 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
10607 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
10608 * BMTRGR TFREP LL_HRTIM_BM_GetTrig\n
10609 * BMTRGR TFRST LL_HRTIM_BM_GetTrig\n
10610 * BMTRGR TFCMP1 LL_HRTIM_BM_GetTrig\n
10611 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
10612 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
10613 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
10614 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
10615 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
10616 * @param HRTIMx High Resolution Timer instance
10617 * @retval Trig This parameter can be a combination of the following values:
10618 * @arg @ref LL_HRTIM_BM_TRIG_NONE
10619 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
10620 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
10621 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
10622 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
10623 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
10624 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
10625 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
10626 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
10627 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
10628 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
10629 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
10630 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
10631 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
10632 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
10633 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
10634 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
10635 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
10636 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
10637 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
10638 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
10639 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
10640 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
10641 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
10642 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
10643 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
10644 * @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
10645 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
10646 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
10647 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
10648 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
10649 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
10650 */
10652 {
10654 }
10656 /**
10657 * @brief Set the burst mode controller compare value.
10658 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
10659 * @param HRTIMx High Resolution Timer instance
10660 * @param CompareValue Compare value must be above or equal to 3
10661 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10662 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10663 * @retval None
10664 */
10666 {
10668 }
10670 /**
10671 * @brief Get actual burst mode controller compare value.
10672 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
10673 * @param HRTIMx High Resolution Timer instance
10674 * @retval CompareValue Compare value must be above or equal to 3
10675 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
10676 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10677 */
10679 {
10681 }
10683 /**
10684 * @brief Set the burst mode controller period.
10685 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
10686 * @param HRTIMx High Resolution Timer instance
10687 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
10688 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10689 * The maximum value is 0x0000 FFDF.
10690 * @retval None
10691 */
10693 {
10695 }
10697 /**
10698 * @brief Get actual burst mode controller period.
10699 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
10700 * @param HRTIMx High Resolution Timer instance
10701 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
10702 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
10703 * The maximum value is 0x0000 FFDF.
10704 */
10706 {
10708 }
10710 /**
10711 * @brief Enable the burst mode controller
10712 * @rmtoll BMCR BME LL_HRTIM_BM_Enable
10713 * @param HRTIMx High Resolution Timer instance
10714 * @retval None
10715 */
10717 {
10719 }
10721 /**
10722 * @brief Disable the burst mode controller
10723 * @rmtoll BMCR BME LL_HRTIM_BM_Disable
10724 * @param HRTIMx High Resolution Timer instance
10725 * @retval None
10726 */
10728 {
10730 }
10732 /**
10733 * @brief Indicate whether the burst mode controller is enabled.
10734 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
10735 * @param HRTIMx High Resolution Timer instance
10736 * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
10737 */
10739 {
10740 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
10741 }
10743 /**
10744 * @brief Trigger the burst operation (software trigger)
10745 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start
10746 * @param HRTIMx High Resolution Timer instance
10747 * @retval None
10748 */
10750 {
10752 }
10754 /**
10755 * @brief Stop the burst mode operation.
10756 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
10757 * @note Causes a burst mode early termination.
10758 * @param HRTIMx High Resolution Timer instance
10759 * @retval None
10760 */
10762 {
10764 }
10766 /**
10767 * @brief Get actual burst mode status
10768 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
10769 * @param HRTIMx High Resolution Timer instance
10770 * @retval Status This parameter can be one of the following values:
10771 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL
10772 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
10773 */
10775 {
10777 }
10779 /**
10780 * @}
10781 */
10783 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
10784 * @{
10785 */
10787 /**
10788 * @brief Clear the Fault 1 interrupt flag.
10789 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
10790 * @param HRTIMx High Resolution Timer instance
10791 * @retval None
10792 */
10794 {
10796 }
10798 /**
10799 * @brief Indicate whether Fault 1 interrupt occurred.
10800 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
10801 * @param HRTIMx High Resolution Timer instance
10802 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
10803 */
10805 {
10807 }
10809 /**
10810 * @brief Clear the Fault 2 interrupt flag.
10811 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
10812 * @param HRTIMx High Resolution Timer instance
10813 * @retval None
10814 */
10816 {
10818 }
10820 /**
10821 * @brief Indicate whether Fault 2 interrupt occurred.
10822 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
10823 * @param HRTIMx High Resolution Timer instance
10824 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
10825 */
10827 {
10829 }
10831 /**
10832 * @brief Clear the Fault 3 interrupt flag.
10833 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
10834 * @param HRTIMx High Resolution Timer instance
10835 * @retval None
10836 */
10838 {
10840 }
10842 /**
10843 * @brief Indicate whether Fault 3 interrupt occurred.
10844 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
10845 * @param HRTIMx High Resolution Timer instance
10846 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
10847 */
10849 {
10851 }
10853 /**
10854 * @brief Clear the Fault 4 interrupt flag.
10855 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
10856 * @param HRTIMx High Resolution Timer instance
10857 * @retval None
10858 */
10860 {
10862 }
10864 /**
10865 * @brief Indicate whether Fault 4 interrupt occurred.
10866 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
10867 * @param HRTIMx High Resolution Timer instance
10868 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
10869 */
10871 {
10873 }
10875 /**
10876 * @brief Clear the Fault 5 interrupt flag.
10877 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
10878 * @param HRTIMx High Resolution Timer instance
10879 * @retval None
10880 */
10882 {
10884 }
10886 /**
10887 * @brief Indicate whether Fault 5 interrupt occurred.
10888 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
10889 * @param HRTIMx High Resolution Timer instance
10890 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
10891 */
10893 {
10895 }
10897 /**
10898 * @brief Clear the Fault 6 interrupt flag.
10899 * @rmtoll ICR FLT6C LL_HRTIM_ClearFlag_FLT6
10900 * @param HRTIMx High Resolution Timer instance
10901 * @retval None
10902 */
10904 {
10906 }
10908 /**
10909 * @brief Indicate whether Fault 6 interrupt occurred.
10910 * @rmtoll ICR FLT6 LL_HRTIM_IsActiveFlag_FLT6
10911 * @param HRTIMx High Resolution Timer instance
10912 * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
10913 */
10915 {
10917 }
10919 /**
10920 * @brief Clear the System Fault interrupt flag.
10921 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
10922 * @param HRTIMx High Resolution Timer instance
10923 * @retval None
10924 */
10926 {
10928 }
10930 /**
10931 * @brief Indicate whether System Fault interrupt occurred.
10932 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
10933 * @param HRTIMx High Resolution Timer instance
10934 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
10935 */
10937 {
10938 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
10939 }
10941 /**
10942 * @brief Clear the DLL ready interrupt flag.
10943 * @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
10944 * @param HRTIMx High Resolution Timer instance
10945 * @retval None
10946 */
10948 {
10950 }
10952 /**
10953 * @brief Indicate whether DLL ready interrupt occurred.
10954 * @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
10955 * @param HRTIMx High Resolution Timer instance
10956 * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
10957 */
10959 {
10960 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
10961 }
10963 /**
10964 * @brief Clear the Burst Mode period interrupt flag.
10965 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
10966 * @param HRTIMx High Resolution Timer instance
10967 * @retval None
10968 */
10970 {
10972 }
10974 /**
10975 * @brief Indicate whether Burst Mode period interrupt occurred.
10976 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
10977 * @param HRTIMx High Resolution Timer instance
10978 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
10979 */
10981 {
10982 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
10983 }
10985 /**
10986 * @brief Clear the Synchronization Input interrupt flag.
10987 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
10988 * @param HRTIMx High Resolution Timer instance
10989 * @retval None
10990 */
10992 {
10994 }
10996 /**
10997 * @brief Indicate whether the Synchronization Input interrupt occurred.
10998 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
10999 * @param HRTIMx High Resolution Timer instance
11000 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
11001 */
11003 {
11004 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
11005 }
11007 /**
11008 * @brief Clear the update interrupt flag for a given timer (including the master timer) .
11009 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
11010 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
11011 * @param HRTIMx High Resolution Timer instance
11012 * @param Timer This parameter can be one of the following values:
11013 * @arg @ref LL_HRTIM_TIMER_MASTER
11014 * @arg @ref LL_HRTIM_TIMER_A
11015 * @arg @ref LL_HRTIM_TIMER_B
11016 * @arg @ref LL_HRTIM_TIMER_C
11017 * @arg @ref LL_HRTIM_TIMER_D
11018 * @arg @ref LL_HRTIM_TIMER_E
11019 * @arg @ref LL_HRTIM_TIMER_F
11020 * @retval None
11021 */
11023 {
11025 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11028 }
11030 /**
11031 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
11032 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
11033 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
11034 * @param HRTIMx High Resolution Timer instance
11035 * @param Timer This parameter can be one of the following values:
11036 * @arg @ref LL_HRTIM_TIMER_MASTER
11037 * @arg @ref LL_HRTIM_TIMER_A
11038 * @arg @ref LL_HRTIM_TIMER_B
11039 * @arg @ref LL_HRTIM_TIMER_C
11040 * @arg @ref LL_HRTIM_TIMER_D
11041 * @arg @ref LL_HRTIM_TIMER_E
11042 * @arg @ref LL_HRTIM_TIMER_F
11043 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11044 */
11046 {
11048 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11052 }
11054 /**
11055 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
11056 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
11057 * TIMxICR REPC LL_HRTIM_ClearFlag_REP
11058 * @param HRTIMx High Resolution Timer instance
11059 * @param Timer This parameter can be one of the following values:
11060 * @arg @ref LL_HRTIM_TIMER_MASTER
11061 * @arg @ref LL_HRTIM_TIMER_A
11062 * @arg @ref LL_HRTIM_TIMER_B
11063 * @arg @ref LL_HRTIM_TIMER_C
11064 * @arg @ref LL_HRTIM_TIMER_D
11065 * @arg @ref LL_HRTIM_TIMER_E
11066 * @arg @ref LL_HRTIM_TIMER_F
11067 * @retval None
11068 */
11070 {
11072 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11076 }
11078 /**
11079 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
11080 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
11081 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP
11082 * @param HRTIMx High Resolution Timer instance
11083 * @param Timer This parameter can be one of the following values:
11084 * @arg @ref LL_HRTIM_TIMER_MASTER
11085 * @arg @ref LL_HRTIM_TIMER_A
11086 * @arg @ref LL_HRTIM_TIMER_B
11087 * @arg @ref LL_HRTIM_TIMER_C
11088 * @arg @ref LL_HRTIM_TIMER_D
11089 * @arg @ref LL_HRTIM_TIMER_E
11090 * @arg @ref LL_HRTIM_TIMER_F
11091 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11092 */
11094 {
11096 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11100 }
11102 /**
11103 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
11104 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
11105 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
11106 * @param HRTIMx High Resolution Timer instance
11107 * @param Timer This parameter can be one of the following values:
11108 * @arg @ref LL_HRTIM_TIMER_MASTER
11109 * @arg @ref LL_HRTIM_TIMER_A
11110 * @arg @ref LL_HRTIM_TIMER_B
11111 * @arg @ref LL_HRTIM_TIMER_C
11112 * @arg @ref LL_HRTIM_TIMER_D
11113 * @arg @ref LL_HRTIM_TIMER_E
11114 * @arg @ref LL_HRTIM_TIMER_F
11115 * @retval None
11116 */
11118 {
11120 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11123 }
11125 /**
11126 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
11127 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
11128 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
11129 * @param HRTIMx High Resolution Timer instance
11130 * @param Timer This parameter can be one of the following values:
11131 * @arg @ref LL_HRTIM_TIMER_MASTER
11132 * @arg @ref LL_HRTIM_TIMER_A
11133 * @arg @ref LL_HRTIM_TIMER_B
11134 * @arg @ref LL_HRTIM_TIMER_C
11135 * @arg @ref LL_HRTIM_TIMER_D
11136 * @arg @ref LL_HRTIM_TIMER_E
11137 * @arg @ref LL_HRTIM_TIMER_F
11138 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11139 */
11141 {
11143 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11147 }
11149 /**
11150 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
11151 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
11152 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
11153 * @param HRTIMx High Resolution Timer instance
11154 * @param Timer This parameter can be one of the following values:
11155 * @arg @ref LL_HRTIM_TIMER_MASTER
11156 * @arg @ref LL_HRTIM_TIMER_A
11157 * @arg @ref LL_HRTIM_TIMER_B
11158 * @arg @ref LL_HRTIM_TIMER_C
11159 * @arg @ref LL_HRTIM_TIMER_D
11160 * @arg @ref LL_HRTIM_TIMER_E
11161 * @arg @ref LL_HRTIM_TIMER_F
11162 * @retval None
11163 */
11165 {
11167 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11170 }
11172 /**
11173 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
11174 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
11175 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
11176 * @param HRTIMx High Resolution Timer instance
11177 * @param Timer This parameter can be one of the following values:
11178 * @arg @ref LL_HRTIM_TIMER_MASTER
11179 * @arg @ref LL_HRTIM_TIMER_A
11180 * @arg @ref LL_HRTIM_TIMER_B
11181 * @arg @ref LL_HRTIM_TIMER_C
11182 * @arg @ref LL_HRTIM_TIMER_D
11183 * @arg @ref LL_HRTIM_TIMER_E
11184 * @arg @ref LL_HRTIM_TIMER_F
11185 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11186 */
11188 {
11190 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11194 }
11196 /**
11197 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
11198 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
11199 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
11200 * @param HRTIMx High Resolution Timer instance
11201 * @param Timer This parameter can be one of the following values:
11202 * @arg @ref LL_HRTIM_TIMER_MASTER
11203 * @arg @ref LL_HRTIM_TIMER_A
11204 * @arg @ref LL_HRTIM_TIMER_B
11205 * @arg @ref LL_HRTIM_TIMER_C
11206 * @arg @ref LL_HRTIM_TIMER_D
11207 * @arg @ref LL_HRTIM_TIMER_E
11208 * @arg @ref LL_HRTIM_TIMER_F
11209 * @retval None
11210 */
11212 {
11214 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11217 }
11219 /**
11220 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
11221 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
11222 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
11223 * @param HRTIMx High Resolution Timer instance
11224 * @param Timer This parameter can be one of the following values:
11225 * @arg @ref LL_HRTIM_TIMER_MASTER
11226 * @arg @ref LL_HRTIM_TIMER_A
11227 * @arg @ref LL_HRTIM_TIMER_B
11228 * @arg @ref LL_HRTIM_TIMER_C
11229 * @arg @ref LL_HRTIM_TIMER_D
11230 * @arg @ref LL_HRTIM_TIMER_E
11231 * @arg @ref LL_HRTIM_TIMER_F
11232 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11233 */
11235 {
11237 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11241 }
11243 /**
11244 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
11245 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
11246 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
11247 * @param HRTIMx High Resolution Timer instance
11248 * @param Timer This parameter can be one of the following values:
11249 * @arg @ref LL_HRTIM_TIMER_MASTER
11250 * @arg @ref LL_HRTIM_TIMER_A
11251 * @arg @ref LL_HRTIM_TIMER_B
11252 * @arg @ref LL_HRTIM_TIMER_C
11253 * @arg @ref LL_HRTIM_TIMER_D
11254 * @arg @ref LL_HRTIM_TIMER_E
11255 * @arg @ref LL_HRTIM_TIMER_F
11256 * @retval None
11257 */
11259 {
11261 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11264 }
11266 /**
11267 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
11268 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
11269 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
11270 * @param HRTIMx High Resolution Timer instance
11271 * @param Timer This parameter can be one of the following values:
11272 * @arg @ref LL_HRTIM_TIMER_MASTER
11273 * @arg @ref LL_HRTIM_TIMER_A
11274 * @arg @ref LL_HRTIM_TIMER_B
11275 * @arg @ref LL_HRTIM_TIMER_C
11276 * @arg @ref LL_HRTIM_TIMER_D
11277 * @arg @ref LL_HRTIM_TIMER_E
11278 * @arg @ref LL_HRTIM_TIMER_F
11279 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
11280 */
11282 {
11284 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11288 }
11290 /**
11291 * @brief Clear the capture 1 interrupt flag for a given timer.
11292 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
11293 * @param HRTIMx High Resolution Timer instance
11294 * @param Timer This parameter can be one of the following values:
11295 * @arg @ref LL_HRTIM_TIMER_A
11296 * @arg @ref LL_HRTIM_TIMER_B
11297 * @arg @ref LL_HRTIM_TIMER_C
11298 * @arg @ref LL_HRTIM_TIMER_D
11299 * @arg @ref LL_HRTIM_TIMER_E
11300 * @arg @ref LL_HRTIM_TIMER_F
11301 * @retval None
11302 */
11304 {
11306 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11309 }
11311 /**
11312 * @brief Indicate whether the capture 1 interrupt occurred for a given timer.
11313 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
11314 * @param HRTIMx High Resolution Timer instance
11315 * @param Timer This parameter can be one of the following values:
11316 * @arg @ref LL_HRTIM_TIMER_A
11317 * @arg @ref LL_HRTIM_TIMER_B
11318 * @arg @ref LL_HRTIM_TIMER_C
11319 * @arg @ref LL_HRTIM_TIMER_D
11320 * @arg @ref LL_HRTIM_TIMER_E
11321 * @arg @ref LL_HRTIM_TIMER_F
11322 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
11323 */
11325 {
11327 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11331 }
11333 /**
11334 * @brief Clear the capture 2 interrupt flag for a given timer.
11335 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
11336 * @param HRTIMx High Resolution Timer instance
11337 * @param Timer This parameter can be one of the following values:
11338 * @arg @ref LL_HRTIM_TIMER_A
11339 * @arg @ref LL_HRTIM_TIMER_B
11340 * @arg @ref LL_HRTIM_TIMER_C
11341 * @arg @ref LL_HRTIM_TIMER_D
11342 * @arg @ref LL_HRTIM_TIMER_E
11343 * @arg @ref LL_HRTIM_TIMER_F
11344 * @retval None
11345 */
11347 {
11349 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11352 }
11354 /**
11355 * @brief Indicate whether the capture 2 interrupt occurred for a given timer.
11356 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
11357 * @param HRTIMx High Resolution Timer instance
11358 * @param Timer This parameter can be one of the following values:
11359 * @arg @ref LL_HRTIM_TIMER_A
11360 * @arg @ref LL_HRTIM_TIMER_B
11361 * @arg @ref LL_HRTIM_TIMER_C
11362 * @arg @ref LL_HRTIM_TIMER_D
11363 * @arg @ref LL_HRTIM_TIMER_E
11364 * @arg @ref LL_HRTIM_TIMER_F
11365 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
11366 */
11368 {
11370 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11374 }
11376 /**
11377 * @brief Clear the output 1 set interrupt flag for a given timer.
11378 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
11379 * @param HRTIMx High Resolution Timer instance
11380 * @param Timer This parameter can be one of the following values:
11381 * @arg @ref LL_HRTIM_TIMER_A
11382 * @arg @ref LL_HRTIM_TIMER_B
11383 * @arg @ref LL_HRTIM_TIMER_C
11384 * @arg @ref LL_HRTIM_TIMER_D
11385 * @arg @ref LL_HRTIM_TIMER_E
11386 * @arg @ref LL_HRTIM_TIMER_F
11387 * @retval None
11388 */
11390 {
11392 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11395 }
11397 /**
11398 * @brief Indicate whether the output 1 set interrupt occurred for a given timer.
11399 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
11400 * @param HRTIMx High Resolution Timer instance
11401 * @param Timer This parameter can be one of the following values:
11402 * @arg @ref LL_HRTIM_TIMER_A
11403 * @arg @ref LL_HRTIM_TIMER_B
11404 * @arg @ref LL_HRTIM_TIMER_C
11405 * @arg @ref LL_HRTIM_TIMER_D
11406 * @arg @ref LL_HRTIM_TIMER_E
11407 * @arg @ref LL_HRTIM_TIMER_F
11408 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
11409 */
11411 {
11413 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11417 }
11419 /**
11420 * @brief Clear the output 1 reset interrupt flag for a given timer.
11421 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
11422 * @param HRTIMx High Resolution Timer instance
11423 * @param Timer This parameter can be one of the following values:
11424 * @arg @ref LL_HRTIM_TIMER_A
11425 * @arg @ref LL_HRTIM_TIMER_B
11426 * @arg @ref LL_HRTIM_TIMER_C
11427 * @arg @ref LL_HRTIM_TIMER_D
11428 * @arg @ref LL_HRTIM_TIMER_E
11429 * @arg @ref LL_HRTIM_TIMER_F
11430 * @retval None
11431 */
11433 {
11435 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11438 }
11440 /**
11441 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
11442 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
11443 * @param HRTIMx High Resolution Timer instance
11444 * @param Timer This parameter can be one of the following values:
11445 * @arg @ref LL_HRTIM_TIMER_A
11446 * @arg @ref LL_HRTIM_TIMER_B
11447 * @arg @ref LL_HRTIM_TIMER_C
11448 * @arg @ref LL_HRTIM_TIMER_D
11449 * @arg @ref LL_HRTIM_TIMER_E
11450 * @arg @ref LL_HRTIM_TIMER_F
11451 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
11452 */
11454 {
11456 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11460 }
11462 /**
11463 * @brief Clear the output 2 set interrupt flag for a given timer.
11464 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
11465 * @param HRTIMx High Resolution Timer instance
11466 * @param Timer This parameter can be one of the following values:
11467 * @arg @ref LL_HRTIM_TIMER_A
11468 * @arg @ref LL_HRTIM_TIMER_B
11469 * @arg @ref LL_HRTIM_TIMER_C
11470 * @arg @ref LL_HRTIM_TIMER_D
11471 * @arg @ref LL_HRTIM_TIMER_E
11472 * @arg @ref LL_HRTIM_TIMER_F
11473 * @retval None
11474 */
11476 {
11478 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11481 }
11483 /**
11484 * @brief Indicate whether the output 2 set interrupt occurred for a given timer.
11485 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
11486 * @param HRTIMx High Resolution Timer instance
11487 * @param Timer This parameter can be one of the following values:
11488 * @arg @ref LL_HRTIM_TIMER_A
11489 * @arg @ref LL_HRTIM_TIMER_B
11490 * @arg @ref LL_HRTIM_TIMER_C
11491 * @arg @ref LL_HRTIM_TIMER_D
11492 * @arg @ref LL_HRTIM_TIMER_E
11493 * @arg @ref LL_HRTIM_TIMER_F
11494 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
11495 */
11497 {
11499 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11503 }
11505 /**
11506 * @brief Clear the output 2reset interrupt flag for a given timer.
11507 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
11508 * @param HRTIMx High Resolution Timer instance
11509 * @param Timer This parameter can be one of the following values:
11510 * @arg @ref LL_HRTIM_TIMER_A
11511 * @arg @ref LL_HRTIM_TIMER_B
11512 * @arg @ref LL_HRTIM_TIMER_C
11513 * @arg @ref LL_HRTIM_TIMER_D
11514 * @arg @ref LL_HRTIM_TIMER_E
11515 * @arg @ref LL_HRTIM_TIMER_F
11516 * @retval None
11517 */
11519 {
11521 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11524 }
11526 /**
11527 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
11528 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
11529 * @param HRTIMx High Resolution Timer instance
11530 * @param Timer This parameter can be one of the following values:
11531 * @arg @ref LL_HRTIM_TIMER_A
11532 * @arg @ref LL_HRTIM_TIMER_B
11533 * @arg @ref LL_HRTIM_TIMER_C
11534 * @arg @ref LL_HRTIM_TIMER_D
11535 * @arg @ref LL_HRTIM_TIMER_E
11536 * @arg @ref LL_HRTIM_TIMER_F
11537 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
11538 */
11540 {
11542 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11546 }
11548 /**
11549 * @brief Clear the reset and/or roll-over interrupt flag for a given timer.
11550 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
11551 * @param HRTIMx High Resolution Timer instance
11552 * @param Timer This parameter can be one of the following values:
11553 * @arg @ref LL_HRTIM_TIMER_A
11554 * @arg @ref LL_HRTIM_TIMER_B
11555 * @arg @ref LL_HRTIM_TIMER_C
11556 * @arg @ref LL_HRTIM_TIMER_D
11557 * @arg @ref LL_HRTIM_TIMER_E
11558 * @arg @ref LL_HRTIM_TIMER_F
11559 * @retval None
11560 */
11562 {
11564 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11567 }
11569 /**
11570 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
11571 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
11572 * @param HRTIMx High Resolution Timer instance
11573 * @param Timer This parameter can be one of the following values:
11574 * @arg @ref LL_HRTIM_TIMER_A
11575 * @arg @ref LL_HRTIM_TIMER_B
11576 * @arg @ref LL_HRTIM_TIMER_C
11577 * @arg @ref LL_HRTIM_TIMER_D
11578 * @arg @ref LL_HRTIM_TIMER_E
11579 * @arg @ref LL_HRTIM_TIMER_F
11580 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
11581 */
11583 {
11585 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11589 }
11591 /**
11592 * @brief Clear the delayed protection interrupt flag for a given timer.
11593 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
11594 * @param HRTIMx High Resolution Timer instance
11595 * @param Timer This parameter can be one of the following values:
11596 * @arg @ref LL_HRTIM_TIMER_A
11597 * @arg @ref LL_HRTIM_TIMER_B
11598 * @arg @ref LL_HRTIM_TIMER_C
11599 * @arg @ref LL_HRTIM_TIMER_D
11600 * @arg @ref LL_HRTIM_TIMER_E
11601 * @arg @ref LL_HRTIM_TIMER_F
11602 * @retval None
11603 */
11605 {
11607 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
11610 }
11612 /**
11613 * @brief Indicate whether the delayed protection interrupt occurred for a given timer.
11614 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
11615 * @param HRTIMx High Resolution Timer instance
11616 * @param Timer This parameter can be one of the following values:
11617 * @arg @ref LL_HRTIM_TIMER_A
11618 * @arg @ref LL_HRTIM_TIMER_B
11619 * @arg @ref LL_HRTIM_TIMER_C
11620 * @arg @ref LL_HRTIM_TIMER_D
11621 * @arg @ref LL_HRTIM_TIMER_E
11622 * @arg @ref LL_HRTIM_TIMER_F
11623 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
11624 */
11626 {
11628 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
11632 }
11634 /**
11635 * @}
11636 */
11638 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management
11639 * @{
11640 */
11642 /**
11643 * @brief Enable the fault 1 interrupt.
11644 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
11645 * @param HRTIMx High Resolution Timer instance
11646 * @retval None
11647 */
11649 {
11651 }
11653 /**
11654 * @brief Disable the fault 1 interrupt.
11655 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
11656 * @param HRTIMx High Resolution Timer instance
11657 * @retval None
11658 */
11660 {
11662 }
11664 /**
11665 * @brief Indicate whether the fault 1 interrupt is enabled.
11666 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
11667 * @param HRTIMx High Resolution Timer instance
11668 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
11669 */
11671 {
11673 }
11675 /**
11676 * @brief Enable the fault 2 interrupt.
11677 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
11678 * @param HRTIMx High Resolution Timer instance
11679 * @retval None
11680 */
11682 {
11684 }
11686 /**
11687 * @brief Disable the fault 2 interrupt.
11688 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
11689 * @param HRTIMx High Resolution Timer instance
11690 * @retval None
11691 */
11693 {
11695 }
11697 /**
11698 * @brief Indicate whether the fault 2 interrupt is enabled.
11699 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
11700 * @param HRTIMx High Resolution Timer instance
11701 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
11702 */
11704 {
11706 }
11708 /**
11709 * @brief Enable the fault 3 interrupt.
11710 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
11711 * @param HRTIMx High Resolution Timer instance
11712 * @retval None
11713 */
11715 {
11717 }
11719 /**
11720 * @brief Disable the fault 3 interrupt.
11721 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
11722 * @param HRTIMx High Resolution Timer instance
11723 * @retval None
11724 */
11726 {
11728 }
11730 /**
11731 * @brief Indicate whether the fault 3 interrupt is enabled.
11732 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
11733 * @param HRTIMx High Resolution Timer instance
11734 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
11735 */
11737 {
11739 }
11741 /**
11742 * @brief Enable the fault 4 interrupt.
11743 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
11744 * @param HRTIMx High Resolution Timer instance
11745 * @retval None
11746 */
11748 {
11750 }
11752 /**
11753 * @brief Disable the fault 4 interrupt.
11754 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
11755 * @param HRTIMx High Resolution Timer instance
11756 * @retval None
11757 */
11759 {
11761 }
11763 /**
11764 * @brief Indicate whether the fault 4 interrupt is enabled.
11765 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
11766 * @param HRTIMx High Resolution Timer instance
11767 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
11768 */
11770 {
11772 }
11774 /**
11775 * @brief Enable the fault 5 interrupt.
11776 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
11777 * @param HRTIMx High Resolution Timer instance
11778 * @retval None
11779 */
11781 {
11783 }
11785 /**
11786 * @brief Disable the fault 5 interrupt.
11787 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
11788 * @param HRTIMx High Resolution Timer instance
11789 * @retval None
11790 */
11792 {
11794 }
11796 /**
11797 * @brief Indicate whether the fault 5 interrupt is enabled.
11798 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
11799 * @param HRTIMx High Resolution Timer instance
11800 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
11801 */
11803 {
11805 }
11807 /**
11808 * @brief Enable the fault 6 interrupt.
11809 * @rmtoll IER FLT6IE LL_HRTIM_EnableIT_FLT6
11810 * @param HRTIMx High Resolution Timer instance
11811 * @retval None
11812 */
11814 {
11816 }
11818 /**
11819 * @brief Disable the fault 6 interrupt.
11820 * @rmtoll IER FLT6IE LL_HRTIM_DisableIT_FLT6
11821 * @param HRTIMx High Resolution Timer instance
11822 * @retval None
11823 */
11825 {
11827 }
11829 /**
11830 * @brief Indicate whether the fault 6 interrupt is enabled.
11831 * @rmtoll IER FLT6IE LL_HRTIM_IsEnabledIT_FLT6
11832 * @param HRTIMx High Resolution Timer instance
11833 * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
11834 */
11836 {
11838 }
11840 /**
11841 * @brief Enable the system fault interrupt.
11842 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
11843 * @param HRTIMx High Resolution Timer instance
11844 * @retval None
11845 */
11847 {
11849 }
11851 /**
11852 * @brief Disable the system fault interrupt.
11853 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
11854 * @param HRTIMx High Resolution Timer instance
11855 * @retval None
11856 */
11858 {
11860 }
11862 /**
11863 * @brief Indicate whether the system fault interrupt is enabled.
11864 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
11865 * @param HRTIMx High Resolution Timer instance
11866 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
11867 */
11869 {
11870 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
11871 }
11873 /**
11874 * @brief Enable the DLL ready interrupt.
11875 * @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
11876 * @param HRTIMx High Resolution Timer instance
11877 * @retval None
11878 */
11880 {
11882 }
11884 /**
11885 * @brief Disable the DLL ready interrupt.
11886 * @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
11887 * @param HRTIMx High Resolution Timer instance
11888 * @retval None
11889 */
11891 {
11893 }
11895 /**
11896 * @brief Indicate whether the DLL ready interrupt is enabled.
11897 * @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
11898 * @param HRTIMx High Resolution Timer instance
11899 * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
11900 */
11902 {
11903 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
11904 }
11906 /**
11907 * @brief Enable the burst mode period interrupt.
11908 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
11909 * @param HRTIMx High Resolution Timer instance
11910 * @retval None
11911 */
11913 {
11915 }
11917 /**
11918 * @brief Disable the burst mode period interrupt.
11919 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
11920 * @param HRTIMx High Resolution Timer instance
11921 * @retval None
11922 */
11924 {
11926 }
11928 /**
11929 * @brief Indicate whether the burst mode period interrupt is enabled.
11930 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
11931 * @param HRTIMx High Resolution Timer instance
11932 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
11933 */
11935 {
11936 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
11937 }
11939 /**
11940 * @brief Enable the synchronization input interrupt.
11941 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
11942 * @param HRTIMx High Resolution Timer instance
11943 * @retval None
11944 */
11946 {
11948 }
11950 /**
11951 * @brief Disable the synchronization input interrupt.
11952 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
11953 * @param HRTIMx High Resolution Timer instance
11954 * @retval None
11955 */
11957 {
11959 }
11961 /**
11962 * @brief Indicate whether the synchronization input interrupt is enabled.
11963 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
11964 * @param HRTIMx High Resolution Timer instance
11965 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
11966 */
11968 {
11969 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
11970 }
11972 /**
11973 * @brief Enable the update interrupt for a given timer.
11974 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
11975 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
11976 * @param HRTIMx High Resolution Timer instance
11977 * @param Timer This parameter can be one of the following values:
11978 * @arg @ref LL_HRTIM_TIMER_MASTER
11979 * @arg @ref LL_HRTIM_TIMER_A
11980 * @arg @ref LL_HRTIM_TIMER_B
11981 * @arg @ref LL_HRTIM_TIMER_C
11982 * @arg @ref LL_HRTIM_TIMER_D
11983 * @arg @ref LL_HRTIM_TIMER_E
11984 * @arg @ref LL_HRTIM_TIMER_F
11985 * @retval None
11986 */
11988 {
11990 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
11993 }
11995 /**
11996 * @brief Disable the update interrupt for a given timer.
11997 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
11998 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
11999 * @param HRTIMx High Resolution Timer instance
12000 * @param Timer This parameter can be one of the following values:
12001 * @arg @ref LL_HRTIM_TIMER_MASTER
12002 * @arg @ref LL_HRTIM_TIMER_A
12003 * @arg @ref LL_HRTIM_TIMER_B
12004 * @arg @ref LL_HRTIM_TIMER_C
12005 * @arg @ref LL_HRTIM_TIMER_D
12006 * @arg @ref LL_HRTIM_TIMER_E
12007 * @arg @ref LL_HRTIM_TIMER_F
12008 * @retval None
12009 */
12011 {
12013 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12016 }
12018 /**
12019 * @brief Indicate whether the update interrupt is enabled for a given timer.
12020 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
12021 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
12022 * @param HRTIMx High Resolution Timer instance
12023 * @param Timer This parameter can be one of the following values:
12024 * @arg @ref LL_HRTIM_TIMER_MASTER
12025 * @arg @ref LL_HRTIM_TIMER_A
12026 * @arg @ref LL_HRTIM_TIMER_B
12027 * @arg @ref LL_HRTIM_TIMER_C
12028 * @arg @ref LL_HRTIM_TIMER_D
12029 * @arg @ref LL_HRTIM_TIMER_E
12030 * @arg @ref LL_HRTIM_TIMER_F
12031 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12032 */
12034 {
12036 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12040 }
12042 /**
12043 * @brief Enable the repetition interrupt for a given timer.
12044 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
12045 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP
12046 * @param HRTIMx High Resolution Timer instance
12047 * @param Timer This parameter can be one of the following values:
12048 * @arg @ref LL_HRTIM_TIMER_MASTER
12049 * @arg @ref LL_HRTIM_TIMER_A
12050 * @arg @ref LL_HRTIM_TIMER_B
12051 * @arg @ref LL_HRTIM_TIMER_C
12052 * @arg @ref LL_HRTIM_TIMER_D
12053 * @arg @ref LL_HRTIM_TIMER_E
12054 * @arg @ref LL_HRTIM_TIMER_F
12055 * @retval None
12056 */
12058 {
12060 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12063 }
12065 /**
12066 * @brief Disable the repetition interrupt for a given timer.
12067 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
12068 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP
12069 * @param HRTIMx High Resolution Timer instance
12070 * @param Timer This parameter can be one of the following values:
12071 * @arg @ref LL_HRTIM_TIMER_MASTER
12072 * @arg @ref LL_HRTIM_TIMER_A
12073 * @arg @ref LL_HRTIM_TIMER_B
12074 * @arg @ref LL_HRTIM_TIMER_C
12075 * @arg @ref LL_HRTIM_TIMER_D
12076 * @arg @ref LL_HRTIM_TIMER_E
12077 * @arg @ref LL_HRTIM_TIMER_F
12078 * @retval None
12079 */
12081 {
12083 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12086 }
12088 /**
12089 * @brief Indicate whether the repetition interrupt is enabled for a given timer.
12090 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
12091 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
12092 * @param HRTIMx High Resolution Timer instance
12093 * @param Timer This parameter can be one of the following values:
12094 * @arg @ref LL_HRTIM_TIMER_MASTER
12095 * @arg @ref LL_HRTIM_TIMER_A
12096 * @arg @ref LL_HRTIM_TIMER_B
12097 * @arg @ref LL_HRTIM_TIMER_C
12098 * @arg @ref LL_HRTIM_TIMER_D
12099 * @arg @ref LL_HRTIM_TIMER_E
12100 * @arg @ref LL_HRTIM_TIMER_F
12101 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12102 */
12104 {
12106 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12110 }
12112 /**
12113 * @brief Enable the compare 1 interrupt for a given timer.
12114 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
12115 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
12116 * @param HRTIMx High Resolution Timer instance
12117 * @param Timer This parameter can be one of the following values:
12118 * @arg @ref LL_HRTIM_TIMER_MASTER
12119 * @arg @ref LL_HRTIM_TIMER_A
12120 * @arg @ref LL_HRTIM_TIMER_B
12121 * @arg @ref LL_HRTIM_TIMER_C
12122 * @arg @ref LL_HRTIM_TIMER_D
12123 * @arg @ref LL_HRTIM_TIMER_E
12124 * @arg @ref LL_HRTIM_TIMER_F
12125 * @retval None
12126 */
12128 {
12130 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12133 }
12135 /**
12136 * @brief Disable the compare 1 interrupt for a given timer.
12137 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
12138 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
12139 * @param HRTIMx High Resolution Timer instance
12140 * @param Timer This parameter can be one of the following values:
12141 * @arg @ref LL_HRTIM_TIMER_MASTER
12142 * @arg @ref LL_HRTIM_TIMER_A
12143 * @arg @ref LL_HRTIM_TIMER_B
12144 * @arg @ref LL_HRTIM_TIMER_C
12145 * @arg @ref LL_HRTIM_TIMER_D
12146 * @arg @ref LL_HRTIM_TIMER_E
12147 * @arg @ref LL_HRTIM_TIMER_F
12148 * @retval None
12149 */
12151 {
12153 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12156 }
12158 /**
12159 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
12160 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
12161 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
12162 * @param HRTIMx High Resolution Timer instance
12163 * @param Timer This parameter can be one of the following values:
12164 * @arg @ref LL_HRTIM_TIMER_MASTER
12165 * @arg @ref LL_HRTIM_TIMER_A
12166 * @arg @ref LL_HRTIM_TIMER_B
12167 * @arg @ref LL_HRTIM_TIMER_C
12168 * @arg @ref LL_HRTIM_TIMER_D
12169 * @arg @ref LL_HRTIM_TIMER_E
12170 * @arg @ref LL_HRTIM_TIMER_F
12171 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12172 */
12174 {
12176 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12180 }
12182 /**
12183 * @brief Enable the compare 2 interrupt for a given timer.
12184 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
12185 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
12186 * @param HRTIMx High Resolution Timer instance
12187 * @param Timer This parameter can be one of the following values:
12188 * @arg @ref LL_HRTIM_TIMER_MASTER
12189 * @arg @ref LL_HRTIM_TIMER_A
12190 * @arg @ref LL_HRTIM_TIMER_B
12191 * @arg @ref LL_HRTIM_TIMER_C
12192 * @arg @ref LL_HRTIM_TIMER_D
12193 * @arg @ref LL_HRTIM_TIMER_E
12194 * @arg @ref LL_HRTIM_TIMER_F
12195 * @retval None
12196 */
12198 {
12200 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12203 }
12205 /**
12206 * @brief Disable the compare 2 interrupt for a given timer.
12207 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
12208 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
12209 * @param HRTIMx High Resolution Timer instance
12210 * @param Timer This parameter can be one of the following values:
12211 * @arg @ref LL_HRTIM_TIMER_MASTER
12212 * @arg @ref LL_HRTIM_TIMER_A
12213 * @arg @ref LL_HRTIM_TIMER_B
12214 * @arg @ref LL_HRTIM_TIMER_C
12215 * @arg @ref LL_HRTIM_TIMER_D
12216 * @arg @ref LL_HRTIM_TIMER_E
12217 * @arg @ref LL_HRTIM_TIMER_F
12218 * @retval None
12219 */
12221 {
12223 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12226 }
12228 /**
12229 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
12230 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
12231 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
12232 * @param HRTIMx High Resolution Timer instance
12233 * @param Timer This parameter can be one of the following values:
12234 * @arg @ref LL_HRTIM_TIMER_MASTER
12235 * @arg @ref LL_HRTIM_TIMER_A
12236 * @arg @ref LL_HRTIM_TIMER_B
12237 * @arg @ref LL_HRTIM_TIMER_C
12238 * @arg @ref LL_HRTIM_TIMER_D
12239 * @arg @ref LL_HRTIM_TIMER_E
12240 * @arg @ref LL_HRTIM_TIMER_F
12241 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12242 */
12244 {
12246 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12250 }
12252 /**
12253 * @brief Enable the compare 3 interrupt for a given timer.
12254 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
12255 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
12256 * @param HRTIMx High Resolution Timer instance
12257 * @param Timer This parameter can be one of the following values:
12258 * @arg @ref LL_HRTIM_TIMER_MASTER
12259 * @arg @ref LL_HRTIM_TIMER_A
12260 * @arg @ref LL_HRTIM_TIMER_B
12261 * @arg @ref LL_HRTIM_TIMER_C
12262 * @arg @ref LL_HRTIM_TIMER_D
12263 * @arg @ref LL_HRTIM_TIMER_E
12264 * @arg @ref LL_HRTIM_TIMER_F
12265 * @retval None
12266 */
12268 {
12270 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12273 }
12275 /**
12276 * @brief Disable the compare 3 interrupt for a given timer.
12277 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
12278 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
12279 * @param HRTIMx High Resolution Timer instance
12280 * @param Timer This parameter can be one of the following values:
12281 * @arg @ref LL_HRTIM_TIMER_MASTER
12282 * @arg @ref LL_HRTIM_TIMER_A
12283 * @arg @ref LL_HRTIM_TIMER_B
12284 * @arg @ref LL_HRTIM_TIMER_C
12285 * @arg @ref LL_HRTIM_TIMER_D
12286 * @arg @ref LL_HRTIM_TIMER_E
12287 * @arg @ref LL_HRTIM_TIMER_F
12288 * @retval None
12289 */
12291 {
12293 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12296 }
12298 /**
12299 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
12300 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
12301 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
12302 * @param HRTIMx High Resolution Timer instance
12303 * @param Timer This parameter can be one of the following values:
12304 * @arg @ref LL_HRTIM_TIMER_MASTER
12305 * @arg @ref LL_HRTIM_TIMER_A
12306 * @arg @ref LL_HRTIM_TIMER_B
12307 * @arg @ref LL_HRTIM_TIMER_C
12308 * @arg @ref LL_HRTIM_TIMER_D
12309 * @arg @ref LL_HRTIM_TIMER_E
12310 * @arg @ref LL_HRTIM_TIMER_F
12311 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12312 */
12314 {
12316 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12320 }
12322 /**
12323 * @brief Enable the compare 4 interrupt for a given timer.
12324 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
12325 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
12326 * @param HRTIMx High Resolution Timer instance
12327 * @param Timer This parameter can be one of the following values:
12328 * @arg @ref LL_HRTIM_TIMER_MASTER
12329 * @arg @ref LL_HRTIM_TIMER_A
12330 * @arg @ref LL_HRTIM_TIMER_B
12331 * @arg @ref LL_HRTIM_TIMER_C
12332 * @arg @ref LL_HRTIM_TIMER_D
12333 * @arg @ref LL_HRTIM_TIMER_E
12334 * @arg @ref LL_HRTIM_TIMER_F
12335 * @retval None
12336 */
12338 {
12340 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12343 }
12345 /**
12346 * @brief Disable the compare 4 interrupt for a given timer.
12347 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
12348 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
12349 * @param HRTIMx High Resolution Timer instance
12350 * @param Timer This parameter can be one of the following values:
12351 * @arg @ref LL_HRTIM_TIMER_MASTER
12352 * @arg @ref LL_HRTIM_TIMER_A
12353 * @arg @ref LL_HRTIM_TIMER_B
12354 * @arg @ref LL_HRTIM_TIMER_C
12355 * @arg @ref LL_HRTIM_TIMER_D
12356 * @arg @ref LL_HRTIM_TIMER_E
12357 * @arg @ref LL_HRTIM_TIMER_F
12358 * @retval None
12359 */
12361 {
12363 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12366 }
12368 /**
12369 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
12370 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
12371 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
12372 * @param HRTIMx High Resolution Timer instance
12373 * @param Timer This parameter can be one of the following values:
12374 * @arg @ref LL_HRTIM_TIMER_MASTER
12375 * @arg @ref LL_HRTIM_TIMER_A
12376 * @arg @ref LL_HRTIM_TIMER_B
12377 * @arg @ref LL_HRTIM_TIMER_C
12378 * @arg @ref LL_HRTIM_TIMER_D
12379 * @arg @ref LL_HRTIM_TIMER_E
12380 * @arg @ref LL_HRTIM_TIMER_F
12381 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
12382 */
12384 {
12386 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12390 }
12392 /**
12393 * @brief Enable the capture 1 interrupt for a given timer.
12394 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
12395 * @param HRTIMx High Resolution Timer instance
12396 * @param Timer This parameter can be one of the following values:
12397 * @arg @ref LL_HRTIM_TIMER_A
12398 * @arg @ref LL_HRTIM_TIMER_B
12399 * @arg @ref LL_HRTIM_TIMER_C
12400 * @arg @ref LL_HRTIM_TIMER_D
12401 * @arg @ref LL_HRTIM_TIMER_E
12402 * @arg @ref LL_HRTIM_TIMER_F
12403 * @retval None
12404 */
12406 {
12408 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12411 }
12413 /**
12414 * @brief Enable the capture 1 interrupt for a given timer.
12415 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
12416 * @param HRTIMx High Resolution Timer instance
12417 * @param Timer This parameter can be one of the following values:
12418 * @arg @ref LL_HRTIM_TIMER_A
12419 * @arg @ref LL_HRTIM_TIMER_B
12420 * @arg @ref LL_HRTIM_TIMER_C
12421 * @arg @ref LL_HRTIM_TIMER_D
12422 * @arg @ref LL_HRTIM_TIMER_E
12423 * @arg @ref LL_HRTIM_TIMER_F
12424 * @retval None
12425 */
12427 {
12429 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12432 }
12434 /**
12435 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
12436 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
12437 * @param HRTIMx High Resolution Timer instance
12438 * @param Timer This parameter can be one of the following values:
12439 * @arg @ref LL_HRTIM_TIMER_A
12440 * @arg @ref LL_HRTIM_TIMER_B
12441 * @arg @ref LL_HRTIM_TIMER_C
12442 * @arg @ref LL_HRTIM_TIMER_D
12443 * @arg @ref LL_HRTIM_TIMER_E
12444 * @arg @ref LL_HRTIM_TIMER_F
12445 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
12446 */
12448 {
12450 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12454 }
12456 /**
12457 * @brief Enable the capture 2 interrupt for a given timer.
12458 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
12459 * @param HRTIMx High Resolution Timer instance
12460 * @param Timer This parameter can be one of the following values:
12461 * @arg @ref LL_HRTIM_TIMER_A
12462 * @arg @ref LL_HRTIM_TIMER_B
12463 * @arg @ref LL_HRTIM_TIMER_C
12464 * @arg @ref LL_HRTIM_TIMER_D
12465 * @arg @ref LL_HRTIM_TIMER_E
12466 * @arg @ref LL_HRTIM_TIMER_F
12467 * @retval None
12468 */
12470 {
12472 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12475 }
12477 /**
12478 * @brief Enable the capture 2 interrupt for a given timer.
12479 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
12480 * @param HRTIMx High Resolution Timer instance
12481 * @param Timer This parameter can be one of the following values:
12482 * @arg @ref LL_HRTIM_TIMER_A
12483 * @arg @ref LL_HRTIM_TIMER_B
12484 * @arg @ref LL_HRTIM_TIMER_C
12485 * @arg @ref LL_HRTIM_TIMER_D
12486 * @arg @ref LL_HRTIM_TIMER_E
12487 * @arg @ref LL_HRTIM_TIMER_F
12488 * @retval None
12489 */
12491 {
12493 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12496 }
12498 /**
12499 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
12500 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
12501 * @param HRTIMx High Resolution Timer instance
12502 * @param Timer This parameter can be one of the following values:
12503 * @arg @ref LL_HRTIM_TIMER_A
12504 * @arg @ref LL_HRTIM_TIMER_B
12505 * @arg @ref LL_HRTIM_TIMER_C
12506 * @arg @ref LL_HRTIM_TIMER_D
12507 * @arg @ref LL_HRTIM_TIMER_E
12508 * @arg @ref LL_HRTIM_TIMER_F
12509 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
12510 */
12512 {
12514 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12518 }
12520 /**
12521 * @brief Enable the output 1 set interrupt for a given timer.
12522 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
12523 * @param HRTIMx High Resolution Timer instance
12524 * @param Timer This parameter can be one of the following values:
12525 * @arg @ref LL_HRTIM_TIMER_A
12526 * @arg @ref LL_HRTIM_TIMER_B
12527 * @arg @ref LL_HRTIM_TIMER_C
12528 * @arg @ref LL_HRTIM_TIMER_D
12529 * @arg @ref LL_HRTIM_TIMER_E
12530 * @arg @ref LL_HRTIM_TIMER_F
12531 * @retval None
12532 */
12534 {
12536 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12539 }
12541 /**
12542 * @brief Disable the output 1 set interrupt for a given timer.
12543 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
12544 * @param HRTIMx High Resolution Timer instance
12545 * @param Timer This parameter can be one of the following values:
12546 * @arg @ref LL_HRTIM_TIMER_A
12547 * @arg @ref LL_HRTIM_TIMER_B
12548 * @arg @ref LL_HRTIM_TIMER_C
12549 * @arg @ref LL_HRTIM_TIMER_D
12550 * @arg @ref LL_HRTIM_TIMER_E
12551 * @arg @ref LL_HRTIM_TIMER_F
12552 * @retval None
12553 */
12555 {
12557 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12560 }
12562 /**
12563 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
12564 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
12565 * @param HRTIMx High Resolution Timer instance
12566 * @param Timer This parameter can be one of the following values:
12567 * @arg @ref LL_HRTIM_TIMER_A
12568 * @arg @ref LL_HRTIM_TIMER_B
12569 * @arg @ref LL_HRTIM_TIMER_C
12570 * @arg @ref LL_HRTIM_TIMER_D
12571 * @arg @ref LL_HRTIM_TIMER_E
12572 * @arg @ref LL_HRTIM_TIMER_F
12573 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12574 */
12576 {
12578 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12582 }
12584 /**
12585 * @brief Enable the output 1 reset interrupt for a given timer.
12586 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
12587 * @param HRTIMx High Resolution Timer instance
12588 * @param Timer This parameter can be one of the following values:
12589 * @arg @ref LL_HRTIM_TIMER_A
12590 * @arg @ref LL_HRTIM_TIMER_B
12591 * @arg @ref LL_HRTIM_TIMER_C
12592 * @arg @ref LL_HRTIM_TIMER_D
12593 * @arg @ref LL_HRTIM_TIMER_E
12594 * @arg @ref LL_HRTIM_TIMER_F
12595 * @retval None
12596 */
12598 {
12600 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12603 }
12605 /**
12606 * @brief Disable the output 1 reset interrupt for a given timer.
12607 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
12608 * @param HRTIMx High Resolution Timer instance
12609 * @param Timer This parameter can be one of the following values:
12610 * @arg @ref LL_HRTIM_TIMER_A
12611 * @arg @ref LL_HRTIM_TIMER_B
12612 * @arg @ref LL_HRTIM_TIMER_C
12613 * @arg @ref LL_HRTIM_TIMER_D
12614 * @arg @ref LL_HRTIM_TIMER_E
12615 * @arg @ref LL_HRTIM_TIMER_F
12616 * @retval None
12617 */
12619 {
12621 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12624 }
12626 /**
12627 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
12628 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
12629 * @param HRTIMx High Resolution Timer instance
12630 * @param Timer This parameter can be one of the following values:
12631 * @arg @ref LL_HRTIM_TIMER_A
12632 * @arg @ref LL_HRTIM_TIMER_B
12633 * @arg @ref LL_HRTIM_TIMER_C
12634 * @arg @ref LL_HRTIM_TIMER_D
12635 * @arg @ref LL_HRTIM_TIMER_E
12636 * @arg @ref LL_HRTIM_TIMER_F
12637 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
12638 */
12640 {
12642 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12646 }
12648 /**
12649 * @brief Enable the output 2 set interrupt for a given timer.
12650 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
12651 * @param HRTIMx High Resolution Timer instance
12652 * @param Timer This parameter can be one of the following values:
12653 * @arg @ref LL_HRTIM_TIMER_A
12654 * @arg @ref LL_HRTIM_TIMER_B
12655 * @arg @ref LL_HRTIM_TIMER_C
12656 * @arg @ref LL_HRTIM_TIMER_D
12657 * @arg @ref LL_HRTIM_TIMER_E
12658 * @arg @ref LL_HRTIM_TIMER_F
12659 * @retval None
12660 */
12662 {
12664 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12667 }
12669 /**
12670 * @brief Disable the output 2 set interrupt for a given timer.
12671 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
12672 * @param HRTIMx High Resolution Timer instance
12673 * @param Timer This parameter can be one of the following values:
12674 * @arg @ref LL_HRTIM_TIMER_A
12675 * @arg @ref LL_HRTIM_TIMER_B
12676 * @arg @ref LL_HRTIM_TIMER_C
12677 * @arg @ref LL_HRTIM_TIMER_D
12678 * @arg @ref LL_HRTIM_TIMER_E
12679 * @arg @ref LL_HRTIM_TIMER_F
12680 * @retval None
12681 */
12683 {
12685 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12688 }
12690 /**
12691 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
12692 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
12693 * @param HRTIMx High Resolution Timer instance
12694 * @param Timer This parameter can be one of the following values:
12695 * @arg @ref LL_HRTIM_TIMER_A
12696 * @arg @ref LL_HRTIM_TIMER_B
12697 * @arg @ref LL_HRTIM_TIMER_C
12698 * @arg @ref LL_HRTIM_TIMER_D
12699 * @arg @ref LL_HRTIM_TIMER_E
12700 * @arg @ref LL_HRTIM_TIMER_F
12701 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12702 */
12704 {
12706 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12710 }
12712 /**
12713 * @brief Enable the output 2 reset interrupt for a given timer.
12714 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
12715 * @param HRTIMx High Resolution Timer instance
12716 * @param Timer This parameter can be one of the following values:
12717 * @arg @ref LL_HRTIM_TIMER_A
12718 * @arg @ref LL_HRTIM_TIMER_B
12719 * @arg @ref LL_HRTIM_TIMER_C
12720 * @arg @ref LL_HRTIM_TIMER_D
12721 * @arg @ref LL_HRTIM_TIMER_E
12722 * @arg @ref LL_HRTIM_TIMER_F
12723 * @retval None
12724 */
12726 {
12728 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12731 }
12733 /**
12734 * @brief Disable the output 2 reset interrupt for a given timer.
12735 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12736 * @param HRTIMx High Resolution Timer instance
12737 * @param Timer This parameter can be one of the following values:
12738 * @arg @ref LL_HRTIM_TIMER_A
12739 * @arg @ref LL_HRTIM_TIMER_B
12740 * @arg @ref LL_HRTIM_TIMER_C
12741 * @arg @ref LL_HRTIM_TIMER_D
12742 * @arg @ref LL_HRTIM_TIMER_E
12743 * @arg @ref LL_HRTIM_TIMER_F
12744 * @retval None
12745 */
12747 {
12749 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12752 }
12754 /**
12755 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
12756 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
12757 * @param HRTIMx High Resolution Timer instance
12758 * @param Timer This parameter can be one of the following values:
12759 * @arg @ref LL_HRTIM_TIMER_A
12760 * @arg @ref LL_HRTIM_TIMER_B
12761 * @arg @ref LL_HRTIM_TIMER_C
12762 * @arg @ref LL_HRTIM_TIMER_D
12763 * @arg @ref LL_HRTIM_TIMER_E
12764 * @arg @ref LL_HRTIM_TIMER_F
12765 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
12766 */
12768 {
12770 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12774 }
12776 /**
12777 * @brief Enable the reset/roll-over interrupt for a given timer.
12778 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
12779 * @param HRTIMx High Resolution Timer instance
12780 * @param Timer This parameter can be one of the following values:
12781 * @arg @ref LL_HRTIM_TIMER_A
12782 * @arg @ref LL_HRTIM_TIMER_B
12783 * @arg @ref LL_HRTIM_TIMER_C
12784 * @arg @ref LL_HRTIM_TIMER_D
12785 * @arg @ref LL_HRTIM_TIMER_E
12786 * @arg @ref LL_HRTIM_TIMER_F
12787 * @retval None
12788 */
12790 {
12792 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12795 }
12797 /**
12798 * @brief Disable the reset/roll-over interrupt for a given timer.
12799 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
12800 * @param HRTIMx High Resolution Timer instance
12801 * @param Timer This parameter can be one of the following values:
12802 * @arg @ref LL_HRTIM_TIMER_A
12803 * @arg @ref LL_HRTIM_TIMER_B
12804 * @arg @ref LL_HRTIM_TIMER_C
12805 * @arg @ref LL_HRTIM_TIMER_D
12806 * @arg @ref LL_HRTIM_TIMER_E
12807 * @arg @ref LL_HRTIM_TIMER_F
12808 * @retval None
12809 */
12811 {
12813 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12816 }
12818 /**
12819 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
12820 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
12821 * @param HRTIMx High Resolution Timer instance
12822 * @param Timer This parameter can be one of the following values:
12823 * @arg @ref LL_HRTIM_TIMER_A
12824 * @arg @ref LL_HRTIM_TIMER_B
12825 * @arg @ref LL_HRTIM_TIMER_C
12826 * @arg @ref LL_HRTIM_TIMER_D
12827 * @arg @ref LL_HRTIM_TIMER_E
12828 * @arg @ref LL_HRTIM_TIMER_F
12829 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
12830 */
12832 {
12834 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12838 }
12840 /**
12841 * @brief Enable the delayed protection interrupt for a given timer.
12842 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
12843 * @param HRTIMx High Resolution Timer instance
12844 * @param Timer This parameter can be one of the following values:
12845 * @arg @ref LL_HRTIM_TIMER_A
12846 * @arg @ref LL_HRTIM_TIMER_B
12847 * @arg @ref LL_HRTIM_TIMER_C
12848 * @arg @ref LL_HRTIM_TIMER_D
12849 * @arg @ref LL_HRTIM_TIMER_E
12850 * @arg @ref LL_HRTIM_TIMER_F
12851 * @retval None
12852 */
12854 {
12856 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12859 }
12861 /**
12862 * @brief Disable the delayed protection interrupt for a given timer.
12863 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
12864 * @param HRTIMx High Resolution Timer instance
12865 * @param Timer This parameter can be one of the following values:
12866 * @arg @ref LL_HRTIM_TIMER_A
12867 * @arg @ref LL_HRTIM_TIMER_B
12868 * @arg @ref LL_HRTIM_TIMER_C
12869 * @arg @ref LL_HRTIM_TIMER_D
12870 * @arg @ref LL_HRTIM_TIMER_E
12871 * @arg @ref LL_HRTIM_TIMER_F
12872 * @retval None
12873 */
12875 {
12877 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12880 }
12882 /**
12883 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
12884 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
12885 * @param HRTIMx High Resolution Timer instance
12886 * @param Timer This parameter can be one of the following values:
12887 * @arg @ref LL_HRTIM_TIMER_A
12888 * @arg @ref LL_HRTIM_TIMER_B
12889 * @arg @ref LL_HRTIM_TIMER_C
12890 * @arg @ref LL_HRTIM_TIMER_D
12891 * @arg @ref LL_HRTIM_TIMER_E
12892 * @arg @ref LL_HRTIM_TIMER_F
12893 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
12894 */
12896 {
12898 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12902 }
12904 /**
12905 * @}
12906 */
12908 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
12909 * @{
12910 */
12912 /**
12913 * @brief Enable the synchronization input DMA request.
12914 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
12915 * @param HRTIMx High Resolution Timer instance
12916 * @retval None
12917 */
12919 {
12921 }
12923 /**
12924 * @brief Disable the synchronization input DMA request
12925 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
12926 * @param HRTIMx High Resolution Timer instance
12927 * @retval None
12928 */
12930 {
12932 }
12934 /**
12935 * @brief Indicate whether the synchronization input DMA request is enabled.
12936 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
12937 * @param HRTIMx High Resolution Timer instance
12938 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
12939 */
12941 {
12942 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
12943 }
12945 /**
12946 * @brief Enable the update DMA request for a given timer.
12947 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
12948 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
12949 * @param HRTIMx High Resolution Timer instance
12950 * @param Timer This parameter can be one of the following values:
12951 * @arg @ref LL_HRTIM_TIMER_MASTER
12952 * @arg @ref LL_HRTIM_TIMER_A
12953 * @arg @ref LL_HRTIM_TIMER_B
12954 * @arg @ref LL_HRTIM_TIMER_C
12955 * @arg @ref LL_HRTIM_TIMER_D
12956 * @arg @ref LL_HRTIM_TIMER_E
12957 * @arg @ref LL_HRTIM_TIMER_F
12958 * @retval None
12959 */
12961 {
12963 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12966 }
12968 /**
12969 * @brief Disable the update DMA request for a given timer.
12970 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
12971 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
12972 * @param HRTIMx High Resolution Timer instance
12973 * @param Timer This parameter can be one of the following values:
12974 * @arg @ref LL_HRTIM_TIMER_MASTER
12975 * @arg @ref LL_HRTIM_TIMER_A
12976 * @arg @ref LL_HRTIM_TIMER_B
12977 * @arg @ref LL_HRTIM_TIMER_C
12978 * @arg @ref LL_HRTIM_TIMER_D
12979 * @arg @ref LL_HRTIM_TIMER_E
12980 * @arg @ref LL_HRTIM_TIMER_F
12981 * @retval None
12982 */
12984 {
12986 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
12989 }
12991 /**
12992 * @brief Indicate whether the update DMA request is enabled for a given timer.
12993 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
12994 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
12995 * @param HRTIMx High Resolution Timer instance
12996 * @param Timer This parameter can be one of the following values:
12997 * @arg @ref LL_HRTIM_TIMER_MASTER
12998 * @arg @ref LL_HRTIM_TIMER_A
12999 * @arg @ref LL_HRTIM_TIMER_B
13000 * @arg @ref LL_HRTIM_TIMER_C
13001 * @arg @ref LL_HRTIM_TIMER_D
13002 * @arg @ref LL_HRTIM_TIMER_E
13003 * @arg @ref LL_HRTIM_TIMER_F
13004 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13005 */
13006 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13007 {
13009 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13013 }
13015 /**
13016 * @brief Enable the repetition DMA request for a given timer.
13017 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
13018 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
13019 * @param HRTIMx High Resolution Timer instance
13020 * @param Timer This parameter can be one of the following values:
13021 * @arg @ref LL_HRTIM_TIMER_MASTER
13022 * @arg @ref LL_HRTIM_TIMER_A
13023 * @arg @ref LL_HRTIM_TIMER_B
13024 * @arg @ref LL_HRTIM_TIMER_C
13025 * @arg @ref LL_HRTIM_TIMER_D
13026 * @arg @ref LL_HRTIM_TIMER_E
13027 * @arg @ref LL_HRTIM_TIMER_F
13028 * @retval None
13029 */
13031 {
13033 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13036 }
13038 /**
13039 * @brief Disable the repetition DMA request for a given timer.
13040 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
13041 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
13042 * @param HRTIMx High Resolution Timer instance
13043 * @param Timer This parameter can be one of the following values:
13044 * @arg @ref LL_HRTIM_TIMER_MASTER
13045 * @arg @ref LL_HRTIM_TIMER_A
13046 * @arg @ref LL_HRTIM_TIMER_B
13047 * @arg @ref LL_HRTIM_TIMER_C
13048 * @arg @ref LL_HRTIM_TIMER_D
13049 * @arg @ref LL_HRTIM_TIMER_E
13050 * @arg @ref LL_HRTIM_TIMER_F
13051 * @retval None
13052 */
13054 {
13056 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13059 }
13061 /**
13062 * @brief Indicate whether the repetition DMA request is enabled for a given timer.
13063 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
13064 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
13065 * @param HRTIMx High Resolution Timer instance
13066 * @param Timer This parameter can be one of the following values:
13067 * @arg @ref LL_HRTIM_TIMER_MASTER
13068 * @arg @ref LL_HRTIM_TIMER_A
13069 * @arg @ref LL_HRTIM_TIMER_B
13070 * @arg @ref LL_HRTIM_TIMER_C
13071 * @arg @ref LL_HRTIM_TIMER_D
13072 * @arg @ref LL_HRTIM_TIMER_E
13073 * @arg @ref LL_HRTIM_TIMER_F
13074 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13075 */
13077 {
13079 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13083 }
13085 /**
13086 * @brief Enable the compare 1 DMA request for a given timer.
13087 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
13088 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
13089 * @param HRTIMx High Resolution Timer instance
13090 * @param Timer This parameter can be one of the following values:
13091 * @arg @ref LL_HRTIM_TIMER_MASTER
13092 * @arg @ref LL_HRTIM_TIMER_A
13093 * @arg @ref LL_HRTIM_TIMER_B
13094 * @arg @ref LL_HRTIM_TIMER_C
13095 * @arg @ref LL_HRTIM_TIMER_D
13096 * @arg @ref LL_HRTIM_TIMER_E
13097 * @arg @ref LL_HRTIM_TIMER_F
13098 * @retval None
13099 */
13101 {
13103 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13106 }
13108 /**
13109 * @brief Disable the compare 1 DMA request for a given timer.
13110 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
13111 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
13112 * @param HRTIMx High Resolution Timer instance
13113 * @param Timer This parameter can be one of the following values:
13114 * @arg @ref LL_HRTIM_TIMER_MASTER
13115 * @arg @ref LL_HRTIM_TIMER_A
13116 * @arg @ref LL_HRTIM_TIMER_B
13117 * @arg @ref LL_HRTIM_TIMER_C
13118 * @arg @ref LL_HRTIM_TIMER_D
13119 * @arg @ref LL_HRTIM_TIMER_E
13120 * @arg @ref LL_HRTIM_TIMER_F
13121 * @retval None
13122 */
13124 {
13126 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13129 }
13131 /**
13132 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
13133 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
13134 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
13135 * @param HRTIMx High Resolution Timer instance
13136 * @param Timer This parameter can be one of the following values:
13137 * @arg @ref LL_HRTIM_TIMER_MASTER
13138 * @arg @ref LL_HRTIM_TIMER_A
13139 * @arg @ref LL_HRTIM_TIMER_B
13140 * @arg @ref LL_HRTIM_TIMER_C
13141 * @arg @ref LL_HRTIM_TIMER_D
13142 * @arg @ref LL_HRTIM_TIMER_E
13143 * @arg @ref LL_HRTIM_TIMER_F
13144 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13145 */
13147 {
13149 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13153 }
13155 /**
13156 * @brief Enable the compare 2 DMA request for a given timer.
13157 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
13158 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
13159 * @param HRTIMx High Resolution Timer instance
13160 * @param Timer This parameter can be one of the following values:
13161 * @arg @ref LL_HRTIM_TIMER_MASTER
13162 * @arg @ref LL_HRTIM_TIMER_A
13163 * @arg @ref LL_HRTIM_TIMER_B
13164 * @arg @ref LL_HRTIM_TIMER_C
13165 * @arg @ref LL_HRTIM_TIMER_D
13166 * @arg @ref LL_HRTIM_TIMER_E
13167 * @arg @ref LL_HRTIM_TIMER_F
13168 * @retval None
13169 */
13171 {
13173 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13176 }
13178 /**
13179 * @brief Disable the compare 2 DMA request for a given timer.
13180 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
13181 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
13182 * @param HRTIMx High Resolution Timer instance
13183 * @param Timer This parameter can be one of the following values:
13184 * @arg @ref LL_HRTIM_TIMER_MASTER
13185 * @arg @ref LL_HRTIM_TIMER_A
13186 * @arg @ref LL_HRTIM_TIMER_B
13187 * @arg @ref LL_HRTIM_TIMER_C
13188 * @arg @ref LL_HRTIM_TIMER_D
13189 * @arg @ref LL_HRTIM_TIMER_E
13190 * @arg @ref LL_HRTIM_TIMER_F
13191 * @retval None
13192 */
13194 {
13196 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13199 }
13201 /**
13202 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
13203 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
13204 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
13205 * @param HRTIMx High Resolution Timer instance
13206 * @param Timer This parameter can be one of the following values:
13207 * @arg @ref LL_HRTIM_TIMER_MASTER
13208 * @arg @ref LL_HRTIM_TIMER_A
13209 * @arg @ref LL_HRTIM_TIMER_B
13210 * @arg @ref LL_HRTIM_TIMER_C
13211 * @arg @ref LL_HRTIM_TIMER_D
13212 * @arg @ref LL_HRTIM_TIMER_E
13213 * @arg @ref LL_HRTIM_TIMER_F
13214 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13215 */
13217 {
13219 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13223 }
13225 /**
13226 * @brief Enable the compare 3 DMA request for a given timer.
13227 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
13228 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
13229 * @param HRTIMx High Resolution Timer instance
13230 * @param Timer This parameter can be one of the following values:
13231 * @arg @ref LL_HRTIM_TIMER_MASTER
13232 * @arg @ref LL_HRTIM_TIMER_A
13233 * @arg @ref LL_HRTIM_TIMER_B
13234 * @arg @ref LL_HRTIM_TIMER_C
13235 * @arg @ref LL_HRTIM_TIMER_D
13236 * @arg @ref LL_HRTIM_TIMER_E
13237 * @arg @ref LL_HRTIM_TIMER_F
13238 * @retval None
13239 */
13241 {
13243 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13246 }
13248 /**
13249 * @brief Disable the compare 3 DMA request for a given timer.
13250 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
13251 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
13252 * @param HRTIMx High Resolution Timer instance
13253 * @param Timer This parameter can be one of the following values:
13254 * @arg @ref LL_HRTIM_TIMER_MASTER
13255 * @arg @ref LL_HRTIM_TIMER_A
13256 * @arg @ref LL_HRTIM_TIMER_B
13257 * @arg @ref LL_HRTIM_TIMER_C
13258 * @arg @ref LL_HRTIM_TIMER_D
13259 * @arg @ref LL_HRTIM_TIMER_E
13260 * @arg @ref LL_HRTIM_TIMER_F
13261 * @retval None
13262 */
13264 {
13266 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13269 }
13271 /**
13272 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
13273 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
13274 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
13275 * @param HRTIMx High Resolution Timer instance
13276 * @param Timer This parameter can be one of the following values:
13277 * @arg @ref LL_HRTIM_TIMER_MASTER
13278 * @arg @ref LL_HRTIM_TIMER_A
13279 * @arg @ref LL_HRTIM_TIMER_B
13280 * @arg @ref LL_HRTIM_TIMER_C
13281 * @arg @ref LL_HRTIM_TIMER_D
13282 * @arg @ref LL_HRTIM_TIMER_E
13283 * @arg @ref LL_HRTIM_TIMER_F
13284 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13285 */
13287 {
13289 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13293 }
13295 /**
13296 * @brief Enable the compare 4 DMA request for a given timer.
13297 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
13298 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
13299 * @param HRTIMx High Resolution Timer instance
13300 * @param Timer This parameter can be one of the following values:
13301 * @arg @ref LL_HRTIM_TIMER_MASTER
13302 * @arg @ref LL_HRTIM_TIMER_A
13303 * @arg @ref LL_HRTIM_TIMER_B
13304 * @arg @ref LL_HRTIM_TIMER_C
13305 * @arg @ref LL_HRTIM_TIMER_D
13306 * @arg @ref LL_HRTIM_TIMER_E
13307 * @arg @ref LL_HRTIM_TIMER_F
13308 * @retval None
13309 */
13311 {
13313 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13316 }
13318 /**
13319 * @brief Disable the compare 4 DMA request for a given timer.
13320 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
13321 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
13322 * @param HRTIMx High Resolution Timer instance
13323 * @param Timer This parameter can be one of the following values:
13324 * @arg @ref LL_HRTIM_TIMER_MASTER
13325 * @arg @ref LL_HRTIM_TIMER_A
13326 * @arg @ref LL_HRTIM_TIMER_B
13327 * @arg @ref LL_HRTIM_TIMER_C
13328 * @arg @ref LL_HRTIM_TIMER_D
13329 * @arg @ref LL_HRTIM_TIMER_E
13330 * @arg @ref LL_HRTIM_TIMER_F
13331 * @retval None
13332 */
13334 {
13336 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13339 }
13341 /**
13342 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
13343 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
13344 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
13345 * @param HRTIMx High Resolution Timer instance
13346 * @param Timer This parameter can be one of the following values:
13347 * @arg @ref LL_HRTIM_TIMER_MASTER
13348 * @arg @ref LL_HRTIM_TIMER_A
13349 * @arg @ref LL_HRTIM_TIMER_B
13350 * @arg @ref LL_HRTIM_TIMER_C
13351 * @arg @ref LL_HRTIM_TIMER_D
13352 * @arg @ref LL_HRTIM_TIMER_E
13353 * @arg @ref LL_HRTIM_TIMER_F
13354 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
13355 */
13357 {
13359 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13363 }
13365 /**
13366 * @brief Enable the capture 1 DMA request for a given timer.
13367 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
13368 * @param HRTIMx High Resolution Timer instance
13369 * @param Timer This parameter can be one of the following values:
13370 * @arg @ref LL_HRTIM_TIMER_A
13371 * @arg @ref LL_HRTIM_TIMER_B
13372 * @arg @ref LL_HRTIM_TIMER_C
13373 * @arg @ref LL_HRTIM_TIMER_D
13374 * @arg @ref LL_HRTIM_TIMER_E
13375 * @arg @ref LL_HRTIM_TIMER_F
13376 * @retval None
13377 */
13379 {
13381 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13384 }
13386 /**
13387 * @brief Disable the capture 1 DMA request for a given timer.
13388 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
13389 * @param HRTIMx High Resolution Timer instance
13390 * @param Timer This parameter can be one of the following values:
13391 * @arg @ref LL_HRTIM_TIMER_A
13392 * @arg @ref LL_HRTIM_TIMER_B
13393 * @arg @ref LL_HRTIM_TIMER_C
13394 * @arg @ref LL_HRTIM_TIMER_D
13395 * @arg @ref LL_HRTIM_TIMER_E
13396 * @arg @ref LL_HRTIM_TIMER_F
13397 * @retval None
13398 */
13400 {
13402 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13405 }
13407 /**
13408 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
13409 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
13410 * @param HRTIMx High Resolution Timer instance
13411 * @param Timer This parameter can be one of the following values:
13412 * @arg @ref LL_HRTIM_TIMER_A
13413 * @arg @ref LL_HRTIM_TIMER_B
13414 * @arg @ref LL_HRTIM_TIMER_C
13415 * @arg @ref LL_HRTIM_TIMER_D
13416 * @arg @ref LL_HRTIM_TIMER_E
13417 * @arg @ref LL_HRTIM_TIMER_F
13418 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
13419 */
13421 {
13423 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13427 }
13429 /**
13430 * @brief Enable the capture 2 DMA request for a given timer.
13431 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
13432 * @param HRTIMx High Resolution Timer instance
13433 * @param Timer This parameter can be one of the following values:
13434 * @arg @ref LL_HRTIM_TIMER_A
13435 * @arg @ref LL_HRTIM_TIMER_B
13436 * @arg @ref LL_HRTIM_TIMER_C
13437 * @arg @ref LL_HRTIM_TIMER_D
13438 * @arg @ref LL_HRTIM_TIMER_E
13439 * @arg @ref LL_HRTIM_TIMER_F
13440 * @retval None
13441 */
13443 {
13445 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13448 }
13450 /**
13451 * @brief Disable the capture 2 DMA request for a given timer.
13452 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
13453 * @param HRTIMx High Resolution Timer instance
13454 * @param Timer This parameter can be one of the following values:
13455 * @arg @ref LL_HRTIM_TIMER_A
13456 * @arg @ref LL_HRTIM_TIMER_B
13457 * @arg @ref LL_HRTIM_TIMER_C
13458 * @arg @ref LL_HRTIM_TIMER_D
13459 * @arg @ref LL_HRTIM_TIMER_E
13460 * @arg @ref LL_HRTIM_TIMER_F
13461 * @retval None
13462 */
13464 {
13466 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13469 }
13471 /**
13472 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
13473 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
13474 * @param HRTIMx High Resolution Timer instance
13475 * @param Timer This parameter can be one of the following values:
13476 * @arg @ref LL_HRTIM_TIMER_A
13477 * @arg @ref LL_HRTIM_TIMER_B
13478 * @arg @ref LL_HRTIM_TIMER_C
13479 * @arg @ref LL_HRTIM_TIMER_D
13480 * @arg @ref LL_HRTIM_TIMER_E
13481 * @arg @ref LL_HRTIM_TIMER_F
13482 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
13483 */
13485 {
13487 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13491 }
13493 /**
13494 * @brief Enable the output 1 set DMA request for a given timer.
13495 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
13496 * @param HRTIMx High Resolution Timer instance
13497 * @param Timer This parameter can be one of the following values:
13498 * @arg @ref LL_HRTIM_TIMER_A
13499 * @arg @ref LL_HRTIM_TIMER_B
13500 * @arg @ref LL_HRTIM_TIMER_C
13501 * @arg @ref LL_HRTIM_TIMER_D
13502 * @arg @ref LL_HRTIM_TIMER_E
13503 * @arg @ref LL_HRTIM_TIMER_F
13504 * @retval None
13505 */
13507 {
13509 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13512 }
13514 /**
13515 * @brief Disable the output 1 set DMA request for a given timer.
13516 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
13517 * @param HRTIMx High Resolution Timer instance
13518 * @param Timer This parameter can be one of the following values:
13519 * @arg @ref LL_HRTIM_TIMER_A
13520 * @arg @ref LL_HRTIM_TIMER_B
13521 * @arg @ref LL_HRTIM_TIMER_C
13522 * @arg @ref LL_HRTIM_TIMER_D
13523 * @arg @ref LL_HRTIM_TIMER_E
13524 * @arg @ref LL_HRTIM_TIMER_F
13525 * @retval None
13526 */
13528 {
13530 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13533 }
13535 /**
13536 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
13537 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
13538 * @param HRTIMx High Resolution Timer instance
13539 * @param Timer This parameter can be one of the following values:
13540 * @arg @ref LL_HRTIM_TIMER_A
13541 * @arg @ref LL_HRTIM_TIMER_B
13542 * @arg @ref LL_HRTIM_TIMER_C
13543 * @arg @ref LL_HRTIM_TIMER_D
13544 * @arg @ref LL_HRTIM_TIMER_E
13545 * @arg @ref LL_HRTIM_TIMER_F
13546 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13547 */
13549 {
13551 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13555 }
13557 /**
13558 * @brief Enable the output 1 reset DMA request for a given timer.
13559 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
13560 * @param HRTIMx High Resolution Timer instance
13561 * @param Timer This parameter can be one of the following values:
13562 * @arg @ref LL_HRTIM_TIMER_A
13563 * @arg @ref LL_HRTIM_TIMER_B
13564 * @arg @ref LL_HRTIM_TIMER_C
13565 * @arg @ref LL_HRTIM_TIMER_D
13566 * @arg @ref LL_HRTIM_TIMER_E
13567 * @arg @ref LL_HRTIM_TIMER_F
13568 * @retval None
13569 */
13571 {
13573 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13576 }
13578 /**
13579 * @brief Disable the output 1 reset DMA request for a given timer.
13580 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
13581 * @param HRTIMx High Resolution Timer instance
13582 * @param Timer This parameter can be one of the following values:
13583 * @arg @ref LL_HRTIM_TIMER_A
13584 * @arg @ref LL_HRTIM_TIMER_B
13585 * @arg @ref LL_HRTIM_TIMER_C
13586 * @arg @ref LL_HRTIM_TIMER_D
13587 * @arg @ref LL_HRTIM_TIMER_E
13588 * @arg @ref LL_HRTIM_TIMER_F
13589 * @retval None
13590 */
13592 {
13594 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13597 }
13599 /**
13600 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
13601 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
13602 * @param HRTIMx High Resolution Timer instance
13603 * @param Timer This parameter can be one of the following values:
13604 * @arg @ref LL_HRTIM_TIMER_A
13605 * @arg @ref LL_HRTIM_TIMER_B
13606 * @arg @ref LL_HRTIM_TIMER_C
13607 * @arg @ref LL_HRTIM_TIMER_D
13608 * @arg @ref LL_HRTIM_TIMER_E
13609 * @arg @ref LL_HRTIM_TIMER_F
13610 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
13611 */
13613 {
13615 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13619 }
13621 /**
13622 * @brief Enable the output 2 set DMA request for a given timer.
13623 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
13624 * @param HRTIMx High Resolution Timer instance
13625 * @param Timer This parameter can be one of the following values:
13626 * @arg @ref LL_HRTIM_TIMER_A
13627 * @arg @ref LL_HRTIM_TIMER_B
13628 * @arg @ref LL_HRTIM_TIMER_C
13629 * @arg @ref LL_HRTIM_TIMER_D
13630 * @arg @ref LL_HRTIM_TIMER_E
13631 * @arg @ref LL_HRTIM_TIMER_F
13632 * @retval None
13633 */
13635 {
13637 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13640 }
13642 /**
13643 * @brief Disable the output 2 set DMA request for a given timer.
13644 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
13645 * @param HRTIMx High Resolution Timer instance
13646 * @param Timer This parameter can be one of the following values:
13647 * @arg @ref LL_HRTIM_TIMER_A
13648 * @arg @ref LL_HRTIM_TIMER_B
13649 * @arg @ref LL_HRTIM_TIMER_C
13650 * @arg @ref LL_HRTIM_TIMER_D
13651 * @arg @ref LL_HRTIM_TIMER_E
13652 * @arg @ref LL_HRTIM_TIMER_F
13653 * @retval None
13654 */
13656 {
13658 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13661 }
13663 /**
13664 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
13665 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
13666 * @param HRTIMx High Resolution Timer instance
13667 * @param Timer This parameter can be one of the following values:
13668 * @arg @ref LL_HRTIM_TIMER_A
13669 * @arg @ref LL_HRTIM_TIMER_B
13670 * @arg @ref LL_HRTIM_TIMER_C
13671 * @arg @ref LL_HRTIM_TIMER_D
13672 * @arg @ref LL_HRTIM_TIMER_E
13673 * @arg @ref LL_HRTIM_TIMER_F
13674 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13675 */
13677 {
13679 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13683 }
13685 /**
13686 * @brief Enable the output 2 reset DMA request for a given timer.
13687 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
13688 * @param HRTIMx High Resolution Timer instance
13689 * @param Timer This parameter can be one of the following values:
13690 * @arg @ref LL_HRTIM_TIMER_A
13691 * @arg @ref LL_HRTIM_TIMER_B
13692 * @arg @ref LL_HRTIM_TIMER_C
13693 * @arg @ref LL_HRTIM_TIMER_D
13694 * @arg @ref LL_HRTIM_TIMER_E
13695 * @arg @ref LL_HRTIM_TIMER_F
13696 * @retval None
13697 */
13699 {
13701 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13704 }
13706 /**
13707 * @brief Disable the output 2 reset DMA request for a given timer.
13708 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
13709 * @param HRTIMx High Resolution Timer instance
13710 * @param Timer This parameter can be one of the following values:
13711 * @arg @ref LL_HRTIM_TIMER_A
13712 * @arg @ref LL_HRTIM_TIMER_B
13713 * @arg @ref LL_HRTIM_TIMER_C
13714 * @arg @ref LL_HRTIM_TIMER_D
13715 * @arg @ref LL_HRTIM_TIMER_E
13716 * @arg @ref LL_HRTIM_TIMER_F
13717 * @retval None
13718 */
13720 {
13722 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13725 }
13727 /**
13728 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
13729 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
13730 * @param HRTIMx High Resolution Timer instance
13731 * @param Timer This parameter can be one of the following values:
13732 * @arg @ref LL_HRTIM_TIMER_A
13733 * @arg @ref LL_HRTIM_TIMER_B
13734 * @arg @ref LL_HRTIM_TIMER_C
13735 * @arg @ref LL_HRTIM_TIMER_D
13736 * @arg @ref LL_HRTIM_TIMER_E
13737 * @arg @ref LL_HRTIM_TIMER_F
13738 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
13739 */
13741 {
13743 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13747 }
13749 /**
13750 * @brief Enable the reset/roll-over DMA request for a given timer.
13751 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
13752 * @param HRTIMx High Resolution Timer instance
13753 * @param Timer This parameter can be one of the following values:
13754 * @arg @ref LL_HRTIM_TIMER_A
13755 * @arg @ref LL_HRTIM_TIMER_B
13756 * @arg @ref LL_HRTIM_TIMER_C
13757 * @arg @ref LL_HRTIM_TIMER_D
13758 * @arg @ref LL_HRTIM_TIMER_E
13759 * @arg @ref LL_HRTIM_TIMER_F
13760 * @retval None
13761 */
13763 {
13765 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13768 }
13770 /**
13771 * @brief Disable the reset/roll-over DMA request for a given timer.
13772 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
13773 * @param HRTIMx High Resolution Timer instance
13774 * @param Timer This parameter can be one of the following values:
13775 * @arg @ref LL_HRTIM_TIMER_A
13776 * @arg @ref LL_HRTIM_TIMER_B
13777 * @arg @ref LL_HRTIM_TIMER_C
13778 * @arg @ref LL_HRTIM_TIMER_D
13779 * @arg @ref LL_HRTIM_TIMER_E
13780 * @arg @ref LL_HRTIM_TIMER_F
13781 * @retval None
13782 */
13784 {
13786 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13789 }
13791 /**
13792 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
13793 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
13794 * @param HRTIMx High Resolution Timer instance
13795 * @param Timer This parameter can be one of the following values:
13796 * @arg @ref LL_HRTIM_TIMER_A
13797 * @arg @ref LL_HRTIM_TIMER_B
13798 * @arg @ref LL_HRTIM_TIMER_C
13799 * @arg @ref LL_HRTIM_TIMER_D
13800 * @arg @ref LL_HRTIM_TIMER_E
13801 * @arg @ref LL_HRTIM_TIMER_F
13802 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
13803 */
13805 {
13807 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13811 }
13813 /**
13814 * @brief Enable the delayed protection DMA request for a given timer.
13815 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
13816 * @param HRTIMx High Resolution Timer instance
13817 * @param Timer This parameter can be one of the following values:
13818 * @arg @ref LL_HRTIM_TIMER_A
13819 * @arg @ref LL_HRTIM_TIMER_B
13820 * @arg @ref LL_HRTIM_TIMER_C
13821 * @arg @ref LL_HRTIM_TIMER_D
13822 * @arg @ref LL_HRTIM_TIMER_E
13823 * @arg @ref LL_HRTIM_TIMER_F
13824 * @retval None
13825 */
13827 {
13829 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13832 }
13834 /**
13835 * @brief Disable the delayed protection DMA request for a given timer.
13836 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
13837 * @param HRTIMx High Resolution Timer instance
13838 * @param Timer This parameter can be one of the following values:
13839 * @arg @ref LL_HRTIM_TIMER_A
13840 * @arg @ref LL_HRTIM_TIMER_B
13841 * @arg @ref LL_HRTIM_TIMER_C
13842 * @arg @ref LL_HRTIM_TIMER_D
13843 * @arg @ref LL_HRTIM_TIMER_E
13844 * @arg @ref LL_HRTIM_TIMER_F
13845 * @retval None
13846 */
13848 {
13850 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13853 }
13855 /**
13856 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
13857 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
13858 * @param HRTIMx High Resolution Timer instance
13859 * @param Timer This parameter can be one of the following values:
13860 * @arg @ref LL_HRTIM_TIMER_A
13861 * @arg @ref LL_HRTIM_TIMER_B
13862 * @arg @ref LL_HRTIM_TIMER_C
13863 * @arg @ref LL_HRTIM_TIMER_D
13864 * @arg @ref LL_HRTIM_TIMER_E
13865 * @arg @ref LL_HRTIM_TIMER_F
13866 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
13867 */
13868 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
13869 {
13871 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
13875 }
13877 /**
13878 * @}
13879 */
13881 #if defined(USE_FULL_LL_DRIVER)
13882 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
13883 * @{
13884 */
13886 /**
13887 * @}
13888 */
13891 /**
13892 * @}
13893 */
13895 /**
13896 * @}
13897 */
13901 /**
13902 * @}
13903 */
13905 #ifdef __cplusplus
13906 }
13907 #endif
13911 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/