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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_lptim.h
blobb49a6caee62cfd6180d61fe7242ba5dab8022b31
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_lptim.h
4 * @author MCD Application Team
5 * @brief Header file of LPTIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_LPTIM_H
22 #define STM32G4xx_LL_LPTIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35
36
37 /** @defgroup LPTIM_LL LPTIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47 #if defined(USE_FULL_LL_DRIVER)
48 /** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
49 * @{
50 */
51 /**
52 * @}
53 */
54 #endif /*USE_FULL_LL_DRIVER*/
55
56 /* Exported types ------------------------------------------------------------*/
57 #if defined(USE_FULL_LL_DRIVER)
58 /** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
59 * @{
60 */
61
62 /**
63 * @brief LPTIM Init structure definition
64 */
65 typedef struct
66 {
67 uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
68 This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
69
70 This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/
71
72 uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
73 This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
74
75 This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/
76
77 uint32_t Waveform; /*!< Specifies the waveform shape.
78 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
79
80 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
81
82 uint32_t Polarity; /*!< Specifies waveform polarity.
83 This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
84
85 This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/
86 } LL_LPTIM_InitTypeDef;
87
88 /**
89 * @}
90 */
91 #endif /* USE_FULL_LL_DRIVER */
92
93 /* Exported constants --------------------------------------------------------*/
94 /** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
95 * @{
96 */
97
98 /** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
99 * @brief Flags defines which can be used with LL_LPTIM_ReadReg function
100 * @{
101 */
102 #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
103 #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
104 #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
105 #define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
106 #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
107 #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
108 #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
109 /**
110 * @}
111 */
112
113 /** @defgroup LPTIM_LL_EC_IT IT Defines
114 * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
115 * @{
116 */
117 #define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */
118 #define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */
119 #define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */
120 #define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */
121 #define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */
122 #define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */
123 #define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */
124 /**
125 * @}
126 */
127
128 /** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
129 * @{
130 */
131 #define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
132 #define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
133 /**
134 * @}
135 */
136
137 /** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
138 * @{
139 */
140 #define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
141 #define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
142 /**
143 * @}
144 */
145
146 /** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
147 * @{
148 */
149 #define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
150 #define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
151 /**
152 * @}
153 */
154
155 /** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
156 * @{
157 */
158 #define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/
159 #define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
160 /**
161 * @}
162 */
163
164 /** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
165 * @{
166 */
167 #define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
168 #define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
169 /**
170 * @}
171 */
172
173 /** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
174 * @{
175 */
176 #define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
177 #define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
178 #define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
179 #define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
180 #define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
181 #define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
182 #define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
183 #define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
184 /**
185 * @}
186 */
187
188 /** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
189 * @{
190 */
191 #define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
192 #define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
193 #define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
194 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
195 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
196 #define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
197 #define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
198 #define LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP2 output*/
199 #define LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3 /*!<External input trigger is connected to COMP3 output*/
200 #define LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP4 output*/
201 #if defined(COMP5)
202 #define LL_LPTIM_TRIG_SOURCE_COMP5 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP5 output*/
203 #endif /* COMP5 */
204 #if defined(COMP6)
205 #define LL_LPTIM_TRIG_SOURCE_COMP6 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP6 output*/
206 #endif /* COMP6 */
207 #if defined(COMP7)
208 #define LL_LPTIM_TRIG_SOURCE_COMP7 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_2) /*!<External input trigger is connected to COMP7 output*/
209 #endif /* COMP7 */
210 /**
211 * @}
212 */
213
214 /** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
215 * @{
216 */
217 #define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
218 #define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
219 #define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
220 #define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
221 /**
222 * @}
223 */
224
225 /** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
226 * @{
227 */
228 #define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
229 #define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
230 #define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
231 /**
232 * @}
233 */
234
235 /** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
236 * @{
237 */
238 #define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
239 #define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
240 /**
241 * @}
242 */
243
244 /** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
245 * @{
246 */
247 #define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
248 #define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
249 #define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
250 #define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
251 /**
252 * @}
253 */
254
255 /** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
256 * @{
257 */
258 #define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
259 #define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
260 #define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
261 /**
262 * @}
263 */
264
265 /** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
266 * @{
267 */
268 #define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
269 #define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
270 #define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
271 /**
272 * @}
273 */
274
275 /** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
276 * @{
277 */
278 #define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
279 #define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
280 #define LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
281 #if defined(COMP5)
282 #define LL_LPTIM_INPUT1_SRC_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
283 #endif /* COMP5 */
284 #if defined(COMP7)
285 #define LL_LPTIM_INPUT1_SRC_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
286 #endif /* COMP7 */
287 /**
288 * @}
289 */
290
291 /** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
292 * @{
293 */
294 #define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
295 #define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
296 #define LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
297 #if defined(COMP6)
298 #define LL_LPTIM_INPUT2_SRC_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
299 #endif /* COMP6 */
300 /**
301 * @}
302 */
303
304
305 /**
306 * @}
307 */
308
309 /* Exported macro ------------------------------------------------------------*/
310 /** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
311 * @{
312 */
313
314 /** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
315 * @{
316 */
317
318 /**
319 * @brief Write a value in LPTIM register
320 * @param __INSTANCE__ LPTIM Instance
321 * @param __REG__ Register to be written
322 * @param __VALUE__ Value to be written in the register
323 * @retval None
324 */
325 #define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
326
327 /**
328 * @brief Read a value in LPTIM register
329 * @param __INSTANCE__ LPTIM Instance
330 * @param __REG__ Register to be read
331 * @retval Register value
332 */
333 #define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
334 /**
335 * @}
336 */
337
338 /**
339 * @}
340 */
341
342 /* Exported functions --------------------------------------------------------*/
343 /** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
344 * @{
345 */
346
347 #if defined(USE_FULL_LL_DRIVER)
348 /** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
349 * @{
350 */
351
352 ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
353 void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
354 ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
355 void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
356 /**
357 * @}
358 */
359 #endif /* USE_FULL_LL_DRIVER */
360
361 /** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
362 * @{
363 */
364
365 /**
366 * @brief Enable the LPTIM instance
367 * @note After setting the ENABLE bit, a delay of two counter clock is needed
368 * before the LPTIM instance is actually enabled.
369 * @rmtoll CR ENABLE LL_LPTIM_Enable
370 * @param LPTIMx Low-Power Timer instance
371 * @retval None
372 */
373 __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
374 {
375 SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
376 }
377
378 /**
379 * @brief Indicates whether the LPTIM instance is enabled.
380 * @rmtoll CR ENABLE LL_LPTIM_IsEnabled
381 * @param LPTIMx Low-Power Timer instance
382 * @retval State of bit (1 or 0).
383 */
384 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
385 {
386 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE)? 1UL : 0UL));
387 }
388
389 /**
390 * @brief Starts the LPTIM counter in the desired mode.
391 * @note LPTIM instance must be enabled before starting the counter.
392 * @note It is possible to change on the fly from One Shot mode to
393 * Continuous mode.
394 * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
395 * CR SNGSTRT LL_LPTIM_StartCounter
396 * @param LPTIMx Low-Power Timer instance
397 * @param OperatingMode This parameter can be one of the following values:
398 * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
399 * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
400 * @retval None
401 */
402 __STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
403 {
404 MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
405 }
406
407 /**
408 * @brief Enable reset after read.
409 * @note After calling this function any read access to LPTIM_CNT
410 * register will asynchronously reset the LPTIM_CNT register content.
411 * @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
412 * @param LPTIMx Low-Power Timer instance
413 * @retval None
414 */
415 __STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
416 {
417 SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
418 }
419
420 /**
421 * @brief Disable reset after read.
422 * @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
423 * @param LPTIMx Low-Power Timer instance
424 * @retval None
425 */
426 __STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
427 {
428 CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
429 }
430
431 /**
432 * @brief Indicate whether the reset after read feature is enabled.
433 * @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
434 * @param LPTIMx Low-Power Timer instance
435 * @retval State of bit (1 or 0).
436 */
437 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
438 {
439 return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE)? 1UL : 0UL));
440 }
441
442 /**
443 * @brief Reset of the LPTIM_CNT counter register (synchronous).
444 * @note Due to the synchronous nature of this reset, it only takes
445 * place after a synchronization delay of 3 LPTIM core clock cycles
446 * (LPTIM core clock may be different from APB clock).
447 * @note COUNTRST is automatically cleared by hardware
448 * @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
449 * @param LPTIMx Low-Power Timer instance
450 * @retval None
451 */
452 __STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
453 {
454 SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
455 }
456
457 /**
458 * @brief Set the LPTIM registers update mode (enable/disable register preload)
459 * @note This function must be called when the LPTIM instance is disabled.
460 * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
461 * @param LPTIMx Low-Power Timer instance
462 * @param UpdateMode This parameter can be one of the following values:
463 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
464 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
465 * @retval None
466 */
467 __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
468 {
469 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
470 }
471
472 /**
473 * @brief Get the LPTIM registers update mode
474 * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
475 * @param LPTIMx Low-Power Timer instance
476 * @retval Returned value can be one of the following values:
477 * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
478 * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
479 */
480 __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
481 {
482 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
483 }
484
485 /**
486 * @brief Set the auto reload value
487 * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
488 * @note After a write to the LPTIMx_ARR register a new write operation to the
489 * same register can only be performed when the previous write operation
490 * is completed. Any successive write before the ARROK flag be set, will
491 * lead to unpredictable results.
492 * @note autoreload value be strictly greater than the compare value.
493 * @rmtoll ARR ARR LL_LPTIM_SetAutoReload
494 * @param LPTIMx Low-Power Timer instance
495 * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
496 * @retval None
497 */
498 __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
499 {
500 MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
501 }
502
503 /**
504 * @brief Get actual auto reload value
505 * @rmtoll ARR ARR LL_LPTIM_GetAutoReload
506 * @param LPTIMx Low-Power Timer instance
507 * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
508 */
509 __STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
510 {
511 return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
512 }
513
514 /**
515 * @brief Set the compare value
516 * @note After a write to the LPTIMx_CMP register a new write operation to the
517 * same register can only be performed when the previous write operation
518 * is completed. Any successive write before the CMPOK flag be set, will
519 * lead to unpredictable results.
520 * @rmtoll CMP CMP LL_LPTIM_SetCompare
521 * @param LPTIMx Low-Power Timer instance
522 * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
523 * @retval None
524 */
525 __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
526 {
527 MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
528 }
529
530 /**
531 * @brief Get actual compare value
532 * @rmtoll CMP CMP LL_LPTIM_GetCompare
533 * @param LPTIMx Low-Power Timer instance
534 * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
535 */
536 __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
537 {
538 return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
539 }
540
541 /**
542 * @brief Get actual counter value
543 * @note When the LPTIM instance is running with an asynchronous clock, reading
544 * the LPTIMx_CNT register may return unreliable values. So in this case
545 * it is necessary to perform two consecutive read accesses and verify
546 * that the two returned values are identical.
547 * @rmtoll CNT CNT LL_LPTIM_GetCounter
548 * @param LPTIMx Low-Power Timer instance
549 * @retval Counter value
550 */
551 __STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
552 {
553 return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
554 }
555
556 /**
557 * @brief Set the counter mode (selection of the LPTIM counter clock source).
558 * @note The counter mode can be set only when the LPTIM instance is disabled.
559 * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
560 * @param LPTIMx Low-Power Timer instance
561 * @param CounterMode This parameter can be one of the following values:
562 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
563 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
564 * @retval None
565 */
566 __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
567 {
568 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
569 }
570
571 /**
572 * @brief Get the counter mode
573 * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
574 * @param LPTIMx Low-Power Timer instance
575 * @retval Returned value can be one of the following values:
576 * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
577 * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
578 */
579 __STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
580 {
581 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
582 }
583
584 /**
585 * @brief Configure the LPTIM instance output (LPTIMx_OUT)
586 * @note This function must be called when the LPTIM instance is disabled.
587 * @note Regarding the LPTIM output polarity the change takes effect
588 * immediately, so the output default value will change immediately after
589 * the polarity is re-configured, even before the timer is enabled.
590 * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
591 * CFGR WAVPOL LL_LPTIM_ConfigOutput
592 * @param LPTIMx Low-Power Timer instance
593 * @param Waveform This parameter can be one of the following values:
594 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
595 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
596 * @param Polarity This parameter can be one of the following values:
597 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
598 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
599 * @retval None
600 */
601 __STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
602 {
603 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
604 }
605
606 /**
607 * @brief Set waveform shape
608 * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
609 * @param LPTIMx Low-Power Timer instance
610 * @param Waveform This parameter can be one of the following values:
611 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
612 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
613 * @retval None
614 */
615 __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
616 {
617 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
618 }
619
620 /**
621 * @brief Get actual waveform shape
622 * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
623 * @param LPTIMx Low-Power Timer instance
624 * @retval Returned value can be one of the following values:
625 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
626 * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
627 */
628 __STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
629 {
630 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
631 }
632
633 /**
634 * @brief Set output polarity
635 * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
636 * @param LPTIMx Low-Power Timer instance
637 * @param Polarity This parameter can be one of the following values:
638 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
639 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
640 * @retval None
641 */
642 __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
643 {
644 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
645 }
646
647 /**
648 * @brief Get actual output polarity
649 * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
650 * @param LPTIMx Low-Power Timer instance
651 * @retval Returned value can be one of the following values:
652 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
653 * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
654 */
655 __STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
656 {
657 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
658 }
659
660 /**
661 * @brief Set actual prescaler division ratio.
662 * @note This function must be called when the LPTIM instance is disabled.
663 * @note When the LPTIM is configured to be clocked by an internal clock source
664 * and the LPTIM counter is configured to be updated by active edges
665 * detected on the LPTIM external Input1, the internal clock provided to
666 * the LPTIM must be not be prescaled.
667 * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
668 * @param LPTIMx Low-Power Timer instance
669 * @param Prescaler This parameter can be one of the following values:
670 * @arg @ref LL_LPTIM_PRESCALER_DIV1
671 * @arg @ref LL_LPTIM_PRESCALER_DIV2
672 * @arg @ref LL_LPTIM_PRESCALER_DIV4
673 * @arg @ref LL_LPTIM_PRESCALER_DIV8
674 * @arg @ref LL_LPTIM_PRESCALER_DIV16
675 * @arg @ref LL_LPTIM_PRESCALER_DIV32
676 * @arg @ref LL_LPTIM_PRESCALER_DIV64
677 * @arg @ref LL_LPTIM_PRESCALER_DIV128
678 * @retval None
679 */
680 __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
681 {
682 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
683 }
684
685 /**
686 * @brief Get actual prescaler division ratio.
687 * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
688 * @param LPTIMx Low-Power Timer instance
689 * @retval Returned value can be one of the following values:
690 * @arg @ref LL_LPTIM_PRESCALER_DIV1
691 * @arg @ref LL_LPTIM_PRESCALER_DIV2
692 * @arg @ref LL_LPTIM_PRESCALER_DIV4
693 * @arg @ref LL_LPTIM_PRESCALER_DIV8
694 * @arg @ref LL_LPTIM_PRESCALER_DIV16
695 * @arg @ref LL_LPTIM_PRESCALER_DIV32
696 * @arg @ref LL_LPTIM_PRESCALER_DIV64
697 * @arg @ref LL_LPTIM_PRESCALER_DIV128
698 */
699 __STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
700 {
701 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
702 }
703
704 /**
705 * @brief Set LPTIM input 1 source (default GPIO).
706 * @rmtoll OR IN1 LL_LPTIM_SetInput1Src
707 * @param LPTIMx Low-Power Timer instance
708 * @param Src This parameter can be one of the following values:
709 * @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
710 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
711 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP3
712 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP5 (*)
713 * @arg @ref LL_LPTIM_INPUT1_SRC_COMP7 (*)
714 * (*) Value not defined for all devices
715 * @retval None
716 */
717 __STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
718 {
719 WRITE_REG(LPTIMx->OR, Src);
720 }
721
722 /**
723 * @brief Set LPTIM input 2 source (default GPIO).
724 * @rmtoll OR IN2 LL_LPTIM_SetInput2Src
725 * @param LPTIMx Low-Power Timer instance
726 * @param Src This parameter can be one of the following values:
727 * @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
728 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
729 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP4
730 * @arg @ref LL_LPTIM_INPUT2_SRC_COMP6 (*)
731 * (*) Value not defined for all devices
732 * @retval None
733 */
734 __STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
735 {
736 WRITE_REG(LPTIMx->OR, Src);
737 }
738
739 /**
740 * @}
741 */
742
743 /** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
744 * @{
745 */
746
747 /**
748 * @brief Enable the timeout function
749 * @note This function must be called when the LPTIM instance is disabled.
750 * @note The first trigger event will start the timer, any successive trigger
751 * event will reset the counter and the timer will restart.
752 * @note The timeout value corresponds to the compare value; if no trigger
753 * occurs within the expected time frame, the MCU is waked-up by the
754 * compare match event.
755 * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
756 * @param LPTIMx Low-Power Timer instance
757 * @retval None
758 */
759 __STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
760 {
761 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
762 }
763
764 /**
765 * @brief Disable the timeout function
766 * @note This function must be called when the LPTIM instance is disabled.
767 * @note A trigger event arriving when the timer is already started will be
768 * ignored.
769 * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
770 * @param LPTIMx Low-Power Timer instance
771 * @retval None
772 */
773 __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
774 {
775 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
776 }
777
778 /**
779 * @brief Indicate whether the timeout function is enabled.
780 * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
781 * @param LPTIMx Low-Power Timer instance
782 * @retval State of bit (1 or 0).
783 */
784 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
785 {
786 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT)? 1UL : 0UL));
787 }
788
789 /**
790 * @brief Start the LPTIM counter
791 * @note This function must be called when the LPTIM instance is disabled.
792 * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
793 * @param LPTIMx Low-Power Timer instance
794 * @retval None
795 */
796 __STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
797 {
798 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
799 }
800
801 /**
802 * @brief Configure the external trigger used as a trigger event for the LPTIM.
803 * @note This function must be called when the LPTIM instance is disabled.
804 * @note An internal clock source must be present when a digital filter is
805 * required for the trigger.
806 * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
807 * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
808 * CFGR TRIGEN LL_LPTIM_ConfigTrigger
809 * @param LPTIMx Low-Power Timer instance
810 * @param Source This parameter can be one of the following values:
811 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
812 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
813 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
814 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
815 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
816 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
817 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
818 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
819 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
820 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
821 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
822 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
823 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
824 *
825 * (*) Value not defined in all devices. \n
826 *
827 * @param Filter This parameter can be one of the following values:
828 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
829 * @arg @ref LL_LPTIM_TRIG_FILTER_2
830 * @arg @ref LL_LPTIM_TRIG_FILTER_4
831 * @arg @ref LL_LPTIM_TRIG_FILTER_8
832 * @param Polarity This parameter can be one of the following values:
833 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
834 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
835 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
836 * @retval None
837 */
838 __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
839 {
840 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
841 }
842
843 /**
844 * @brief Get actual external trigger source.
845 * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
846 * @param LPTIMx Low-Power Timer instance
847 * @retval Returned value can be one of the following values:
848 * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
849 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
850 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
851 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
852 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
853 * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
854 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
855 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
856 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
857 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
858 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
859 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
860 * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
861 *
862 * (*) Value not defined in all devices. \n
863 */
864 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
865 {
866 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
867 }
868
869 /**
870 * @brief Get actual external trigger filter.
871 * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
872 * @param LPTIMx Low-Power Timer instance
873 * @retval Returned value can be one of the following values:
874 * @arg @ref LL_LPTIM_TRIG_FILTER_NONE
875 * @arg @ref LL_LPTIM_TRIG_FILTER_2
876 * @arg @ref LL_LPTIM_TRIG_FILTER_4
877 * @arg @ref LL_LPTIM_TRIG_FILTER_8
878 */
879 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
880 {
881 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
882 }
883
884 /**
885 * @brief Get actual external trigger polarity.
886 * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
887 * @param LPTIMx Low-Power Timer instance
888 * @retval Returned value can be one of the following values:
889 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
890 * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
891 * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
892 */
893 __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
894 {
895 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
896 }
897
898 /**
899 * @}
900 */
901
902 /** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
903 * @{
904 */
905
906 /**
907 * @brief Set the source of the clock used by the LPTIM instance.
908 * @note This function must be called when the LPTIM instance is disabled.
909 * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
910 * @param LPTIMx Low-Power Timer instance
911 * @param ClockSource This parameter can be one of the following values:
912 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
913 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
914 * @retval None
915 */
916 __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
917 {
918 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
919 }
920
921 /**
922 * @brief Get actual LPTIM instance clock source.
923 * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
924 * @param LPTIMx Low-Power Timer instance
925 * @retval Returned value can be one of the following values:
926 * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
927 * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
928 */
929 __STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
930 {
931 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
932 }
933
934 /**
935 * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.
936 * @note This function must be called when the LPTIM instance is disabled.
937 * @note When both external clock signal edges are considered active ones,
938 * the LPTIM must also be clocked by an internal clock source with a
939 * frequency equal to at least four times the external clock frequency.
940 * @note An internal clock source must be present when a digital filter is
941 * required for external clock.
942 * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
943 * CFGR CKPOL LL_LPTIM_ConfigClock
944 * @param LPTIMx Low-Power Timer instance
945 * @param ClockFilter This parameter can be one of the following values:
946 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
947 * @arg @ref LL_LPTIM_CLK_FILTER_2
948 * @arg @ref LL_LPTIM_CLK_FILTER_4
949 * @arg @ref LL_LPTIM_CLK_FILTER_8
950 * @param ClockPolarity This parameter can be one of the following values:
951 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
952 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
953 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
954 * @retval None
955 */
956 __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
957 {
958 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
959 }
960
961 /**
962 * @brief Get actual clock polarity
963 * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
964 * @param LPTIMx Low-Power Timer instance
965 * @retval Returned value can be one of the following values:
966 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING
967 * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
968 * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
969 */
970 __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
971 {
972 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
973 }
974
975 /**
976 * @brief Get actual clock digital filter
977 * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
978 * @param LPTIMx Low-Power Timer instance
979 * @retval Returned value can be one of the following values:
980 * @arg @ref LL_LPTIM_CLK_FILTER_NONE
981 * @arg @ref LL_LPTIM_CLK_FILTER_2
982 * @arg @ref LL_LPTIM_CLK_FILTER_4
983 * @arg @ref LL_LPTIM_CLK_FILTER_8
984 */
985 __STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
986 {
987 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
988 }
989
990 /**
991 * @}
992 */
993
994 /** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
995 * @{
996 */
997
998 /**
999 * @brief Configure the encoder mode.
1000 * @note This function must be called when the LPTIM instance is disabled.
1001 * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
1002 * @param LPTIMx Low-Power Timer instance
1003 * @param EncoderMode This parameter can be one of the following values:
1004 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1005 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1006 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1007 * @retval None
1008 */
1009 __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
1010 {
1011 MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
1012 }
1013
1014 /**
1015 * @brief Get actual encoder mode.
1016 * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
1017 * @param LPTIMx Low-Power Timer instance
1018 * @retval Returned value can be one of the following values:
1019 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING
1020 * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
1021 * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
1022 */
1023 __STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
1024 {
1025 return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
1026 }
1027
1028 /**
1029 * @brief Enable the encoder mode
1030 * @note This function must be called when the LPTIM instance is disabled.
1031 * @note In this mode the LPTIM instance must be clocked by an internal clock
1032 * source. Also, the prescaler division ratio must be equal to 1.
1033 * @note LPTIM instance must be configured in continuous mode prior enabling
1034 * the encoder mode.
1035 * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
1036 * @param LPTIMx Low-Power Timer instance
1037 * @retval None
1038 */
1039 __STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
1040 {
1041 SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1042 }
1043
1044 /**
1045 * @brief Disable the encoder mode
1046 * @note This function must be called when the LPTIM instance is disabled.
1047 * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
1048 * @param LPTIMx Low-Power Timer instance
1049 * @retval None
1050 */
1051 __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
1052 {
1053 CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
1054 }
1055
1056 /**
1057 * @brief Indicates whether the LPTIM operates in encoder mode.
1058 * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
1059 * @param LPTIMx Low-Power Timer instance
1060 * @retval State of bit (1 or 0).
1061 */
1062 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
1063 {
1064 return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC)? 1UL : 0UL));
1065 }
1066
1067 /**
1068 * @}
1069 */
1070
1071 /** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
1072 * @{
1073 */
1074
1075 /**
1076 * @brief Clear the compare match flag (CMPMCF)
1077 * @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
1078 * @param LPTIMx Low-Power Timer instance
1079 * @retval None
1080 */
1081 __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
1082 {
1083 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
1084 }
1085
1086 /**
1087 * @brief Inform application whether a compare match interrupt has occurred.
1088 * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
1089 * @param LPTIMx Low-Power Timer instance
1090 * @retval State of bit (1 or 0).
1091 */
1092 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
1093 {
1094 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM)? 1UL : 0UL));
1095 }
1096
1097 /**
1098 * @brief Clear the autoreload match flag (ARRMCF)
1099 * @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
1100 * @param LPTIMx Low-Power Timer instance
1101 * @retval None
1102 */
1103 __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
1104 {
1105 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
1106 }
1107
1108 /**
1109 * @brief Inform application whether a autoreload match interrupt has occured.
1110 * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
1111 * @param LPTIMx Low-Power Timer instance
1112 * @retval State of bit (1 or 0).
1113 */
1114 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
1115 {
1116 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM)? 1UL : 0UL));
1117 }
1118
1119 /**
1120 * @brief Clear the external trigger valid edge flag(EXTTRIGCF).
1121 * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
1122 * @param LPTIMx Low-Power Timer instance
1123 * @retval None
1124 */
1125 __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1126 {
1127 SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
1128 }
1129
1130 /**
1131 * @brief Inform application whether a valid edge on the selected external trigger input has occurred.
1132 * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
1133 * @param LPTIMx Low-Power Timer instance
1134 * @retval State of bit (1 or 0).
1135 */
1136 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1137 {
1138 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG)? 1UL : 0UL));
1139 }
1140
1141 /**
1142 * @brief Clear the compare register update interrupt flag (CMPOKCF).
1143 * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
1144 * @param LPTIMx Low-Power Timer instance
1145 * @retval None
1146 */
1147 __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1148 {
1149 SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
1150 }
1151
1152 /**
1153 * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.
1154 * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
1155 * @param LPTIMx Low-Power Timer instance
1156 * @retval State of bit (1 or 0).
1157 */
1158 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
1159 {
1160 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK)? 1UL : 0UL));
1161 }
1162
1163 /**
1164 * @brief Clear the autoreload register update interrupt flag (ARROKCF).
1165 * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
1166 * @param LPTIMx Low-Power Timer instance
1167 * @retval None
1168 */
1169 __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1170 {
1171 SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
1172 }
1173
1174 /**
1175 * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.
1176 * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
1177 * @param LPTIMx Low-Power Timer instance
1178 * @retval State of bit (1 or 0).
1179 */
1180 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
1181 {
1182 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK)? 1UL : 0UL));
1183 }
1184
1185 /**
1186 * @brief Clear the counter direction change to up interrupt flag (UPCF).
1187 * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
1188 * @param LPTIMx Low-Power Timer instance
1189 * @retval None
1190 */
1191 __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
1192 {
1193 SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
1194 }
1195
1196 /**
1197 * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).
1198 * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
1199 * @param LPTIMx Low-Power Timer instance
1200 * @retval State of bit (1 or 0).
1201 */
1202 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
1203 {
1204 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP)? 1UL : 0UL));
1205 }
1206
1207 /**
1208 * @brief Clear the counter direction change to down interrupt flag (DOWNCF).
1209 * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
1210 * @param LPTIMx Low-Power Timer instance
1211 * @retval None
1212 */
1213 __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1214 {
1215 SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
1216 }
1217
1218 /**
1219 * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).
1220 * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
1221 * @param LPTIMx Low-Power Timer instance
1222 * @retval State of bit (1 or 0).
1223 */
1224 __STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
1225 {
1226 return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN)? 1UL : 0UL));
1227 }
1228
1229 /**
1230 * @}
1231 */
1232
1233 /** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
1234 * @{
1235 */
1236
1237 /**
1238 * @brief Enable compare match interrupt (CMPMIE).
1239 * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
1240 * @param LPTIMx Low-Power Timer instance
1241 * @retval None
1242 */
1243 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1244 {
1245 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1246 }
1247
1248 /**
1249 * @brief Disable compare match interrupt (CMPMIE).
1250 * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
1251 * @param LPTIMx Low-Power Timer instance
1252 * @retval None
1253 */
1254 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
1255 {
1256 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
1257 }
1258
1259 /**
1260 * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
1261 * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
1262 * @param LPTIMx Low-Power Timer instance
1263 * @retval State of bit (1 or 0).
1264 */
1265 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
1266 {
1267 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE)? 1UL : 0UL));
1268 }
1269
1270 /**
1271 * @brief Enable autoreload match interrupt (ARRMIE).
1272 * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
1273 * @param LPTIMx Low-Power Timer instance
1274 * @retval None
1275 */
1276 __STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1277 {
1278 SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1279 }
1280
1281 /**
1282 * @brief Disable autoreload match interrupt (ARRMIE).
1283 * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
1284 * @param LPTIMx Low-Power Timer instance
1285 * @retval None
1286 */
1287 __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
1288 {
1289 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
1290 }
1291
1292 /**
1293 * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
1294 * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
1295 * @param LPTIMx Low-Power Timer instance
1296 * @retval State of bit (1 or 0).
1297 */
1298 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
1299 {
1300 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE)? 1UL : 0UL));
1301 }
1302
1303 /**
1304 * @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
1305 * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
1306 * @param LPTIMx Low-Power Timer instance
1307 * @retval None
1308 */
1309 __STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1310 {
1311 SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1312 }
1313
1314 /**
1315 * @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
1316 * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
1317 * @param LPTIMx Low-Power Timer instance
1318 * @retval None
1319 */
1320 __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1321 {
1322 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
1323 }
1324
1325 /**
1326 * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
1327 * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
1328 * @param LPTIMx Low-Power Timer instance
1329 * @retval State of bit (1 or 0).
1330 */
1331 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
1332 {
1333 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE)? 1UL : 0UL));
1334 }
1335
1336 /**
1337 * @brief Enable compare register write completed interrupt (CMPOKIE).
1338 * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
1339 * @param LPTIMx Low-Power Timer instance
1340 * @retval None
1341 */
1342 __STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1343 {
1344 SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1345 }
1346
1347 /**
1348 * @brief Disable compare register write completed interrupt (CMPOKIE).
1349 * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
1350 * @param LPTIMx Low-Power Timer instance
1351 * @retval None
1352 */
1353 __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1354 {
1355 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
1356 }
1357
1358 /**
1359 * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
1360 * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
1361 * @param LPTIMx Low-Power Timer instance
1362 * @retval State of bit (1 or 0).
1363 */
1364 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
1365 {
1366 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE)? 1UL : 0UL));
1367 }
1368
1369 /**
1370 * @brief Enable autoreload register write completed interrupt (ARROKIE).
1371 * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
1372 * @param LPTIMx Low-Power Timer instance
1373 * @retval None
1374 */
1375 __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1376 {
1377 SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1378 }
1379
1380 /**
1381 * @brief Disable autoreload register write completed interrupt (ARROKIE).
1382 * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
1383 * @param LPTIMx Low-Power Timer instance
1384 * @retval None
1385 */
1386 __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
1387 {
1388 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
1389 }
1390
1391 /**
1392 * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
1393 * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
1394 * @param LPTIMx Low-Power Timer instance
1395 * @retval State of bit (1 or 0).
1396 */
1397 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
1398 {
1399 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE)? 1UL : 0UL));
1400 }
1401
1402 /**
1403 * @brief Enable direction change to up interrupt (UPIE).
1404 * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
1405 * @param LPTIMx Low-Power Timer instance
1406 * @retval None
1407 */
1408 __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
1409 {
1410 SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1411 }
1412
1413 /**
1414 * @brief Disable direction change to up interrupt (UPIE).
1415 * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
1416 * @param LPTIMx Low-Power Timer instance
1417 * @retval None
1418 */
1419 __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
1420 {
1421 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
1422 }
1423
1424 /**
1425 * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
1426 * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
1427 * @param LPTIMx Low-Power Timer instance
1428 * @retval State of bit (1 or 0).
1429 */
1430 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
1431 {
1432 return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE)? 1UL : 0UL));
1433 }
1434
1435 /**
1436 * @brief Enable direction change to down interrupt (DOWNIE).
1437 * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
1438 * @param LPTIMx Low-Power Timer instance
1439 * @retval None
1440 */
1441 __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1442 {
1443 SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1444 }
1445
1446 /**
1447 * @brief Disable direction change to down interrupt (DOWNIE).
1448 * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
1449 * @param LPTIMx Low-Power Timer instance
1450 * @retval None
1451 */
1452 __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
1453 {
1454 CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
1455 }
1456
1457 /**
1458 * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
1459 * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
1460 * @param LPTIMx Low-Power Timer instance
1461 * @retval State of bit (1 or 0).
1462 */
1463 __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
1464 {
1465 return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE)? 1UL : 0UL);
1466 }
1467
1468 /**
1469 * @}
1470 */
1471
1472 /**
1473 * @}
1474 */
1475
1476 /**
1477 * @}
1478 */
1479
1480
1481
1482 /**
1483 * @}
1484 */
1485
1486 #ifdef __cplusplus
1487 }
1488 #endif
1489
1490 #endif /* STM32G4xx_LL_LPTIM_H */
1491
1492 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/