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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_pwr.h
blob4224b5c39fdfc925bfc4ee47f5516d47ba330a98
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_PWR_H
22 #define STM32G4xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47
48 /* Exported types ------------------------------------------------------------*/
49 /* Exported constants --------------------------------------------------------*/
50 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
51 * @{
52 */
53
54 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
55 * @brief Flags defines which can be used with LL_PWR_WriteReg function
56 * @{
57 */
58 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
59 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
60 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
61 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
62 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
63 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
64 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
74 #define LL_PWR_SR1_SBF PWR_SR1_SBF
75 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
76 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
77 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
78 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
79 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
80 #if defined(PWR_SR2_PVMO4)
81 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
82 #endif /* PWR_SR2_PVMO4 */
83 #if defined(PWR_SR2_PVMO3)
84 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
85 #endif /* PWR_SR2_PVMO3 */
86 #if defined(PWR_SR2_PVMO2)
87 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
88 #endif /* PWR_SR2_PVMO2 */
89 #if defined(PWR_SR2_PVMO1)
90 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
91 #endif /* PWR_SR2_PVMO1 */
92 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
93 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
94 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
95 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
96 /**
97 * @}
98 */
99
100 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
101 * @{
102 */
103 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
104 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
105 /**
106 * @}
107 */
108
109 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
110 * @{
111 */
112 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
113 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
114 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
115 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
116 /**
117 * @}
118 */
119
120 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
121 * @{
122 */
123 #if defined(PWR_CR2_PVME1)
124 #define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
125 #endif
126 #if defined(PWR_CR2_PVME2)
127 #define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
128 #endif
129 #if defined(PWR_CR2_PVME3)
130 #define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
131 #endif
132 #if defined(PWR_CR2_PVME4)
133 #define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
134 #endif
135 /**
136 * @}
137 */
138
139 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
140 * @{
141 */
142 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
143 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
144 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
145 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
146 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
147 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
148 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
149 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
150 /**
151 * @}
152 */
153
154 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
155 * @{
156 */
157 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
158 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
159 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
160 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
161 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
162 /**
163 * @}
164 */
165
166 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
167 * @{
168 */
169 #define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
170 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
171 /**
172 * @}
173 */
174
175 /** @defgroup PWR_LL_EC_GPIO GPIO
176 * @{
177 */
178 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
179 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
180 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
181 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
182 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
183 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
184 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
185 /**
186 * @}
187 */
188
189 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
190 * @{
191 */
192 #define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
193 #define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
194 #define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
195 #define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
196 #define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
197 #define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
198 #define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
199 #define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
200 #define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
201 #define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
202 #define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
203 #define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
204 #define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
205 #define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
206 #define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
207 #define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
208 /**
209 * @}
210 */
211
212 /**
213 * @}
214 */
215
216 /* Exported macro ------------------------------------------------------------*/
217 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
218 * @{
219 */
220
221 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
222 * @{
223 */
224
225 /**
226 * @brief Write a value in PWR register
227 * @param __REG__ Register to be written
228 * @param __VALUE__ Value to be written in the register
229 * @retval None
230 */
231 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
232
233 /**
234 * @brief Read a value in PWR register
235 * @param __REG__ Register to be read
236 * @retval Register value
237 */
238 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
239 /**
240 * @}
241 */
242
243 /**
244 * @}
245 */
246
247
248 /* Exported functions --------------------------------------------------------*/
249 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
250 * @{
251 */
252
253 /** @defgroup PWR_LL_EF_Configuration Configuration
254 * @{
255 */
256
257 /**
258 * @brief Switch the regulator from main mode to low-power mode
259 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
260 * @retval None
261 */
262 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
263 {
264 SET_BIT(PWR->CR1, PWR_CR1_LPR);
265 }
266
267 /**
268 * @brief Switch the regulator from low-power mode to main mode
269 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
270 * @retval None
271 */
272 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
273 {
274 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
275 }
276
277 /**
278 * @brief Check if the regulator is in low-power mode
279 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
280 * @retval State of bit (1 or 0).
281 */
282 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
283 {
284 uint32_t temp;
285 temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
286
287 return ((temp == (PWR_CR1_LPR))?1U:0U);
288
289 }
290
291 /**
292 * @brief Switch from run main mode to run low-power mode.
293 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
294 * @retval None
295 */
296 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
297 {
298 LL_PWR_EnableLowPowerRunMode();
299 }
300
301 /**
302 * @brief Switch from run main mode to low-power mode.
303 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
304 * @retval None
305 */
306 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
307 {
308 LL_PWR_DisableLowPowerRunMode();
309 }
310
311 /**
312 * @brief Set the main internal regulator output voltage
313 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
314 * @param VoltageScaling This parameter can be one of the following values:
315 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
316 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
317 * @retval None
318 */
319 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
320 {
321 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
322 }
323
324 /**
325 * @brief Get the main internal regulator output voltage
326 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
327 * @retval Returned value can be one of the following values:
328 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
329 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
330 */
331 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
332 {
333 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
334 }
335
336 #if defined(PWR_CR5_R1MODE)
337 /**
338 * @brief Enable main regulator voltage range 1 boost mode
339 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
340 * @retval None
341 */
342 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
343 {
344 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
345 }
346
347 /**
348 * @brief Disable main regulator voltage range 1 boost mode
349 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
350 * @retval None
351 */
352 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
353 {
354 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
355 }
356
357 /**
358 * @brief Check if the main regulator voltage range 1 boost mode is enabled
359 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
360 * @retval Inverted state of bit (0 or 1).
361 */
362 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
363 {
364 uint32_t temp;
365 temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
366
367 return ((temp == (0U))?1U:0U);
368 }
369 #endif /* PWR_CR5_R1MODE */
370
371 /**
372 * @brief Enable access to the backup domain
373 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
374 * @retval None
375 */
376 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
377 {
378 SET_BIT(PWR->CR1, PWR_CR1_DBP);
379 }
380
381 /**
382 * @brief Disable access to the backup domain
383 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
384 * @retval None
385 */
386 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
387 {
388 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
389 }
390
391 /**
392 * @brief Check if the backup domain is enabled
393 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
394 * @retval State of bit (1 or 0).
395 */
396 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
397 {
398 uint32_t temp;
399 temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
400
401 return ((temp == (PWR_CR1_DBP))?1U:0U);
402
403 }
404
405 /**
406 * @brief Set Low-Power mode
407 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
408 * @param LowPowerMode This parameter can be one of the following values:
409 * @arg @ref LL_PWR_MODE_STOP0
410 * @arg @ref LL_PWR_MODE_STOP1
411 * @arg @ref LL_PWR_MODE_STANDBY
412 * @arg @ref LL_PWR_MODE_SHUTDOWN
413 * @retval None
414 */
415 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
416 {
417 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
418 }
419
420 /**
421 * @brief Get Low-Power mode
422 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
423 * @retval Returned value can be one of the following values:
424 * @arg @ref LL_PWR_MODE_STOP0
425 * @arg @ref LL_PWR_MODE_STOP1
426 * @arg @ref LL_PWR_MODE_STANDBY
427 * @arg @ref LL_PWR_MODE_SHUTDOWN
428 */
429 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
430 {
431 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
432 }
433
434 #if defined(PWR_CR3_UCPD_STDBY)
435 /**
436 * @brief Enable (write 1) the USB Type-C and Power Delivery standby mode.
437 * @note Enable just before entering standby when using UCPD1.
438 * @rmtoll CR3 UCPD1_STDBY LL_PWR_EnableUSBStandByModePD
439 * @retval None
440 */
441 __STATIC_INLINE void LL_PWR_EnableUSBStandByModePD(void)
442 {
443 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
444 }
445
446 /**
447 * @brief Disable (write 0) USB Type-C and Power Delivery standby mode.
448 * @note Disable immediately after standby exit when using UCPD1,
449 * (and before writing any UCPD1 registers).
450 * @rmtoll CR3 UCPD1_STDBY LL_PWR_DisableUSBStandByModePD
451 * @retval None
452 */
453 __STATIC_INLINE void LL_PWR_DisableUSBStandByModePD(void)
454 {
455 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
456 }
457
458 /**
459 * @brief Check the USB Type-C and Power Delivery standby mode.
460 * @rmtoll CR3 UCPD1_STDBY LL_PWR_IsEnabledUSBStandByModePD
461 * @retval State of bit (1 or 0).
462 */
463 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBStandByModePD(void)
464 {
465
466 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY))?1UL:0UL);
467
468 }
469 #endif /* PWR_CR3_UCPD_STDBY */
470
471 #if defined(PWR_CR3_UCPD_DBDIS)
472 /**
473 * @brief Enable (write 0) USB Type-C dead battery pull-down behavior
474 * on UCPD1_CC1 and UCPD1_CC2 pins.
475 * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
476 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
477 * in all cases, either to stop this pull-down or to hand over control to the UCPD1
478 * (which should therefore be initialized before doing the disable).
479 * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_EnableUSBDeadBattery
480 * @retval None
481 */
482 __STATIC_INLINE void LL_PWR_EnableUSBDeadBattery(void)
483 {
484 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
485 }
486
487 /**
488 * @brief Disable (write 1) USB Type-C dead battery pull-down behavior
489 * on UCPD1_CC1 and UCPD1_CC2 pins.
490 * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
491 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
492 * in all cases, either to stop this pull-down or to hand over control to the UCPD1
493 * (which should therefore be initialized before doing the disable).
494 * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_DisableUSBDeadBattery
495 * @retval None
496 */
497 __STATIC_INLINE void LL_PWR_DisableUSBDeadBattery(void)
498 {
499 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
500 }
501
502 /**
503 * @brief Check USB Type-C dead battery pull-down behavior
504 * on UCPD1_CC1 and UCPD1_CC2 pins.
505 * @note After exiting reset, the USB Type-C “dead battery” behavior will be enabled,
506 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it
507 * in all cases, either to stop this pull-down or to hand over control to the UCPD1
508 * (which should therefore be initialized before doing the disable).
509 * @rmtoll CR3 PWR_CR3_UCPD_DBDIS LL_PWR_IsEnabledUSBDeadBattery
510 * @retval State of bit.
511 */
512 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBDeadBattery(void)
513 {
514
515 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS))?1UL:0UL);
516
517 }
518 #endif /* PWR_CR3_UCPD_DBDIS */
519
520 #if defined(PWR_CR2_USV)
521 /**
522 * @brief Enable VDDUSB supply
523 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
524 * @retval None
525 */
526 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
527 {
528 SET_BIT(PWR->CR2, PWR_CR2_USV);
529 }
530
531 /**
532 * @brief Disable VDDUSB supply
533 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
534 * @retval None
535 */
536 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
537 {
538 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
539 }
540
541 /**
542 * @brief Check if VDDUSB supply is enabled
543 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
544 * @retval State of bit (1 or 0).
545 */
546 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
547 {
548 uint32_t temp;
549 temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
550
551 return ((temp == (PWR_CR2_USV))?1U:0U);
552
553 }
554 #endif
555
556 #if defined(PWR_CR2_IOSV)
557 /**
558 * @brief Enable VDDIO2 supply
559 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
560 * @retval None
561 */
562 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
563 {
564 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
565 }
566
567 /**
568 * @brief Disable VDDIO2 supply
569 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
570 * @retval None
571 */
572 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
573 {
574 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
575 }
576
577 /**
578 * @brief Check if VDDIO2 supply is enabled
579 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
580 * @retval State of bit (1 or 0).
581 */
582 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
583 {
584 uint32_t temp;
585 temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
586
587 return ((temp == (PWR_CR2_IOSV))?1U:0U);
588
589 }
590 #endif
591
592 /**
593 * @brief Enable the Power Voltage Monitoring on a peripheral
594 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
595 * CR2 PVME2 LL_PWR_EnablePVM\n
596 * CR2 PVME3 LL_PWR_EnablePVM\n
597 * CR2 PVME4 LL_PWR_EnablePVM
598 * @param PeriphVoltage This parameter can be one of the following values:
599 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
600 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
601 * @arg @ref LL_PWR_PVM_VDDA_ADC
602 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
603 *
604 * (*) value not defined in all devices
605 * @retval None
606 */
607 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
608 {
609 SET_BIT(PWR->CR2, PeriphVoltage);
610 }
611
612 /**
613 * @brief Disable the Power Voltage Monitoring on a peripheral
614 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
615 * CR2 PVME2 LL_PWR_DisablePVM\n
616 * CR2 PVME3 LL_PWR_DisablePVM\n
617 * CR2 PVME4 LL_PWR_DisablePVM
618 * @param PeriphVoltage This parameter can be one of the following values:
619 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
620 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
621 * @arg @ref LL_PWR_PVM_VDDA_ADC
622 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
623 *
624 * (*) value not defined in all devices
625 * @retval None
626 */
627 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
628 {
629 CLEAR_BIT(PWR->CR2, PeriphVoltage);
630 }
631
632 /**
633 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
634 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
635 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
636 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
637 * CR2 PVME4 LL_PWR_IsEnabledPVM
638 * @param PeriphVoltage This parameter can be one of the following values:
639 * @arg @ref LL_PWR_PVM_VDDA_COMP (*)
640 * @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
641 * @arg @ref LL_PWR_PVM_VDDA_ADC
642 * @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
643 *
644 * (*) value not defined in all devices
645 * @retval State of bit (1 or 0).
646 */
647 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
648 {
649 uint32_t temp;
650 temp = READ_BIT(PWR->CR2, PeriphVoltage);
651
652 return ((temp == (PeriphVoltage))?1U:0U);
653
654 }
655
656 /**
657 * @brief Configure the voltage threshold detected by the Power Voltage Detector
658 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
659 * @param PVDLevel This parameter can be one of the following values:
660 * @arg @ref LL_PWR_PVDLEVEL_0
661 * @arg @ref LL_PWR_PVDLEVEL_1
662 * @arg @ref LL_PWR_PVDLEVEL_2
663 * @arg @ref LL_PWR_PVDLEVEL_3
664 * @arg @ref LL_PWR_PVDLEVEL_4
665 * @arg @ref LL_PWR_PVDLEVEL_5
666 * @arg @ref LL_PWR_PVDLEVEL_6
667 * @arg @ref LL_PWR_PVDLEVEL_7
668 * @retval None
669 */
670 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
671 {
672 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
673 }
674
675 /**
676 * @brief Get the voltage threshold detection
677 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
678 * @retval Returned value can be one of the following values:
679 * @arg @ref LL_PWR_PVDLEVEL_0
680 * @arg @ref LL_PWR_PVDLEVEL_1
681 * @arg @ref LL_PWR_PVDLEVEL_2
682 * @arg @ref LL_PWR_PVDLEVEL_3
683 * @arg @ref LL_PWR_PVDLEVEL_4
684 * @arg @ref LL_PWR_PVDLEVEL_5
685 * @arg @ref LL_PWR_PVDLEVEL_6
686 * @arg @ref LL_PWR_PVDLEVEL_7
687 */
688 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
689 {
690 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
691 }
692
693 /**
694 * @brief Enable Power Voltage Detector
695 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
696 * @retval None
697 */
698 __STATIC_INLINE void LL_PWR_EnablePVD(void)
699 {
700 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
701 }
702
703 /**
704 * @brief Disable Power Voltage Detector
705 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
706 * @retval None
707 */
708 __STATIC_INLINE void LL_PWR_DisablePVD(void)
709 {
710 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
711 }
712
713 /**
714 * @brief Check if Power Voltage Detector is enabled
715 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
716 * @retval State of bit (1 or 0).
717 */
718 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
719 {
720 uint32_t temp;
721 temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
722
723 return ((temp == (PWR_CR2_PVDE))?1U:0U);
724 }
725
726 /**
727 * @brief Enable Internal Wake-up line
728 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
729 * @retval None
730 */
731 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
732 {
733 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
734 }
735
736 /**
737 * @brief Disable Internal Wake-up line
738 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
739 * @retval None
740 */
741 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
742 {
743 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
744 }
745
746 /**
747 * @brief Check if Internal Wake-up line is enabled
748 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
749 * @retval State of bit (1 or 0).
750 */
751 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
752 {
753 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
754 }
755
756 #if defined (PWR_CR3_UCPD_DBDIS)
757 /**
758 * @brief Enable USB Type-C and Power Delivery Dead Battery disable
759 * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableDeadBatteryPD
760 * @retval None
761 */
762 __STATIC_INLINE void LL_PWR_EnableDeadBatteryPD(void)
763 {
764 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
765 }
766
767 /**
768 * @brief Disable USB Type-C and Power Delivery Dead Battery disable
769 * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableDeadBatteryPD
770 * @retval None
771 */
772 __STATIC_INLINE void LL_PWR_DisableDeadBatteryPD(void)
773 {
774 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
775 }
776 #endif /* PWR_CR3_UCPD_DBDIS */
777
778 #if defined(PWR_CR3_UCPD_STDBY)
779 /**
780 * @brief Enable USB Type-C and Power Delivery standby mode.
781 * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableStandByModePD
782 * @retval None
783 */
784 __STATIC_INLINE void LL_PWR_EnableStandByModePD(void)
785 {
786 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
787 }
788
789 /**
790 * @brief Disable USB Type-C and Power Delivery standby mode.
791 * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableStandByModePD
792 * @retval None
793 */
794 __STATIC_INLINE void LL_PWR_DisableStandByModePD(void)
795 {
796 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
797 }
798 #endif /* PWR_CR3_UCPD_STDBY */
799
800 /**
801 * @brief Enable pull-up and pull-down configuration
802 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
803 * @retval None
804 */
805 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
806 {
807 SET_BIT(PWR->CR3, PWR_CR3_APC);
808 }
809
810 /**
811 * @brief Disable pull-up and pull-down configuration
812 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
813 * @retval None
814 */
815 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
816 {
817 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
818 }
819
820 /**
821 * @brief Check if pull-up and pull-down configuration is enabled
822 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
823 * @retval State of bit (1 or 0).
824 */
825 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
826 {
827 uint32_t temp;
828 temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
829
830 return ((temp == (PWR_CR3_APC))?1U:0U);
831 }
832
833 /**
834 * @brief Enable SRAM2 content retention in Standby mode
835 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
836 * @retval None
837 */
838 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
839 {
840 SET_BIT(PWR->CR3, PWR_CR3_RRS);
841 }
842
843 /**
844 * @brief Disable SRAM2 content retention in Standby mode
845 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
846 * @retval None
847 */
848 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
849 {
850 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
851 }
852
853 /**
854 * @brief Check if SRAM2 content retention in Standby mode is enabled
855 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
856 * @retval State of bit (1 or 0).
857 */
858 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
859 {
860 uint32_t temp;
861 temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
862
863 return ((temp == (PWR_CR3_RRS))?1U:0U);
864 }
865
866 /**
867 * @brief Enable the WakeUp PINx functionality
868 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
869 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
870 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
871 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
872 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
873 * @param WakeUpPin This parameter can be one of the following values:
874 * @arg @ref LL_PWR_WAKEUP_PIN1
875 * @arg @ref LL_PWR_WAKEUP_PIN2
876 * @arg @ref LL_PWR_WAKEUP_PIN3
877 * @arg @ref LL_PWR_WAKEUP_PIN4
878 * @arg @ref LL_PWR_WAKEUP_PIN5
879 * @retval None
880 */
881 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
882 {
883 SET_BIT(PWR->CR3, WakeUpPin);
884 }
885
886 /**
887 * @brief Disable the WakeUp PINx functionality
888 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
889 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
890 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
891 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
892 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
893 * @param WakeUpPin This parameter can be one of the following values:
894 * @arg @ref LL_PWR_WAKEUP_PIN1
895 * @arg @ref LL_PWR_WAKEUP_PIN2
896 * @arg @ref LL_PWR_WAKEUP_PIN3
897 * @arg @ref LL_PWR_WAKEUP_PIN4
898 * @arg @ref LL_PWR_WAKEUP_PIN5
899 * @retval None
900 */
901 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
902 {
903 CLEAR_BIT(PWR->CR3, WakeUpPin);
904 }
905
906 /**
907 * @brief Check if the WakeUp PINx functionality is enabled
908 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
909 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
910 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
911 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
912 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
913 * @param WakeUpPin This parameter can be one of the following values:
914 * @arg @ref LL_PWR_WAKEUP_PIN1
915 * @arg @ref LL_PWR_WAKEUP_PIN2
916 * @arg @ref LL_PWR_WAKEUP_PIN3
917 * @arg @ref LL_PWR_WAKEUP_PIN4
918 * @arg @ref LL_PWR_WAKEUP_PIN5
919 * @retval State of bit (1 or 0).
920 */
921 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
922 {
923 uint32_t temp;
924 temp = READ_BIT(PWR->CR3, WakeUpPin);
925
926 return ((temp == (WakeUpPin))?1U:0U);
927 }
928
929 /**
930 * @brief Set the resistor impedance
931 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
932 * @param Resistor This parameter can be one of the following values:
933 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
934 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
935 * @retval None
936 */
937 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
938 {
939 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
940 }
941
942 /**
943 * @brief Get the resistor impedance
944 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
945 * @retval Returned value can be one of the following values:
946 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
947 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
948 */
949 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
950 {
951 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
952 }
953
954 /**
955 * @brief Enable battery charging
956 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
957 * @retval None
958 */
959 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
960 {
961 SET_BIT(PWR->CR4, PWR_CR4_VBE);
962 }
963
964 /**
965 * @brief Disable battery charging
966 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
967 * @retval None
968 */
969 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
970 {
971 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
972 }
973
974 /**
975 * @brief Check if battery charging is enabled
976 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
977 * @retval State of bit (1 or 0).
978 */
979 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
980 {
981 uint32_t temp;
982 temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
983
984 return ((temp == (PWR_CR4_VBE))?1U:0U);
985 }
986
987 /**
988 * @brief Set the Wake-Up pin polarity low for the event detection
989 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
990 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
991 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
992 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
993 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
994 * @param WakeUpPin This parameter can be one of the following values:
995 * @arg @ref LL_PWR_WAKEUP_PIN1
996 * @arg @ref LL_PWR_WAKEUP_PIN2
997 * @arg @ref LL_PWR_WAKEUP_PIN3
998 * @arg @ref LL_PWR_WAKEUP_PIN4
999 * @arg @ref LL_PWR_WAKEUP_PIN5
1000 * @retval None
1001 */
1002 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1003 {
1004 SET_BIT(PWR->CR4, WakeUpPin);
1005 }
1006
1007 /**
1008 * @brief Set the Wake-Up pin polarity high for the event detection
1009 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1010 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1011 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1012 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1013 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
1014 * @param WakeUpPin This parameter can be one of the following values:
1015 * @arg @ref LL_PWR_WAKEUP_PIN1
1016 * @arg @ref LL_PWR_WAKEUP_PIN2
1017 * @arg @ref LL_PWR_WAKEUP_PIN3
1018 * @arg @ref LL_PWR_WAKEUP_PIN4
1019 * @arg @ref LL_PWR_WAKEUP_PIN5
1020 * @retval None
1021 */
1022 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1023 {
1024 CLEAR_BIT(PWR->CR4, WakeUpPin);
1025 }
1026
1027 /**
1028 * @brief Get the Wake-Up pin polarity for the event detection
1029 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1030 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1031 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1032 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1033 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1034 * @param WakeUpPin This parameter can be one of the following values:
1035 * @arg @ref LL_PWR_WAKEUP_PIN1
1036 * @arg @ref LL_PWR_WAKEUP_PIN2
1037 * @arg @ref LL_PWR_WAKEUP_PIN3
1038 * @arg @ref LL_PWR_WAKEUP_PIN4
1039 * @arg @ref LL_PWR_WAKEUP_PIN5
1040 * @retval State of bit (1 or 0).
1041 */
1042 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1043 {
1044 uint32_t temp;
1045 temp = READ_BIT(PWR->CR4, WakeUpPin);
1046
1047 return ((temp == (WakeUpPin))?1U:0U);
1048 }
1049
1050 /**
1051 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1052 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1053 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1054 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1055 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1056 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1057 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1058 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1059 * @param GPIO This parameter can be one of the following values:
1060 * @arg @ref LL_PWR_GPIO_A
1061 * @arg @ref LL_PWR_GPIO_B
1062 * @arg @ref LL_PWR_GPIO_C
1063 * @arg @ref LL_PWR_GPIO_D
1064 * @arg @ref LL_PWR_GPIO_E
1065 * @arg @ref LL_PWR_GPIO_F
1066 * @arg @ref LL_PWR_GPIO_G
1067 *
1068 * (*) value not defined in all devices
1069 * @param GPIONumber This parameter can be one of the following values:
1070 * @arg @ref LL_PWR_GPIO_BIT_0
1071 * @arg @ref LL_PWR_GPIO_BIT_1
1072 * @arg @ref LL_PWR_GPIO_BIT_2
1073 * @arg @ref LL_PWR_GPIO_BIT_3
1074 * @arg @ref LL_PWR_GPIO_BIT_4
1075 * @arg @ref LL_PWR_GPIO_BIT_5
1076 * @arg @ref LL_PWR_GPIO_BIT_6
1077 * @arg @ref LL_PWR_GPIO_BIT_7
1078 * @arg @ref LL_PWR_GPIO_BIT_8
1079 * @arg @ref LL_PWR_GPIO_BIT_9
1080 * @arg @ref LL_PWR_GPIO_BIT_10
1081 * @arg @ref LL_PWR_GPIO_BIT_11
1082 * @arg @ref LL_PWR_GPIO_BIT_12
1083 * @arg @ref LL_PWR_GPIO_BIT_13
1084 * @arg @ref LL_PWR_GPIO_BIT_14
1085 * @arg @ref LL_PWR_GPIO_BIT_15
1086 * @retval None
1087 */
1088 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1089 {
1090 SET_BIT(*((uint32_t *)GPIO), GPIONumber);
1091 }
1092
1093 /**
1094 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1095 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1096 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1097 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1098 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1099 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1100 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1101 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1102 * @param GPIO This parameter can be one of the following values:
1103 * @arg @ref LL_PWR_GPIO_A
1104 * @arg @ref LL_PWR_GPIO_B
1105 * @arg @ref LL_PWR_GPIO_C
1106 * @arg @ref LL_PWR_GPIO_D
1107 * @arg @ref LL_PWR_GPIO_E
1108 * @arg @ref LL_PWR_GPIO_F
1109 * @arg @ref LL_PWR_GPIO_G
1110 *
1111 * (*) value not defined in all devices
1112 * @param GPIONumber This parameter can be one of the following values:
1113 * @arg @ref LL_PWR_GPIO_BIT_0
1114 * @arg @ref LL_PWR_GPIO_BIT_1
1115 * @arg @ref LL_PWR_GPIO_BIT_2
1116 * @arg @ref LL_PWR_GPIO_BIT_3
1117 * @arg @ref LL_PWR_GPIO_BIT_4
1118 * @arg @ref LL_PWR_GPIO_BIT_5
1119 * @arg @ref LL_PWR_GPIO_BIT_6
1120 * @arg @ref LL_PWR_GPIO_BIT_7
1121 * @arg @ref LL_PWR_GPIO_BIT_8
1122 * @arg @ref LL_PWR_GPIO_BIT_9
1123 * @arg @ref LL_PWR_GPIO_BIT_10
1124 * @arg @ref LL_PWR_GPIO_BIT_11
1125 * @arg @ref LL_PWR_GPIO_BIT_12
1126 * @arg @ref LL_PWR_GPIO_BIT_13
1127 * @arg @ref LL_PWR_GPIO_BIT_14
1128 * @arg @ref LL_PWR_GPIO_BIT_15
1129 * @retval None
1130 */
1131 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1132 {
1133 CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber);
1134 }
1135
1136 /**
1137 * @brief Check if GPIO pull-up state is enabled
1138 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1139 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1140 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1141 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1142 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1143 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1144 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1145 * @param GPIO This parameter can be one of the following values:
1146 * @arg @ref LL_PWR_GPIO_A
1147 * @arg @ref LL_PWR_GPIO_B
1148 * @arg @ref LL_PWR_GPIO_C
1149 * @arg @ref LL_PWR_GPIO_D
1150 * @arg @ref LL_PWR_GPIO_E
1151 * @arg @ref LL_PWR_GPIO_F
1152 * @arg @ref LL_PWR_GPIO_G
1153 *
1154 * (*) value not defined in all devices
1155 * @param GPIONumber This parameter can be one of the following values:
1156 * @arg @ref LL_PWR_GPIO_BIT_0
1157 * @arg @ref LL_PWR_GPIO_BIT_1
1158 * @arg @ref LL_PWR_GPIO_BIT_2
1159 * @arg @ref LL_PWR_GPIO_BIT_3
1160 * @arg @ref LL_PWR_GPIO_BIT_4
1161 * @arg @ref LL_PWR_GPIO_BIT_5
1162 * @arg @ref LL_PWR_GPIO_BIT_6
1163 * @arg @ref LL_PWR_GPIO_BIT_7
1164 * @arg @ref LL_PWR_GPIO_BIT_8
1165 * @arg @ref LL_PWR_GPIO_BIT_9
1166 * @arg @ref LL_PWR_GPIO_BIT_10
1167 * @arg @ref LL_PWR_GPIO_BIT_11
1168 * @arg @ref LL_PWR_GPIO_BIT_12
1169 * @arg @ref LL_PWR_GPIO_BIT_13
1170 * @arg @ref LL_PWR_GPIO_BIT_14
1171 * @arg @ref LL_PWR_GPIO_BIT_15
1172 * @retval State of bit (1 or 0).
1173 */
1174 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1175 {
1176 uint32_t temp;
1177 temp = READ_BIT(*((uint32_t *)(GPIO)), GPIONumber);
1178
1179 return ((temp == (GPIONumber))?1U:0U);
1180 }
1181
1182 /**
1183 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1184 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1185 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1186 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1187 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1188 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1189 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1190 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1191 * @param GPIO This parameter can be one of the following values:
1192 * @arg @ref LL_PWR_GPIO_A
1193 * @arg @ref LL_PWR_GPIO_B
1194 * @arg @ref LL_PWR_GPIO_C
1195 * @arg @ref LL_PWR_GPIO_D
1196 * @arg @ref LL_PWR_GPIO_E
1197 * @arg @ref LL_PWR_GPIO_F
1198 * @arg @ref LL_PWR_GPIO_G
1199 *
1200 * (*) value not defined in all devices
1201 * @param GPIONumber This parameter can be one of the following values:
1202 * @arg @ref LL_PWR_GPIO_BIT_0
1203 * @arg @ref LL_PWR_GPIO_BIT_1
1204 * @arg @ref LL_PWR_GPIO_BIT_2
1205 * @arg @ref LL_PWR_GPIO_BIT_3
1206 * @arg @ref LL_PWR_GPIO_BIT_4
1207 * @arg @ref LL_PWR_GPIO_BIT_5
1208 * @arg @ref LL_PWR_GPIO_BIT_6
1209 * @arg @ref LL_PWR_GPIO_BIT_7
1210 * @arg @ref LL_PWR_GPIO_BIT_8
1211 * @arg @ref LL_PWR_GPIO_BIT_9
1212 * @arg @ref LL_PWR_GPIO_BIT_10
1213 * @arg @ref LL_PWR_GPIO_BIT_11
1214 * @arg @ref LL_PWR_GPIO_BIT_12
1215 * @arg @ref LL_PWR_GPIO_BIT_13
1216 * @arg @ref LL_PWR_GPIO_BIT_14
1217 * @arg @ref LL_PWR_GPIO_BIT_15
1218 * @retval None
1219 */
1220 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1221 {
1222 register uint32_t temp = (uint32_t)(GPIO) + 4U;
1223 SET_BIT(*((uint32_t *)(temp)), GPIONumber);
1224 }
1225
1226 /**
1227 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1228 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1229 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1230 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1231 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1232 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1233 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1234 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1235 * @param GPIO This parameter can be one of the following values:
1236 * @arg @ref LL_PWR_GPIO_A
1237 * @arg @ref LL_PWR_GPIO_B
1238 * @arg @ref LL_PWR_GPIO_C
1239 * @arg @ref LL_PWR_GPIO_D
1240 * @arg @ref LL_PWR_GPIO_E
1241 * @arg @ref LL_PWR_GPIO_F
1242 * @arg @ref LL_PWR_GPIO_G
1243 *
1244 * (*) value not defined in all devices
1245 * @param GPIONumber This parameter can be one of the following values:
1246 * @arg @ref LL_PWR_GPIO_BIT_0
1247 * @arg @ref LL_PWR_GPIO_BIT_1
1248 * @arg @ref LL_PWR_GPIO_BIT_2
1249 * @arg @ref LL_PWR_GPIO_BIT_3
1250 * @arg @ref LL_PWR_GPIO_BIT_4
1251 * @arg @ref LL_PWR_GPIO_BIT_5
1252 * @arg @ref LL_PWR_GPIO_BIT_6
1253 * @arg @ref LL_PWR_GPIO_BIT_7
1254 * @arg @ref LL_PWR_GPIO_BIT_8
1255 * @arg @ref LL_PWR_GPIO_BIT_9
1256 * @arg @ref LL_PWR_GPIO_BIT_10
1257 * @arg @ref LL_PWR_GPIO_BIT_11
1258 * @arg @ref LL_PWR_GPIO_BIT_12
1259 * @arg @ref LL_PWR_GPIO_BIT_13
1260 * @arg @ref LL_PWR_GPIO_BIT_14
1261 * @arg @ref LL_PWR_GPIO_BIT_15
1262 * @retval None
1263 */
1264 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1265 {
1266 register uint32_t temp = (uint32_t)(GPIO) + 4U;
1267 CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber);
1268 }
1269
1270 /**
1271 * @brief Check if GPIO pull-down state is enabled
1272 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1273 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1274 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1275 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1276 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1277 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1278 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1279 * @param GPIO This parameter can be one of the following values:
1280 * @arg @ref LL_PWR_GPIO_A
1281 * @arg @ref LL_PWR_GPIO_B
1282 * @arg @ref LL_PWR_GPIO_C
1283 * @arg @ref LL_PWR_GPIO_D
1284 * @arg @ref LL_PWR_GPIO_E
1285 * @arg @ref LL_PWR_GPIO_F
1286 * @arg @ref LL_PWR_GPIO_G
1287 *
1288 * (*) value not defined in all devices
1289 * @param GPIONumber This parameter can be one of the following values:
1290 * @arg @ref LL_PWR_GPIO_BIT_0
1291 * @arg @ref LL_PWR_GPIO_BIT_1
1292 * @arg @ref LL_PWR_GPIO_BIT_2
1293 * @arg @ref LL_PWR_GPIO_BIT_3
1294 * @arg @ref LL_PWR_GPIO_BIT_4
1295 * @arg @ref LL_PWR_GPIO_BIT_5
1296 * @arg @ref LL_PWR_GPIO_BIT_6
1297 * @arg @ref LL_PWR_GPIO_BIT_7
1298 * @arg @ref LL_PWR_GPIO_BIT_8
1299 * @arg @ref LL_PWR_GPIO_BIT_9
1300 * @arg @ref LL_PWR_GPIO_BIT_10
1301 * @arg @ref LL_PWR_GPIO_BIT_11
1302 * @arg @ref LL_PWR_GPIO_BIT_12
1303 * @arg @ref LL_PWR_GPIO_BIT_13
1304 * @arg @ref LL_PWR_GPIO_BIT_14
1305 * @arg @ref LL_PWR_GPIO_BIT_15
1306 * @retval State of bit (1 or 0).
1307 */
1308 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1309 {
1310 register uint32_t temp_reg = (uint32_t)(GPIO) + 4U;
1311 uint32_t temp;
1312 temp = READ_BIT(*((uint32_t *)(temp_reg)), GPIONumber);
1313
1314 return ((temp == (GPIONumber))?1U:0U);
1315
1316 }
1317
1318 /**
1319 * @}
1320 */
1321
1322 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1323 * @{
1324 */
1325
1326 /**
1327 * @brief Get Internal Wake-up line Flag
1328 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1329 * @retval State of bit (1 or 0).
1330 */
1331 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1332 {
1333 uint32_t temp;
1334 temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
1335
1336 return ((temp == (PWR_SR1_WUFI))?1U:0U);
1337
1338 }
1339
1340 /**
1341 * @brief Get Stand-By Flag
1342 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1343 * @retval State of bit (1 or 0).
1344 */
1345 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1346 {
1347 uint32_t temp;
1348 temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
1349
1350 return ((temp == (PWR_SR1_SBF))?1U:0U);
1351
1352 }
1353
1354 /**
1355 * @brief Get Wake-up Flag 5
1356 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1357 * @retval State of bit (1 or 0).
1358 */
1359 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1360 {
1361 uint32_t temp;
1362 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
1363
1364 return ((temp == (PWR_SR1_WUF5))?1U:0U);
1365 }
1366
1367 /**
1368 * @brief Get Wake-up Flag 4
1369 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1370 * @retval State of bit (1 or 0).
1371 */
1372 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1373 {
1374 uint32_t temp;
1375 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
1376
1377 return ((temp == (PWR_SR1_WUF4))?1U:0U);
1378 }
1379
1380 /**
1381 * @brief Get Wake-up Flag 3
1382 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1383 * @retval State of bit (1 or 0).
1384 */
1385 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1386 {
1387 uint32_t temp;
1388 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
1389
1390 return ((temp == (PWR_SR1_WUF3))?1U:0U);
1391 }
1392
1393 /**
1394 * @brief Get Wake-up Flag 2
1395 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1396 * @retval State of bit (1 or 0).
1397 */
1398 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1399 {
1400 uint32_t temp;
1401 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
1402
1403 return ((temp == (PWR_SR1_WUF2))?1U:0U);
1404 }
1405
1406 /**
1407 * @brief Get Wake-up Flag 1
1408 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1409 * @retval State of bit (1 or 0).
1410 */
1411 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1412 {
1413 uint32_t temp;
1414 temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
1415
1416 return ((temp == (PWR_SR1_WUF1))?1U:0U);
1417 }
1418
1419 /**
1420 * @brief Clear Stand-By Flag
1421 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1422 * @retval None
1423 */
1424 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1425 {
1426 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1427 }
1428
1429 /**
1430 * @brief Clear Wake-up Flags
1431 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1432 * @retval None
1433 */
1434 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1435 {
1436 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1437 }
1438
1439 /**
1440 * @brief Clear Wake-up Flag 5
1441 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1442 * @retval None
1443 */
1444 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1445 {
1446 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1447 }
1448
1449 /**
1450 * @brief Clear Wake-up Flag 4
1451 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1452 * @retval None
1453 */
1454 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1455 {
1456 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1457 }
1458
1459 /**
1460 * @brief Clear Wake-up Flag 3
1461 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1462 * @retval None
1463 */
1464 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1465 {
1466 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1467 }
1468
1469 /**
1470 * @brief Clear Wake-up Flag 2
1471 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1472 * @retval None
1473 */
1474 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1475 {
1476 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1477 }
1478
1479 /**
1480 * @brief Clear Wake-up Flag 1
1481 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1482 * @retval None
1483 */
1484 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1485 {
1486 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1487 }
1488
1489 /**
1490 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1491 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1492 * @retval State of bit (1 or 0).
1493 */
1494 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1495 {
1496 uint32_t temp;
1497 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
1498
1499 return ((temp == (PWR_SR2_PVMO4))?1U:0U);
1500
1501 }
1502
1503 /**
1504 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1505 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1506 * @retval State of bit (1 or 0).
1507 */
1508 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1509 {
1510 uint32_t temp;
1511 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
1512
1513 return ((temp == (PWR_SR2_PVMO3))?1U:0U);
1514
1515 }
1516
1517 #if defined(PWR_SR2_PVMO2)
1518 /**
1519 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1520 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1521 * @retval State of bit (1 or 0).
1522 */
1523 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1524 {
1525 uint32_t temp;
1526 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
1527
1528 return ((temp == (PWR_SR2_PVMO2))?1U:0U);
1529
1530 }
1531 #endif /* PWR_SR2_PVMO2 */
1532
1533 #if defined(PWR_SR2_PVMO1)
1534 /**
1535 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1536 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1537 * @retval State of bit (1 or 0).
1538 */
1539 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1540 {
1541 uint32_t temp;
1542 temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
1543
1544 return ((temp == (PWR_SR2_PVMO1))?1U:0U);
1545
1546 }
1547 #endif /* PWR_SR2_PVMO1 */
1548
1549 /**
1550 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1551 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1552 * @retval State of bit (1 or 0).
1553 */
1554 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1555 {
1556 uint32_t temp;
1557 temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
1558
1559 return ((temp == (PWR_SR2_PVDO))?1U:0U);
1560
1561 }
1562
1563 /**
1564 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1565 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1566 * @retval State of bit (1 or 0).
1567 */
1568 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1569 {
1570 uint32_t temp;
1571 temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
1572
1573 return ((temp == (PWR_SR2_VOSF))?1U:0U);
1574
1575 }
1576
1577 /**
1578 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1579 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1580 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1581 * @retval State of bit (1 or 0).
1582 */
1583 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1584 {
1585 uint32_t temp;
1586 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
1587
1588 return ((temp == (PWR_SR2_REGLPF))?1U:0U);
1589
1590 }
1591
1592 /**
1593 * @brief Indicate whether or not the low-power regulator is ready
1594 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1595 * @retval State of bit (1 or 0).
1596 */
1597 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1598 {
1599 uint32_t temp;
1600 temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
1601
1602 return ((temp == (PWR_SR2_REGLPS))?1U:0U);
1603
1604 }
1605
1606 /**
1607 * @}
1608 */
1609
1610 #if defined(USE_FULL_LL_DRIVER)
1611 /** @defgroup PWR_LL_EF_Init De-initialization function
1612 * @{
1613 */
1614 ErrorStatus LL_PWR_DeInit(void);
1615 /**
1616 * @}
1617 */
1618 #endif /* USE_FULL_LL_DRIVER */
1619
1620 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1621 * @{
1622 */
1623 /* Old functions name kept for legacy purpose, to be replaced by the */
1624 /* current functions name. */
1625 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1626 /**
1627 * @}
1628 */
1629
1630 /**
1631 * @}
1632 */
1633
1634 /**
1635 * @}
1636 */
1637
1638 #endif /* defined(PWR) */
1639
1640 /**
1641 * @}
1642 */
1643
1644 #ifdef __cplusplus
1645 }
1646 #endif
1647
1648 #endif /* STM32G4xx_LL_PWR_H */
1649
1650 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/