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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_rcc.h
blobce741d842007117ebe18b8e3141cfd3d8b437f14
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_RCC_H
22 #define STM32G4xx_LL_RCC_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 /** @defgroup RCC_LL RCC
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
42 * @{
43 */
44
45 /**
46 * @}
47 */
48
49 /* Private constants ---------------------------------------------------------*/
50 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
51 * @{
52 */
53 /* Defines used to perform offsets*/
54 /* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
55 #define RCC_OFFSET_CCIPR 0U
56 #define RCC_OFFSET_CCIPR2 0x14U
57
58 /**
59 * @}
60 */
61
62 /* Private macros ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
65 * @{
66 */
67 /**
68 * @}
69 */
70 #endif /*USE_FULL_LL_DRIVER*/
71
72 /* Exported types ------------------------------------------------------------*/
73 #if defined(USE_FULL_LL_DRIVER)
74 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
75 * @{
76 */
77
78 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
79 * @{
80 */
81
82 /**
83 * @brief RCC Clocks Frequency Structure
84 */
85 typedef struct
86 {
87 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
88 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
89 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
90 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
91 } LL_RCC_ClocksTypeDef;
92
93 /**
94 * @}
95 */
96
97 /**
98 * @}
99 */
100 #endif /* USE_FULL_LL_DRIVER */
101
102 /* Exported constants --------------------------------------------------------*/
103 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
104 * @{
105 */
106
107 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
108 * @brief Defines used to adapt values of different oscillators
109 * @note These values could be modified in the user environment according to
110 * HW set-up.
111 * @{
112 */
113 #if !defined (HSE_VALUE)
114 #define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
115 #endif /* HSE_VALUE */
116
117 #if !defined (HSI_VALUE)
118 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
119 #endif /* HSI_VALUE */
120
121 #if !defined (LSE_VALUE)
122 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
123 #endif /* LSE_VALUE */
124
125 #if !defined (LSI_VALUE)
126 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
127 #endif /* LSI_VALUE */
128
129 #if !defined (HSI48_VALUE)
130 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
131 #endif /* HSI48_VALUE */
132
133 #if !defined (EXTERNAL_CLOCK_VALUE)
134 #define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
135 #endif /* EXTERNAL_CLOCK_VALUE */
136
137 /**
138 * @}
139 */
140
141 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
142 * @brief Flags defines which can be used with LL_RCC_WriteReg function
143 * @{
144 */
145 #define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
146 #define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
147 #define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
148 #define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
149 #define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
150 #define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
151 #define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
152 #define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
153 /**
154 * @}
155 */
156
157 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
158 * @brief Flags defines which can be used with LL_RCC_ReadReg function
159 * @{
160 */
161 #define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
162 #define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
163 #define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
164 #define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
165 #define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
166 #define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
167 #define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
168 #define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
169 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
170 #define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
171 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
172 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
173 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
174 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
175 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
176 /**
177 * @}
178 */
179
180 /** @defgroup RCC_LL_EC_IT IT Defines
181 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
182 * @{
183 */
184 #define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
185 #define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
186 #define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
187 #define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
188 #define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
189 #define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
190 #define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
191 /**
192 * @}
193 */
194
195 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
196 * @{
197 */
198 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
199 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
200 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
201 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
202 /**
203 * @}
204 */
205
206 /** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
207 * @{
208 */
209 #define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
210 #define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
211 /**
212 * @}
213 */
214
215 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
216 * @{
217 */
218 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
219 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
220 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
221 /**
222 * @}
223 */
224
225 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
226 * @{
227 */
228 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
229 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
230 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
231 /**
232 * @}
233 */
234
235 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
236 * @{
237 */
238 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
239 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
240 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
241 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
242 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
243 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
244 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
245 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
246 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
247 /**
248 * @}
249 */
250
251 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
252 * @{
253 */
254 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
255 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
256 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
257 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
258 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
259 /**
260 * @}
261 */
262
263 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
264 * @{
265 */
266 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
267 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
268 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
269 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
270 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
271 /**
272 * @}
273 */
274
275 /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
276 * @{
277 */
278 #define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
279 #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
280 #define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
281 #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
282 #define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
283 #define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
284 #define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
285 #define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
286 /**
287 * @}
288 */
289
290 /** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
291 * @{
292 */
293 #define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
294 #define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
295 #define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
296 #define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
297 #define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
298 /**
299 * @}
300 */
301
302 #if defined(USE_FULL_LL_DRIVER)
303 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
304 * @{
305 */
306 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
307 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
308 /**
309 * @}
310 */
311 #endif /* USE_FULL_LL_DRIVER */
312
313 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
314 * @{
315 */
316 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
317 #define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
318 #define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
319 #define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
320 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
321 #define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
322 #define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
323 #define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
324 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
325 #define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
326 #define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
327 #define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
328 /**
329 * @}
330 */
331
332 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
333 * @{
334 */
335 #if defined(RCC_CCIPR_UART4SEL)
336 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
337 #define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
338 #define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
339 #define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
340 #endif /* RCC_CCIPR_UART4SEL */
341 #if defined(RCC_CCIPR_UART5SEL)
342 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
343 #define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
344 #define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
345 #define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
346 #endif /* RCC_CCIPR_UART5SEL */
347 /**
348 * @}
349 */
350
351 /** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
352 * @{
353 */
354 #define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
355 #define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
356 #define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
357 #define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
358 /**
359 * @}
360 */
361
362 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
363 * @{
364 */
365 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
366 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
367 #define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
368 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
369 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
370 #define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
371 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
372 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
373 #define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
374 #if defined(RCC_CCIPR2_I2C4SEL)
375 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
376 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
377 #define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
378 #endif /* RCC_CCIPR2_I2C4SEL */
379 /**
380 * @}
381 */
382
383 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
384 * @{
385 */
386 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
387 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
388 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
389 #define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
390 /**
391 * @}
392 */
393
394 /** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
395 * @{
396 */
397 #define LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as SAI1 clock source */
398 #define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
399 #define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
400 #define LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
401 /**
402 * @}
403 */
404
405 /** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
406 * @{
407 */
408 #define LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as I2S clock source */
409 #define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
410 #define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
411 #define LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
412 /**
413 * @}
414 */
415
416 #if defined(FDCAN1)
417 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
418 * @{
419 */
420 #define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN clock source */
421 #define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
422 #define LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
423 /**
424 * @}
425 */
426 #endif /* FDCAN1 */
427
428 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
429 * @{
430 */
431 #define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
432 #define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
433 /**
434 * @}
435 */
436
437 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
438 * @{
439 */
440 #define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
441 #define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
442 /**
443 * @}
444 */
445
446 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
447 * @{
448 */
449 #define LL_RCC_ADC12_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */
450 #define LL_RCC_ADC12_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
451 #define LL_RCC_ADC12_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
452 #if defined(RCC_CCIPR_ADC345SEL)
453 #define LL_RCC_ADC345_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */
454 #define LL_RCC_ADC345_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
455 #define LL_RCC_ADC345_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
456 #endif /* RCC_CCIPR_ADC345SEL */
457 /**
458 * @}
459 */
460
461 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
462 * @{
463 */
464 #define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
465 #define LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
466 #define LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
467 /**
468 * @}
469 */
470
471
472 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
473 * @{
474 */
475 #define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
476 #define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
477 #define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
478 /**
479 * @}
480 */
481
482 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
483 * @{
484 */
485 #if defined(RCC_CCIPR_UART4SEL)
486 #define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
487 #endif /* RCC_CCIPR_UART4SEL */
488 #if defined(RCC_CCIPR_UART5SEL)
489 #define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
490 #endif /* RCC_CCIPR_UART5SEL */
491 /**
492 * @}
493 */
494
495 /** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
496 * @{
497 */
498 #define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
499 /**
500 * @}
501 */
502
503 /** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
504 * @{
505 */
506 #define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
507 #define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
508 #define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
509 #if defined(RCC_CCIPR2_I2C4SEL)
510 #define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
511 #endif /* RCC_CCIPR2_I2C4SEL */
512 /**
513 * @}
514 */
515
516 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
517 * @{
518 */
519 #define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
520 /**
521 * @}
522 */
523
524 /** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
525 * @{
526 */
527 #define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
528 /**
529 * @}
530 */
531
532 /** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
533 * @{
534 */
535 #define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
536 /**
537 * @}
538 */
539
540 #if defined(FDCAN1)
541 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
542 * @{
543 */
544 #define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
545 #endif /* FDCAN1 */
546
547 /**
548 * @}
549 */
550
551 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
552 * @{
553 */
554 #define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
555 /**
556 * @}
557 */
558
559 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
560 * @{
561 */
562 #define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
563 /**
564 * @}
565 */
566
567 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
568 * @{
569 */
570 #define LL_RCC_ADC12_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
571 #if defined(RCC_CCIPR_ADC345SEL_Pos)
572 #define LL_RCC_ADC345_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
573 #endif /* RCC_CCIPR_ADC345SEL_Pos */
574 /**
575 * @}
576 */
577
578 /** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
579 * @{
580 */
581 #define LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
582 /**
583 * @}
584 */
585
586 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
587 * @{
588 */
589 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
590 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
591 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
592 #define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
593 /**
594 * @}
595 */
596
597
598 /** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
599 * @{
600 */
601 #define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
602 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
603 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
604 /**
605 * @}
606 */
607
608 /** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
609 * @{
610 */
611 #define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
612 #define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
613 #define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
614 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
615 #define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
616 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
617 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
618 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
619 #define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
620 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
621 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
622 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
623 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
624 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
625 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
626 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
627 /**
628 * @}
629 */
630
631 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
632 * @{
633 */
634 #define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
635 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
636 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
637 #define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
638 /**
639 * @}
640 */
641
642 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
643 * @{
644 */
645 #define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
646 #define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
647 #define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
648 #define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
649 #define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
650 #define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
651 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
652 #define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
653 #define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
654 #define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
655 #define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
656 #define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
657 #define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
658 #define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
659 #define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
660 #define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
661 #define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
662 #define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
663 #define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
664 #define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
665 #define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
666 #define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
667 #define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
668 #define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
669 #define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
670 #define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
671 #define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
672 #define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
673 #define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
674 #define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
675 /**
676 * @}
677 */
678
679 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
680 * @{
681 */
682 #define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
683 #define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
684 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
685 #define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
686 /**
687 * @}
688 */
689
690 /**
691 * @}
692 */
693
694 /* Exported macro ------------------------------------------------------------*/
695 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
696 * @{
697 */
698
699 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
700 * @{
701 */
702
703 /**
704 * @brief Write a value in RCC register
705 * @param __REG__ Register to be written
706 * @param __VALUE__ Value to be written in the register
707 * @retval None
708 */
709 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
710
711 /**
712 * @brief Read a value in RCC register
713 * @param __REG__ Register to be read
714 * @retval Register value
715 */
716 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
717 /**
718 * @}
719 */
720
721 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
722 * @{
723 */
724
725 /**
726 * @brief Helper macro to calculate the PLLCLK frequency on system domain
727 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
728 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
729 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
730 * @param __PLLM__ This parameter can be one of the following values:
731 * @arg @ref LL_RCC_PLLM_DIV_1
732 * @arg @ref LL_RCC_PLLM_DIV_2
733 * @arg @ref LL_RCC_PLLM_DIV_3
734 * @arg @ref LL_RCC_PLLM_DIV_4
735 * @arg @ref LL_RCC_PLLM_DIV_5
736 * @arg @ref LL_RCC_PLLM_DIV_6
737 * @arg @ref LL_RCC_PLLM_DIV_7
738 * @arg @ref LL_RCC_PLLM_DIV_8
739 * @arg @ref LL_RCC_PLLM_DIV_9
740 * @arg @ref LL_RCC_PLLM_DIV_10
741 * @arg @ref LL_RCC_PLLM_DIV_11
742 * @arg @ref LL_RCC_PLLM_DIV_12
743 * @arg @ref LL_RCC_PLLM_DIV_13
744 * @arg @ref LL_RCC_PLLM_DIV_14
745 * @arg @ref LL_RCC_PLLM_DIV_15
746 * @arg @ref LL_RCC_PLLM_DIV_16
747 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
748 * @param __PLLR__ This parameter can be one of the following values:
749 * @arg @ref LL_RCC_PLLR_DIV_2
750 * @arg @ref LL_RCC_PLLR_DIV_4
751 * @arg @ref LL_RCC_PLLR_DIV_6
752 * @arg @ref LL_RCC_PLLR_DIV_8
753 * @retval PLL clock frequency (in Hz)
754 */
755 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
756 ((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
757
758 /**
759 * @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
760 * @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
761 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
762 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
763 * @param __PLLM__ This parameter can be one of the following values:
764 * @arg @ref LL_RCC_PLLM_DIV_1
765 * @arg @ref LL_RCC_PLLM_DIV_2
766 * @arg @ref LL_RCC_PLLM_DIV_3
767 * @arg @ref LL_RCC_PLLM_DIV_4
768 * @arg @ref LL_RCC_PLLM_DIV_5
769 * @arg @ref LL_RCC_PLLM_DIV_6
770 * @arg @ref LL_RCC_PLLM_DIV_7
771 * @arg @ref LL_RCC_PLLM_DIV_8
772 * @arg @ref LL_RCC_PLLM_DIV_9
773 * @arg @ref LL_RCC_PLLM_DIV_10
774 * @arg @ref LL_RCC_PLLM_DIV_11
775 * @arg @ref LL_RCC_PLLM_DIV_12
776 * @arg @ref LL_RCC_PLLM_DIV_13
777 * @arg @ref LL_RCC_PLLM_DIV_14
778 * @arg @ref LL_RCC_PLLM_DIV_15
779 * @arg @ref LL_RCC_PLLM_DIV_16
780
781 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
782 * @param __PLLP__ This parameter can be one of the following values:
783 * @arg @ref LL_RCC_PLLP_DIV_2
784 * @arg @ref LL_RCC_PLLP_DIV_3
785 * @arg @ref LL_RCC_PLLP_DIV_4
786 * @arg @ref LL_RCC_PLLP_DIV_5
787 * @arg @ref LL_RCC_PLLP_DIV_6
788 * @arg @ref LL_RCC_PLLP_DIV_7
789 * @arg @ref LL_RCC_PLLP_DIV_8
790 * @arg @ref LL_RCC_PLLP_DIV_9
791 * @arg @ref LL_RCC_PLLP_DIV_10
792 * @arg @ref LL_RCC_PLLP_DIV_11
793 * @arg @ref LL_RCC_PLLP_DIV_12
794 * @arg @ref LL_RCC_PLLP_DIV_13
795 * @arg @ref LL_RCC_PLLP_DIV_14
796 * @arg @ref LL_RCC_PLLP_DIV_15
797 * @arg @ref LL_RCC_PLLP_DIV_16
798 * @arg @ref LL_RCC_PLLP_DIV_17
799 * @arg @ref LL_RCC_PLLP_DIV_18
800 * @arg @ref LL_RCC_PLLP_DIV_19
801 * @arg @ref LL_RCC_PLLP_DIV_20
802 * @arg @ref LL_RCC_PLLP_DIV_21
803 * @arg @ref LL_RCC_PLLP_DIV_22
804 * @arg @ref LL_RCC_PLLP_DIV_23
805 * @arg @ref LL_RCC_PLLP_DIV_24
806 * @arg @ref LL_RCC_PLLP_DIV_25
807 * @arg @ref LL_RCC_PLLP_DIV_26
808 * @arg @ref LL_RCC_PLLP_DIV_27
809 * @arg @ref LL_RCC_PLLP_DIV_28
810 * @arg @ref LL_RCC_PLLP_DIV_29
811 * @arg @ref LL_RCC_PLLP_DIV_30
812 * @arg @ref LL_RCC_PLLP_DIV_31
813 * @retval PLL clock frequency (in Hz)
814 */
815 #define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
816 ((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
817
818 /**
819 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
820 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
821 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
822 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
823 * @param __PLLM__ This parameter can be one of the following values:
824 * @arg @ref LL_RCC_PLLM_DIV_1
825 * @arg @ref LL_RCC_PLLM_DIV_2
826 * @arg @ref LL_RCC_PLLM_DIV_3
827 * @arg @ref LL_RCC_PLLM_DIV_4
828 * @arg @ref LL_RCC_PLLM_DIV_5
829 * @arg @ref LL_RCC_PLLM_DIV_6
830 * @arg @ref LL_RCC_PLLM_DIV_7
831 * @arg @ref LL_RCC_PLLM_DIV_8
832 * @arg @ref LL_RCC_PLLM_DIV_9
833 * @arg @ref LL_RCC_PLLM_DIV_10
834 * @arg @ref LL_RCC_PLLM_DIV_11
835 * @arg @ref LL_RCC_PLLM_DIV_12
836 * @arg @ref LL_RCC_PLLM_DIV_13
837 * @arg @ref LL_RCC_PLLM_DIV_14
838 * @arg @ref LL_RCC_PLLM_DIV_15
839 * @arg @ref LL_RCC_PLLM_DIV_16
840 * @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
841 * @param __PLLQ__ This parameter can be one of the following values:
842 * @arg @ref LL_RCC_PLLQ_DIV_2
843 * @arg @ref LL_RCC_PLLQ_DIV_4
844 * @arg @ref LL_RCC_PLLQ_DIV_6
845 * @arg @ref LL_RCC_PLLQ_DIV_8
846 * @retval PLL clock frequency (in Hz)
847 */
848 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
849 ((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
850
851 /**
852 * @brief Helper macro to calculate the HCLK frequency
853 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
854 * @param __AHBPRESCALER__ This parameter can be one of the following values:
855 * @arg @ref LL_RCC_SYSCLK_DIV_1
856 * @arg @ref LL_RCC_SYSCLK_DIV_2
857 * @arg @ref LL_RCC_SYSCLK_DIV_4
858 * @arg @ref LL_RCC_SYSCLK_DIV_8
859 * @arg @ref LL_RCC_SYSCLK_DIV_16
860 * @arg @ref LL_RCC_SYSCLK_DIV_64
861 * @arg @ref LL_RCC_SYSCLK_DIV_128
862 * @arg @ref LL_RCC_SYSCLK_DIV_256
863 * @arg @ref LL_RCC_SYSCLK_DIV_512
864 * @retval HCLK clock frequency (in Hz)
865 */
866 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
867
868 /**
869 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
870 * @param __HCLKFREQ__ HCLK frequency
871 * @param __APB1PRESCALER__ This parameter can be one of the following values:
872 * @arg @ref LL_RCC_APB1_DIV_1
873 * @arg @ref LL_RCC_APB1_DIV_2
874 * @arg @ref LL_RCC_APB1_DIV_4
875 * @arg @ref LL_RCC_APB1_DIV_8
876 * @arg @ref LL_RCC_APB1_DIV_16
877 * @retval PCLK1 clock frequency (in Hz)
878 */
879 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
880
881 /**
882 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
883 * @param __HCLKFREQ__ HCLK frequency
884 * @param __APB2PRESCALER__ This parameter can be one of the following values:
885 * @arg @ref LL_RCC_APB2_DIV_1
886 * @arg @ref LL_RCC_APB2_DIV_2
887 * @arg @ref LL_RCC_APB2_DIV_4
888 * @arg @ref LL_RCC_APB2_DIV_8
889 * @arg @ref LL_RCC_APB2_DIV_16
890 * @retval PCLK2 clock frequency (in Hz)
891 */
892 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
893
894 /**
895 * @}
896 */
897
898 /**
899 * @}
900 */
901
902 /* Exported functions --------------------------------------------------------*/
903 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
904 * @{
905 */
906
907 /** @defgroup RCC_LL_EF_HSE HSE
908 * @{
909 */
910
911 /**
912 * @brief Enable the Clock Security System.
913 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
914 * @retval None
915 */
916 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
917 {
918 SET_BIT(RCC->CR, RCC_CR_CSSON);
919 }
920
921 /**
922 * @brief Enable HSE external oscillator (HSE Bypass)
923 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
924 * @retval None
925 */
926 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
927 {
928 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
929 }
930
931 /**
932 * @brief Disable HSE external oscillator (HSE Bypass)
933 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
934 * @retval None
935 */
936 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
937 {
938 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
939 }
940
941 /**
942 * @brief Enable HSE crystal oscillator (HSE ON)
943 * @rmtoll CR HSEON LL_RCC_HSE_Enable
944 * @retval None
945 */
946 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
947 {
948 SET_BIT(RCC->CR, RCC_CR_HSEON);
949 }
950
951 /**
952 * @brief Disable HSE crystal oscillator (HSE ON)
953 * @rmtoll CR HSEON LL_RCC_HSE_Disable
954 * @retval None
955 */
956 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
957 {
958 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
959 }
960
961 /**
962 * @brief Check if HSE oscillator Ready
963 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
964 * @retval State of bit (1 or 0).
965 */
966 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
967 {
968 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
969 }
970
971 /**
972 * @}
973 */
974
975 /** @defgroup RCC_LL_EF_HSI HSI
976 * @{
977 */
978
979 /**
980 * @brief Enable HSI even in stop mode
981 * @note HSI oscillator is forced ON even in Stop mode
982 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
983 * @retval None
984 */
985 __STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
986 {
987 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
988 }
989
990 /**
991 * @brief Disable HSI in stop mode
992 * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
993 * @retval None
994 */
995 __STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
996 {
997 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
998 }
999
1000 /**
1001 * @brief Enable HSI oscillator
1002 * @rmtoll CR HSION LL_RCC_HSI_Enable
1003 * @retval None
1004 */
1005 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1006 {
1007 SET_BIT(RCC->CR, RCC_CR_HSION);
1008 }
1009
1010 /**
1011 * @brief Disable HSI oscillator
1012 * @rmtoll CR HSION LL_RCC_HSI_Disable
1013 * @retval None
1014 */
1015 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1016 {
1017 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1018 }
1019
1020 /**
1021 * @brief Check if HSI clock is ready
1022 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1023 * @retval State of bit (1 or 0).
1024 */
1025 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1026 {
1027 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1028 }
1029
1030 /**
1031 * @brief Get HSI Calibration value
1032 * @note When HSITRIM is written, HSICAL is updated with the sum of
1033 * HSITRIM and the factory trim value
1034 * @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
1035 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
1036 */
1037 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1038 {
1039 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
1040 }
1041
1042 /**
1043 * @brief Set HSI Calibration trimming
1044 * @note user-programmable trimming value that is added to the HSICAL
1045 * @note Default value is 16, which, when added to the HSICAL value,
1046 * should trim the HSI to 16 MHz +/- 1 %
1047 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
1048 * @param Value Between Min_Data = 0 and Max_Data = 127
1049 * @retval None
1050 */
1051 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1052 {
1053 MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
1054 }
1055
1056 /**
1057 * @brief Get HSI Calibration trimming
1058 * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
1059 * @retval Between Min_Data = 0 and Max_Data = 127
1060 */
1061 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1062 {
1063 return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
1064 }
1065
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup RCC_LL_EF_HSI48 HSI48
1071 * @{
1072 */
1073
1074 /**
1075 * @brief Enable HSI48
1076 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
1077 * @retval None
1078 */
1079 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1080 {
1081 SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1082 }
1083
1084 /**
1085 * @brief Disable HSI48
1086 * @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
1087 * @retval None
1088 */
1089 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
1090 {
1091 CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
1092 }
1093
1094 /**
1095 * @brief Check if HSI48 oscillator Ready
1096 * @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
1097 * @retval State of bit (1 or 0).
1098 */
1099 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
1100 {
1101 return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
1102 }
1103
1104 /**
1105 * @brief Get HSI48 Calibration value
1106 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
1107 * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
1108 */
1109 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
1110 {
1111 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
1112 }
1113
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup RCC_LL_EF_LSE LSE
1119 * @{
1120 */
1121
1122 /**
1123 * @brief Enable Low Speed External (LSE) crystal.
1124 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
1125 * @retval None
1126 */
1127 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
1128 {
1129 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1130 }
1131
1132 /**
1133 * @brief Disable Low Speed External (LSE) crystal.
1134 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
1135 * @retval None
1136 */
1137 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
1138 {
1139 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
1140 }
1141
1142 /**
1143 * @brief Enable external clock source (LSE bypass).
1144 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
1145 * @retval None
1146 */
1147 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
1148 {
1149 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1150 }
1151
1152 /**
1153 * @brief Disable external clock source (LSE bypass).
1154 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
1155 * @retval None
1156 */
1157 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
1158 {
1159 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
1160 }
1161
1162 /**
1163 * @brief Set LSE oscillator drive capability
1164 * @note The oscillator is in Xtal mode when it is not in bypass mode.
1165 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
1166 * @param LSEDrive This parameter can be one of the following values:
1167 * @arg @ref LL_RCC_LSEDRIVE_LOW
1168 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1169 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1170 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1171 * @retval None
1172 */
1173 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
1174 {
1175 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
1176 }
1177
1178 /**
1179 * @brief Get LSE oscillator drive capability
1180 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
1181 * @retval Returned value can be one of the following values:
1182 * @arg @ref LL_RCC_LSEDRIVE_LOW
1183 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
1184 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
1185 * @arg @ref LL_RCC_LSEDRIVE_HIGH
1186 */
1187 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
1188 {
1189 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
1190 }
1191
1192 /**
1193 * @brief Enable Clock security system on LSE.
1194 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
1195 * @retval None
1196 */
1197 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
1198 {
1199 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1200 }
1201
1202 /**
1203 * @brief Disable Clock security system on LSE.
1204 * @note Clock security system can be disabled only after a LSE
1205 * failure detection. In that case it MUST be disabled by software.
1206 * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
1207 * @retval None
1208 */
1209 __STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
1210 {
1211 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
1212 }
1213
1214 /**
1215 * @brief Check if LSE oscillator Ready
1216 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
1217 * @retval State of bit (1 or 0).
1218 */
1219 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
1220 {
1221 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
1222 }
1223
1224 /**
1225 * @brief Check if CSS on LSE failure Detection
1226 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
1227 * @retval State of bit (1 or 0).
1228 */
1229 __STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
1230 {
1231 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
1232 }
1233
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup RCC_LL_EF_LSI LSI
1239 * @{
1240 */
1241
1242 /**
1243 * @brief Enable LSI Oscillator
1244 * @rmtoll CSR LSION LL_RCC_LSI_Enable
1245 * @retval None
1246 */
1247 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
1248 {
1249 SET_BIT(RCC->CSR, RCC_CSR_LSION);
1250 }
1251
1252 /**
1253 * @brief Disable LSI Oscillator
1254 * @rmtoll CSR LSION LL_RCC_LSI_Disable
1255 * @retval None
1256 */
1257 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
1258 {
1259 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
1260 }
1261
1262 /**
1263 * @brief Check if LSI is Ready
1264 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
1265 * @retval State of bit (1 or 0).
1266 */
1267 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
1268 {
1269 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
1270 }
1271
1272 /**
1273 * @}
1274 */
1275
1276 /** @defgroup RCC_LL_EF_LSCO LSCO
1277 * @{
1278 */
1279
1280 /**
1281 * @brief Enable Low speed clock
1282 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
1283 * @retval None
1284 */
1285 __STATIC_INLINE void LL_RCC_LSCO_Enable(void)
1286 {
1287 SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1288 }
1289
1290 /**
1291 * @brief Disable Low speed clock
1292 * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
1293 * @retval None
1294 */
1295 __STATIC_INLINE void LL_RCC_LSCO_Disable(void)
1296 {
1297 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
1298 }
1299
1300 /**
1301 * @brief Configure Low speed clock selection
1302 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
1303 * @param Source This parameter can be one of the following values:
1304 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1305 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1306 * @retval None
1307 */
1308 __STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
1309 {
1310 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
1311 }
1312
1313 /**
1314 * @brief Get Low speed clock selection
1315 * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
1316 * @retval Returned value can be one of the following values:
1317 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
1318 * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
1319 */
1320 __STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
1321 {
1322 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
1323 }
1324
1325 /**
1326 * @}
1327 */
1328
1329 /** @defgroup RCC_LL_EF_System System
1330 * @{
1331 */
1332
1333 /**
1334 * @brief Configure the system clock source
1335 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
1336 * @param Source This parameter can be one of the following values:
1337 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
1338 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
1339 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
1340 * @retval None
1341 */
1342 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
1343 {
1344 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
1345 }
1346
1347 /**
1348 * @brief Get the system clock source
1349 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
1350 * @retval Returned value can be one of the following values:
1351 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
1352 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
1353 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
1354 */
1355 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
1356 {
1357 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
1358 }
1359
1360 /**
1361 * @brief Set AHB prescaler
1362 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
1363 * @param Prescaler This parameter can be one of the following values:
1364 * @arg @ref LL_RCC_SYSCLK_DIV_1
1365 * @arg @ref LL_RCC_SYSCLK_DIV_2
1366 * @arg @ref LL_RCC_SYSCLK_DIV_4
1367 * @arg @ref LL_RCC_SYSCLK_DIV_8
1368 * @arg @ref LL_RCC_SYSCLK_DIV_16
1369 * @arg @ref LL_RCC_SYSCLK_DIV_64
1370 * @arg @ref LL_RCC_SYSCLK_DIV_128
1371 * @arg @ref LL_RCC_SYSCLK_DIV_256
1372 * @arg @ref LL_RCC_SYSCLK_DIV_512
1373 * @retval None
1374 */
1375 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
1376 {
1377 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
1378 }
1379
1380 /**
1381 * @brief Set APB1 prescaler
1382 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
1383 * @param Prescaler This parameter can be one of the following values:
1384 * @arg @ref LL_RCC_APB1_DIV_1
1385 * @arg @ref LL_RCC_APB1_DIV_2
1386 * @arg @ref LL_RCC_APB1_DIV_4
1387 * @arg @ref LL_RCC_APB1_DIV_8
1388 * @arg @ref LL_RCC_APB1_DIV_16
1389 * @retval None
1390 */
1391 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
1392 {
1393 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
1394 }
1395
1396 /**
1397 * @brief Set APB2 prescaler
1398 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
1399 * @param Prescaler This parameter can be one of the following values:
1400 * @arg @ref LL_RCC_APB2_DIV_1
1401 * @arg @ref LL_RCC_APB2_DIV_2
1402 * @arg @ref LL_RCC_APB2_DIV_4
1403 * @arg @ref LL_RCC_APB2_DIV_8
1404 * @arg @ref LL_RCC_APB2_DIV_16
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
1408 {
1409 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
1410 }
1411
1412 /**
1413 * @brief Get AHB prescaler
1414 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
1415 * @retval Returned value can be one of the following values:
1416 * @arg @ref LL_RCC_SYSCLK_DIV_1
1417 * @arg @ref LL_RCC_SYSCLK_DIV_2
1418 * @arg @ref LL_RCC_SYSCLK_DIV_4
1419 * @arg @ref LL_RCC_SYSCLK_DIV_8
1420 * @arg @ref LL_RCC_SYSCLK_DIV_16
1421 * @arg @ref LL_RCC_SYSCLK_DIV_64
1422 * @arg @ref LL_RCC_SYSCLK_DIV_128
1423 * @arg @ref LL_RCC_SYSCLK_DIV_256
1424 * @arg @ref LL_RCC_SYSCLK_DIV_512
1425 */
1426 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
1427 {
1428 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
1429 }
1430
1431 /**
1432 * @brief Get APB1 prescaler
1433 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
1434 * @retval Returned value can be one of the following values:
1435 * @arg @ref LL_RCC_APB1_DIV_1
1436 * @arg @ref LL_RCC_APB1_DIV_2
1437 * @arg @ref LL_RCC_APB1_DIV_4
1438 * @arg @ref LL_RCC_APB1_DIV_8
1439 * @arg @ref LL_RCC_APB1_DIV_16
1440 */
1441 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
1442 {
1443 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
1444 }
1445
1446 /**
1447 * @brief Get APB2 prescaler
1448 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
1449 * @retval Returned value can be one of the following values:
1450 * @arg @ref LL_RCC_APB2_DIV_1
1451 * @arg @ref LL_RCC_APB2_DIV_2
1452 * @arg @ref LL_RCC_APB2_DIV_4
1453 * @arg @ref LL_RCC_APB2_DIV_8
1454 * @arg @ref LL_RCC_APB2_DIV_16
1455 */
1456 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
1457 {
1458 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
1459 }
1460
1461 /**
1462 * @}
1463 */
1464
1465 /** @defgroup RCC_LL_EF_MCO MCO
1466 * @{
1467 */
1468
1469 /**
1470 * @brief Configure MCOx
1471 * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
1472 * CFGR MCOPRE LL_RCC_ConfigMCO
1473 * @param MCOxSource This parameter can be one of the following values:
1474 * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
1475 * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
1476 * @arg @ref LL_RCC_MCO1SOURCE_HSI
1477 * @arg @ref LL_RCC_MCO1SOURCE_HSE
1478 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
1479 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
1480 * @arg @ref LL_RCC_MCO1SOURCE_LSI
1481 * @arg @ref LL_RCC_MCO1SOURCE_LSE
1482 *
1483 * (*) value not defined in all devices.
1484 * @param MCOxPrescaler This parameter can be one of the following values:
1485 * @arg @ref LL_RCC_MCO1_DIV_1
1486 * @arg @ref LL_RCC_MCO1_DIV_2
1487 * @arg @ref LL_RCC_MCO1_DIV_4
1488 * @arg @ref LL_RCC_MCO1_DIV_8
1489 * @arg @ref LL_RCC_MCO1_DIV_16
1490 * @retval None
1491 */
1492 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
1493 {
1494 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
1495 }
1496
1497 /**
1498 * @}
1499 */
1500
1501 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
1502 * @{
1503 */
1504
1505 /**
1506 * @brief Configure USARTx clock source
1507 * @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
1508 * @param USARTxSource This parameter can be one of the following values:
1509 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1510 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1511 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1512 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1513 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1514 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1515 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1516 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1517 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1518 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1519 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1520 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1521 * @retval None
1522 */
1523 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
1524 {
1525 MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
1526 }
1527
1528 #if defined(UART4)
1529 /**
1530 * @brief Configure UARTx clock source
1531 * @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
1532 * @param UARTxSource This parameter can be one of the following values:
1533 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1534 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1535 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1536 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1537 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1538 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1539 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1540 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1541 *
1542 * (*) value not defined in all devices.
1543 * @retval None
1544 */
1545 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
1546 {
1547 MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
1548 }
1549 #endif /* UART4 */
1550
1551 /**
1552 * @brief Configure LPUART1x clock source
1553 * @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
1554 * @param LPUARTxSource This parameter can be one of the following values:
1555 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1556 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1557 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1558 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1559 * @retval None
1560 */
1561 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
1562 {
1563 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
1564 }
1565
1566 /**
1567 * @brief Configure I2Cx clock source
1568 * @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
1569 * @param I2CxSource This parameter can be one of the following values:
1570 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1571 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1572 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1573 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1574 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1575 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1576 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1577 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1578 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1579 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1580 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1581 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1582 *
1583 * (*) value not defined in all devices.
1584 * @retval None
1585 */
1586 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
1587 {
1588 __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
1589 MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
1590 }
1591
1592 /**
1593 * @brief Configure LPTIMx clock source
1594 * @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
1595 * @param LPTIMxSource This parameter can be one of the following values:
1596 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1597 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1598 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1599 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1600 * @retval None
1601 */
1602 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
1603 {
1604 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
1605 }
1606
1607 /**
1608 * @brief Configure SAIx clock source
1609 * @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
1610 * @param SAIxSource This parameter can be one of the following values:
1611 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1612 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1613 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1614 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1615 *
1616 * (*) value not defined in all devices.
1617 * @retval None
1618 */
1619 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
1620 {
1621 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
1622 }
1623
1624 /**
1625 * @brief Configure I2S clock source
1626 * @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
1627 * @param I2SxSource This parameter can be one of the following values:
1628 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1629 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1630 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1631 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1632 * @retval None
1633 */
1634 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
1635 {
1636 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
1637 }
1638
1639 #if defined(FDCAN1)
1640 /**
1641 * @brief Configure FDCAN clock source
1642 * @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
1643 * @param FDCANxSource This parameter can be one of the following values:
1644 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1645 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1646 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1647 * @retval None
1648 */
1649 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
1650 {
1651 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
1652 }
1653 #endif /* FDCAN1 */
1654
1655 /**
1656 * @brief Configure RNG clock source
1657 * @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
1658 * @param RNGxSource This parameter can be one of the following values:
1659 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1660 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1661 * @retval None
1662 */
1663 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
1664 {
1665 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
1666 }
1667
1668 /**
1669 * @brief Configure USB clock source
1670 * @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
1671 * @param USBxSource This parameter can be one of the following values:
1672 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1673 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1674 * @retval None
1675 */
1676 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
1677 {
1678 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
1679 }
1680
1681 /**
1682 * @brief Configure ADC clock source
1683 * @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
1684 * CCIPR ADC345SEL LL_RCC_SetADCClockSource
1685 * @param ADCxSource This parameter can be one of the following values:
1686 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1687 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1688 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1689 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1690 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1691 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1692 *
1693 * (*) value not defined in all devices.
1694 * @retval None
1695 */
1696 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
1697 {
1698 MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
1699 }
1700
1701 #if defined(QUADSPI)
1702 /**
1703 * @brief Configure QUADSPI clock source
1704 * @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
1705 * @param Source This parameter can be one of the following values:
1706 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1707 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1708 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1709 * @retval None
1710 */
1711 __STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
1712 {
1713 MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
1714 }
1715 #endif /* QUADSPI */
1716
1717 /**
1718 * @brief Get USARTx clock source
1719 * @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
1720 * @param USARTx This parameter can be one of the following values:
1721 * @arg @ref LL_RCC_USART1_CLKSOURCE
1722 * @arg @ref LL_RCC_USART2_CLKSOURCE
1723 * @arg @ref LL_RCC_USART3_CLKSOURCE
1724 * @retval Returned value can be one of the following values:
1725 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
1726 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
1727 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
1728 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
1729 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
1730 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
1731 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
1732 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
1733 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
1734 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
1735 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
1736 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
1737 */
1738 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
1739 {
1740 return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
1741 }
1742
1743 #if defined(UART4)
1744 /**
1745 * @brief Get UARTx clock source
1746 * @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
1747 * @param UARTx This parameter can be one of the following values:
1748 * @arg @ref LL_RCC_UART4_CLKSOURCE (*)
1749 * @arg @ref LL_RCC_UART5_CLKSOURCE (*)
1750 * @retval Returned value can be one of the following values:
1751 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
1752 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
1753 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
1754 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
1755 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
1756 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
1757 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
1758 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
1759 *
1760 * (*) value not defined in all devices.
1761 */
1762 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
1763 {
1764 return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
1765 }
1766 #endif /* UART4 */
1767
1768 /**
1769 * @brief Get LPUARTx clock source
1770 * @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
1771 * @param LPUARTx This parameter can be one of the following values:
1772 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
1773 * @retval Returned value can be one of the following values:
1774 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
1775 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
1776 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
1777 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
1778 */
1779 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
1780 {
1781 return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
1782 }
1783
1784 /**
1785 * @brief Get I2Cx clock source
1786 * @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
1787 * @param I2Cx This parameter can be one of the following values:
1788 * @arg @ref LL_RCC_I2C1_CLKSOURCE
1789 * @arg @ref LL_RCC_I2C2_CLKSOURCE
1790 * @arg @ref LL_RCC_I2C3_CLKSOURCE
1791 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
1792 *
1793 * (*) value not defined in all devices.
1794 * @retval Returned value can be one of the following values:
1795 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
1796 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
1797 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
1798 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
1799 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
1800 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
1801 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
1802 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
1803 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
1804 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
1805 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
1806 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
1807 *
1808 * (*) value not defined in all devices.
1809 */
1810 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
1811 {
1812 __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
1813 return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
1814 }
1815
1816 /**
1817 * @brief Get LPTIMx clock source
1818 * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
1819 * @param LPTIMx This parameter can be one of the following values:
1820 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
1821 * @retval Returned value can be one of the following values:
1822 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
1823 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
1824 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
1825 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
1826 */
1827 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
1828 {
1829 return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
1830 }
1831
1832 /**
1833 * @brief Get SAIx clock source
1834 * @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
1835 * @param SAIx This parameter can be one of the following values:
1836 * @arg @ref LL_RCC_SAI1_CLKSOURCE
1837 *
1838 * (*) value not defined in all devices.
1839 * @retval Returned value can be one of the following values:
1840 * @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
1841 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
1842 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
1843 * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
1844 *
1845 * (*) value not defined in all devices.
1846 */
1847 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
1848 {
1849 return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
1850 }
1851
1852 /**
1853 * @brief Get I2Sx clock source
1854 * @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
1855 * @param I2Sx This parameter can be one of the following values:
1856 * @arg @ref LL_RCC_I2S_CLKSOURCE
1857 * @retval Returned value can be one of the following values:
1858 * @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
1859 * @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
1860 * @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
1861 * @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
1862 */
1863 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
1864 {
1865 return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
1866 }
1867
1868 #if defined(FDCAN1)
1869 /**
1870 * @brief Get FDCANx clock source
1871 * @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
1872 * @param FDCANx This parameter can be one of the following values:
1873 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
1874 * @retval Returned value can be one of the following values:
1875 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
1876 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
1877 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
1878 * @retval None
1879 */
1880 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
1881 {
1882 return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
1883 }
1884 #endif /* FDCAN1 */
1885
1886 /**
1887 * @brief Get RNGx clock source
1888 * @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
1889 * @param RNGx This parameter can be one of the following values:
1890 * @arg @ref LL_RCC_RNG_CLKSOURCE
1891 * @retval Returned value can be one of the following values:
1892 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
1893 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
1894 */
1895 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
1896 {
1897 return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
1898 }
1899
1900 /**
1901 * @brief Get USBx clock source
1902 * @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
1903 * @param USBx This parameter can be one of the following values:
1904 * @arg @ref LL_RCC_USB_CLKSOURCE
1905 * @retval Returned value can be one of the following values:
1906 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
1907 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
1908 */
1909 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
1910 {
1911 return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
1912 }
1913
1914 /**
1915 * @brief Get ADCx clock source
1916 * @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
1917 * @param ADCx This parameter can be one of the following values:
1918 * @arg @ref LL_RCC_ADC12_CLKSOURCE
1919 * @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
1920 * @retval Returned value can be one of the following values:
1921 * @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
1922 * @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
1923 * @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
1924 * @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
1925 * @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
1926 * @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
1927 *
1928 * (*) value not defined in all devices.
1929 */
1930 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
1931 {
1932 return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
1933 }
1934
1935 #if defined(QUADSPI)
1936 /**
1937 * @brief Get QUADSPI clock source
1938 * @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
1939 * @param QUADSPIx This parameter can be one of the following values:
1940 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE
1941 * @retval Returned value can be one of the following values:
1942 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
1943 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
1944 * @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
1945 */
1946 __STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
1947 {
1948 return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
1949 }
1950 #endif /* QUADSPI */
1951 /**
1952 * @}
1953 */
1954
1955 /** @defgroup RCC_LL_EF_RTC RTC
1956 * @{
1957 */
1958
1959 /**
1960 * @brief Set RTC Clock Source
1961 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
1962 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
1963 * set). The BDRST bit can be used to reset them.
1964 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
1965 * @param Source This parameter can be one of the following values:
1966 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1967 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1968 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1969 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1970 * @retval None
1971 */
1972 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
1973 {
1974 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
1975 }
1976
1977 /**
1978 * @brief Get RTC Clock Source
1979 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
1980 * @retval Returned value can be one of the following values:
1981 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
1982 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
1983 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
1984 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
1985 */
1986 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
1987 {
1988 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
1989 }
1990
1991 /**
1992 * @brief Enable RTC
1993 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
1994 * @retval None
1995 */
1996 __STATIC_INLINE void LL_RCC_EnableRTC(void)
1997 {
1998 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
1999 }
2000
2001 /**
2002 * @brief Disable RTC
2003 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2004 * @retval None
2005 */
2006 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2007 {
2008 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2009 }
2010
2011 /**
2012 * @brief Check if RTC has been enabled or not
2013 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2014 * @retval State of bit (1 or 0).
2015 */
2016 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2017 {
2018 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
2019 }
2020
2021 /**
2022 * @brief Force the Backup domain reset
2023 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2024 * @retval None
2025 */
2026 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
2027 {
2028 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2029 }
2030
2031 /**
2032 * @brief Release the Backup domain reset
2033 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
2034 * @retval None
2035 */
2036 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
2037 {
2038 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
2039 }
2040
2041 /**
2042 * @}
2043 */
2044
2045
2046 /** @defgroup RCC_LL_EF_PLL PLL
2047 * @{
2048 */
2049
2050 /**
2051 * @brief Enable PLL
2052 * @rmtoll CR PLLON LL_RCC_PLL_Enable
2053 * @retval None
2054 */
2055 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
2056 {
2057 SET_BIT(RCC->CR, RCC_CR_PLLON);
2058 }
2059
2060 /**
2061 * @brief Disable PLL
2062 * @note Cannot be disabled if the PLL clock is used as the system clock
2063 * @rmtoll CR PLLON LL_RCC_PLL_Disable
2064 * @retval None
2065 */
2066 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
2067 {
2068 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
2069 }
2070
2071 /**
2072 * @brief Check if PLL Ready
2073 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
2074 * @retval State of bit (1 or 0).
2075 */
2076 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
2077 {
2078 return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
2079 }
2080
2081 /**
2082 * @brief Configure PLL used for SYSCLK Domain
2083 * @note PLL Source and PLLM Divider can be written only when PLL
2084 * is disabled.
2085 * @note PLLN/PLLR can be written only when PLL is disabled.
2086 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
2087 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
2088 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
2089 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
2090 * @param Source This parameter can be one of the following values:
2091 * @arg @ref LL_RCC_PLLSOURCE_NONE
2092 * @arg @ref LL_RCC_PLLSOURCE_HSI
2093 * @arg @ref LL_RCC_PLLSOURCE_HSE
2094 * @param PLLM This parameter can be one of the following values:
2095 * @arg @ref LL_RCC_PLLM_DIV_1
2096 * @arg @ref LL_RCC_PLLM_DIV_2
2097 * @arg @ref LL_RCC_PLLM_DIV_3
2098 * @arg @ref LL_RCC_PLLM_DIV_4
2099 * @arg @ref LL_RCC_PLLM_DIV_5
2100 * @arg @ref LL_RCC_PLLM_DIV_6
2101 * @arg @ref LL_RCC_PLLM_DIV_7
2102 * @arg @ref LL_RCC_PLLM_DIV_8
2103 * @arg @ref LL_RCC_PLLM_DIV_9
2104 * @arg @ref LL_RCC_PLLM_DIV_10
2105 * @arg @ref LL_RCC_PLLM_DIV_11
2106 * @arg @ref LL_RCC_PLLM_DIV_12
2107 * @arg @ref LL_RCC_PLLM_DIV_13
2108 * @arg @ref LL_RCC_PLLM_DIV_14
2109 * @arg @ref LL_RCC_PLLM_DIV_15
2110 * @arg @ref LL_RCC_PLLM_DIV_16
2111 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2112 * @param PLLR This parameter can be one of the following values:
2113 * @arg @ref LL_RCC_PLLR_DIV_2
2114 * @arg @ref LL_RCC_PLLR_DIV_4
2115 * @arg @ref LL_RCC_PLLR_DIV_6
2116 * @arg @ref LL_RCC_PLLR_DIV_8
2117 * @retval None
2118 */
2119 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
2120 {
2121 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
2122 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
2123 }
2124
2125 /**
2126 * @brief Configure PLL used for ADC domain clock
2127 * @note PLL Source and PLLM Divider can be written only when PLL
2128 * is disabled.
2129 * @note PLLN/PLLP can be written only when PLL is disabled.
2130 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
2131 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
2132 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
2133 * PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
2134 * @param Source This parameter can be one of the following values:
2135 * @arg @ref LL_RCC_PLLSOURCE_NONE
2136 * @arg @ref LL_RCC_PLLSOURCE_HSI
2137 * @arg @ref LL_RCC_PLLSOURCE_HSE
2138 * @param PLLM This parameter can be one of the following values:
2139 * @arg @ref LL_RCC_PLLM_DIV_1
2140 * @arg @ref LL_RCC_PLLM_DIV_2
2141 * @arg @ref LL_RCC_PLLM_DIV_3
2142 * @arg @ref LL_RCC_PLLM_DIV_4
2143 * @arg @ref LL_RCC_PLLM_DIV_5
2144 * @arg @ref LL_RCC_PLLM_DIV_6
2145 * @arg @ref LL_RCC_PLLM_DIV_7
2146 * @arg @ref LL_RCC_PLLM_DIV_8
2147 * @arg @ref LL_RCC_PLLM_DIV_9
2148 * @arg @ref LL_RCC_PLLM_DIV_10
2149 * @arg @ref LL_RCC_PLLM_DIV_11
2150 * @arg @ref LL_RCC_PLLM_DIV_12
2151 * @arg @ref LL_RCC_PLLM_DIV_13
2152 * @arg @ref LL_RCC_PLLM_DIV_14
2153 * @arg @ref LL_RCC_PLLM_DIV_15
2154 * @arg @ref LL_RCC_PLLM_DIV_16
2155 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2156 * @param PLLP This parameter can be one of the following values:
2157 * @arg @ref LL_RCC_PLLP_DIV_2
2158 * @arg @ref LL_RCC_PLLP_DIV_3
2159 * @arg @ref LL_RCC_PLLP_DIV_4
2160 * @arg @ref LL_RCC_PLLP_DIV_5
2161 * @arg @ref LL_RCC_PLLP_DIV_6
2162 * @arg @ref LL_RCC_PLLP_DIV_7
2163 * @arg @ref LL_RCC_PLLP_DIV_8
2164 * @arg @ref LL_RCC_PLLP_DIV_9
2165 * @arg @ref LL_RCC_PLLP_DIV_10
2166 * @arg @ref LL_RCC_PLLP_DIV_11
2167 * @arg @ref LL_RCC_PLLP_DIV_12
2168 * @arg @ref LL_RCC_PLLP_DIV_13
2169 * @arg @ref LL_RCC_PLLP_DIV_14
2170 * @arg @ref LL_RCC_PLLP_DIV_15
2171 * @arg @ref LL_RCC_PLLP_DIV_16
2172 * @arg @ref LL_RCC_PLLP_DIV_17
2173 * @arg @ref LL_RCC_PLLP_DIV_18
2174 * @arg @ref LL_RCC_PLLP_DIV_19
2175 * @arg @ref LL_RCC_PLLP_DIV_20
2176 * @arg @ref LL_RCC_PLLP_DIV_21
2177 * @arg @ref LL_RCC_PLLP_DIV_22
2178 * @arg @ref LL_RCC_PLLP_DIV_23
2179 * @arg @ref LL_RCC_PLLP_DIV_24
2180 * @arg @ref LL_RCC_PLLP_DIV_25
2181 * @arg @ref LL_RCC_PLLP_DIV_26
2182 * @arg @ref LL_RCC_PLLP_DIV_27
2183 * @arg @ref LL_RCC_PLLP_DIV_28
2184 * @arg @ref LL_RCC_PLLP_DIV_29
2185 * @arg @ref LL_RCC_PLLP_DIV_30
2186 * @arg @ref LL_RCC_PLLP_DIV_31
2187 * @retval None
2188 */
2189 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
2190 {
2191 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
2192 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
2193 }
2194
2195 /**
2196 * @brief Configure PLL used for 48Mhz domain clock
2197 * @note PLL Source and PLLM Divider can be written only when PLL,
2198 * is disabled.
2199 * @note PLLN/PLLQ can be written only when PLL is disabled.
2200 * @note This can be selected for USB, RNG
2201 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
2202 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
2203 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
2204 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
2205 * @param Source This parameter can be one of the following values:
2206 * @arg @ref LL_RCC_PLLSOURCE_NONE
2207 * @arg @ref LL_RCC_PLLSOURCE_HSI
2208 * @arg @ref LL_RCC_PLLSOURCE_HSE
2209 * @param PLLM This parameter can be one of the following values:
2210 * @arg @ref LL_RCC_PLLM_DIV_1
2211 * @arg @ref LL_RCC_PLLM_DIV_2
2212 * @arg @ref LL_RCC_PLLM_DIV_3
2213 * @arg @ref LL_RCC_PLLM_DIV_4
2214 * @arg @ref LL_RCC_PLLM_DIV_5
2215 * @arg @ref LL_RCC_PLLM_DIV_6
2216 * @arg @ref LL_RCC_PLLM_DIV_7
2217 * @arg @ref LL_RCC_PLLM_DIV_8
2218 * @arg @ref LL_RCC_PLLM_DIV_9
2219 * @arg @ref LL_RCC_PLLM_DIV_10
2220 * @arg @ref LL_RCC_PLLM_DIV_11
2221 * @arg @ref LL_RCC_PLLM_DIV_12
2222 * @arg @ref LL_RCC_PLLM_DIV_13
2223 * @arg @ref LL_RCC_PLLM_DIV_14
2224 * @arg @ref LL_RCC_PLLM_DIV_15
2225 * @arg @ref LL_RCC_PLLM_DIV_16
2226 * @param PLLN Between Min_Data = 8 and Max_Data = 127
2227 * @param PLLQ This parameter can be one of the following values:
2228 * @arg @ref LL_RCC_PLLQ_DIV_2
2229 * @arg @ref LL_RCC_PLLQ_DIV_4
2230 * @arg @ref LL_RCC_PLLQ_DIV_6
2231 * @arg @ref LL_RCC_PLLQ_DIV_8
2232 * @retval None
2233 */
2234 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
2235 {
2236 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
2237 Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
2238 }
2239
2240 /**
2241 * @brief Configure PLL clock source
2242 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
2243 * @param PLLSource This parameter can be one of the following values:
2244 * @arg @ref LL_RCC_PLLSOURCE_NONE
2245 * @arg @ref LL_RCC_PLLSOURCE_HSI
2246 * @arg @ref LL_RCC_PLLSOURCE_HSE
2247 * @retval None
2248 */
2249 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
2250 {
2251 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
2252 }
2253
2254 /**
2255 * @brief Get the oscillator used as PLL clock source.
2256 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
2257 * @retval Returned value can be one of the following values:
2258 * @arg @ref LL_RCC_PLLSOURCE_NONE
2259 * @arg @ref LL_RCC_PLLSOURCE_HSI
2260 * @arg @ref LL_RCC_PLLSOURCE_HSE
2261 */
2262 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
2263 {
2264 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
2265 }
2266
2267 /**
2268 * @brief Get Main PLL multiplication factor for VCO
2269 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
2270 * @retval Between Min_Data = 8 and Max_Data = 127
2271 */
2272 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
2273 {
2274 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
2275 }
2276
2277 /**
2278 * @brief Get Main PLL division factor for PLLP
2279 * @note Used for PLLADCCLK (ADC clock)
2280 * @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
2281 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
2282 * @retval Returned value can be one of the following values:
2283 * @arg @ref LL_RCC_PLLP_DIV_2
2284 * @arg @ref LL_RCC_PLLP_DIV_3
2285 * @arg @ref LL_RCC_PLLP_DIV_4
2286 * @arg @ref LL_RCC_PLLP_DIV_5
2287 * @arg @ref LL_RCC_PLLP_DIV_6
2288 * @arg @ref LL_RCC_PLLP_DIV_7
2289 * @arg @ref LL_RCC_PLLP_DIV_8
2290 * @arg @ref LL_RCC_PLLP_DIV_9
2291 * @arg @ref LL_RCC_PLLP_DIV_10
2292 * @arg @ref LL_RCC_PLLP_DIV_11
2293 * @arg @ref LL_RCC_PLLP_DIV_12
2294 * @arg @ref LL_RCC_PLLP_DIV_13
2295 * @arg @ref LL_RCC_PLLP_DIV_14
2296 * @arg @ref LL_RCC_PLLP_DIV_15
2297 * @arg @ref LL_RCC_PLLP_DIV_16
2298 * @arg @ref LL_RCC_PLLP_DIV_17
2299 * @arg @ref LL_RCC_PLLP_DIV_18
2300 * @arg @ref LL_RCC_PLLP_DIV_19
2301 * @arg @ref LL_RCC_PLLP_DIV_20
2302 * @arg @ref LL_RCC_PLLP_DIV_21
2303 * @arg @ref LL_RCC_PLLP_DIV_22
2304 * @arg @ref LL_RCC_PLLP_DIV_23
2305 * @arg @ref LL_RCC_PLLP_DIV_24
2306 * @arg @ref LL_RCC_PLLP_DIV_25
2307 * @arg @ref LL_RCC_PLLP_DIV_26
2308 * @arg @ref LL_RCC_PLLP_DIV_27
2309 * @arg @ref LL_RCC_PLLP_DIV_28
2310 * @arg @ref LL_RCC_PLLP_DIV_29
2311 * @arg @ref LL_RCC_PLLP_DIV_30
2312 * @arg @ref LL_RCC_PLLP_DIV_31
2313 */
2314 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
2315 {
2316 return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
2317 }
2318
2319 /**
2320 * @brief Get Main PLL division factor for PLLQ
2321 * @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
2322 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
2323 * @retval Returned value can be one of the following values:
2324 * @arg @ref LL_RCC_PLLQ_DIV_2
2325 * @arg @ref LL_RCC_PLLQ_DIV_4
2326 * @arg @ref LL_RCC_PLLQ_DIV_6
2327 * @arg @ref LL_RCC_PLLQ_DIV_8
2328 */
2329 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
2330 {
2331 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
2332 }
2333
2334 /**
2335 * @brief Get Main PLL division factor for PLLR
2336 * @note Used for PLLCLK (system clock)
2337 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
2338 * @retval Returned value can be one of the following values:
2339 * @arg @ref LL_RCC_PLLR_DIV_2
2340 * @arg @ref LL_RCC_PLLR_DIV_4
2341 * @arg @ref LL_RCC_PLLR_DIV_6
2342 * @arg @ref LL_RCC_PLLR_DIV_8
2343 */
2344 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
2345 {
2346 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
2347 }
2348
2349 /**
2350 * @brief Get Division factor for the main PLL and other PLL
2351 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
2352 * @retval Returned value can be one of the following values:
2353 * @arg @ref LL_RCC_PLLM_DIV_1
2354 * @arg @ref LL_RCC_PLLM_DIV_2
2355 * @arg @ref LL_RCC_PLLM_DIV_3
2356 * @arg @ref LL_RCC_PLLM_DIV_4
2357 * @arg @ref LL_RCC_PLLM_DIV_5
2358 * @arg @ref LL_RCC_PLLM_DIV_6
2359 * @arg @ref LL_RCC_PLLM_DIV_7
2360 * @arg @ref LL_RCC_PLLM_DIV_8
2361 * @arg @ref LL_RCC_PLLM_DIV_9
2362 * @arg @ref LL_RCC_PLLM_DIV_10
2363 * @arg @ref LL_RCC_PLLM_DIV_11
2364 * @arg @ref LL_RCC_PLLM_DIV_12
2365 * @arg @ref LL_RCC_PLLM_DIV_13
2366 * @arg @ref LL_RCC_PLLM_DIV_14
2367 * @arg @ref LL_RCC_PLLM_DIV_15
2368 * @arg @ref LL_RCC_PLLM_DIV_16
2369 */
2370 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
2371 {
2372 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
2373 }
2374
2375 /**
2376 * @brief Enable PLL output mapped on ADC domain clock
2377 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
2378 * @retval None
2379 */
2380 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
2381 {
2382 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2383 }
2384
2385 /**
2386 * @brief Disable PLL output mapped on ADC domain clock
2387 * @note Cannot be disabled if the PLL clock is used as the system
2388 * clock
2389 * @note In order to save power, when the PLLCLK of the PLL is
2390 * not used, should be 0
2391 * @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
2392 * @retval None
2393 */
2394 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
2395 {
2396 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
2397 }
2398
2399 /**
2400 * @brief Enable PLL output mapped on 48MHz domain clock
2401 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
2402 * @retval None
2403 */
2404 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
2405 {
2406 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2407 }
2408
2409 /**
2410 * @brief Disable PLL output mapped on 48MHz domain clock
2411 * @note Cannot be disabled if the PLL clock is used as the system
2412 * clock
2413 * @note In order to save power, when the PLLCLK of the PLL is
2414 * not used, should be 0
2415 * @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
2416 * @retval None
2417 */
2418 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
2419 {
2420 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
2421 }
2422
2423 /**
2424 * @brief Enable PLL output mapped on SYSCLK domain
2425 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
2426 * @retval None
2427 */
2428 __STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
2429 {
2430 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2431 }
2432
2433 /**
2434 * @brief Disable PLL output mapped on SYSCLK domain
2435 * @note Cannot be disabled if the PLL clock is used as the system
2436 * clock
2437 * @note In order to save power, when the PLLCLK of the PLL is
2438 * not used, Main PLL should be 0
2439 * @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
2440 * @retval None
2441 */
2442 __STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
2443 {
2444 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
2445 }
2446
2447 /**
2448 * @}
2449 */
2450
2451 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
2452 * @{
2453 */
2454
2455 /**
2456 * @brief Clear LSI ready interrupt flag
2457 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
2458 * @retval None
2459 */
2460 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
2461 {
2462 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
2463 }
2464
2465 /**
2466 * @brief Clear LSE ready interrupt flag
2467 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
2468 * @retval None
2469 */
2470 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
2471 {
2472 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
2473 }
2474
2475 /**
2476 * @brief Clear HSI ready interrupt flag
2477 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
2478 * @retval None
2479 */
2480 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
2481 {
2482 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
2483 }
2484
2485 /**
2486 * @brief Clear HSE ready interrupt flag
2487 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
2488 * @retval None
2489 */
2490 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
2491 {
2492 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
2493 }
2494
2495 /**
2496 * @brief Clear PLL ready interrupt flag
2497 * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
2498 * @retval None
2499 */
2500 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
2501 {
2502 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
2503 }
2504
2505 /**
2506 * @brief Clear HSI48 ready interrupt flag
2507 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
2508 * @retval None
2509 */
2510 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
2511 {
2512 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
2513 }
2514
2515 /**
2516 * @brief Clear Clock security system interrupt flag
2517 * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
2518 * @retval None
2519 */
2520 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
2521 {
2522 SET_BIT(RCC->CICR, RCC_CICR_CSSC);
2523 }
2524
2525 /**
2526 * @brief Clear LSE Clock security system interrupt flag
2527 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
2528 * @retval None
2529 */
2530 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
2531 {
2532 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
2533 }
2534
2535 /**
2536 * @brief Check if LSI ready interrupt occurred or not
2537 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
2538 * @retval State of bit (1 or 0).
2539 */
2540 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
2541 {
2542 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
2543 }
2544
2545 /**
2546 * @brief Check if LSE ready interrupt occurred or not
2547 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
2548 * @retval State of bit (1 or 0).
2549 */
2550 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
2551 {
2552 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
2553 }
2554
2555 /**
2556 * @brief Check if HSI ready interrupt occurred or not
2557 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
2558 * @retval State of bit (1 or 0).
2559 */
2560 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
2561 {
2562 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
2563 }
2564
2565 /**
2566 * @brief Check if HSE ready interrupt occurred or not
2567 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
2568 * @retval State of bit (1 or 0).
2569 */
2570 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
2571 {
2572 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
2573 }
2574
2575 /**
2576 * @brief Check if PLL ready interrupt occurred or not
2577 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
2578 * @retval State of bit (1 or 0).
2579 */
2580 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
2581 {
2582 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
2583 }
2584
2585 /**
2586 * @brief Check if HSI48 ready interrupt occurred or not
2587 * @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
2588 * @retval State of bit (1 or 0).
2589 */
2590 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
2591 {
2592 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
2593 }
2594
2595 /**
2596 * @brief Check if Clock security system interrupt occurred or not
2597 * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
2598 * @retval State of bit (1 or 0).
2599 */
2600 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
2601 {
2602 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
2603 }
2604
2605 /**
2606 * @brief Check if LSE Clock security system interrupt occurred or not
2607 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
2608 * @retval State of bit (1 or 0).
2609 */
2610 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
2611 {
2612 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
2613 }
2614
2615 /**
2616 * @brief Check if RCC flag Independent Watchdog reset is set or not.
2617 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
2618 * @retval State of bit (1 or 0).
2619 */
2620 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
2621 {
2622 return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
2623 }
2624
2625 /**
2626 * @brief Check if RCC flag Low Power reset is set or not.
2627 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
2628 * @retval State of bit (1 or 0).
2629 */
2630 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
2631 {
2632 return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
2633 }
2634
2635 /**
2636 * @brief Check if RCC flag Option byte reset is set or not.
2637 * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
2638 * @retval State of bit (1 or 0).
2639 */
2640 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
2641 {
2642 return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
2643 }
2644
2645 /**
2646 * @brief Check if RCC flag Pin reset is set or not.
2647 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
2648 * @retval State of bit (1 or 0).
2649 */
2650 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
2651 {
2652 return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
2653 }
2654
2655 /**
2656 * @brief Check if RCC flag Software reset is set or not.
2657 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
2658 * @retval State of bit (1 or 0).
2659 */
2660 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
2661 {
2662 return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
2663 }
2664
2665 /**
2666 * @brief Check if RCC flag Window Watchdog reset is set or not.
2667 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
2668 * @retval State of bit (1 or 0).
2669 */
2670 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
2671 {
2672 return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
2673 }
2674
2675 /**
2676 * @brief Check if RCC flag BOR reset is set or not.
2677 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
2678 * @retval State of bit (1 or 0).
2679 */
2680 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
2681 {
2682 return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
2683 }
2684
2685 /**
2686 * @brief Set RMVF bit to clear the reset flags.
2687 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
2688 * @retval None
2689 */
2690 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
2691 {
2692 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
2693 }
2694
2695 /**
2696 * @}
2697 */
2698
2699 /** @defgroup RCC_LL_EF_IT_Management IT Management
2700 * @{
2701 */
2702
2703 /**
2704 * @brief Enable LSI ready interrupt
2705 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
2706 * @retval None
2707 */
2708 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
2709 {
2710 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2711 }
2712
2713 /**
2714 * @brief Enable LSE ready interrupt
2715 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
2716 * @retval None
2717 */
2718 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
2719 {
2720 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2721 }
2722
2723 /**
2724 * @brief Enable HSI ready interrupt
2725 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
2726 * @retval None
2727 */
2728 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
2729 {
2730 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2731 }
2732
2733 /**
2734 * @brief Enable HSE ready interrupt
2735 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
2736 * @retval None
2737 */
2738 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
2739 {
2740 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2741 }
2742
2743 /**
2744 * @brief Enable PLL ready interrupt
2745 * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
2746 * @retval None
2747 */
2748 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
2749 {
2750 SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2751 }
2752
2753 /**
2754 * @brief Enable HSI48 ready interrupt
2755 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
2756 * @retval None
2757 */
2758 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
2759 {
2760 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2761 }
2762
2763 /**
2764 * @brief Enable LSE clock security system interrupt
2765 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
2766 * @retval None
2767 */
2768 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
2769 {
2770 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2771 }
2772
2773 /**
2774 * @brief Disable LSI ready interrupt
2775 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
2776 * @retval None
2777 */
2778 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
2779 {
2780 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
2781 }
2782
2783 /**
2784 * @brief Disable LSE ready interrupt
2785 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
2786 * @retval None
2787 */
2788 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
2789 {
2790 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
2791 }
2792
2793 /**
2794 * @brief Disable HSI ready interrupt
2795 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
2796 * @retval None
2797 */
2798 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
2799 {
2800 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
2801 }
2802
2803 /**
2804 * @brief Disable HSE ready interrupt
2805 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
2806 * @retval None
2807 */
2808 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
2809 {
2810 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
2811 }
2812
2813 /**
2814 * @brief Disable PLL ready interrupt
2815 * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
2816 * @retval None
2817 */
2818 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
2819 {
2820 CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
2821 }
2822
2823 /**
2824 * @brief Disable HSI48 ready interrupt
2825 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
2826 * @retval None
2827 */
2828 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
2829 {
2830 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
2831 }
2832
2833 /**
2834 * @brief Disable LSE clock security system interrupt
2835 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
2836 * @retval None
2837 */
2838 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
2839 {
2840 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
2841 }
2842
2843 /**
2844 * @brief Checks if LSI ready interrupt source is enabled or disabled.
2845 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
2846 * @retval State of bit (1 or 0).
2847 */
2848 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
2849 {
2850 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
2851 }
2852
2853 /**
2854 * @brief Checks if LSE ready interrupt source is enabled or disabled.
2855 * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
2856 * @retval State of bit (1 or 0).
2857 */
2858 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
2859 {
2860 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
2861 }
2862
2863 /**
2864 * @brief Checks if HSI ready interrupt source is enabled or disabled.
2865 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
2866 * @retval State of bit (1 or 0).
2867 */
2868 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
2869 {
2870 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
2871 }
2872
2873 /**
2874 * @brief Checks if HSE ready interrupt source is enabled or disabled.
2875 * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
2876 * @retval State of bit (1 or 0).
2877 */
2878 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
2879 {
2880 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
2881 }
2882
2883 /**
2884 * @brief Checks if PLL ready interrupt source is enabled or disabled.
2885 * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
2886 * @retval State of bit (1 or 0).
2887 */
2888 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
2889 {
2890 return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
2891 }
2892
2893 /**
2894 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
2895 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
2896 * @retval State of bit (1 or 0).
2897 */
2898 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
2899 {
2900 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
2901 }
2902
2903 /**
2904 * @brief Checks if LSECSS interrupt source is enabled or disabled.
2905 * @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
2906 * @retval State of bit (1 or 0).
2907 */
2908 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
2909 {
2910 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
2911 }
2912
2913 /**
2914 * @}
2915 */
2916
2917 #if defined(USE_FULL_LL_DRIVER)
2918 /** @defgroup RCC_LL_EF_Init De-initialization function
2919 * @{
2920 */
2921 ErrorStatus LL_RCC_DeInit(void);
2922 /**
2923 * @}
2924 */
2925
2926 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
2927 * @{
2928 */
2929 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
2930 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
2931 #if defined(UART4)
2932 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
2933 #endif /* UART4 */
2934 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
2935 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
2936 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
2937 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
2938 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
2939 #if defined(FDCAN1)
2940 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
2941 #endif /* FDCAN1 */
2942 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
2943 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
2944 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
2945 #if defined(QUADSPI)
2946 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
2947 #endif /* QUADSPI */
2948 /**
2949 * @}
2950 */
2951 #endif /* USE_FULL_LL_DRIVER */
2952
2953 /**
2954 * @}
2955 */
2956
2957 /**
2958 * @}
2959 */
2960
2961 /**
2962 * @}
2963 */
2964
2965 #ifdef __cplusplus
2966 }
2967 #endif
2968
2969 #endif /* STM32G4xx_LL_RCC_H */
2970
2971 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/