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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_tim.h
blob1d064341a422f3e6b227faf54786f54ed7a3bcaa
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32G4xx_LL_TIM_H
22 #define __STM32G4xx_LL_TIM_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
36
37 /** @defgroup TIM_LL TIM
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
44 * @{
45 */
46 static const uint8_t OFFSET_TAB_CCMRx[] =
47 {
48 0x00U, /* 0: TIMx_CH1 */
49 0x00U, /* 1: TIMx_CH1N */
50 0x00U, /* 2: TIMx_CH2 */
51 0x00U, /* 3: TIMx_CH2N */
52 0x04U, /* 4: TIMx_CH3 */
53 0x04U, /* 5: TIMx_CH3N */
54 0x04U, /* 6: TIMx_CH4 */
55 0x04U, /* 7: TIMx_CH4N */
56 0x38U, /* 8: TIMx_CH5 */
57 0x38U /* 9: TIMx_CH6 */
58
59 };
60
61 static const uint8_t SHIFT_TAB_OCxx[] =
62 {
63 0U, /* 0: OC1M, OC1FE, OC1PE */
64 0U, /* 1: - NA */
65 8U, /* 2: OC2M, OC2FE, OC2PE */
66 0U, /* 3: - NA */
67 0U, /* 4: OC3M, OC3FE, OC3PE */
68 0U, /* 5: - NA */
69 8U, /* 6: OC4M, OC4FE, OC4PE */
70 0U, /* 7: - NA */
71 0U, /* 8: OC5M, OC5FE, OC5PE */
72 8U /* 9: OC6M, OC6FE, OC6PE */
73 };
74
75 static const uint8_t SHIFT_TAB_ICxx[] =
76 {
77 0U, /* 0: CC1S, IC1PSC, IC1F */
78 0U, /* 1: - NA */
79 8U, /* 2: CC2S, IC2PSC, IC2F */
80 0U, /* 3: - NA */
81 0U, /* 4: CC3S, IC3PSC, IC3F */
82 0U, /* 5: - NA */
83 8U, /* 6: CC4S, IC4PSC, IC4F */
84 0U, /* 7: - NA */
85 0U, /* 8: - NA */
86 0U /* 9: - NA */
87 };
88
89 static const uint8_t SHIFT_TAB_CCxP[] =
90 {
91 0U, /* 0: CC1P */
92 2U, /* 1: CC1NP */
93 4U, /* 2: CC2P */
94 6U, /* 3: CC2NP */
95 8U, /* 4: CC3P */
96 10U, /* 5: CC3NP */
97 12U, /* 6: CC4P */
98 14U, /* 7: CC4NP */
99 16U, /* 8: CC5P */
100 20U /* 9: CC6P */
101 };
102
103 static const uint8_t SHIFT_TAB_OISx[] =
104 {
105 0U, /* 0: OIS1 */
106 1U, /* 1: OIS1N */
107 2U, /* 2: OIS2 */
108 3U, /* 3: OIS2N */
109 4U, /* 4: OIS3 */
110 5U, /* 5: OIS3N */
111 6U, /* 6: OIS4 */
112 7U, /* 7: OIS4N */
113 8U, /* 8: OIS5 */
114 10U /* 9: OIS6 */
115 };
116 /**
117 * @}
118 */
119
120 /* Private constants ---------------------------------------------------------*/
121 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
122 * @{
123 */
124
125 /* Defines used for the bit position in the register and perform offsets */
126 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
127
128 /* Generic bit definitions for TIMx_AF1 register */
129 #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKIN input enable */
130 #define TIMx_AF1_BKCOMP1E TIM1_AF1_BKCMP1E /*!< BRK COMP1 enable */
131 #define TIMx_AF1_BKCOMP2E TIM1_AF1_BKCMP2E /*!< BRK COMP2 enable */
132 #define TIMx_AF1_BKCOMP3E TIM1_AF1_BKCMP3E /*!< BRK COMP3 enable */
133 #define TIMx_AF1_BKCOMP4E TIM1_AF1_BKCMP4E /*!< BRK COMP4 enable */
134 #if defined(COMP5)
135 #define TIMx_AF1_BKCOMP5E TIM1_AF1_BKCMP5E /*!< BRK COMP5 enable */
136 #endif /* COMP5 */
137 #if defined(COMP6)
138 #define TIMx_AF1_BKCOMP6E TIM1_AF1_BKCMP6E /*!< BRK COMP6 enable */
139 #endif /* COMP6 */
140 #if defined(COMP7)
141 #define TIMx_AF1_BKCOMP7E TIM1_AF1_BKCMP7E /*!< BRK COMP7 enable */
142 #endif /* COMP7 */
143 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
144 #define TIMx_AF1_BKCOMP1P TIM1_AF1_BKCMP1P /*!< BRK COMP1 input polarity */
145 #define TIMx_AF1_BKCOMP2P TIM1_AF1_BKCMP2P /*!< BRK COMP2 input polarity */
146 #define TIMx_AF1_BKCOMP3P TIM1_AF1_BKCMP3P /*!< BRK COMP3 input polarity */
147 #define TIMx_AF1_BKCOMP4P TIM1_AF1_BKCMP4P /*!< BRK COMP4 input polarity */
148 #define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
149
150 /* Generic bit definitions for TIMx_AF2 register */
151 #define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK2 BKIN2 input enable */
152 #define TIMx_AF2_BK2COMP1E TIM1_AF2_BK2CMP1E /*!< BRK2 COMP1 enable */
153 #define TIMx_AF2_BK2COMP2E TIM1_AF2_BK2CMP2E /*!< BRK2 COMP2 enable */
154 #define TIMx_AF2_BK2COMP3E TIM1_AF2_BK2CMP3E /*!< BRK2 COMP3 enable */
155 #define TIMx_AF2_BK2COMP4E TIM1_AF2_BK2CMP4E /*!< BRK2 COMP4 enable */
156 #if defined(COMP5)
157 #define TIMx_AF2_BK2COMP5E TIM1_AF2_BK2CMP5E /*!< BRK2 COMP5 enable */
158 #endif /* COMP5 */
159 #if defined(COMP6)
160 #define TIMx_AF2_BK2COMP6E TIM1_AF2_BK2CMP6E /*!< BRK2 COMP6 enable */
161 #endif /* COMP6 */
162 #if defined(COMP7)
163 #define TIMx_AF2_BK2COMP7E TIM1_AF2_BK2CMP7E /*!< BRK2 COMP7 enable */
164 #endif /* COMP7 */
165 #define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK2 BKIN2 input polarity */
166 #define TIMx_AF2_BK2COMP1P TIM1_AF2_BK2CMP1P /*!< BRK2 COMP1 input polarity */
167 #define TIMx_AF2_BK2COMP2P TIM1_AF2_BK2CMP2P /*!< BRK2 COMP2 input polarity */
168 #define TIMx_AF2_BK2COMP3P TIM1_AF2_BK2CMP3P /*!< BRK2 COMP3 input polarity */
169 #define TIMx_AF2_BK2COMP4P TIM1_AF2_BK2CMP4P /*!< BRK2 COMP4 input polarity */
170
171
172 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
173 #define DT_DELAY_1 ((uint8_t)0x7F)
174 #define DT_DELAY_2 ((uint8_t)0x3F)
175 #define DT_DELAY_3 ((uint8_t)0x1F)
176 #define DT_DELAY_4 ((uint8_t)0x1F)
177
178 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
179 #define DT_RANGE_1 ((uint8_t)0x00)
180 #define DT_RANGE_2 ((uint8_t)0x80)
181 #define DT_RANGE_3 ((uint8_t)0xC0)
182 #define DT_RANGE_4 ((uint8_t)0xE0)
183
184 /** Legacy definitions for compatibility purpose
185 @cond 0
186 */
187 /**
188 @endcond
189 */
190
191 #define OCREF_CLEAR_SELECT_Pos (28U)
192 #define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
193 /**
194 * @}
195 */
196
197 /* Private macros ------------------------------------------------------------*/
198 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
199 * @{
200 */
201 /** @brief Convert channel id into channel index.
202 * @param __CHANNEL__ This parameter can be one of the following values:
203 * @arg @ref LL_TIM_CHANNEL_CH1
204 * @arg @ref LL_TIM_CHANNEL_CH1N
205 * @arg @ref LL_TIM_CHANNEL_CH2
206 * @arg @ref LL_TIM_CHANNEL_CH2N
207 * @arg @ref LL_TIM_CHANNEL_CH3
208 * @arg @ref LL_TIM_CHANNEL_CH3N
209 * @arg @ref LL_TIM_CHANNEL_CH4
210 * @arg @ref LL_TIM_CHANNEL_CH4N
211 * @arg @ref LL_TIM_CHANNEL_CH5
212 * @arg @ref LL_TIM_CHANNEL_CH6
213 * @retval none
214 */
215 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
216 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
217 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
218 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
219 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
220 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
221 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
222 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
223 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
224 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
225
226 /** @brief Calculate the deadtime sampling period(in ps).
227 * @param __TIMCLK__ timer input clock frequency (in Hz).
228 * @param __CKD__ This parameter can be one of the following values:
229 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
230 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
231 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
232 * @retval none
233 */
234 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
235 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
236 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
237 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
238 /**
239 * @}
240 */
241
242
243 /* Exported types ------------------------------------------------------------*/
244 #if defined(USE_FULL_LL_DRIVER)
245 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
246 * @{
247 */
248
249 /**
250 * @brief TIM Time Base configuration structure definition.
251 */
252 typedef struct
253 {
254 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
255 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
256
257 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
258
259 uint32_t CounterMode; /*!< Specifies the counter mode.
260 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
261
262 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
263
264 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
265 Auto-Reload Register at the next update event.
266 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
267 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
268
269 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
270
271 uint32_t ClockDivision; /*!< Specifies the clock division.
272 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
273
274 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
275
276 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
277 reaches zero, an update event is generated and counting restarts
278 from the RCR value (N).
279 This means in PWM mode that (N+1) corresponds to:
280 - the number of PWM periods in edge-aligned mode
281 - the number of half PWM period in center-aligned mode
282 This parameter must be a number between 0x00 and 0xFF.
283
284 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
285 } LL_TIM_InitTypeDef;
286
287 /**
288 * @brief TIM Output Compare configuration structure definition.
289 */
290 typedef struct
291 {
292 uint32_t OCMode; /*!< Specifies the output mode.
293 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
294
295 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
296
297 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
298 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
299
300 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
301
302 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
303 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
304
305 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
306
307 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
308 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
309
310 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
311
312 uint32_t OCPolarity; /*!< Specifies the output polarity.
313 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
314
315 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
316
317 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
318 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
319
320 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
321
322
323 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
324 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
325
326 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
327
328 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
329 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
330
331 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
332 } LL_TIM_OC_InitTypeDef;
333
334 /**
335 * @brief TIM Input Capture configuration structure definition.
336 */
337
338 typedef struct
339 {
340
341 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
343
344 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
345
346 uint32_t ICActiveInput; /*!< Specifies the input.
347 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
348
349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
350
351 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
352 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
353
354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
355
356 uint32_t ICFilter; /*!< Specifies the input capture filter.
357 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
358
359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
360 } LL_TIM_IC_InitTypeDef;
361
362
363 /**
364 * @brief TIM Encoder interface configuration structure definition.
365 */
366 typedef struct
367 {
368 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
369 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
370
371 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
372
373 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
374 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
375
376 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
377
378 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
379 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
380
381 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
382
383 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
384 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
385
386 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
387
388 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
389 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
390
391 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
392
393 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
394 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
395
396 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
397
398 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
399 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
400
401 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
402
403 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
404 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
405
406 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
407
408 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
409 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
410
411 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
412
413 } LL_TIM_ENCODER_InitTypeDef;
414
415 /**
416 * @brief TIM Hall sensor interface configuration structure definition.
417 */
418 typedef struct
419 {
420
421 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
422 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
423
424 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
425
426 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
427 Prescaler must be set to get a maximum counter period longer than the
428 time interval between 2 consecutive changes on the Hall inputs.
429 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
430
431 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
432
433 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
434 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
435
436 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
437
438 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
439 A positive pulse (TRGO event) is generated with a programmable delay every time
440 a change occurs on the Hall inputs.
441 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
442
443 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
444 } LL_TIM_HALLSENSOR_InitTypeDef;
445
446 /**
447 * @brief BDTR (Break and Dead Time) structure definition
448 */
449 typedef struct
450 {
451 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
452 This parameter can be a value of @ref TIM_LL_EC_OSSR
453
454 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
455
456 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
457
458 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
459 This parameter can be a value of @ref TIM_LL_EC_OSSI
460
461 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
462
463 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
464
465 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
466 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
467
468 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
469 has been written, their content is frozen until the next reset.*/
470
471 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
472 switching-on of the outputs.
473 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
474
475 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
476
477 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
478
479 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
480 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
481
482 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
483
484 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
485
486 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
487 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
488
489 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
490
491 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
492
493 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
494 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
495
496 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
497
498 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
499
500 uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
501 This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
502
503 This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK()
504
505 @note Bidirectional break input is only supported by advanced timers instances.
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
508
509 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
510 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
511
512 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
513
514 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
515
516 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
517 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
518
519 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
520
521 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
522
523 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
524 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
525
526 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
527
528 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
529
530 uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
531 This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
532
533 This feature can be modified afterwards using unitary functions @ref LL_TIM_ConfigBRK2()
534
535 @note Bidirectional break input is only supported by advanced timers instances.
536
537 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
538
539 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
540 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
541
542 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
543
544 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
545 } LL_TIM_BDTR_InitTypeDef;
546
547 /**
548 * @}
549 */
550 #endif /* USE_FULL_LL_DRIVER */
551
552 /* Exported constants --------------------------------------------------------*/
553 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
554 * @{
555 */
556
557 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
558 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
559 * @{
560 */
561 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
562 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
563 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
564 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
565 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
566 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
567 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
568 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
569 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
570 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
571 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
572 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
573 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
574 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
575 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
576 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
577 #define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
578 #define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
579 #define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
580 #define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
581 /**
582 * @}
583 */
584
585 #if defined(USE_FULL_LL_DRIVER)
586 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
587 * @{
588 */
589 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
590 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
591 /**
592 * @}
593 */
594
595 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
596 * @{
597 */
598 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
599 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
600 /**
601 * @}
602 */
603
604 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
605 * @{
606 */
607 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
608 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
609 /**
610 * @}
611 */
612 #endif /* USE_FULL_LL_DRIVER */
613
614 /** @defgroup TIM_LL_EC_IT IT Defines
615 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
616 * @{
617 */
618 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
619 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
620 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
621 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
622 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
623 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
624 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
625 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
626 #define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
627 #define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
628 #define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
629 #define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
630 /**
631 * @}
632 */
633
634 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
635 * @{
636 */
637 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
638 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
639 /**
640 * @}
641 */
642
643 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
644 * @{
645 */
646 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
647 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
648 /**
649 * @}
650 */
651
652 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
653 * @{
654 */
655 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
656 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
657 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
658 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
659 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
660 /**
661 * @}
662 */
663
664 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
665 * @{
666 */
667 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
668 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
669 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
670 /**
671 * @}
672 */
673
674 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
675 * @{
676 */
677 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
678 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
679 /**
680 * @}
681 */
682
683 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
684 * @{
685 */
686 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
687 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
688 /**
689 * @}
690 */
691
692 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
693 * @{
694 */
695 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
696 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
697 /**
698 * @}
699 */
700
701 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
702 * @{
703 */
704 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
705 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
706 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
707 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
708 /**
709 * @}
710 */
711
712 /** @defgroup TIM_LL_EC_CHANNEL Channel
713 * @{
714 */
715 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
716 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
717 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
718 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
719 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
720 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
721 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
722 #define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
723 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
724 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
725 /**
726 * @}
727 */
728
729 #if defined(USE_FULL_LL_DRIVER)
730 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
731 * @{
732 */
733 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
734 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
735 /**
736 * @}
737 */
738 #endif /* USE_FULL_LL_DRIVER */
739
740 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
741 * @{
742 */
743 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
744 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
745 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
746 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
747 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
748 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
749 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
750 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
751 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
752 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
753 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
754 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
755 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
756 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
757 #define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
758 #define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
759 /**
760 * @}
761 */
762
763 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
764 * @{
765 */
766 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
767 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
768 /**
769 * @}
770 */
771
772 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
773 * @{
774 */
775 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
776 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
782 * @{
783 */
784 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
785 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
786 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
787 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
788 /**
789 * @}
790 */
791
792 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
793 * @{
794 */
795 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
796 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
797 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
798 /**
799 * @}
800 */
801
802 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
803 * @{
804 */
805 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
806 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
807 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
808 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
809 /**
810 * @}
811 */
812
813 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
814 * @{
815 */
816 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
817 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
818 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
819 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
820 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
821 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
822 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
823 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
824 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
825 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
826 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
827 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
828 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
829 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
830 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
831 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
832 /**
833 * @}
834 */
835
836 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
837 * @{
838 */
839 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
840 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
841 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
842 /**
843 * @}
844 */
845
846 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
847 * @{
848 */
849 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
850 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
851 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
852 /**
853 * @}
854 */
855
856 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
857 * @{
858 */
859 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
860 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
861 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
862 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
863 #define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
864 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
865 #define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
866 #define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
867 #define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
868 /**
869 * @}
870 */
871
872 /** @defgroup TIM_LL_EC_TRGO Trigger Output
873 * @{
874 */
875 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
876 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
877 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
878 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
879 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
880 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
881 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
882 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
883 #define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
884 /**
885 * @}
886 */
887
888 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
889 * @{
890 */
891 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
892 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
893 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
894 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
895 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
896 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
897 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
898 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
899 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
900 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
901 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
902 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
903 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
904 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
905 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
906 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
907 /**
908 * @}
909 */
910
911 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
912 * @{
913 */
914 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
915 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
916 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
917 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
918 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
919 #define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.
920 Both start and stop of the counter are controlled. */
921 /**
922 * @}
923 */
924
925 /** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
926 * @{
927 */
928 #define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
929 #define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
930 /**
931 * @}
932 */
933
934 /** @defgroup TIM_LL_EC_TS Trigger Selection
935 * @{
936 */
937 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
938 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
939 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
940 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
941 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
942 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
943 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
944 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
945 #define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
946 #define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
947 #define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
948 #define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
949 #define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
950 #define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
951 #define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
952 #define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
953 /**
954 * @}
955 */
956
957 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
958 * @{
959 */
960 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
961 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
962 /**
963 * @}
964 */
965
966 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
967 * @{
968 */
969 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
970 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
971 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
972 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
973 /**
974 * @}
975 */
976
977 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
978 * @{
979 */
980 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
981 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
982 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
983 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
984 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
985 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
986 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
987 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
988 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
989 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
990 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
991 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
992 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
993 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
994 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
995 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
996 /**
997 * @}
998 */
999
1000 /** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
1001 * @{
1002 */
1003 #define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1004 #define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1005 #define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1006 #define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1007 #define LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1008 #if defined(COMP5)
1009 #define LL_TIM_TIM1_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1010 #endif /* COMP5 */
1011 #if defined(COMP6)
1012 #define LL_TIM_TIM1_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1013 #endif /* COMP6 */
1014 #if defined(COMP7)
1015 #define LL_TIM_TIM1_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1016 #endif /* COMP7 */
1017 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
1018 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
1019 #define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
1020 #if defined(ADC4)
1021 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
1022 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
1023 #define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
1024 #endif /* ADC4 */
1025 /**
1026 * @}
1027 */
1028
1029 /** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
1030 * @{
1031 */
1032 #define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1033 #define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1034 #define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1035 #define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1036 #define LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1037 #if defined(COMP5)
1038 #define LL_TIM_TIM2_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1039 #endif /* COMP5 */
1040 #if defined(COMP6)
1041 #define LL_TIM_TIM2_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1042 #endif /* COMP6 */
1043 #if defined(COMP7)
1044 #define LL_TIM_TIM2_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1045 #endif /* COMP7 */
1046 #define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1047 #define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1048 #if defined(TIM5)
1049 #define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
1050 #endif /* TIM5 */
1051 #define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
1052 /**
1053 * @}
1054 */
1055
1056 /** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
1057 * @{
1058 */
1059 #define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1060 #define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1061 #define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1062 #define LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1063 #define LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1064 #if defined(COMP5)
1065 #define LL_TIM_TIM3_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1066 #endif /* COMP5 */
1067 #if defined(COMP6)
1068 #define LL_TIM_TIM3_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1069 #endif /* COMP6 */
1070 #if defined(COMP7)
1071 #define LL_TIM_TIM3_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1072 #endif /* COMP7 */
1073 #define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1074 #define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
1075 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
1076 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
1077 #define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
1078 /**
1079 * @}
1080 */
1081
1082 /** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
1083 * @{
1084 */
1085 #define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1086 #define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1087 #define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1088 #define LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1089 #define LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1090 #if defined(COMP5)
1091 #define LL_TIM_TIM4_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1092 #endif /* COMP5 */
1093 #if defined(COMP6)
1094 #define LL_TIM_TIM4_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1095 #endif /* COMP6 */
1096 #if defined(COMP7)
1097 #define LL_TIM_TIM4_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1098 #endif /* COMP7 */
1099 #define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
1100 #if defined(TIM5)
1101 #define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
1102 #endif /* TIM5 */
1103 /**
1104 * @}
1105 */
1106
1107 #if defined(TIM5)
1108 /** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
1109 * @{
1110 */
1111 #define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1112 #define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1113 #define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1114 #define LL_TIM_TIM5_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1115 #define LL_TIM_TIM5_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1116 #if defined(COMP5)
1117 #define LL_TIM_TIM5_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1118 #endif /* COMP5 */
1119 #if defined(COMP6)
1120 #define LL_TIM_TIM5_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1121 #endif /* COMP6 */
1122 #if defined(COMP7)
1123 #define LL_TIM_TIM5_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1124 #endif /* COMP7 */
1125 #define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
1126 #define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
1127 /**
1128 * @}
1129 */
1130 #endif /* TIM5 */
1131
1132 /** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
1133 * @{
1134 */
1135 #define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1136 #define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1137 #define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1138 #define LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1139 #define LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1140 #if defined(COMP5)
1141 #define LL_TIM_TIM8_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1142 #endif /* COMP5 */
1143 #if defined(COMP6)
1144 #define LL_TIM_TIM8_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1145 #endif /* COMP6 */
1146 #if defined(COMP7)
1147 #define LL_TIM_TIM8_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1148 #endif /* COMP7 */
1149 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
1150 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
1151 #define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
1152 #if defined(ADC3)
1153 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
1154 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
1155 #define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
1156 #endif /* ADC3 */
1157 /**
1158 * @}
1159 */
1160
1161 #if defined(TIM20)
1162 /** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
1163 * @{
1164 */
1165 #define LL_TIM_TIM20_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
1166 #define LL_TIM_TIM20_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
1167 #define LL_TIM_TIM20_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
1168 #define LL_TIM_TIM20_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
1169 #define LL_TIM_TIM20_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
1170 #if defined(COMP5)
1171 #define LL_TIM_TIM20_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
1172 #endif /* COMP5 */
1173 #if defined(COMP6)
1174 #define LL_TIM_TIM20_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
1175 #endif /* COMP6 */
1176 #if defined(COMP7)
1177 #define LL_TIM_TIM20_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
1178 #endif /* COMP7 */
1179 #if defined(ADC3)
1180 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
1181 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
1182 #define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
1183 #endif /* ADC3 */
1184 #if defined(ADC5)
1185 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
1186 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
1187 #define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
1188 #endif /* ADC5 */
1189 /**
1190 * @}
1191 */
1192 #endif /* TIM20 */
1193
1194 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
1195 * @{
1196 */
1197 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
1198 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
1199 /**
1200 * @}
1201 */
1202
1203 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
1204 * @{
1205 */
1206 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1207 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
1208 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
1209 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
1210 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
1211 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
1212 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
1213 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
1214 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
1215 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
1216 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
1217 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
1218 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
1219 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
1220 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
1221 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
1222 /**
1223 * @}
1224 */
1225
1226 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
1227 * @{
1228 */
1229 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
1230 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
1231 /**
1232 * @}
1233 */
1234
1235 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
1236 * @{
1237 */
1238 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
1239 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
1240 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
1241 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
1242 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
1243 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
1244 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
1245 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
1246 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
1247 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
1248 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
1249 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
1250 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
1251 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
1252 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
1253 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
1254 /**
1255 * @}
1256 */
1257
1258 /** @defgroup TIM_LL_EC_OSSI OSSI
1259 * @{
1260 */
1261 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1262 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup TIM_LL_EC_OSSR OSSR
1268 * @{
1269 */
1270 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1271 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1272 /**
1273 * @}
1274 */
1275
1276 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1277 * @{
1278 */
1279 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1280 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1281 /**
1282 * @}
1283 */
1284
1285 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1286 * @{
1287 */
1288 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1289 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
1290 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
1291 #define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
1292 #define LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
1293 #if defined(COMP5)
1294 #define LL_TIM_BKIN_SOURCE_BKCOMP5 TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
1295 #endif /* COMP5 */
1296 #if defined(COMP6)
1297 #define LL_TIM_BKIN_SOURCE_BKCOMP6 TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
1298 #endif /* COMP6 */
1299 #if defined(COMP7)
1300 #define LL_TIM_BKIN_SOURCE_BKCOMP7 TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
1301 #endif /* COMP7 */
1302 /**
1303 * @}
1304 */
1305
1306 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1307 * @{
1308 */
1309 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1310 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1311 /**
1312 * @}
1313 */
1314
1315 /** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
1316 * @{
1317 */
1318 #define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
1319 #define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
1320 /**
1321 * @}
1322 */
1323
1324 /** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
1325 * @{
1326 */
1327 #define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
1328 #define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
1329 /**
1330 * @}
1331 */
1332
1333 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1334 * @{
1335 */
1336 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1337 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1338 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1339 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1340 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1341 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1342 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1343 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1344 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1345 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1346 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1347 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1348 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1349 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1350 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1351 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1352 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1353 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1354 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1355 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1356 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1357 #define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
1358 #define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
1359 #define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
1360 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1361 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1362 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
1363 /**
1364 * @}
1365 */
1366
1367 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1368 * @{
1369 */
1370 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1371 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1372 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1373 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1374 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1375 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1376 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1377 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1378 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1379 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1380 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1381 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1382 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1383 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1384 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1385 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1386 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1387 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1388 #define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
1389 #define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
1390 #define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
1391 #define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
1392 #define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
1393 #define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
1394 #define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
1395 #define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
1396 /**
1397 * @}
1398 */
1399
1400 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
1401 * @{
1402 */
1403 #define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
1404 #define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
1405 #define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
1406 #define LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
1407 #define LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
1408 /**
1409 * @}
1410 */
1411
1412 /** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
1413 * @{
1414 */
1415 #define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
1416 #define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
1417 #define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
1418 #define LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
1419 #define LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
1420 #if defined(COMP5)
1421 #define LL_TIM_TIM2_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
1422 #endif /* COMP5 */
1423 /**
1424 * @}
1425 */
1426
1427 /** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
1428 * @{
1429 */
1430 #define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
1431 #define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
1432 #define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
1433 #define LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
1434 #define LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
1435 #if defined(COMP6)
1436 #define LL_TIM_TIM2_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
1437 #endif /* COMP6 */
1438 /**
1439 * @}
1440 */
1441
1442 /** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
1443 * @{
1444 */
1445 #define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
1446 #define LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
1452 * @{
1453 */
1454 #define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
1455 #define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
1456 #define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
1457 /**
1458 * @}
1459 */
1460
1461 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
1462 * @{
1463 */
1464 #define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
1465 #define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
1466 #define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
1467 #define LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
1468 #define LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
1469 #if defined(COMP5)
1470 #define LL_TIM_TIM3_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
1471 #endif /* COMP5 */
1472 #if defined(COMP6)
1473 #define LL_TIM_TIM3_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
1474 #endif /* COMP6 */
1475 #if defined(COMP7)
1476 #define LL_TIM_TIM3_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
1477 #endif /* COMP7 */
1478 /**
1479 * @}
1480 */
1481
1482 /** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
1483 * @{
1484 */
1485 #define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
1486 #define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
1487 #define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
1488 #define LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
1489 #define LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
1490 #if defined(COMP5)
1491 #define LL_TIM_TIM3_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
1492 #endif /* COMP5 */
1493 #if defined(COMP6)
1494 #define LL_TIM_TIM3_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
1495 #endif /* COMP6 */
1496 #if defined(COMP7)
1497 #define LL_TIM_TIM3_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
1498 #endif /* COMP7 */
1499 /**
1500 * @}
1501 */
1502
1503 /** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
1504 * @{
1505 */
1506 #define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
1507 #define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
1513 * @{
1514 */
1515 #define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
1516 #define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
1517 #define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
1518 #define LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
1519 #define LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
1520 #if defined(COMP5)
1521 #define LL_TIM_TIM4_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
1522 #endif /* COMP5 */
1523 #if defined(COMP6)
1524 #define LL_TIM_TIM4_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
1525 #endif /* COMP6 */
1526 #if defined(COMP7)
1527 #define LL_TIM_TIM4_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
1528 #endif /* COMP7 */
1529 /**
1530 * @}
1531 */
1532
1533 /** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
1534 * @{
1535 */
1536 #define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
1537 #define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
1538 #define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
1539 #define LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
1540 #define LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
1541 #if defined(COMP5)
1542 #define LL_TIM_TIM4_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
1543 #endif /* COMP5 */
1544 #if defined(COMP6)
1545 #define LL_TIM_TIM4_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
1546 #endif /* COMP6 */
1547 #if defined(COMP7)
1548 #define LL_TIM_TIM4_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
1549 #endif /* COMP7 */
1550 /**
1551 * @}
1552 */
1553
1554 /** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
1555 * @{
1556 */
1557 #define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
1558 #if defined(COMP5)
1559 #define LL_TIM_TIM4_TI3_RMP_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
1560 #endif /* COMP5 */
1561 /**
1562 * @}
1563 */
1564
1565 /** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
1566 * @{
1567 */
1568 #define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
1569 #if defined(COMP6)
1570 #define LL_TIM_TIM4_TI4_RMP_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
1571 #endif /* COMP6 */
1572 /**
1573 * @}
1574 */
1575
1576 #if defined(TIM5)
1577 /** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
1578 * @{
1579 */
1580 #define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
1581 #define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
1582 #define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
1583 #define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
1584 #define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
1585 #define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
1586 #define LL_TIM_TIM5_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
1587 #define LL_TIM_TIM5_TI1_RMP_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
1588 #if defined(COMP5)
1589 #define LL_TIM_TIM5_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
1590 #endif /* COMP5 */
1591 #if defined(COMP6)
1592 #define LL_TIM_TIM5_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
1593 #endif /* COMP6 */
1594 #if defined(COMP7)
1595 #define LL_TIM_TIM5_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
1596 #endif /* COMP7 */
1597 /**
1598 * @}
1599 */
1600
1601 /** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
1602 * @{
1603 */
1604 #define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
1605 #define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
1606 #define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
1607 #define LL_TIM_TIM5_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
1608 #define LL_TIM_TIM5_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
1609 #if defined(COMP5)
1610 #define LL_TIM_TIM5_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
1611 #endif /* COMP5 */
1612 #if defined(COMP6)
1613 #define LL_TIM_TIM5_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
1614 #endif /* COMP6 */
1615 #if defined(COMP7)
1616 #define LL_TIM_TIM5_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
1617 #endif /* COMP7 */
1618 /**
1619 * @}
1620 */
1621 #endif /* TIM5 */
1622
1623 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
1624 * @{
1625 */
1626 #define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
1627 #define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
1628 #define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
1629 #define LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
1630 #define LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
1631 /**
1632 * @}
1633 */
1634
1635 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
1636 * @{
1637 */
1638 #define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
1639 #define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
1640 #define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
1641 #define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
1642 #if defined(COMP5)
1643 #define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
1644 #endif /* COMP5 */
1645 #if defined(COMP7)
1646 #define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
1647 #endif /* COMP7 */
1648 /**
1649 * @}
1650 */
1651
1652 /** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
1653 * @{
1654 */
1655 #define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
1656 #define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
1657 #define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
1658 #if defined(COMP6)
1659 #define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
1660 #endif /* COMP6 */
1661 #if defined(COMP7)
1662 #define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
1663 #endif /* COMP7 */
1664 /**
1665 * @}
1666 */
1667
1668 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
1669 * @{
1670 */
1671 #define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
1672 #if defined(COMP6)
1673 #define LL_TIM_TIM16_TI1_RMP_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
1674 #endif /* COMP6 */
1675 #define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
1676 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
1677 #define LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
1678 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
1679 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
1680 /**
1681 * @}
1682 */
1683
1684 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
1685 * @{
1686 */
1687 #define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
1688 #if defined(COMP5)
1689 #define LL_TIM_TIM17_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
1690 #endif /* COMP5 */
1691 #define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
1692 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
1693 #define LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
1694 #define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
1695 #define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
1696 /**
1697 * @}
1698 */
1699
1700 #if defined(TIM20)
1701 /** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
1702 * @{
1703 */
1704 #define LL_TIM_TIM20_TI1_RMP_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
1705 #define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
1706 #define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
1707 #define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
1708 #define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
1709 /**
1710 * @}
1711 */
1712 #endif /* TIM20 */
1713
1714 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
1715 * @{
1716 */
1717 #define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
1718 #define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
1719 #define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
1720 #define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
1721 #define LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
1722 #if defined(COMP5)
1723 #define LL_TIM_OCREF_CLR_INT_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
1724 #endif /* COMP5 */
1725 #if defined(COMP6)
1726 #define LL_TIM_OCREF_CLR_INT_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
1727 #endif /* COMP6 */
1728 #if defined(COMP7)
1729 #define LL_TIM_OCREF_CLR_INT_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
1730 #endif /* COMP7 */
1731 /**
1732 * @}
1733 */
1734
1735 /** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
1736 * @{
1737 */
1738 #define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
1739 #define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
1740 #define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
1741 /**
1742 * @}
1743 */
1744
1745 /** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
1746 * @{
1747 */
1748 #define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
1749 #define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
1750 #define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
1751 #define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
1752 #define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
1753 #define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
1754 /**
1755 * @}
1756 */
1757
1758 /** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
1759 * @{
1760 */
1761 #define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
1762 #define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
1763 /**
1764 * @}
1765 */
1766 /** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
1767 * @{
1768 */
1769 #define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
1770 #define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
1771 #define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
1772 #define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
1773 #define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
1774 #define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
1775 #define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
1776 #define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
1777 /**
1778 * @}
1779 */
1780
1781 /** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
1782 * @{
1783 */
1784 #define LL_TIM_HSE_32_NOT_REQUEST 0x00000000U /*!< Clock HSE/32 not requested */
1785 #define LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
1786 /**
1787 * @}
1788 */
1789
1790 /** Legacy definitions for compatibility purpose
1791 @cond 0
1792 */
1793 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
1794 /**
1795 @endcond
1796 */
1797 /**
1798 * @}
1799 */
1800
1801 /* Exported macro ------------------------------------------------------------*/
1802 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1803 * @{
1804 */
1805
1806 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1807 * @{
1808 */
1809 /**
1810 * @brief Write a value in TIM register.
1811 * @param __INSTANCE__ TIM Instance
1812 * @param __REG__ Register to be written
1813 * @param __VALUE__ Value to be written in the register
1814 * @retval None
1815 */
1816 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
1817
1818 /**
1819 * @brief Read a value in TIM register.
1820 * @param __INSTANCE__ TIM Instance
1821 * @param __REG__ Register to be read
1822 * @retval Register value
1823 */
1824 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
1825 /**
1826 * @}
1827 */
1828
1829 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1830 * @{
1831 */
1832
1833 /**
1834 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1835 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1836 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1837 * to TIMx_CNT register bit 31)
1838 * @param __CNT__ Counter value
1839 * @retval UIF status bit
1840 */
1841 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1842 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1843
1844 /**
1845 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1846 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1847 * @param __TIMCLK__ timer input clock frequency (in Hz)
1848 * @param __CKD__ This parameter can be one of the following values:
1849 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1850 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1851 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1852 * @param __DT__ deadtime duration (in ns)
1853 * @retval DTG[0:7]
1854 */
1855 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1856 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1857 (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
1858 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
1859 (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
1860 0U)
1861
1862 /**
1863 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1864 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1865 * @param __TIMCLK__ timer input clock frequency (in Hz)
1866 * @param __CNTCLK__ counter clock frequency (in Hz)
1867 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1868 */
1869 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1870 (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
1871
1872 /**
1873 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1874 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1875 * @param __TIMCLK__ timer input clock frequency (in Hz)
1876 * @param __PSC__ prescaler
1877 * @param __FREQ__ output signal frequency (in Hz)
1878 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1879 */
1880 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1881 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
1882
1883 /**
1884 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required output signal frequency.
1885 * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1886 * @param __TIMCLK__ timer input clock frequency (in Hz)
1887 * @param __PSC__ prescaler
1888 * @param __FREQ__ output signal frequency (in Hz)
1889 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1890 */
1891 #define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
1892 ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
1893
1894 /**
1895 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1896 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1897 * @param __TIMCLK__ timer input clock frequency (in Hz)
1898 * @param __PSC__ prescaler
1899 * @param __DELAY__ timer output compare active/inactive delay (in us)
1900 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1901 */
1902 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1903 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1904 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1905
1906 /**
1907 * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer output compare active/inactive delay.
1908 * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
1909 * @param __TIMCLK__ timer input clock frequency (in Hz)
1910 * @param __PSC__ prescaler
1911 * @param __DELAY__ timer output compare active/inactive delay (in us)
1912 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1913 */
1914 #define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
1915 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
1916 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1917
1918 /**
1919 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1920 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1921 * @param __TIMCLK__ timer input clock frequency (in Hz)
1922 * @param __PSC__ prescaler
1923 * @param __DELAY__ timer output compare active/inactive delay (in us)
1924 * @param __PULSE__ pulse duration (in us)
1925 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1926 */
1927 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1928 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1929 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1930
1931 /**
1932 * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required pulse duration (when the timer operates in one pulse mode).
1933 * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1934 * @param __TIMCLK__ timer input clock frequency (in Hz)
1935 * @param __PSC__ prescaler
1936 * @param __DELAY__ timer output compare active/inactive delay (in us)
1937 * @param __PULSE__ pulse duration (in us)
1938 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1939 */
1940 #define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1941 ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
1942 + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
1943
1944 /**
1945 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1946 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1947 * @param __ICPSC__ This parameter can be one of the following values:
1948 * @arg @ref LL_TIM_ICPSC_DIV1
1949 * @arg @ref LL_TIM_ICPSC_DIV2
1950 * @arg @ref LL_TIM_ICPSC_DIV4
1951 * @arg @ref LL_TIM_ICPSC_DIV8
1952 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1953 */
1954 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1955 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1956
1957
1958 /**
1959 * @}
1960 */
1961
1962
1963 /**
1964 * @}
1965 */
1966
1967 /* Exported functions --------------------------------------------------------*/
1968 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1969 * @{
1970 */
1971
1972 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1973 * @{
1974 */
1975 /**
1976 * @brief Enable timer counter.
1977 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1978 * @param TIMx Timer instance
1979 * @retval None
1980 */
1981 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1982 {
1983 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1984 }
1985
1986 /**
1987 * @brief Disable timer counter.
1988 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1989 * @param TIMx Timer instance
1990 * @retval None
1991 */
1992 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1993 {
1994 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1995 }
1996
1997 /**
1998 * @brief Indicates whether the timer counter is enabled.
1999 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
2000 * @param TIMx Timer instance
2001 * @retval State of bit (1 or 0).
2002 */
2003 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
2004 {
2005 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
2006 }
2007
2008 /**
2009 * @brief Enable update event generation.
2010 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
2011 * @param TIMx Timer instance
2012 * @retval None
2013 */
2014 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
2015 {
2016 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
2017 }
2018
2019 /**
2020 * @brief Disable update event generation.
2021 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
2022 * @param TIMx Timer instance
2023 * @retval None
2024 */
2025 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
2026 {
2027 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
2028 }
2029
2030 /**
2031 * @brief Indicates whether update event generation is enabled.
2032 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
2033 * @param TIMx Timer instance
2034 * @retval Inverted state of bit (0 or 1).
2035 */
2036 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
2037 {
2038 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
2039 }
2040
2041 /**
2042 * @brief Set update event source
2043 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
2044 * generate an update interrupt or DMA request if enabled:
2045 * - Counter overflow/underflow
2046 * - Setting the UG bit
2047 * - Update generation through the slave mode controller
2048 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
2049 * overflow/underflow generates an update interrupt or DMA request if enabled.
2050 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
2051 * @param TIMx Timer instance
2052 * @param UpdateSource This parameter can be one of the following values:
2053 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2054 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2055 * @retval None
2056 */
2057 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
2058 {
2059 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
2060 }
2061
2062 /**
2063 * @brief Get actual event update source
2064 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
2065 * @param TIMx Timer instance
2066 * @retval Returned value can be one of the following values:
2067 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
2068 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
2069 */
2070 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
2071 {
2072 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
2073 }
2074
2075 /**
2076 * @brief Set one pulse mode (one shot v.s. repetitive).
2077 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
2078 * @param TIMx Timer instance
2079 * @param OnePulseMode This parameter can be one of the following values:
2080 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2081 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2082 * @retval None
2083 */
2084 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
2085 {
2086 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
2087 }
2088
2089 /**
2090 * @brief Get actual one pulse mode.
2091 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
2092 * @param TIMx Timer instance
2093 * @retval Returned value can be one of the following values:
2094 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
2095 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
2096 */
2097 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
2098 {
2099 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
2100 }
2101
2102 /**
2103 * @brief Set the timer counter counting mode.
2104 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2105 * check whether or not the counter mode selection feature is supported
2106 * by a timer instance.
2107 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2108 * requires a timer reset to avoid unexpected direction
2109 * due to DIR bit readonly in center aligned mode.
2110 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
2111 * CR1 CMS LL_TIM_SetCounterMode
2112 * @param TIMx Timer instance
2113 * @param CounterMode This parameter can be one of the following values:
2114 * @arg @ref LL_TIM_COUNTERMODE_UP
2115 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2116 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2117 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2118 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2119 * @retval None
2120 */
2121 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
2122 {
2123 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
2124 }
2125
2126 /**
2127 * @brief Get actual counter mode.
2128 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
2129 * check whether or not the counter mode selection feature is supported
2130 * by a timer instance.
2131 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
2132 * CR1 CMS LL_TIM_GetCounterMode
2133 * @param TIMx Timer instance
2134 * @retval Returned value can be one of the following values:
2135 * @arg @ref LL_TIM_COUNTERMODE_UP
2136 * @arg @ref LL_TIM_COUNTERMODE_DOWN
2137 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
2138 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
2139 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
2140 */
2141 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
2142 {
2143 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
2144 }
2145
2146 /**
2147 * @brief Enable auto-reload (ARR) preload.
2148 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
2149 * @param TIMx Timer instance
2150 * @retval None
2151 */
2152 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
2153 {
2154 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
2155 }
2156
2157 /**
2158 * @brief Disable auto-reload (ARR) preload.
2159 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
2160 * @param TIMx Timer instance
2161 * @retval None
2162 */
2163 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
2164 {
2165 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
2166 }
2167
2168 /**
2169 * @brief Indicates whether auto-reload (ARR) preload is enabled.
2170 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
2171 * @param TIMx Timer instance
2172 * @retval State of bit (1 or 0).
2173 */
2174 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
2175 {
2176 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
2177 }
2178
2179 /**
2180 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
2181 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2182 * whether or not the clock division feature is supported by the timer
2183 * instance.
2184 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
2185 * @param TIMx Timer instance
2186 * @param ClockDivision This parameter can be one of the following values:
2187 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2188 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2189 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2190 * @retval None
2191 */
2192 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
2193 {
2194 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
2195 }
2196
2197 /**
2198 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
2199 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
2200 * whether or not the clock division feature is supported by the timer
2201 * instance.
2202 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
2203 * @param TIMx Timer instance
2204 * @retval Returned value can be one of the following values:
2205 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
2206 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
2207 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
2208 */
2209 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
2210 {
2211 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
2212 }
2213
2214 /**
2215 * @brief Set the counter value.
2216 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2217 * whether or not a timer instance supports a 32 bits counter.
2218 * @note If dithering is activated, pay attention to the Counter value interpretation
2219 * @rmtoll CNT CNT LL_TIM_SetCounter
2220 * @param TIMx Timer instance
2221 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2222 * @retval None
2223 */
2224 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
2225 {
2226 WRITE_REG(TIMx->CNT, Counter);
2227 }
2228
2229 /**
2230 * @brief Get the counter value.
2231 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2232 * whether or not a timer instance supports a 32 bits counter.
2233 * @note If dithering is activated, pay attention to the Counter value interpretation
2234 * @rmtoll CNT CNT LL_TIM_GetCounter
2235 * @param TIMx Timer instance
2236 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
2237 */
2238 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
2239 {
2240 return (uint32_t)(READ_REG(TIMx->CNT));
2241 }
2242
2243 /**
2244 * @brief Get the current direction of the counter
2245 * @rmtoll CR1 DIR LL_TIM_GetDirection
2246 * @param TIMx Timer instance
2247 * @retval Returned value can be one of the following values:
2248 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
2249 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
2250 */
2251 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
2252 {
2253 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
2254 }
2255
2256 /**
2257 * @brief Set the prescaler value.
2258 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
2259 * @note The prescaler can be changed on the fly as this control register is buffered. The new
2260 * prescaler ratio is taken into account at the next update event.
2261 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
2262 * @rmtoll PSC PSC LL_TIM_SetPrescaler
2263 * @param TIMx Timer instance
2264 * @param Prescaler between Min_Data=0 and Max_Data=65535
2265 * @retval None
2266 */
2267 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
2268 {
2269 WRITE_REG(TIMx->PSC, Prescaler);
2270 }
2271
2272 /**
2273 * @brief Get the prescaler value.
2274 * @rmtoll PSC PSC LL_TIM_GetPrescaler
2275 * @param TIMx Timer instance
2276 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
2277 */
2278 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
2279 {
2280 return (uint32_t)(READ_REG(TIMx->PSC));
2281 }
2282
2283 /**
2284 * @brief Set the auto-reload value.
2285 * @note The counter is blocked while the auto-reload value is null.
2286 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2287 * whether or not a timer instance supports a 32 bits counter.
2288 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
2289 * In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload parameter.
2290 * @rmtoll ARR ARR LL_TIM_SetAutoReload
2291 * @param TIMx Timer instance
2292 * @param AutoReload between Min_Data=0 and Max_Data=65535
2293 * @retval None
2294 */
2295 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
2296 {
2297 WRITE_REG(TIMx->ARR, AutoReload);
2298 }
2299
2300 /**
2301 * @brief Get the auto-reload value.
2302 * @rmtoll ARR ARR LL_TIM_GetAutoReload
2303 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2304 * whether or not a timer instance supports a 32 bits counter.
2305 * @note If dithering is activated, pay attention to the returned value interpretation
2306 * @param TIMx Timer instance
2307 * @retval Auto-reload value
2308 */
2309 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
2310 {
2311 return (uint32_t)(READ_REG(TIMx->ARR));
2312 }
2313
2314 /**
2315 * @brief Set the repetition counter value.
2316 * @note For advanced timer instances RepetitionCounter can be up to 65535.
2317 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2318 * whether or not a timer instance supports a repetition counter.
2319 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
2320 * @param TIMx Timer instance
2321 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
2322 * @retval None
2323 */
2324 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
2325 {
2326 WRITE_REG(TIMx->RCR, RepetitionCounter);
2327 }
2328
2329 /**
2330 * @brief Get the repetition counter value.
2331 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
2332 * whether or not a timer instance supports a repetition counter.
2333 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
2334 * @param TIMx Timer instance
2335 * @retval Repetition counter value
2336 */
2337 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
2338 {
2339 return (uint32_t)(READ_REG(TIMx->RCR));
2340 }
2341
2342 /**
2343 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
2344 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
2345 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
2346 * @param TIMx Timer instance
2347 * @retval None
2348 */
2349 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
2350 {
2351 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2352 }
2353
2354 /**
2355 * @brief Disable update interrupt flag (UIF) remapping.
2356 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
2357 * @param TIMx Timer instance
2358 * @retval None
2359 */
2360 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
2361 {
2362 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
2363 }
2364
2365 /**
2366 * @brief Enable dithering.
2367 * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2368 * a timer instance provides dithering.
2369 * @rmtoll CR1 DITHEN LL_TIM_EnableDithering
2370 * @param TIMx Timer instance
2371 * @retval None
2372 */
2373 __STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
2374 {
2375 SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2376 }
2377
2378 /**
2379 * @brief Disable dithering.
2380 * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2381 * a timer instance provides dithering.
2382 * @rmtoll CR1 DITHEN LL_TIM_DisableDithering
2383 * @param TIMx Timer instance
2384 * @retval None
2385 */
2386 __STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
2387 {
2388 CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
2389 }
2390
2391 /**
2392 * @brief Indicates whether dithering is activated.
2393 * @note Macro @ref IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
2394 * a timer instance provides dithering.
2395 * @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
2396 * @param TIMx Timer instance
2397 * @retval State of bit (1 or 0).
2398 */
2399 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
2400 {
2401 return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
2402 }
2403
2404 /**
2405 * @}
2406 */
2407
2408 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
2409 * @{
2410 */
2411 /**
2412 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2413 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
2414 * they are updated only when a commutation event (COM) occurs.
2415 * @note Only on channels that have a complementary output.
2416 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2417 * whether or not a timer instance is able to generate a commutation event.
2418 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
2419 * @param TIMx Timer instance
2420 * @retval None
2421 */
2422 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
2423 {
2424 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
2425 }
2426
2427 /**
2428 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
2429 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2430 * whether or not a timer instance is able to generate a commutation event.
2431 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
2432 * @param TIMx Timer instance
2433 * @retval None
2434 */
2435 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
2436 {
2437 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
2438 }
2439
2440 /**
2441 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
2442 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
2443 * whether or not a timer instance is able to generate a commutation event.
2444 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
2445 * @param TIMx Timer instance
2446 * @param CCUpdateSource This parameter can be one of the following values:
2447 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
2448 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
2449 * @retval None
2450 */
2451 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
2452 {
2453 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
2454 }
2455
2456 /**
2457 * @brief Set the trigger of the capture/compare DMA request.
2458 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
2459 * @param TIMx Timer instance
2460 * @param DMAReqTrigger This parameter can be one of the following values:
2461 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2462 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2463 * @retval None
2464 */
2465 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
2466 {
2467 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
2468 }
2469
2470 /**
2471 * @brief Get actual trigger of the capture/compare DMA request.
2472 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
2473 * @param TIMx Timer instance
2474 * @retval Returned value can be one of the following values:
2475 * @arg @ref LL_TIM_CCDMAREQUEST_CC
2476 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
2477 */
2478 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
2479 {
2480 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
2481 }
2482
2483 /**
2484 * @brief Set the lock level to freeze the
2485 * configuration of several capture/compare parameters.
2486 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2487 * the lock mechanism is supported by a timer instance.
2488 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
2489 * @param TIMx Timer instance
2490 * @param LockLevel This parameter can be one of the following values:
2491 * @arg @ref LL_TIM_LOCKLEVEL_OFF
2492 * @arg @ref LL_TIM_LOCKLEVEL_1
2493 * @arg @ref LL_TIM_LOCKLEVEL_2
2494 * @arg @ref LL_TIM_LOCKLEVEL_3
2495 * @retval None
2496 */
2497 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
2498 {
2499 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
2500 }
2501
2502 /**
2503 * @brief Enable capture/compare channels.
2504 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
2505 * CCER CC1NE LL_TIM_CC_EnableChannel\n
2506 * CCER CC2E LL_TIM_CC_EnableChannel\n
2507 * CCER CC2NE LL_TIM_CC_EnableChannel\n
2508 * CCER CC3E LL_TIM_CC_EnableChannel\n
2509 * CCER CC3NE LL_TIM_CC_EnableChannel\n
2510 * CCER CC4E LL_TIM_CC_EnableChannel\n
2511 * CCER CC4NE LL_TIM_CC_EnableChannel\n
2512 * CCER CC5E LL_TIM_CC_EnableChannel\n
2513 * CCER CC6E LL_TIM_CC_EnableChannel
2514 * @param TIMx Timer instance
2515 * @param Channels This parameter can be a combination of the following values:
2516 * @arg @ref LL_TIM_CHANNEL_CH1
2517 * @arg @ref LL_TIM_CHANNEL_CH1N
2518 * @arg @ref LL_TIM_CHANNEL_CH2
2519 * @arg @ref LL_TIM_CHANNEL_CH2N
2520 * @arg @ref LL_TIM_CHANNEL_CH3
2521 * @arg @ref LL_TIM_CHANNEL_CH3N
2522 * @arg @ref LL_TIM_CHANNEL_CH4
2523 * @arg @ref LL_TIM_CHANNEL_CH4N
2524 * @arg @ref LL_TIM_CHANNEL_CH5
2525 * @arg @ref LL_TIM_CHANNEL_CH6
2526 * @retval None
2527 */
2528 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2529 {
2530 SET_BIT(TIMx->CCER, Channels);
2531 }
2532
2533 /**
2534 * @brief Disable capture/compare channels.
2535 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
2536 * CCER CC1NE LL_TIM_CC_DisableChannel\n
2537 * CCER CC2E LL_TIM_CC_DisableChannel\n
2538 * CCER CC2NE LL_TIM_CC_DisableChannel\n
2539 * CCER CC3E LL_TIM_CC_DisableChannel\n
2540 * CCER CC3NE LL_TIM_CC_DisableChannel\n
2541 * CCER CC4E LL_TIM_CC_DisableChannel\n
2542 * CCER CC4NE LL_TIM_CC_DisableChannel\n
2543 * CCER CC5E LL_TIM_CC_DisableChannel\n
2544 * CCER CC6E LL_TIM_CC_DisableChannel
2545 * @param TIMx Timer instance
2546 * @param Channels This parameter can be a combination of the following values:
2547 * @arg @ref LL_TIM_CHANNEL_CH1
2548 * @arg @ref LL_TIM_CHANNEL_CH1N
2549 * @arg @ref LL_TIM_CHANNEL_CH2
2550 * @arg @ref LL_TIM_CHANNEL_CH2N
2551 * @arg @ref LL_TIM_CHANNEL_CH3
2552 * @arg @ref LL_TIM_CHANNEL_CH3N
2553 * @arg @ref LL_TIM_CHANNEL_CH4
2554 * @arg @ref LL_TIM_CHANNEL_CH4N
2555 * @arg @ref LL_TIM_CHANNEL_CH5
2556 * @arg @ref LL_TIM_CHANNEL_CH6
2557 * @retval None
2558 */
2559 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2560 {
2561 CLEAR_BIT(TIMx->CCER, Channels);
2562 }
2563
2564 /**
2565 * @brief Indicate whether channel(s) is(are) enabled.
2566 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
2567 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
2568 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
2569 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
2570 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
2571 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
2572 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
2573 * CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
2574 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
2575 * CCER CC6E LL_TIM_CC_IsEnabledChannel
2576 * @param TIMx Timer instance
2577 * @param Channels This parameter can be a combination of the following values:
2578 * @arg @ref LL_TIM_CHANNEL_CH1
2579 * @arg @ref LL_TIM_CHANNEL_CH1N
2580 * @arg @ref LL_TIM_CHANNEL_CH2
2581 * @arg @ref LL_TIM_CHANNEL_CH2N
2582 * @arg @ref LL_TIM_CHANNEL_CH3
2583 * @arg @ref LL_TIM_CHANNEL_CH3N
2584 * @arg @ref LL_TIM_CHANNEL_CH4
2585 * @arg @ref LL_TIM_CHANNEL_CH4N
2586 * @arg @ref LL_TIM_CHANNEL_CH5
2587 * @arg @ref LL_TIM_CHANNEL_CH6
2588 * @retval State of bit (1 or 0).
2589 */
2590 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
2591 {
2592 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
2593 }
2594
2595 /**
2596 * @}
2597 */
2598
2599 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
2600 * @{
2601 */
2602 /**
2603 * @brief Configure an output channel.
2604 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
2605 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
2606 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
2607 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
2608 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
2609 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
2610 * CCER CC1P LL_TIM_OC_ConfigOutput\n
2611 * CCER CC2P LL_TIM_OC_ConfigOutput\n
2612 * CCER CC3P LL_TIM_OC_ConfigOutput\n
2613 * CCER CC4P LL_TIM_OC_ConfigOutput\n
2614 * CCER CC5P LL_TIM_OC_ConfigOutput\n
2615 * CCER CC6P LL_TIM_OC_ConfigOutput\n
2616 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
2617 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
2618 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
2619 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
2620 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
2621 * CR2 OIS6 LL_TIM_OC_ConfigOutput
2622 * @param TIMx Timer instance
2623 * @param Channel This parameter can be one of the following values:
2624 * @arg @ref LL_TIM_CHANNEL_CH1
2625 * @arg @ref LL_TIM_CHANNEL_CH2
2626 * @arg @ref LL_TIM_CHANNEL_CH3
2627 * @arg @ref LL_TIM_CHANNEL_CH4
2628 * @arg @ref LL_TIM_CHANNEL_CH5
2629 * @arg @ref LL_TIM_CHANNEL_CH6
2630 * @param Configuration This parameter must be a combination of all the following values:
2631 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
2632 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
2633 * @retval None
2634 */
2635 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2636 {
2637 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2638 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2639 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
2640 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
2641 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
2642 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
2643 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
2644 }
2645
2646 /**
2647 * @brief Define the behavior of the output reference signal OCxREF from which
2648 * OCx and OCxN (when relevant) are derived.
2649 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
2650 * CCMR1 OC2M LL_TIM_OC_SetMode\n
2651 * CCMR2 OC3M LL_TIM_OC_SetMode\n
2652 * CCMR2 OC4M LL_TIM_OC_SetMode\n
2653 * CCMR3 OC5M LL_TIM_OC_SetMode\n
2654 * CCMR3 OC6M LL_TIM_OC_SetMode
2655 * @param TIMx Timer instance
2656 * @param Channel This parameter can be one of the following values:
2657 * @arg @ref LL_TIM_CHANNEL_CH1
2658 * @arg @ref LL_TIM_CHANNEL_CH2
2659 * @arg @ref LL_TIM_CHANNEL_CH3
2660 * @arg @ref LL_TIM_CHANNEL_CH4
2661 * @arg @ref LL_TIM_CHANNEL_CH5
2662 * @arg @ref LL_TIM_CHANNEL_CH6
2663 * @param Mode This parameter can be one of the following values:
2664 * @arg @ref LL_TIM_OCMODE_FROZEN
2665 * @arg @ref LL_TIM_OCMODE_ACTIVE
2666 * @arg @ref LL_TIM_OCMODE_INACTIVE
2667 * @arg @ref LL_TIM_OCMODE_TOGGLE
2668 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2669 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2670 * @arg @ref LL_TIM_OCMODE_PWM1
2671 * @arg @ref LL_TIM_OCMODE_PWM2
2672 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2673 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2674 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2675 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2676 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2677 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2678 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2679 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2680 * @retval None
2681 */
2682 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
2683 {
2684 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2685 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2686 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
2687 }
2688
2689 /**
2690 * @brief Get the output compare mode of an output channel.
2691 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
2692 * CCMR1 OC2M LL_TIM_OC_GetMode\n
2693 * CCMR2 OC3M LL_TIM_OC_GetMode\n
2694 * CCMR2 OC4M LL_TIM_OC_GetMode\n
2695 * CCMR3 OC5M LL_TIM_OC_GetMode\n
2696 * CCMR3 OC6M LL_TIM_OC_GetMode
2697 * @param TIMx Timer instance
2698 * @param Channel This parameter can be one of the following values:
2699 * @arg @ref LL_TIM_CHANNEL_CH1
2700 * @arg @ref LL_TIM_CHANNEL_CH2
2701 * @arg @ref LL_TIM_CHANNEL_CH3
2702 * @arg @ref LL_TIM_CHANNEL_CH4
2703 * @arg @ref LL_TIM_CHANNEL_CH5
2704 * @arg @ref LL_TIM_CHANNEL_CH6
2705 * @retval Returned value can be one of the following values:
2706 * @arg @ref LL_TIM_OCMODE_FROZEN
2707 * @arg @ref LL_TIM_OCMODE_ACTIVE
2708 * @arg @ref LL_TIM_OCMODE_INACTIVE
2709 * @arg @ref LL_TIM_OCMODE_TOGGLE
2710 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
2711 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
2712 * @arg @ref LL_TIM_OCMODE_PWM1
2713 * @arg @ref LL_TIM_OCMODE_PWM2
2714 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
2715 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
2716 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
2717 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
2718 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
2719 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
2720 * @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
2721 * @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
2722 */
2723 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
2724 {
2725 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2726 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2727 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
2728 }
2729
2730 /**
2731 * @brief Set the polarity of an output channel.
2732 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
2733 * CCER CC1NP LL_TIM_OC_SetPolarity\n
2734 * CCER CC2P LL_TIM_OC_SetPolarity\n
2735 * CCER CC2NP LL_TIM_OC_SetPolarity\n
2736 * CCER CC3P LL_TIM_OC_SetPolarity\n
2737 * CCER CC3NP LL_TIM_OC_SetPolarity\n
2738 * CCER CC4P LL_TIM_OC_SetPolarity\n
2739 * CCER CC4NP LL_TIM_OC_SetPolarity\n
2740 * CCER CC5P LL_TIM_OC_SetPolarity\n
2741 * CCER CC6P LL_TIM_OC_SetPolarity
2742 * @param TIMx Timer instance
2743 * @param Channel This parameter can be one of the following values:
2744 * @arg @ref LL_TIM_CHANNEL_CH1
2745 * @arg @ref LL_TIM_CHANNEL_CH1N
2746 * @arg @ref LL_TIM_CHANNEL_CH2
2747 * @arg @ref LL_TIM_CHANNEL_CH2N
2748 * @arg @ref LL_TIM_CHANNEL_CH3
2749 * @arg @ref LL_TIM_CHANNEL_CH3N
2750 * @arg @ref LL_TIM_CHANNEL_CH4
2751 * @arg @ref LL_TIM_CHANNEL_CH4N
2752 * @arg @ref LL_TIM_CHANNEL_CH5
2753 * @arg @ref LL_TIM_CHANNEL_CH6
2754 * @param Polarity This parameter can be one of the following values:
2755 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2756 * @arg @ref LL_TIM_OCPOLARITY_LOW
2757 * @retval None
2758 */
2759 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2760 {
2761 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2762 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2763 }
2764
2765 /**
2766 * @brief Get the polarity of an output channel.
2767 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2768 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2769 * CCER CC2P LL_TIM_OC_GetPolarity\n
2770 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2771 * CCER CC3P LL_TIM_OC_GetPolarity\n
2772 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2773 * CCER CC4P LL_TIM_OC_GetPolarity\n
2774 * CCER CC4NP LL_TIM_OC_GetPolarity\n
2775 * CCER CC5P LL_TIM_OC_GetPolarity\n
2776 * CCER CC6P LL_TIM_OC_GetPolarity
2777 * @param TIMx Timer instance
2778 * @param Channel This parameter can be one of the following values:
2779 * @arg @ref LL_TIM_CHANNEL_CH1
2780 * @arg @ref LL_TIM_CHANNEL_CH1N
2781 * @arg @ref LL_TIM_CHANNEL_CH2
2782 * @arg @ref LL_TIM_CHANNEL_CH2N
2783 * @arg @ref LL_TIM_CHANNEL_CH3
2784 * @arg @ref LL_TIM_CHANNEL_CH3N
2785 * @arg @ref LL_TIM_CHANNEL_CH4
2786 * @arg @ref LL_TIM_CHANNEL_CH4N
2787 * @arg @ref LL_TIM_CHANNEL_CH5
2788 * @arg @ref LL_TIM_CHANNEL_CH6
2789 * @retval Returned value can be one of the following values:
2790 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2791 * @arg @ref LL_TIM_OCPOLARITY_LOW
2792 */
2793 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2794 {
2795 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2796 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2797 }
2798
2799 /**
2800 * @brief Set the IDLE state of an output channel
2801 * @note This function is significant only for the timer instances
2802 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
2803 * can be used to check whether or not a timer instance provides
2804 * a break input.
2805 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2806 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2807 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2808 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2809 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2810 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2811 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2812 * CR2 OIS4N LL_TIM_OC_SetIdleState\n
2813 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2814 * CR2 OIS6 LL_TIM_OC_SetIdleState
2815 * @param TIMx Timer instance
2816 * @param Channel This parameter can be one of the following values:
2817 * @arg @ref LL_TIM_CHANNEL_CH1
2818 * @arg @ref LL_TIM_CHANNEL_CH1N
2819 * @arg @ref LL_TIM_CHANNEL_CH2
2820 * @arg @ref LL_TIM_CHANNEL_CH2N
2821 * @arg @ref LL_TIM_CHANNEL_CH3
2822 * @arg @ref LL_TIM_CHANNEL_CH3N
2823 * @arg @ref LL_TIM_CHANNEL_CH4
2824 * @arg @ref LL_TIM_CHANNEL_CH4N
2825 * @arg @ref LL_TIM_CHANNEL_CH5
2826 * @arg @ref LL_TIM_CHANNEL_CH6
2827 * @param IdleState This parameter can be one of the following values:
2828 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2829 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2830 * @retval None
2831 */
2832 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2833 {
2834 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2835 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2836 }
2837
2838 /**
2839 * @brief Get the IDLE state of an output channel
2840 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2841 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2842 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2843 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2844 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2845 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2846 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2847 * CR2 OIS4N LL_TIM_OC_GetIdleState\n
2848 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2849 * CR2 OIS6 LL_TIM_OC_GetIdleState
2850 * @param TIMx Timer instance
2851 * @param Channel This parameter can be one of the following values:
2852 * @arg @ref LL_TIM_CHANNEL_CH1
2853 * @arg @ref LL_TIM_CHANNEL_CH1N
2854 * @arg @ref LL_TIM_CHANNEL_CH2
2855 * @arg @ref LL_TIM_CHANNEL_CH2N
2856 * @arg @ref LL_TIM_CHANNEL_CH3
2857 * @arg @ref LL_TIM_CHANNEL_CH3N
2858 * @arg @ref LL_TIM_CHANNEL_CH4
2859 * @arg @ref LL_TIM_CHANNEL_CH4N
2860 * @arg @ref LL_TIM_CHANNEL_CH5
2861 * @arg @ref LL_TIM_CHANNEL_CH6
2862 * @retval Returned value can be one of the following values:
2863 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2864 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2865 */
2866 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2867 {
2868 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2869 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2870 }
2871
2872 /**
2873 * @brief Enable fast mode for the output channel.
2874 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2875 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2876 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2877 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2878 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2879 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2880 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2881 * @param TIMx Timer instance
2882 * @param Channel This parameter can be one of the following values:
2883 * @arg @ref LL_TIM_CHANNEL_CH1
2884 * @arg @ref LL_TIM_CHANNEL_CH2
2885 * @arg @ref LL_TIM_CHANNEL_CH3
2886 * @arg @ref LL_TIM_CHANNEL_CH4
2887 * @arg @ref LL_TIM_CHANNEL_CH5
2888 * @arg @ref LL_TIM_CHANNEL_CH6
2889 * @retval None
2890 */
2891 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2892 {
2893 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2894 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2895 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2896
2897 }
2898
2899 /**
2900 * @brief Disable fast mode for the output channel.
2901 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2902 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2903 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2904 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2905 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2906 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2907 * @param TIMx Timer instance
2908 * @param Channel This parameter can be one of the following values:
2909 * @arg @ref LL_TIM_CHANNEL_CH1
2910 * @arg @ref LL_TIM_CHANNEL_CH2
2911 * @arg @ref LL_TIM_CHANNEL_CH3
2912 * @arg @ref LL_TIM_CHANNEL_CH4
2913 * @arg @ref LL_TIM_CHANNEL_CH5
2914 * @arg @ref LL_TIM_CHANNEL_CH6
2915 * @retval None
2916 */
2917 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2918 {
2919 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2920 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2921 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2922
2923 }
2924
2925 /**
2926 * @brief Indicates whether fast mode is enabled for the output channel.
2927 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2928 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2929 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2930 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2931 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2932 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2933 * @param TIMx Timer instance
2934 * @param Channel This parameter can be one of the following values:
2935 * @arg @ref LL_TIM_CHANNEL_CH1
2936 * @arg @ref LL_TIM_CHANNEL_CH2
2937 * @arg @ref LL_TIM_CHANNEL_CH3
2938 * @arg @ref LL_TIM_CHANNEL_CH4
2939 * @arg @ref LL_TIM_CHANNEL_CH5
2940 * @arg @ref LL_TIM_CHANNEL_CH6
2941 * @retval State of bit (1 or 0).
2942 */
2943 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2944 {
2945 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2946 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2947 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2948 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
2949 }
2950
2951 /**
2952 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2953 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2954 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2955 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2956 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2957 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2958 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2959 * @param TIMx Timer instance
2960 * @param Channel This parameter can be one of the following values:
2961 * @arg @ref LL_TIM_CHANNEL_CH1
2962 * @arg @ref LL_TIM_CHANNEL_CH2
2963 * @arg @ref LL_TIM_CHANNEL_CH3
2964 * @arg @ref LL_TIM_CHANNEL_CH4
2965 * @arg @ref LL_TIM_CHANNEL_CH5
2966 * @arg @ref LL_TIM_CHANNEL_CH6
2967 * @retval None
2968 */
2969 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2970 {
2971 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2972 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2973 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2974 }
2975
2976 /**
2977 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2978 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2979 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2980 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2981 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2982 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2983 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2984 * @param TIMx Timer instance
2985 * @param Channel This parameter can be one of the following values:
2986 * @arg @ref LL_TIM_CHANNEL_CH1
2987 * @arg @ref LL_TIM_CHANNEL_CH2
2988 * @arg @ref LL_TIM_CHANNEL_CH3
2989 * @arg @ref LL_TIM_CHANNEL_CH4
2990 * @arg @ref LL_TIM_CHANNEL_CH5
2991 * @arg @ref LL_TIM_CHANNEL_CH6
2992 * @retval None
2993 */
2994 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2995 {
2996 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2997 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2998 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2999 }
3000
3001 /**
3002 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
3003 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
3004 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
3005 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
3006 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
3007 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
3008 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
3009 * @param TIMx Timer instance
3010 * @param Channel This parameter can be one of the following values:
3011 * @arg @ref LL_TIM_CHANNEL_CH1
3012 * @arg @ref LL_TIM_CHANNEL_CH2
3013 * @arg @ref LL_TIM_CHANNEL_CH3
3014 * @arg @ref LL_TIM_CHANNEL_CH4
3015 * @arg @ref LL_TIM_CHANNEL_CH5
3016 * @arg @ref LL_TIM_CHANNEL_CH6
3017 * @retval State of bit (1 or 0).
3018 */
3019 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
3020 {
3021 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3022 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3023 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
3024 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3025 }
3026
3027 /**
3028 * @brief Enable clearing the output channel on an external event.
3029 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3030 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3031 * or not a timer instance can clear the OCxREF signal on an external event.
3032 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
3033 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
3034 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
3035 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
3036 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
3037 * CCMR3 OC6CE LL_TIM_OC_EnableClear
3038 * @param TIMx Timer instance
3039 * @param Channel This parameter can be one of the following values:
3040 * @arg @ref LL_TIM_CHANNEL_CH1
3041 * @arg @ref LL_TIM_CHANNEL_CH2
3042 * @arg @ref LL_TIM_CHANNEL_CH3
3043 * @arg @ref LL_TIM_CHANNEL_CH4
3044 * @arg @ref LL_TIM_CHANNEL_CH5
3045 * @arg @ref LL_TIM_CHANNEL_CH6
3046 * @retval None
3047 */
3048 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3049 {
3050 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3051 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3052 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3053 }
3054
3055 /**
3056 * @brief Disable clearing the output channel on an external event.
3057 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3058 * or not a timer instance can clear the OCxREF signal on an external event.
3059 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
3060 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
3061 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
3062 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
3063 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
3064 * CCMR3 OC6CE LL_TIM_OC_DisableClear
3065 * @param TIMx Timer instance
3066 * @param Channel This parameter can be one of the following values:
3067 * @arg @ref LL_TIM_CHANNEL_CH1
3068 * @arg @ref LL_TIM_CHANNEL_CH2
3069 * @arg @ref LL_TIM_CHANNEL_CH3
3070 * @arg @ref LL_TIM_CHANNEL_CH4
3071 * @arg @ref LL_TIM_CHANNEL_CH5
3072 * @arg @ref LL_TIM_CHANNEL_CH6
3073 * @retval None
3074 */
3075 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
3076 {
3077 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3078 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3079 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
3080 }
3081
3082 /**
3083 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
3084 * @note This function enables clearing the output channel on an external event.
3085 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
3086 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
3087 * or not a timer instance can clear the OCxREF signal on an external event.
3088 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
3089 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
3090 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
3091 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
3092 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
3093 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
3094 * @param TIMx Timer instance
3095 * @param Channel This parameter can be one of the following values:
3096 * @arg @ref LL_TIM_CHANNEL_CH1
3097 * @arg @ref LL_TIM_CHANNEL_CH2
3098 * @arg @ref LL_TIM_CHANNEL_CH3
3099 * @arg @ref LL_TIM_CHANNEL_CH4
3100 * @arg @ref LL_TIM_CHANNEL_CH5
3101 * @arg @ref LL_TIM_CHANNEL_CH6
3102 * @retval State of bit (1 or 0).
3103 */
3104 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
3105 {
3106 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3107 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3108 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
3109 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
3110 }
3111
3112 /**
3113 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).
3114 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3115 * dead-time insertion feature is supported by a timer instance.
3116 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
3117 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
3118 * @param TIMx Timer instance
3119 * @param DeadTime between Min_Data=0 and Max_Data=255
3120 * @retval None
3121 */
3122 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
3123 {
3124 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
3125 }
3126
3127 /**
3128 * @brief Set compare value for output channel 1 (TIMx_CCR1).
3129 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3130 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3131 * whether or not a timer instance supports a 32 bits counter.
3132 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3133 * output channel 1 is supported by a timer instance.
3134 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3135 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
3136 * @param TIMx Timer instance
3137 * @param CompareValue between Min_Data=0 and Max_Data=65535
3138 * @retval None
3139 */
3140 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
3141 {
3142 WRITE_REG(TIMx->CCR1, CompareValue);
3143 }
3144
3145 /**
3146 * @brief Set compare value for output channel 2 (TIMx_CCR2).
3147 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3148 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3149 * whether or not a timer instance supports a 32 bits counter.
3150 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3151 * output channel 2 is supported by a timer instance.
3152 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3153 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
3154 * @param TIMx Timer instance
3155 * @param CompareValue between Min_Data=0 and Max_Data=65535
3156 * @retval None
3157 */
3158 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
3159 {
3160 WRITE_REG(TIMx->CCR2, CompareValue);
3161 }
3162
3163 /**
3164 * @brief Set compare value for output channel 3 (TIMx_CCR3).
3165 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3166 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3167 * whether or not a timer instance supports a 32 bits counter.
3168 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3169 * output channel is supported by a timer instance.
3170 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3171 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
3172 * @param TIMx Timer instance
3173 * @param CompareValue between Min_Data=0 and Max_Data=65535
3174 * @retval None
3175 */
3176 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
3177 {
3178 WRITE_REG(TIMx->CCR3, CompareValue);
3179 }
3180
3181 /**
3182 * @brief Set compare value for output channel 4 (TIMx_CCR4).
3183 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
3184 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3185 * whether or not a timer instance supports a 32 bits counter.
3186 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3187 * output channel 4 is supported by a timer instance.
3188 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3189 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
3190 * @param TIMx Timer instance
3191 * @param CompareValue between Min_Data=0 and Max_Data=65535
3192 * @retval None
3193 */
3194 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
3195 {
3196 WRITE_REG(TIMx->CCR4, CompareValue);
3197 }
3198
3199 /**
3200 * @brief Set compare value for output channel 5 (TIMx_CCR5).
3201 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3202 * output channel 5 is supported by a timer instance.
3203 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3204 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
3205 * @param TIMx Timer instance
3206 * @param CompareValue between Min_Data=0 and Max_Data=65535
3207 * @retval None
3208 */
3209 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
3210 {
3211 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
3212 }
3213
3214 /**
3215 * @brief Set compare value for output channel 6 (TIMx_CCR6).
3216 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3217 * output channel 6 is supported by a timer instance.
3218 * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
3219 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
3220 * @param TIMx Timer instance
3221 * @param CompareValue between Min_Data=0 and Max_Data=65535
3222 * @retval None
3223 */
3224 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
3225 {
3226 WRITE_REG(TIMx->CCR6, CompareValue);
3227 }
3228
3229 /**
3230 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
3231 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3232 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3233 * whether or not a timer instance supports a 32 bits counter.
3234 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3235 * output channel 1 is supported by a timer instance.
3236 * @note If dithering is activated, pay attention to the returned value interpretation.
3237 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
3238 * @param TIMx Timer instance
3239 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3240 */
3241 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
3242 {
3243 return (uint32_t)(READ_REG(TIMx->CCR1));
3244 }
3245
3246 /**
3247 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
3248 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3249 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3250 * whether or not a timer instance supports a 32 bits counter.
3251 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3252 * output channel 2 is supported by a timer instance.
3253 * @note If dithering is activated, pay attention to the returned value interpretation.
3254 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
3255 * @param TIMx Timer instance
3256 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3257 */
3258 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
3259 {
3260 return (uint32_t)(READ_REG(TIMx->CCR2));
3261 }
3262
3263 /**
3264 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
3265 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3266 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3267 * whether or not a timer instance supports a 32 bits counter.
3268 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3269 * output channel 3 is supported by a timer instance.
3270 * @note If dithering is activated, pay attention to the returned value interpretation.
3271 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
3272 * @param TIMx Timer instance
3273 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3274 */
3275 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
3276 {
3277 return (uint32_t)(READ_REG(TIMx->CCR3));
3278 }
3279
3280 /**
3281 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
3282 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
3283 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3284 * whether or not a timer instance supports a 32 bits counter.
3285 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3286 * output channel 4 is supported by a timer instance.
3287 * @note If dithering is activated, pay attention to the returned value interpretation.
3288 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
3289 * @param TIMx Timer instance
3290 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3291 */
3292 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
3293 {
3294 return (uint32_t)(READ_REG(TIMx->CCR4));
3295 }
3296
3297 /**
3298 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
3299 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
3300 * output channel 5 is supported by a timer instance.
3301 * @note If dithering is activated, pay attention to the returned value interpretation.
3302 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
3303 * @param TIMx Timer instance
3304 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3305 */
3306 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
3307 {
3308 return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
3309 }
3310
3311 /**
3312 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
3313 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
3314 * output channel 6 is supported by a timer instance.
3315 * @note If dithering is activated, pay attention to the returned value interpretation.
3316 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
3317 * @param TIMx Timer instance
3318 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
3319 */
3320 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
3321 {
3322 return (uint32_t)(READ_REG(TIMx->CCR6));
3323 }
3324
3325 /**
3326 * @brief Select on which reference signal the OC5REF is combined to.
3327 * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
3328 * whether or not a timer instance supports the combined 3-phase PWM mode.
3329 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
3330 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
3331 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
3332 * @param TIMx Timer instance
3333 * @param GroupCH5 This parameter can be a combination of the following values:
3334 * @arg @ref LL_TIM_GROUPCH5_NONE
3335 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
3336 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
3337 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
3338 * @retval None
3339 */
3340 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
3341 {
3342 MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
3343 }
3344
3345 /**
3346 * @brief Set the pulse on compare pulse width prescaler.
3347 * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3348 * whether or not the pulse on compare feature is supported by the timer
3349 * instance.
3350 * @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
3351 * @param TIMx Timer instance
3352 * @param PulseWidthPrescaler This parameter can be one of the following values:
3353 * @arg @ref LL_TIM_PWPRSC_X1
3354 * @arg @ref LL_TIM_PWPRSC_X2
3355 * @arg @ref LL_TIM_PWPRSC_X4
3356 * @arg @ref LL_TIM_PWPRSC_X8
3357 * @arg @ref LL_TIM_PWPRSC_X16
3358 * @arg @ref LL_TIM_PWPRSC_X32
3359 * @arg @ref LL_TIM_PWPRSC_X64
3360 * @arg @ref LL_TIM_PWPRSC_X128
3361 * @retval None
3362 */
3363 __STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
3364 {
3365 MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
3366 }
3367
3368 /**
3369 * @brief Get the pulse on compare pulse width prescaler.
3370 * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3371 * whether or not the pulse on compare feature is supported by the timer
3372 * instance.
3373 * @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
3374 * @param TIMx Timer instance
3375 * @retval Returned value can be one of the following values:
3376 * @arg @ref LL_TIM_PWPRSC_X1
3377 * @arg @ref LL_TIM_PWPRSC_X2
3378 * @arg @ref LL_TIM_PWPRSC_X4
3379 * @arg @ref LL_TIM_PWPRSC_X8
3380 * @arg @ref LL_TIM_PWPRSC_X16
3381 * @arg @ref LL_TIM_PWPRSC_X32
3382 * @arg @ref LL_TIM_PWPRSC_X64
3383 * @arg @ref LL_TIM_PWPRSC_X128
3384 */
3385 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
3386 {
3387 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
3388 }
3389
3390 /**
3391 * @brief Set the pulse on compare pulse width duration.
3392 * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3393 * whether or not the pulse on compare feature is supported by the timer
3394 * instance.
3395 * @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
3396 * @param TIMx Timer instance
3397 * @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
3398 * @retval None
3399 */
3400 __STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
3401 {
3402 MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth);
3403 }
3404
3405 /**
3406 * @brief Get the pulse on compare pulse width duration.
3407 * @note Macro @ref IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
3408 * whether or not the pulse on compare feature is supported by the timer
3409 * instance.
3410 * @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
3411 * @param TIMx Timer instance
3412 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
3413 */
3414 __STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
3415 {
3416 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
3417 }
3418
3419 /**
3420 * @}
3421 */
3422
3423 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
3424 * @{
3425 */
3426 /**
3427 * @brief Configure input channel.
3428 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
3429 * CCMR1 IC1PSC LL_TIM_IC_Config\n
3430 * CCMR1 IC1F LL_TIM_IC_Config\n
3431 * CCMR1 CC2S LL_TIM_IC_Config\n
3432 * CCMR1 IC2PSC LL_TIM_IC_Config\n
3433 * CCMR1 IC2F LL_TIM_IC_Config\n
3434 * CCMR2 CC3S LL_TIM_IC_Config\n
3435 * CCMR2 IC3PSC LL_TIM_IC_Config\n
3436 * CCMR2 IC3F LL_TIM_IC_Config\n
3437 * CCMR2 CC4S LL_TIM_IC_Config\n
3438 * CCMR2 IC4PSC LL_TIM_IC_Config\n
3439 * CCMR2 IC4F LL_TIM_IC_Config\n
3440 * CCER CC1P LL_TIM_IC_Config\n
3441 * CCER CC1NP LL_TIM_IC_Config\n
3442 * CCER CC2P LL_TIM_IC_Config\n
3443 * CCER CC2NP LL_TIM_IC_Config\n
3444 * CCER CC3P LL_TIM_IC_Config\n
3445 * CCER CC3NP LL_TIM_IC_Config\n
3446 * CCER CC4P LL_TIM_IC_Config\n
3447 * CCER CC4NP LL_TIM_IC_Config
3448 * @param TIMx Timer instance
3449 * @param Channel This parameter can be one of the following values:
3450 * @arg @ref LL_TIM_CHANNEL_CH1
3451 * @arg @ref LL_TIM_CHANNEL_CH2
3452 * @arg @ref LL_TIM_CHANNEL_CH3
3453 * @arg @ref LL_TIM_CHANNEL_CH4
3454 * @param Configuration This parameter must be a combination of all the following values:
3455 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
3456 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
3457 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
3458 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
3459 * @retval None
3460 */
3461 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
3462 {
3463 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3464 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3465 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
3466 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
3467 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3468 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
3469 }
3470
3471 /**
3472 * @brief Set the active input.
3473 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
3474 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
3475 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
3476 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
3477 * @param TIMx Timer instance
3478 * @param Channel This parameter can be one of the following values:
3479 * @arg @ref LL_TIM_CHANNEL_CH1
3480 * @arg @ref LL_TIM_CHANNEL_CH2
3481 * @arg @ref LL_TIM_CHANNEL_CH3
3482 * @arg @ref LL_TIM_CHANNEL_CH4
3483 * @param ICActiveInput This parameter can be one of the following values:
3484 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3485 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3486 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3487 * @retval None
3488 */
3489 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
3490 {
3491 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3492 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3493 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3494 }
3495
3496 /**
3497 * @brief Get the current active input.
3498 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
3499 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
3500 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
3501 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
3502 * @param TIMx Timer instance
3503 * @param Channel This parameter can be one of the following values:
3504 * @arg @ref LL_TIM_CHANNEL_CH1
3505 * @arg @ref LL_TIM_CHANNEL_CH2
3506 * @arg @ref LL_TIM_CHANNEL_CH3
3507 * @arg @ref LL_TIM_CHANNEL_CH4
3508 * @retval Returned value can be one of the following values:
3509 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
3510 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
3511 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
3512 */
3513 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
3514 {
3515 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3516 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3517 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3518 }
3519
3520 /**
3521 * @brief Set the prescaler of input channel.
3522 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
3523 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
3524 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
3525 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
3526 * @param TIMx Timer instance
3527 * @param Channel This parameter can be one of the following values:
3528 * @arg @ref LL_TIM_CHANNEL_CH1
3529 * @arg @ref LL_TIM_CHANNEL_CH2
3530 * @arg @ref LL_TIM_CHANNEL_CH3
3531 * @arg @ref LL_TIM_CHANNEL_CH4
3532 * @param ICPrescaler This parameter can be one of the following values:
3533 * @arg @ref LL_TIM_ICPSC_DIV1
3534 * @arg @ref LL_TIM_ICPSC_DIV2
3535 * @arg @ref LL_TIM_ICPSC_DIV4
3536 * @arg @ref LL_TIM_ICPSC_DIV8
3537 * @retval None
3538 */
3539 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
3540 {
3541 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3542 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3543 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3544 }
3545
3546 /**
3547 * @brief Get the current prescaler value acting on an input channel.
3548 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
3549 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
3550 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
3551 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
3552 * @param TIMx Timer instance
3553 * @param Channel This parameter can be one of the following values:
3554 * @arg @ref LL_TIM_CHANNEL_CH1
3555 * @arg @ref LL_TIM_CHANNEL_CH2
3556 * @arg @ref LL_TIM_CHANNEL_CH3
3557 * @arg @ref LL_TIM_CHANNEL_CH4
3558 * @retval Returned value can be one of the following values:
3559 * @arg @ref LL_TIM_ICPSC_DIV1
3560 * @arg @ref LL_TIM_ICPSC_DIV2
3561 * @arg @ref LL_TIM_ICPSC_DIV4
3562 * @arg @ref LL_TIM_ICPSC_DIV8
3563 */
3564 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
3565 {
3566 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3567 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3568 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3569 }
3570
3571 /**
3572 * @brief Set the input filter duration.
3573 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
3574 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
3575 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
3576 * CCMR2 IC4F LL_TIM_IC_SetFilter
3577 * @param TIMx Timer instance
3578 * @param Channel This parameter can be one of the following values:
3579 * @arg @ref LL_TIM_CHANNEL_CH1
3580 * @arg @ref LL_TIM_CHANNEL_CH2
3581 * @arg @ref LL_TIM_CHANNEL_CH3
3582 * @arg @ref LL_TIM_CHANNEL_CH4
3583 * @param ICFilter This parameter can be one of the following values:
3584 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3585 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3586 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3587 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3588 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3589 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3590 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3591 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3592 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3593 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3594 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3595 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3596 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3597 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3598 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3599 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3600 * @retval None
3601 */
3602 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
3603 {
3604 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3605 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3606 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
3607 }
3608
3609 /**
3610 * @brief Get the input filter duration.
3611 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
3612 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
3613 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
3614 * CCMR2 IC4F LL_TIM_IC_GetFilter
3615 * @param TIMx Timer instance
3616 * @param Channel This parameter can be one of the following values:
3617 * @arg @ref LL_TIM_CHANNEL_CH1
3618 * @arg @ref LL_TIM_CHANNEL_CH2
3619 * @arg @ref LL_TIM_CHANNEL_CH3
3620 * @arg @ref LL_TIM_CHANNEL_CH4
3621 * @retval Returned value can be one of the following values:
3622 * @arg @ref LL_TIM_IC_FILTER_FDIV1
3623 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
3624 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
3625 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
3626 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
3627 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
3628 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
3629 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
3630 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
3631 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
3632 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
3633 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
3634 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
3635 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
3636 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
3637 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
3638 */
3639 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
3640 {
3641 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3642 register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
3643 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
3644 }
3645
3646 /**
3647 * @brief Set the input channel polarity.
3648 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
3649 * CCER CC1NP LL_TIM_IC_SetPolarity\n
3650 * CCER CC2P LL_TIM_IC_SetPolarity\n
3651 * CCER CC2NP LL_TIM_IC_SetPolarity\n
3652 * CCER CC3P LL_TIM_IC_SetPolarity\n
3653 * CCER CC3NP LL_TIM_IC_SetPolarity\n
3654 * CCER CC4P LL_TIM_IC_SetPolarity\n
3655 * CCER CC4NP LL_TIM_IC_SetPolarity
3656 * @param TIMx Timer instance
3657 * @param Channel This parameter can be one of the following values:
3658 * @arg @ref LL_TIM_CHANNEL_CH1
3659 * @arg @ref LL_TIM_CHANNEL_CH2
3660 * @arg @ref LL_TIM_CHANNEL_CH3
3661 * @arg @ref LL_TIM_CHANNEL_CH4
3662 * @param ICPolarity This parameter can be one of the following values:
3663 * @arg @ref LL_TIM_IC_POLARITY_RISING
3664 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3665 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3666 * @retval None
3667 */
3668 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
3669 {
3670 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3671 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
3672 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
3673 }
3674
3675 /**
3676 * @brief Get the current input channel polarity.
3677 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
3678 * CCER CC1NP LL_TIM_IC_GetPolarity\n
3679 * CCER CC2P LL_TIM_IC_GetPolarity\n
3680 * CCER CC2NP LL_TIM_IC_GetPolarity\n
3681 * CCER CC3P LL_TIM_IC_GetPolarity\n
3682 * CCER CC3NP LL_TIM_IC_GetPolarity\n
3683 * CCER CC4P LL_TIM_IC_GetPolarity\n
3684 * CCER CC4NP LL_TIM_IC_GetPolarity
3685 * @param TIMx Timer instance
3686 * @param Channel This parameter can be one of the following values:
3687 * @arg @ref LL_TIM_CHANNEL_CH1
3688 * @arg @ref LL_TIM_CHANNEL_CH2
3689 * @arg @ref LL_TIM_CHANNEL_CH3
3690 * @arg @ref LL_TIM_CHANNEL_CH4
3691 * @retval Returned value can be one of the following values:
3692 * @arg @ref LL_TIM_IC_POLARITY_RISING
3693 * @arg @ref LL_TIM_IC_POLARITY_FALLING
3694 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
3695 */
3696 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
3697 {
3698 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
3699 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
3700 SHIFT_TAB_CCxP[iChannel]);
3701 }
3702
3703 /**
3704 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
3705 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3706 * a timer instance provides an XOR input.
3707 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
3708 * @param TIMx Timer instance
3709 * @retval None
3710 */
3711 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
3712 {
3713 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
3714 }
3715
3716 /**
3717 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
3718 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3719 * a timer instance provides an XOR input.
3720 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
3721 * @param TIMx Timer instance
3722 * @retval None
3723 */
3724 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
3725 {
3726 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
3727 }
3728
3729 /**
3730 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
3731 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
3732 * a timer instance provides an XOR input.
3733 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
3734 * @param TIMx Timer instance
3735 * @retval State of bit (1 or 0).
3736 */
3737 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
3738 {
3739 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
3740 }
3741
3742 /**
3743 * @brief Get captured value for input channel 1.
3744 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3745 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3746 * whether or not a timer instance supports a 32 bits counter.
3747 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
3748 * input channel 1 is supported by a timer instance.
3749 * @note If dithering is activated, pay attention to the returned value interpretation.
3750 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
3751 * @param TIMx Timer instance
3752 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3753 */
3754 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
3755 {
3756 return (uint32_t)(READ_REG(TIMx->CCR1));
3757 }
3758
3759 /**
3760 * @brief Get captured value for input channel 2.
3761 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3762 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3763 * whether or not a timer instance supports a 32 bits counter.
3764 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
3765 * input channel 2 is supported by a timer instance.
3766 * @note If dithering is activated, pay attention to the returned value interpretation.
3767 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
3768 * @param TIMx Timer instance
3769 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3770 */
3771 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
3772 {
3773 return (uint32_t)(READ_REG(TIMx->CCR2));
3774 }
3775
3776 /**
3777 * @brief Get captured value for input channel 3.
3778 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3779 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3780 * whether or not a timer instance supports a 32 bits counter.
3781 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
3782 * input channel 3 is supported by a timer instance.
3783 * @note If dithering is activated, pay attention to the returned value interpretation.
3784 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
3785 * @param TIMx Timer instance
3786 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3787 */
3788 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
3789 {
3790 return (uint32_t)(READ_REG(TIMx->CCR3));
3791 }
3792
3793 /**
3794 * @brief Get captured value for input channel 4.
3795 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
3796 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
3797 * whether or not a timer instance supports a 32 bits counter.
3798 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
3799 * input channel 4 is supported by a timer instance.
3800 * @note If dithering is activated, pay attention to the returned value interpretation.
3801 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
3802 * @param TIMx Timer instance
3803 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
3804 */
3805 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
3806 {
3807 return (uint32_t)(READ_REG(TIMx->CCR4));
3808 }
3809
3810 /**
3811 * @}
3812 */
3813
3814 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
3815 * @{
3816 */
3817 /**
3818 * @brief Enable external clock mode 2.
3819 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
3820 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3821 * whether or not a timer instance supports external clock mode2.
3822 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
3823 * @param TIMx Timer instance
3824 * @retval None
3825 */
3826 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
3827 {
3828 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3829 }
3830
3831 /**
3832 * @brief Disable external clock mode 2.
3833 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3834 * whether or not a timer instance supports external clock mode2.
3835 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
3836 * @param TIMx Timer instance
3837 * @retval None
3838 */
3839 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
3840 {
3841 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
3842 }
3843
3844 /**
3845 * @brief Indicate whether external clock mode 2 is enabled.
3846 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3847 * whether or not a timer instance supports external clock mode2.
3848 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
3849 * @param TIMx Timer instance
3850 * @retval State of bit (1 or 0).
3851 */
3852 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
3853 {
3854 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
3855 }
3856
3857 /**
3858 * @brief Set the clock source of the counter clock.
3859 * @note when selected clock source is external clock mode 1, the timer input
3860 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3861 * function. This timer input must be configured by calling
3862 * the @ref LL_TIM_IC_Config() function.
3863 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3864 * whether or not a timer instance supports external clock mode1.
3865 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3866 * whether or not a timer instance supports external clock mode2.
3867 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3868 * SMCR ECE LL_TIM_SetClockSource
3869 * @param TIMx Timer instance
3870 * @param ClockSource This parameter can be one of the following values:
3871 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3872 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3873 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3874 * @retval None
3875 */
3876 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3877 {
3878 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3879 }
3880
3881 /**
3882 * @brief Set the encoder interface mode.
3883 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3884 * whether or not a timer instance supports the encoder mode.
3885 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3886 * @param TIMx Timer instance
3887 * @param EncoderMode This parameter can be one of the following values:
3888 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3889 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3890 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3891 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
3892 * @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
3893 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
3894 * @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
3895 * @arg @ref LL_TIM_ENCODERMODE_X1_TI1
3896 * @arg @ref LL_TIM_ENCODERMODE_X1_TI2
3897 * @retval None
3898 */
3899 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3900 {
3901 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3902 }
3903
3904 /**
3905 * @}
3906 */
3907
3908 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3909 * @{
3910 */
3911 /**
3912 * @brief Set the trigger output (TRGO) used for timer synchronization .
3913 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3914 * whether or not a timer instance can operate as a master timer.
3915 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3916 * @param TIMx Timer instance
3917 * @param TimerSynchronization This parameter can be one of the following values:
3918 * @arg @ref LL_TIM_TRGO_RESET
3919 * @arg @ref LL_TIM_TRGO_ENABLE
3920 * @arg @ref LL_TIM_TRGO_UPDATE
3921 * @arg @ref LL_TIM_TRGO_CC1IF
3922 * @arg @ref LL_TIM_TRGO_OC1REF
3923 * @arg @ref LL_TIM_TRGO_OC2REF
3924 * @arg @ref LL_TIM_TRGO_OC3REF
3925 * @arg @ref LL_TIM_TRGO_OC4REF
3926 * @arg @ref LL_TIM_TRGO_ENCODERCLK
3927 * @retval None
3928 */
3929 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3930 {
3931 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3932 }
3933
3934 /**
3935 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3936 * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3937 * whether or not a timer instance can be used for ADC synchronization.
3938 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3939 * @param TIMx Timer Instance
3940 * @param ADCSynchronization This parameter can be one of the following values:
3941 * @arg @ref LL_TIM_TRGO2_RESET
3942 * @arg @ref LL_TIM_TRGO2_ENABLE
3943 * @arg @ref LL_TIM_TRGO2_UPDATE
3944 * @arg @ref LL_TIM_TRGO2_CC1F
3945 * @arg @ref LL_TIM_TRGO2_OC1
3946 * @arg @ref LL_TIM_TRGO2_OC2
3947 * @arg @ref LL_TIM_TRGO2_OC3
3948 * @arg @ref LL_TIM_TRGO2_OC4
3949 * @arg @ref LL_TIM_TRGO2_OC5
3950 * @arg @ref LL_TIM_TRGO2_OC6
3951 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3952 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3953 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3954 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3955 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3956 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3957 * @retval None
3958 */
3959 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3960 {
3961 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3962 }
3963
3964 /**
3965 * @brief Set the synchronization mode of a slave timer.
3966 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3967 * a timer instance can operate as a slave timer.
3968 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3969 * @param TIMx Timer instance
3970 * @param SlaveMode This parameter can be one of the following values:
3971 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3972 * @arg @ref LL_TIM_SLAVEMODE_RESET
3973 * @arg @ref LL_TIM_SLAVEMODE_GATED
3974 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3975 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3976 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
3977 * @retval None
3978 */
3979 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3980 {
3981 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3982 }
3983
3984 /**
3985 * @brief Set the selects the trigger input to be used to synchronize the counter.
3986 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3987 * a timer instance can operate as a slave timer.
3988 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3989 * @param TIMx Timer instance
3990 * @param TriggerInput This parameter can be one of the following values:
3991 * @arg @ref LL_TIM_TS_ITR0
3992 * @arg @ref LL_TIM_TS_ITR1
3993 * @arg @ref LL_TIM_TS_ITR2
3994 * @arg @ref LL_TIM_TS_ITR3
3995 * @arg @ref LL_TIM_TS_TI1F_ED
3996 * @arg @ref LL_TIM_TS_TI1FP1
3997 * @arg @ref LL_TIM_TS_TI2FP2
3998 * @arg @ref LL_TIM_TS_ETRF
3999 * @arg @ref LL_TIM_TS_ITR4
4000 * @arg @ref LL_TIM_TS_ITR5
4001 * @arg @ref LL_TIM_TS_ITR6
4002 * @arg @ref LL_TIM_TS_ITR7
4003 * @arg @ref LL_TIM_TS_ITR8
4004 * @arg @ref LL_TIM_TS_ITR9
4005 * @arg @ref LL_TIM_TS_ITR10
4006 * @arg @ref LL_TIM_TS_ITR11
4007 * @retval None
4008 */
4009 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
4010 {
4011 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
4012 }
4013
4014 /**
4015 * @brief Enable the Master/Slave mode.
4016 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4017 * a timer instance can operate as a slave timer.
4018 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
4019 * @param TIMx Timer instance
4020 * @retval None
4021 */
4022 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
4023 {
4024 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4025 }
4026
4027 /**
4028 * @brief Disable the Master/Slave mode.
4029 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4030 * a timer instance can operate as a slave timer.
4031 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
4032 * @param TIMx Timer instance
4033 * @retval None
4034 */
4035 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
4036 {
4037 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
4038 }
4039
4040 /**
4041 * @brief Indicates whether the Master/Slave mode is enabled.
4042 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
4043 * a timer instance can operate as a slave timer.
4044 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
4045 * @param TIMx Timer instance
4046 * @retval State of bit (1 or 0).
4047 */
4048 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
4049 {
4050 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
4051 }
4052
4053 /**
4054 * @brief Configure the external trigger (ETR) input.
4055 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
4056 * a timer instance provides an external trigger input.
4057 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
4058 * SMCR ETPS LL_TIM_ConfigETR\n
4059 * SMCR ETF LL_TIM_ConfigETR
4060 * @param TIMx Timer instance
4061 * @param ETRPolarity This parameter can be one of the following values:
4062 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
4063 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
4064 * @param ETRPrescaler This parameter can be one of the following values:
4065 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
4066 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
4067 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
4068 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
4069 * @param ETRFilter This parameter can be one of the following values:
4070 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
4071 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
4072 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
4073 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
4074 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
4075 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
4076 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
4077 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
4078 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
4079 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
4080 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
4081 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
4082 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
4083 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
4084 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
4085 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
4086 * @retval None
4087 */
4088 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
4089 uint32_t ETRFilter)
4090 {
4091 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
4092 }
4093
4094 /**
4095 * @brief Select the external trigger (ETR) input source.
4096 * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
4097 * not a timer instance supports ETR source selection.
4098 * @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
4099 * @param TIMx Timer instance
4100 * @param ETRSource This parameter can be one of the following values:
4101 *
4102 * TIM1: any combination of ETR_RMP where
4103 *
4104 * @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
4105 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
4106 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
4107 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
4108 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
4109 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
4110 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
4111 * @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
4112 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
4113 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
4114 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
4115 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
4116 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
4117 * @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
4118 *
4119 * TIM2: any combination of ETR_RMP where
4120 *
4121 * @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
4122 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
4123 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
4124 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
4125 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
4126 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
4127 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
4128 * @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
4129 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
4130 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
4131 * @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
4132 * @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
4133 *
4134 * TIM3: any combination of ETR_RMP where
4135 *
4136 * @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
4137 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
4138 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
4139 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
4140 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
4141 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
4142 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
4143 * @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
4144 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
4145 * @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
4146 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
4147 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
4148 * @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
4149 *
4150 * TIM4: any combination of ETR_RMP where
4151 *
4152 * @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
4153 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
4154 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
4155 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
4156 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
4157 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
4158 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
4159 * @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
4160 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
4161 * @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
4162 *
4163 * TIM5: any combination of ETR_RMP where (**)
4164 *
4165 * @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
4166 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
4167 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
4168 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
4169 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
4170 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
4171 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
4172 * @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
4173 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
4174 * @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
4175 *
4176 * TIM8: any combination of ETR_RMP where
4177 *
4178 * . . ETR_RMP can be one of the following values
4179 * @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
4180 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
4181 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
4182 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
4183 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
4184 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
4185 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
4186 * @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
4187 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
4188 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
4189 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
4190 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
4191 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
4192 * @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
4193 *
4194 * TIM20: any combination of ETR_RMP where (**)
4195 *
4196 * . . ETR_RMP can be one of the following values
4197 * @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
4198 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
4199 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
4200 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
4201 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
4202 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
4203 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
4204 * @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
4205 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
4206 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
4207 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
4208 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
4209 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
4210 * @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
4211 *
4212 * (*) Value not defined in all devices. \n
4213 * (**) Register not available in all devices.
4214 * @retval None
4215 */
4216 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
4217 {
4218
4219 MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
4220 }
4221
4222 /**
4223 * @brief Enable SMS preload.
4224 * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4225 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4226 * @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
4227 * @param TIMx Timer instance
4228 * @retval None
4229 */
4230 __STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
4231 {
4232 SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4233 }
4234
4235 /**
4236 * @brief Disable SMS preload.
4237 * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4238 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4239 * @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
4240 * @param TIMx Timer instance
4241 * @retval None
4242 */
4243 __STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
4244 {
4245 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
4246 }
4247
4248 /**
4249 * @brief Indicate whether SMS preload is enabled.
4250 * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4251 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4252 * @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
4253 * @param TIMx Timer instance
4254 * @retval State of bit (1 or 0).
4255 */
4256 __STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
4257 {
4258 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
4259 }
4260
4261 /**
4262 * @brief Set the preload source of SMS.
4263 * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4264 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4265 * @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
4266 * @param TIMx Timer instance
4267 * @param PreloadSource This parameter can be one of the following values:
4268 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4269 * @arg @ref LL_TIM_SMSPS_INDEX
4270 * @retval None
4271 */
4272 __STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
4273 {
4274 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
4275 }
4276
4277 /**
4278 * @brief Get the preload source of SMS.
4279 * @note Macro @ref IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
4280 * whether or not a timer instance supports the preload of SMS field in SMCR register.
4281 * @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
4282 * @param TIMx Timer instance
4283 * @retval Returned value can be one of the following values:
4284 * @arg @ref LL_TIM_SMSPS_TIMUPDATE
4285 * @arg @ref LL_TIM_SMSPS_INDEX
4286 */
4287 __STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
4288 {
4289 return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
4290 }
4291
4292 /**
4293 * @}
4294 */
4295
4296 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
4297 * @{
4298 */
4299 /**
4300 * @brief Enable the break function.
4301 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4302 * a timer instance provides a break input.
4303 * @rmtoll BDTR BKE LL_TIM_EnableBRK
4304 * @param TIMx Timer instance
4305 * @retval None
4306 */
4307 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
4308 {
4309 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4310 }
4311
4312 /**
4313 * @brief Disable the break function.
4314 * @rmtoll BDTR BKE LL_TIM_DisableBRK
4315 * @param TIMx Timer instance
4316 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4317 * a timer instance provides a break input.
4318 * @retval None
4319 */
4320 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
4321 {
4322 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
4323 }
4324
4325 /**
4326 * @brief Configure the break input.
4327 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4328 * a timer instance provides a break input.
4329 * @note Bidirectional mode is only supported by advanced timer instances.
4330 * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4331 * a timer instance is an advanced-control timer.
4332 * @note In bidirectional mode (BKBID bit set), the Break input is configured both
4333 * in input mode and in open drain output mode. Any active Break event will
4334 * assert a low logic level on the Break input to indicate an internal break
4335 * event to external devices.
4336 * @note When bidirectional mode isn't supported, BreakAFMode must be set to
4337 * LL_TIM_BREAK_AFMODE_INPUT.
4338 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
4339 * BDTR BKF LL_TIM_ConfigBRK\n
4340 * BDTR BKBID LL_TIM_ConfigBRK
4341 * @param TIMx Timer instance
4342 * @param BreakPolarity This parameter can be one of the following values:
4343 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
4344 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
4345 * @param BreakFilter This parameter can be one of the following values:
4346 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
4347 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
4348 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
4349 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
4350 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
4351 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
4352 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
4353 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
4354 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
4355 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
4356 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
4357 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
4358 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
4359 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
4360 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
4361 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
4362 * @param BreakAFMode This parameter can be one of the following values:
4363 * @arg @ref LL_TIM_BREAK_AFMODE_INPUT
4364 * @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
4365 * @retval None
4366 */
4367 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
4368 uint32_t BreakAFMode)
4369 {
4370 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
4371 }
4372
4373 /**
4374 * @brief Disarm the break input (when it operates in bidirectional mode).
4375 * @note The break input can be disarmed only when it is configured in
4376 * bidirectional mode and when when MOE is reset.
4377 * @note Purpose is to be able to have the input voltage back to high-state,
4378 * whatever the time constant on the output .
4379 * @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
4380 * @param TIMx Timer instance
4381 * @retval None
4382 */
4383 __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
4384 {
4385 SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4386 }
4387
4388 /**
4389 * @brief Re-arm the break input (when it operates in bidirectional mode).
4390 * @note The Break input is automatically armed as soon as MOE bit is set.
4391 * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
4392 * @param TIMx Timer instance
4393 * @retval None
4394 */
4395 __STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
4396 {
4397 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
4398 }
4399
4400 /**
4401 * @brief Enable the break 2 function.
4402 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4403 * a timer instance provides a second break input.
4404 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
4405 * @param TIMx Timer instance
4406 * @retval None
4407 */
4408 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
4409 {
4410 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4411 }
4412
4413 /**
4414 * @brief Disable the break 2 function.
4415 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4416 * a timer instance provides a second break input.
4417 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
4418 * @param TIMx Timer instance
4419 * @retval None
4420 */
4421 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
4422 {
4423 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
4424 }
4425
4426 /**
4427 * @brief Configure the break 2 input.
4428 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
4429 * a timer instance provides a second break input.
4430 * @note Bidirectional mode is only supported by advanced timer instances.
4431 * Macro @ref IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
4432 * a timer instance is an advanced-control timer.
4433 * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
4434 * in input mode and in open drain output mode. Any active Break event will
4435 * assert a low logic level on the Break 2 input to indicate an internal break
4436 * event to external devices.
4437 * @note When bidirectional mode isn't supported, Break2AFMode must be set to
4438 * LL_TIM_BREAK2_AFMODE_INPUT.
4439 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
4440 * BDTR BK2F LL_TIM_ConfigBRK2\n
4441 * BDTR BK2BID LL_TIM_ConfigBRK2
4442 * @param TIMx Timer instance
4443 * @param Break2Polarity This parameter can be one of the following values:
4444 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
4445 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
4446 * @param Break2Filter This parameter can be one of the following values:
4447 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
4448 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
4449 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
4450 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
4451 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
4452 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
4453 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
4454 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
4455 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
4456 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
4457 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
4458 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
4459 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
4460 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
4461 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
4462 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
4463 * @param Break2AFMode This parameter can be one of the following values:
4464 * @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
4465 * @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
4466 * @retval None
4467 */
4468 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
4469 uint32_t Break2AFMode)
4470 {
4471 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
4472 }
4473
4474 /**
4475 * @brief Disarm the break 2 input (when it operates in bidirectional mode).
4476 * @note The break 2 input can be disarmed only when it is configured in
4477 * bidirectional mode and when when MOE is reset.
4478 * @note Purpose is to be able to have the input voltage back to high-state,
4479 * whatever the time constant on the output.
4480 * @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
4481 * @param TIMx Timer instance
4482 * @retval None
4483 */
4484 __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
4485 {
4486 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4487 }
4488
4489 /**
4490 * @brief Re-arm the break 2 input (when it operates in bidirectional mode).
4491 * @note The Break 2 input is automatically armed as soon as MOE bit is set.
4492 * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
4493 * @param TIMx Timer instance
4494 * @retval None
4495 */
4496 __STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
4497 {
4498 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
4499 }
4500
4501 /**
4502 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
4503 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4504 * a timer instance provides a break input.
4505 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
4506 * BDTR OSSR LL_TIM_SetOffStates
4507 * @param TIMx Timer instance
4508 * @param OffStateIdle This parameter can be one of the following values:
4509 * @arg @ref LL_TIM_OSSI_DISABLE
4510 * @arg @ref LL_TIM_OSSI_ENABLE
4511 * @param OffStateRun This parameter can be one of the following values:
4512 * @arg @ref LL_TIM_OSSR_DISABLE
4513 * @arg @ref LL_TIM_OSSR_ENABLE
4514 * @retval None
4515 */
4516 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
4517 {
4518 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
4519 }
4520
4521 /**
4522 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
4523 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4524 * a timer instance provides a break input.
4525 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
4526 * @param TIMx Timer instance
4527 * @retval None
4528 */
4529 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
4530 {
4531 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4532 }
4533
4534 /**
4535 * @brief Disable automatic output (MOE can be set only by software).
4536 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4537 * a timer instance provides a break input.
4538 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
4539 * @param TIMx Timer instance
4540 * @retval None
4541 */
4542 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
4543 {
4544 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
4545 }
4546
4547 /**
4548 * @brief Indicate whether automatic output is enabled.
4549 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4550 * a timer instance provides a break input.
4551 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
4552 * @param TIMx Timer instance
4553 * @retval State of bit (1 or 0).
4554 */
4555 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
4556 {
4557 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
4558 }
4559
4560 /**
4561 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
4562 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4563 * software and is reset in case of break or break2 event
4564 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4565 * a timer instance provides a break input.
4566 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
4567 * @param TIMx Timer instance
4568 * @retval None
4569 */
4570 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
4571 {
4572 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4573 }
4574
4575 /**
4576 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
4577 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
4578 * software and is reset in case of break or break2 event.
4579 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4580 * a timer instance provides a break input.
4581 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
4582 * @param TIMx Timer instance
4583 * @retval None
4584 */
4585 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
4586 {
4587 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
4588 }
4589
4590 /**
4591 * @brief Indicates whether outputs are enabled.
4592 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4593 * a timer instance provides a break input.
4594 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
4595 * @param TIMx Timer instance
4596 * @retval State of bit (1 or 0).
4597 */
4598 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
4599 {
4600 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
4601 }
4602
4603 /**
4604 * @brief Enable the signals connected to the designated timer break input.
4605 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4606 * or not a timer instance allows for break input selection.
4607 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
4608 * AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
4609 * AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
4610 * AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
4611 * AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
4612 * AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
4613 * AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
4614 * AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
4615 * AF2 BK2NE LL_TIM_EnableBreakInputSource\n
4616 * AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
4617 * AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
4618 * AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
4619 * AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
4620 * AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
4621 * AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
4622 * AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
4623 * @param TIMx Timer instance
4624 * @param BreakInput This parameter can be one of the following values:
4625 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4626 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4627 * @param Source This parameter can be one of the following values:
4628 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4629 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4630 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4631 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4632 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4633 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4634 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4635 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4636 *
4637 * (*) Value not defined in all devices.
4638 * @retval None
4639 */
4640 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4641 {
4642 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4643 SET_BIT(*pReg, Source);
4644 }
4645
4646 /**
4647 * @brief Disable the signals connected to the designated timer break input.
4648 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4649 * or not a timer instance allows for break input selection.
4650 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
4651 * AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
4652 * AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
4653 * AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
4654 * AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
4655 * AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
4656 * AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
4657 * AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
4658 * AF2 BKINE LL_TIM_DisableBreakInputSource\n
4659 * AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n
4660 * AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n
4661 * AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n
4662 * AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n
4663 * AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n
4664 * AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n
4665 * AF2 BKCMP7E LL_TIM_DisableBreakInputSource
4666 * @param TIMx Timer instance
4667 * @param BreakInput This parameter can be one of the following values:
4668 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4669 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4670 * @param Source This parameter can be one of the following values:
4671 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4672 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4673 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4674 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4675 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4676 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
4677 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
4678 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
4679 *
4680 * (*) Value not defined in all devices.
4681 * @retval None
4682 */
4683 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
4684 {
4685 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4686 CLEAR_BIT(*pReg, Source);
4687 }
4688
4689 /**
4690 * @brief Set the polarity of the break signal for the timer break input.
4691 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
4692 * or not a timer instance allows for break input selection.
4693 * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
4694 * AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
4695 * AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
4696 * AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
4697 * AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
4698 * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
4699 * AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
4700 * AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
4701 * AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
4702 * AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity
4703 * @param TIMx Timer instance
4704 * @param BreakInput This parameter can be one of the following values:
4705 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
4706 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
4707 * @param Source This parameter can be one of the following values:
4708 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
4709 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
4710 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
4711 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
4712 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
4713 * @param Polarity This parameter can be one of the following values:
4714 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
4715 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
4716 * @retval None
4717 */
4718 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
4719 uint32_t Polarity)
4720 {
4721 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
4722 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
4723 }
4724 /**
4725 * @brief Enable asymmetrical deadtime.
4726 * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4727 * a timer instance provides asymmetrical deadtime.
4728 * @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
4729 * @param TIMx Timer instance
4730 * @retval None
4731 */
4732 __STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4733 {
4734 SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4735 }
4736
4737 /**
4738 * @brief Disable asymmetrical dead-time.
4739 * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4740 * a timer instance provides asymmetrical deadtime.
4741 * @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
4742 * @param TIMx Timer instance
4743 * @retval None
4744 */
4745 __STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4746 {
4747 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
4748 }
4749
4750 /**
4751 * @brief Indicates whether asymmetrical deadtime is activated.
4752 * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4753 * a timer instance provides asymmetrical deadtime.
4754 * @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
4755 * @param TIMx Timer instance
4756 * @retval State of bit (1 or 0).
4757 */
4758 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
4759 {
4760 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
4761 }
4762
4763 /**
4764 * @brief Set the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
4765 * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4766 * asymmetrical dead-time insertion feature is supported by a timer instance.
4767 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
4768 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4769 * (LOCK bits in TIMx_BDTR register).
4770 * @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
4771 * @param TIMx Timer instance
4772 * @param DeadTime between Min_Data=0 and Max_Data=255
4773 * @retval None
4774 */
4775 __STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
4776 {
4777 MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
4778 }
4779
4780 /**
4781 * @brief Get the falling egde dead-time delay (delay inserted between the falling edge of the OCxREF signal and the rising edge of OCxN signals).
4782 * @note Macro @ref IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
4783 * asymmetrical dead-time insertion feature is supported by a timer instance.
4784 * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
4785 * (LOCK bits in TIMx_BDTR register).
4786 * @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
4787 * @param TIMx Timer instance
4788 * @retval Returned value can be between Min_Data=0 and Max_Data=255:
4789 */
4790 __STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
4791 {
4792 return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
4793 }
4794
4795 /**
4796 * @brief Enable deadtime preload.
4797 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4798 * a timer instance provides deadtime preload.
4799 * @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
4800 * @param TIMx Timer instance
4801 * @retval None
4802 */
4803 __STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
4804 {
4805 SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4806 }
4807
4808 /**
4809 * @brief Disable dead-time preload.
4810 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4811 * a timer instance provides deadtime preload.
4812 * @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
4813 * @param TIMx Timer instance
4814 * @retval None
4815 */
4816 __STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
4817 {
4818 CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
4819 }
4820
4821 /**
4822 * @brief Indicates whether deadtime preload is activated.
4823 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
4824 * a timer instance provides deadtime preload.
4825 * @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
4826 * @param TIMx Timer instance
4827 * @retval State of bit (1 or 0).
4828 */
4829 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
4830 {
4831 return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
4832 }
4833
4834 /**
4835 * @}
4836 */
4837
4838 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
4839 * @{
4840 */
4841 /**
4842 * @brief Configures the timer DMA burst feature.
4843 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
4844 * not a timer instance supports the DMA burst mode.
4845 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
4846 * DCR DBA LL_TIM_ConfigDMABurst
4847 * @param TIMx Timer instance
4848 * @param DMABurstBaseAddress This parameter can be one of the following values:
4849 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
4850 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
4851 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
4852 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
4853 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
4854 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
4855 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
4856 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
4857 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
4858 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
4859 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
4860 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
4861 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
4862 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
4863 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
4864 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
4865 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
4866 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
4867 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
4868 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
4869 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
4870 * @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
4871 * @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
4872 * @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
4873 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
4874 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
4875 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
4876 * @param DMABurstLength This parameter can be one of the following values:
4877 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
4878 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
4879 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
4880 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
4881 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
4882 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
4883 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
4884 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
4885 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
4886 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
4887 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
4888 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
4889 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
4890 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
4891 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
4892 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
4893 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
4894 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
4895 * @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
4896 * @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
4897 * @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
4898 * @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
4899 * @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
4900 * @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
4901 * @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
4902 * @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
4903 * @retval None
4904 */
4905 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
4906 {
4907 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
4908 }
4909
4910 /**
4911 * @}
4912 */
4913
4914 /** @defgroup TIM_LL_EF_Encoder Encoder configuration
4915 * @{
4916 */
4917
4918 /**
4919 * @brief Enable encoder index.
4920 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4921 * a timer instance provides an index input.
4922 * @rmtoll ECR IE LL_TIM_EnableEncoderIndex
4923 * @param TIMx Timer instance
4924 * @retval None
4925 */
4926 __STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
4927 {
4928 SET_BIT(TIMx->ECR, TIM_ECR_IE);
4929 }
4930
4931 /**
4932 * @brief Disable encoder index.
4933 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4934 * a timer instance provides an index input.
4935 * @rmtoll ECR IE LL_TIM_DisableEncoderIndex
4936 * @param TIMx Timer instance
4937 * @retval None
4938 */
4939 __STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
4940 {
4941 CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
4942 }
4943
4944 /**
4945 * @brief Indicate whether encoder index is enabled.
4946 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4947 * a timer instance provides an index input.
4948 * @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
4949 * @param TIMx Timer instance
4950 * @retval State of bit (1 or 0).
4951 */
4952 __STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
4953 {
4954 return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
4955 }
4956
4957 /**
4958 * @brief Set index direction
4959 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4960 * a timer instance provides an index input.
4961 * @rmtoll ECR IDIR LL_TIM_SetIndexDirection
4962 * @param TIMx Timer instance
4963 * @param IndexDirection This parameter can be one of the following values:
4964 * @arg @ref LL_TIM_INDEX_UP_DOWN
4965 * @arg @ref LL_TIM_INDEX_UP
4966 * @arg @ref LL_TIM_INDEX_DOWN
4967 * @retval None
4968 */
4969 __STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
4970 {
4971 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
4972 }
4973
4974 /**
4975 * @brief Get actual index direction
4976 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4977 * a timer instance provides an index input.
4978 * @rmtoll ECR IDIR LL_TIM_GetIndexDirection
4979 * @param TIMx Timer instance
4980 * @retval Returned value can be one of the following values:
4981 * @arg @ref LL_TIM_INDEX_UP_DOWN
4982 * @arg @ref LL_TIM_INDEX_UP
4983 * @arg @ref LL_TIM_INDEX_DOWN
4984 */
4985 __STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
4986 {
4987 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
4988 }
4989
4990 /**
4991 * @brief Enable first index.
4992 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
4993 * a timer instance provides an index input.
4994 * @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
4995 * @param TIMx Timer instance
4996 * @retval None
4997 */
4998 __STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
4999 {
5000 SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
5001 }
5002
5003 /**
5004 * @brief Disable first index.
5005 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5006 * a timer instance provides an index input.
5007 * @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
5008 * @param TIMx Timer instance
5009 * @retval None
5010 */
5011 __STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
5012 {
5013 CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
5014 }
5015
5016 /**
5017 * @brief Indicates whether first index is enabled.
5018 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5019 * a timer instance provides an index input.
5020 * @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
5021 * @param TIMx Timer instance
5022 * @retval State of bit (1 or 0).
5023 */
5024 __STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
5025 {
5026 return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
5027 }
5028
5029 /**
5030 * @brief Set index positionning
5031 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5032 * a timer instance provides an index input.
5033 * @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
5034 * @param TIMx Timer instance
5035 * @param IndexPositionning This parameter can be one of the following values:
5036 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5037 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5038 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5039 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5040 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5041 * @arg @ref LL_TIM_INDEX_POSITION_UP
5042 * @retval None
5043 */
5044 __STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
5045 {
5046 MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
5047 }
5048
5049 /**
5050 * @brief Get actual index positionning
5051 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5052 * a timer instance provides an index input.
5053 * @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
5054 * @param TIMx Timer instance
5055 * @retval Returned value can be one of the following values:
5056 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
5057 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
5058 * @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
5059 * @arg @ref LL_TIM_INDEX_POSITION_UP_UP
5060 * @arg @ref LL_TIM_INDEX_POSITION_DOWN
5061 * @arg @ref LL_TIM_INDEX_POSITION_UP
5062 */
5063 __STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
5064 {
5065 return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
5066 }
5067
5068 /**
5069 * @brief Configure encoder index.
5070 * @note Macro @ref IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
5071 * a timer instance provides an index input.
5072 * @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
5073 * ECR FIDX LL_TIM_ConfigIDX\n
5074 * ECR IPOS LL_TIM_ConfigIDX
5075 * @param TIMx Timer instance
5076 * @param Configuration This parameter must be a combination of all the following values:
5077 * @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
5078 * @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
5079 * @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
5080 * @retval None
5081 */
5082 __STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
5083 {
5084 MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
5085 }
5086
5087 /**
5088 * @}
5089 */
5090
5091 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
5092 * @{
5093 */
5094 /**
5095 * @brief Remap TIM inputs (input channel, internal/external triggers).
5096 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
5097 * a some timer inputs can be remapped.
5098 * @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
5099 * TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
5100 * TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
5101 * TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
5102 * TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
5103 * TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
5104 * TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
5105 * TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
5106 * TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
5107 * TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
5108 * TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
5109 * TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
5110 * TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
5111 * TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
5112 * TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
5113 * TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
5114 * TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
5115 * TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
5116 * TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
5117 * TIM20_TISEL TI1SEL LL_TIM_SetRemap
5118 * @param TIMx Timer instance
5119 * @param Remap Remap param depends on the TIMx. Description available only
5120 * in CHM version of the User Manual (not in .pdf).
5121 * Otherwise see Reference Manual description of TISEL registers.
5122 *
5123 * Below description summarizes "Timer Instance" and "Remap" param combinations:
5124 *
5125 * TIM1: one of the following values
5126 *
5127 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
5128 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
5129 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
5130 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
5131 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
5132 *
5133 * TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5134 *
5135 * . . TI1_RMP can be one of the following values
5136 * @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
5137 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
5138 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
5139 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
5140 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
5141 * @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
5142 *
5143 * . . TI2_RMP can be one of the following values
5144 * @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
5145 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
5146 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
5147 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
5148 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
5149 * @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
5150 *
5151 * . . TI3_RMP can be one of the following values
5152 * @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
5153 * @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
5154 *
5155 * . . TI4_RMP can be one of the following values
5156 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
5157 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
5158 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
5159 *
5160 * TIM3: any combination of TI1_RMP and TI2_RMP where
5161 *
5162 * . . TI1_RMP can be one of the following values
5163 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
5164 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
5165 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
5166 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
5167 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
5168 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
5169 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
5170 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
5171 *
5172 * . . TI2_RMP can be one of the following values
5173 * @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
5174 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
5175 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
5176 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
5177 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
5178 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
5179 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
5180 * @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
5181 *
5182 * . . TI3_RMP can be one of the following values
5183 * @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
5184 * @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
5185 *
5186 * TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
5187 *
5188 * . . TI1_RMP can be one of the following values
5189 * @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
5190 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
5191 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
5192 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
5193 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
5194 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
5195 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
5196 * @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
5197 *
5198 * . . TI2_RMP can be one of the following values
5199 * @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
5200 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
5201 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
5202 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
5203 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
5204 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
5205 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
5206 * @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
5207 *
5208 * . . TI3_RMP can be one of the following values
5209 * @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
5210 * @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
5211 *
5212 * . . TI4_RMP can be one of the following values
5213 * @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
5214 * @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
5215 *
5216 * TIM5: any combination of TI1_RMP and TI2_RMP where (**)
5217 *
5218 * . . TI1_RMP can be one of the following values
5219 * @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
5220 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
5221 * @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
5222 * @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
5223 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
5224 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
5225 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
5226 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
5227 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
5228 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
5229 * @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
5230 *
5231 * . . TI2_RMP can be one of the following values
5232 * @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
5233 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
5234 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
5235 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
5236 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
5237 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
5238 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
5239 * @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
5240 *
5241 * TIM8: one of the following values
5242 *
5243 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
5244 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
5245 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
5246 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
5247 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
5248 *
5249 * TIM15: any combination of TI1_RMP and TI2_RMP where
5250 *
5251 * . . TI1_RMP can be one of the following values
5252 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
5253 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
5254 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
5255 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
5256 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
5257 * @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
5258 *
5259 * . . TI2_RMP can be one of the following values
5260 * @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
5261 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
5262 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
5263 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
5264 * @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
5265 *
5266 * TIM16: one of the following values
5267 *
5268 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
5269 * @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
5270 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
5271 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
5272 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
5273 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
5274 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
5275 *
5276 * TIM17: one of the following values
5277 *
5278 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
5279 * @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
5280 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
5281 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
5282 * @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
5283 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
5284 * @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
5285 *
5286 * TIM20: one of the following values (**)
5287 *
5288 * @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
5289 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
5290 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
5291 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
5292 * @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
5293 *
5294 * (*) Value not defined in all devices. \n
5295 * (**) Register not available in all devices.
5296 *
5297 *
5298 * @retval None
5299 */
5300 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
5301 {
5302 MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
5303 }
5304
5305 /**
5306 * @brief Enable request for HSE/32 clock used for TISEL remap.
5307 * @note Only TIM16 and TIM17 support HSE/32 remap
5308 * @rmtoll OR HSE32EN LL_TIM_EnableHSE32
5309 * @param TIMx Timer instance
5310 * @retval None
5311 */
5312 __STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
5313 {
5314 SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
5315 }
5316
5317 /**
5318 * @brief Disable request for HSE/32 clock used for TISEL remap.
5319 * @note Only TIM16 and TIM17 support HSE/32 remap
5320 * @rmtoll OR HSE32EN LL_TIM_DisableHSE32
5321 * @param TIMx Timer instance
5322 * @retval None
5323 */
5324 __STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
5325 {
5326 CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
5327 }
5328
5329 /**
5330 * @brief Indicate whether request for HSE/32 clock is enabled.
5331 * @note Only TIM16 and TIM17 support HSE/32 remap
5332 * @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
5333 * @param TIMx Timer instance
5334 * @retval State of bit (1 or 0).
5335 */
5336 __STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
5337 {
5338 return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
5339 }
5340 /**
5341 * @}
5342 */
5343
5344 /**
5345 * @}
5346 */
5347
5348 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
5349 * @{
5350 */
5351 /**
5352 * @brief Set the OCREF clear input source
5353 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
5354 * @note This function can only be used in Output compare and PWM modes.
5355 * @note Macro @ref IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
5356 * or not a timer instance can configure OCREF clear input source.
5357 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
5358 * @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
5359 * @param TIMx Timer instance
5360 * @param OCRefClearInputSource This parameter can be one of the following values:
5361 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
5362 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
5363 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
5364 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
5365 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
5366 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
5367 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
5368 * @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
5369 *
5370 * (*) Value not defined in all devices. \n
5371 * @retval None
5372 */
5373 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
5374 {
5375 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
5376 ((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
5377 MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
5378 }
5379 /**
5380 * @}
5381 */
5382
5383 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
5384 * @{
5385 */
5386 /**
5387 * @brief Clear the update interrupt flag (UIF).
5388 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
5389 * @param TIMx Timer instance
5390 * @retval None
5391 */
5392 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
5393 {
5394 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
5395 }
5396
5397 /**
5398 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
5399 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
5400 * @param TIMx Timer instance
5401 * @retval State of bit (1 or 0).
5402 */
5403 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
5404 {
5405 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
5406 }
5407
5408 /**
5409 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
5410 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
5411 * @param TIMx Timer instance
5412 * @retval None
5413 */
5414 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
5415 {
5416 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
5417 }
5418
5419 /**
5420 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
5421 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
5422 * @param TIMx Timer instance
5423 * @retval State of bit (1 or 0).
5424 */
5425 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
5426 {
5427 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
5428 }
5429
5430 /**
5431 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
5432 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
5433 * @param TIMx Timer instance
5434 * @retval None
5435 */
5436 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
5437 {
5438 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
5439 }
5440
5441 /**
5442 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
5443 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
5444 * @param TIMx Timer instance
5445 * @retval State of bit (1 or 0).
5446 */
5447 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
5448 {
5449 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
5450 }
5451
5452 /**
5453 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
5454 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
5455 * @param TIMx Timer instance
5456 * @retval None
5457 */
5458 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
5459 {
5460 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
5461 }
5462
5463 /**
5464 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
5465 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
5466 * @param TIMx Timer instance
5467 * @retval State of bit (1 or 0).
5468 */
5469 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
5470 {
5471 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
5472 }
5473
5474 /**
5475 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
5476 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
5477 * @param TIMx Timer instance
5478 * @retval None
5479 */
5480 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
5481 {
5482 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
5483 }
5484
5485 /**
5486 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
5487 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
5488 * @param TIMx Timer instance
5489 * @retval State of bit (1 or 0).
5490 */
5491 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
5492 {
5493 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
5494 }
5495
5496 /**
5497 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
5498 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
5499 * @param TIMx Timer instance
5500 * @retval None
5501 */
5502 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
5503 {
5504 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
5505 }
5506
5507 /**
5508 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
5509 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
5510 * @param TIMx Timer instance
5511 * @retval State of bit (1 or 0).
5512 */
5513 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
5514 {
5515 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
5516 }
5517
5518 /**
5519 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
5520 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
5521 * @param TIMx Timer instance
5522 * @retval None
5523 */
5524 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
5525 {
5526 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
5527 }
5528
5529 /**
5530 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
5531 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
5532 * @param TIMx Timer instance
5533 * @retval State of bit (1 or 0).
5534 */
5535 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
5536 {
5537 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
5538 }
5539
5540 /**
5541 * @brief Clear the commutation interrupt flag (COMIF).
5542 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
5543 * @param TIMx Timer instance
5544 * @retval None
5545 */
5546 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
5547 {
5548 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
5549 }
5550
5551 /**
5552 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
5553 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
5554 * @param TIMx Timer instance
5555 * @retval State of bit (1 or 0).
5556 */
5557 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
5558 {
5559 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
5560 }
5561
5562 /**
5563 * @brief Clear the trigger interrupt flag (TIF).
5564 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
5565 * @param TIMx Timer instance
5566 * @retval None
5567 */
5568 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
5569 {
5570 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
5571 }
5572
5573 /**
5574 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
5575 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
5576 * @param TIMx Timer instance
5577 * @retval State of bit (1 or 0).
5578 */
5579 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
5580 {
5581 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
5582 }
5583
5584 /**
5585 * @brief Clear the break interrupt flag (BIF).
5586 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
5587 * @param TIMx Timer instance
5588 * @retval None
5589 */
5590 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
5591 {
5592 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
5593 }
5594
5595 /**
5596 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
5597 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
5598 * @param TIMx Timer instance
5599 * @retval State of bit (1 or 0).
5600 */
5601 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
5602 {
5603 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
5604 }
5605
5606 /**
5607 * @brief Clear the break 2 interrupt flag (B2IF).
5608 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
5609 * @param TIMx Timer instance
5610 * @retval None
5611 */
5612 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
5613 {
5614 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
5615 }
5616
5617 /**
5618 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
5619 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
5620 * @param TIMx Timer instance
5621 * @retval State of bit (1 or 0).
5622 */
5623 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
5624 {
5625 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
5626 }
5627
5628 /**
5629 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
5630 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
5631 * @param TIMx Timer instance
5632 * @retval None
5633 */
5634 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
5635 {
5636 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
5637 }
5638
5639 /**
5640 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
5641 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
5642 * @param TIMx Timer instance
5643 * @retval State of bit (1 or 0).
5644 */
5645 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
5646 {
5647 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
5648 }
5649
5650 /**
5651 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
5652 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
5653 * @param TIMx Timer instance
5654 * @retval None
5655 */
5656 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
5657 {
5658 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
5659 }
5660
5661 /**
5662 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
5663 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
5664 * @param TIMx Timer instance
5665 * @retval State of bit (1 or 0).
5666 */
5667 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
5668 {
5669 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
5670 }
5671
5672 /**
5673 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
5674 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
5675 * @param TIMx Timer instance
5676 * @retval None
5677 */
5678 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
5679 {
5680 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
5681 }
5682
5683 /**
5684 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
5685 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
5686 * @param TIMx Timer instance
5687 * @retval State of bit (1 or 0).
5688 */
5689 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
5690 {
5691 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
5692 }
5693
5694 /**
5695 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
5696 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
5697 * @param TIMx Timer instance
5698 * @retval None
5699 */
5700 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
5701 {
5702 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
5703 }
5704
5705 /**
5706 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
5707 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
5708 * @param TIMx Timer instance
5709 * @retval State of bit (1 or 0).
5710 */
5711 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
5712 {
5713 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
5714 }
5715
5716 /**
5717 * @brief Clear the system break interrupt flag (SBIF).
5718 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
5719 * @param TIMx Timer instance
5720 * @retval None
5721 */
5722 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
5723 {
5724 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
5725 }
5726
5727 /**
5728 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
5729 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
5730 * @param TIMx Timer instance
5731 * @retval State of bit (1 or 0).
5732 */
5733 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
5734 {
5735 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
5736 }
5737
5738 /**
5739 * @brief Clear the transition error interrupt flag (TERRF).
5740 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5741 * a timer instance provides encoder error management.
5742 * @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
5743 * @param TIMx Timer instance
5744 * @retval None
5745 */
5746 __STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
5747 {
5748 WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
5749 }
5750
5751 /**
5752 * @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
5753 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5754 * a timer instance provides encoder error management.
5755 * @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
5756 * @param TIMx Timer instance
5757 * @retval State of bit (1 or 0).
5758 */
5759 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
5760 {
5761 return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
5762 }
5763
5764 /**
5765 * @brief Clear the index error interrupt flag (IERRF).
5766 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5767 * a timer instance provides encoder error management.
5768 * @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
5769 * @param TIMx Timer instance
5770 * @retval None
5771 */
5772 __STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
5773 {
5774 WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
5775 }
5776
5777 /**
5778 * @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
5779 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
5780 * a timer instance provides encoder error management.
5781 * @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
5782 * @param TIMx Timer instance
5783 * @retval State of bit (1 or 0).
5784 */
5785 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
5786 {
5787 return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
5788 }
5789
5790 /**
5791 * @brief Clear the direction change interrupt flag (DIRF).
5792 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5793 * a timer instance provides encoder interrupt management.
5794 * @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
5795 * @param TIMx Timer instance
5796 * @retval None
5797 */
5798 __STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
5799 {
5800 WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
5801 }
5802
5803 /**
5804 * @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
5805 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5806 * a timer instance provides encoder interrupt management.
5807 * @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
5808 * @param TIMx Timer instance
5809 * @retval State of bit (1 or 0).
5810 */
5811 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
5812 {
5813 return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
5814 }
5815
5816 /**
5817 * @brief Clear the index interrupt flag (IDXF).
5818 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5819 * a timer instance provides encoder interrupt management.
5820 * @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
5821 * @param TIMx Timer instance
5822 * @retval None
5823 */
5824 __STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
5825 {
5826 WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
5827 }
5828
5829 /**
5830 * @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
5831 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
5832 * a timer instance provides encoder interrupt management.
5833 * @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
5834 * @param TIMx Timer instance
5835 * @retval State of bit (1 or 0).
5836 */
5837 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
5838 {
5839 return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
5840 }
5841 /**
5842 * @}
5843 */
5844
5845 /** @defgroup TIM_LL_EF_IT_Management IT-Management
5846 * @{
5847 */
5848 /**
5849 * @brief Enable update interrupt (UIE).
5850 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
5851 * @param TIMx Timer instance
5852 * @retval None
5853 */
5854 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
5855 {
5856 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
5857 }
5858
5859 /**
5860 * @brief Disable update interrupt (UIE).
5861 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
5862 * @param TIMx Timer instance
5863 * @retval None
5864 */
5865 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
5866 {
5867 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
5868 }
5869
5870 /**
5871 * @brief Indicates whether the update interrupt (UIE) is enabled.
5872 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
5873 * @param TIMx Timer instance
5874 * @retval State of bit (1 or 0).
5875 */
5876 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
5877 {
5878 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
5879 }
5880
5881 /**
5882 * @brief Enable capture/compare 1 interrupt (CC1IE).
5883 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
5884 * @param TIMx Timer instance
5885 * @retval None
5886 */
5887 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
5888 {
5889 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5890 }
5891
5892 /**
5893 * @brief Disable capture/compare 1 interrupt (CC1IE).
5894 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
5895 * @param TIMx Timer instance
5896 * @retval None
5897 */
5898 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
5899 {
5900 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
5901 }
5902
5903 /**
5904 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
5905 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
5906 * @param TIMx Timer instance
5907 * @retval State of bit (1 or 0).
5908 */
5909 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
5910 {
5911 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
5912 }
5913
5914 /**
5915 * @brief Enable capture/compare 2 interrupt (CC2IE).
5916 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
5917 * @param TIMx Timer instance
5918 * @retval None
5919 */
5920 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
5921 {
5922 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5923 }
5924
5925 /**
5926 * @brief Disable capture/compare 2 interrupt (CC2IE).
5927 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
5928 * @param TIMx Timer instance
5929 * @retval None
5930 */
5931 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
5932 {
5933 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
5934 }
5935
5936 /**
5937 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
5938 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
5939 * @param TIMx Timer instance
5940 * @retval State of bit (1 or 0).
5941 */
5942 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
5943 {
5944 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
5945 }
5946
5947 /**
5948 * @brief Enable capture/compare 3 interrupt (CC3IE).
5949 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
5950 * @param TIMx Timer instance
5951 * @retval None
5952 */
5953 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
5954 {
5955 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5956 }
5957
5958 /**
5959 * @brief Disable capture/compare 3 interrupt (CC3IE).
5960 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
5961 * @param TIMx Timer instance
5962 * @retval None
5963 */
5964 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
5965 {
5966 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
5967 }
5968
5969 /**
5970 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
5971 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
5972 * @param TIMx Timer instance
5973 * @retval State of bit (1 or 0).
5974 */
5975 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
5976 {
5977 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
5978 }
5979
5980 /**
5981 * @brief Enable capture/compare 4 interrupt (CC4IE).
5982 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
5983 * @param TIMx Timer instance
5984 * @retval None
5985 */
5986 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
5987 {
5988 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
5989 }
5990
5991 /**
5992 * @brief Disable capture/compare 4 interrupt (CC4IE).
5993 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
5994 * @param TIMx Timer instance
5995 * @retval None
5996 */
5997 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
5998 {
5999 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
6000 }
6001
6002 /**
6003 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
6004 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
6005 * @param TIMx Timer instance
6006 * @retval State of bit (1 or 0).
6007 */
6008 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
6009 {
6010 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
6011 }
6012
6013 /**
6014 * @brief Enable commutation interrupt (COMIE).
6015 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
6016 * @param TIMx Timer instance
6017 * @retval None
6018 */
6019 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
6020 {
6021 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
6022 }
6023
6024 /**
6025 * @brief Disable commutation interrupt (COMIE).
6026 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
6027 * @param TIMx Timer instance
6028 * @retval None
6029 */
6030 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
6031 {
6032 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
6033 }
6034
6035 /**
6036 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
6037 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
6038 * @param TIMx Timer instance
6039 * @retval State of bit (1 or 0).
6040 */
6041 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
6042 {
6043 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
6044 }
6045
6046 /**
6047 * @brief Enable trigger interrupt (TIE).
6048 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
6049 * @param TIMx Timer instance
6050 * @retval None
6051 */
6052 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
6053 {
6054 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
6055 }
6056
6057 /**
6058 * @brief Disable trigger interrupt (TIE).
6059 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
6060 * @param TIMx Timer instance
6061 * @retval None
6062 */
6063 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
6064 {
6065 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
6066 }
6067
6068 /**
6069 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
6070 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
6071 * @param TIMx Timer instance
6072 * @retval State of bit (1 or 0).
6073 */
6074 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
6075 {
6076 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
6077 }
6078
6079 /**
6080 * @brief Enable break interrupt (BIE).
6081 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
6082 * @param TIMx Timer instance
6083 * @retval None
6084 */
6085 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
6086 {
6087 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
6088 }
6089
6090 /**
6091 * @brief Disable break interrupt (BIE).
6092 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
6093 * @param TIMx Timer instance
6094 * @retval None
6095 */
6096 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
6097 {
6098 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
6099 }
6100
6101 /**
6102 * @brief Indicates whether the break interrupt (BIE) is enabled.
6103 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
6104 * @param TIMx Timer instance
6105 * @retval State of bit (1 or 0).
6106 */
6107 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
6108 {
6109 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
6110 }
6111
6112 /**
6113 * @brief Enable transition error interrupt (TERRIE).
6114 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6115 * a timer instance provides encoder error management.
6116 * @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
6117 * @param TIMx Timer instance
6118 * @retval None
6119 */
6120 __STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
6121 {
6122 SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6123 }
6124
6125 /**
6126 * @brief Disable transition error interrupt (TERRIE).
6127 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6128 * a timer instance provides encoder error management.
6129 * @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
6130 * @param TIMx Timer instance
6131 * @retval None
6132 */
6133 __STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
6134 {
6135 CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
6136 }
6137
6138 /**
6139 * @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
6140 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6141 * a timer instance provides encoder error management.
6142 * @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
6143 * @param TIMx Timer instance
6144 * @retval State of bit (1 or 0).
6145 */
6146 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
6147 {
6148 return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
6149 }
6150
6151 /**
6152 * @brief Enable index error interrupt (IERRIE).
6153 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6154 * a timer instance provides encoder error management.
6155 * @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
6156 * @param TIMx Timer instance
6157 * @retval None
6158 */
6159 __STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
6160 {
6161 SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6162 }
6163
6164 /**
6165 * @brief Disable index error interrupt (IERRIE).
6166 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6167 * a timer instance provides encoder error management.
6168 * @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
6169 * @param TIMx Timer instance
6170 * @retval None
6171 */
6172 __STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
6173 {
6174 CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
6175 }
6176
6177 /**
6178 * @brief Indicates whether the index error interrupt (IERRIE) is enabled.
6179 * @note Macro @ref IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
6180 * a timer instance provides encoder error management.
6181 * @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
6182 * @param TIMx Timer instance
6183 * @retval State of bit (1 or 0).
6184 */
6185 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
6186 {
6187 return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
6188 }
6189
6190 /**
6191 * @brief Enable direction change interrupt (DIRIE).
6192 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6193 * a timer instance provides encoder interrupt management.
6194 * @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
6195 * @param TIMx Timer instance
6196 * @retval None
6197 */
6198 __STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
6199 {
6200 SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6201 }
6202
6203 /**
6204 * @brief Disable direction change interrupt (DIRIE).
6205 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6206 * a timer instance provides encoder interrupt management.
6207 * @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
6208 * @param TIMx Timer instance
6209 * @retval None
6210 */
6211 __STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
6212 {
6213 CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
6214 }
6215
6216 /**
6217 * @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
6218 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6219 * a timer instance provides encoder interrupt management.
6220 * @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
6221 * @param TIMx Timer instance
6222 * @retval State of bit (1 or 0).
6223 */
6224 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
6225 {
6226 return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
6227 }
6228
6229 /**
6230 * @brief Enable index interrupt (IDXIE).
6231 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6232 * a timer instance provides encoder interrupt management.
6233 * @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
6234 * @param TIMx Timer instance
6235 * @retval None
6236 */
6237 __STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
6238 {
6239 SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6240 }
6241
6242 /**
6243 * @brief Disable index interrupt (IDXIE).
6244 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6245 * a timer instance provides encoder interrupt management.
6246 * @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
6247 * @param TIMx Timer instance
6248 * @retval None
6249 */
6250 __STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
6251 {
6252 CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
6253 }
6254
6255 /**
6256 * @brief Indicates whether the index interrupt (IDXIE) is enabled.
6257 * @note Macro @ref IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
6258 * a timer instance provides encoder interrupt management.
6259 * @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
6260 * @param TIMx Timer instance
6261 * @retval State of bit (1 or 0).
6262 */
6263 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
6264 {
6265 return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
6266 }
6267
6268 /**
6269 * @}
6270 */
6271
6272 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
6273 * @{
6274 */
6275 /**
6276 * @brief Enable update DMA request (UDE).
6277 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
6278 * @param TIMx Timer instance
6279 * @retval None
6280 */
6281 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6282 {
6283 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
6284 }
6285
6286 /**
6287 * @brief Disable update DMA request (UDE).
6288 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
6289 * @param TIMx Timer instance
6290 * @retval None
6291 */
6292 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
6293 {
6294 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
6295 }
6296
6297 /**
6298 * @brief Indicates whether the update DMA request (UDE) is enabled.
6299 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
6300 * @param TIMx Timer instance
6301 * @retval State of bit (1 or 0).
6302 */
6303 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
6304 {
6305 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
6306 }
6307
6308 /**
6309 * @brief Enable capture/compare 1 DMA request (CC1DE).
6310 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
6311 * @param TIMx Timer instance
6312 * @retval None
6313 */
6314 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
6315 {
6316 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6317 }
6318
6319 /**
6320 * @brief Disable capture/compare 1 DMA request (CC1DE).
6321 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
6322 * @param TIMx Timer instance
6323 * @retval None
6324 */
6325 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
6326 {
6327 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
6328 }
6329
6330 /**
6331 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
6332 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
6333 * @param TIMx Timer instance
6334 * @retval State of bit (1 or 0).
6335 */
6336 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
6337 {
6338 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
6339 }
6340
6341 /**
6342 * @brief Enable capture/compare 2 DMA request (CC2DE).
6343 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
6344 * @param TIMx Timer instance
6345 * @retval None
6346 */
6347 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
6348 {
6349 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6350 }
6351
6352 /**
6353 * @brief Disable capture/compare 2 DMA request (CC2DE).
6354 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
6355 * @param TIMx Timer instance
6356 * @retval None
6357 */
6358 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
6359 {
6360 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
6361 }
6362
6363 /**
6364 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
6365 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
6366 * @param TIMx Timer instance
6367 * @retval State of bit (1 or 0).
6368 */
6369 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
6370 {
6371 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
6372 }
6373
6374 /**
6375 * @brief Enable capture/compare 3 DMA request (CC3DE).
6376 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
6377 * @param TIMx Timer instance
6378 * @retval None
6379 */
6380 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
6381 {
6382 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6383 }
6384
6385 /**
6386 * @brief Disable capture/compare 3 DMA request (CC3DE).
6387 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
6388 * @param TIMx Timer instance
6389 * @retval None
6390 */
6391 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
6392 {
6393 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
6394 }
6395
6396 /**
6397 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
6398 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
6399 * @param TIMx Timer instance
6400 * @retval State of bit (1 or 0).
6401 */
6402 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
6403 {
6404 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
6405 }
6406
6407 /**
6408 * @brief Enable capture/compare 4 DMA request (CC4DE).
6409 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
6410 * @param TIMx Timer instance
6411 * @retval None
6412 */
6413 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
6414 {
6415 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6416 }
6417
6418 /**
6419 * @brief Disable capture/compare 4 DMA request (CC4DE).
6420 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
6421 * @param TIMx Timer instance
6422 * @retval None
6423 */
6424 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
6425 {
6426 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
6427 }
6428
6429 /**
6430 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
6431 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
6432 * @param TIMx Timer instance
6433 * @retval State of bit (1 or 0).
6434 */
6435 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
6436 {
6437 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
6438 }
6439
6440 /**
6441 * @brief Enable commutation DMA request (COMDE).
6442 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
6443 * @param TIMx Timer instance
6444 * @retval None
6445 */
6446 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
6447 {
6448 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
6449 }
6450
6451 /**
6452 * @brief Disable commutation DMA request (COMDE).
6453 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
6454 * @param TIMx Timer instance
6455 * @retval None
6456 */
6457 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
6458 {
6459 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
6460 }
6461
6462 /**
6463 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
6464 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
6465 * @param TIMx Timer instance
6466 * @retval State of bit (1 or 0).
6467 */
6468 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
6469 {
6470 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
6471 }
6472
6473 /**
6474 * @brief Enable trigger interrupt (TDE).
6475 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
6476 * @param TIMx Timer instance
6477 * @retval None
6478 */
6479 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
6480 {
6481 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
6482 }
6483
6484 /**
6485 * @brief Disable trigger interrupt (TDE).
6486 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
6487 * @param TIMx Timer instance
6488 * @retval None
6489 */
6490 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
6491 {
6492 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
6493 }
6494
6495 /**
6496 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
6497 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
6498 * @param TIMx Timer instance
6499 * @retval State of bit (1 or 0).
6500 */
6501 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
6502 {
6503 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
6504 }
6505
6506 /**
6507 * @}
6508 */
6509
6510 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
6511 * @{
6512 */
6513 /**
6514 * @brief Generate an update event.
6515 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
6516 * @param TIMx Timer instance
6517 * @retval None
6518 */
6519 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
6520 {
6521 SET_BIT(TIMx->EGR, TIM_EGR_UG);
6522 }
6523
6524 /**
6525 * @brief Generate Capture/Compare 1 event.
6526 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
6527 * @param TIMx Timer instance
6528 * @retval None
6529 */
6530 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
6531 {
6532 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
6533 }
6534
6535 /**
6536 * @brief Generate Capture/Compare 2 event.
6537 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
6538 * @param TIMx Timer instance
6539 * @retval None
6540 */
6541 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
6542 {
6543 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
6544 }
6545
6546 /**
6547 * @brief Generate Capture/Compare 3 event.
6548 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
6549 * @param TIMx Timer instance
6550 * @retval None
6551 */
6552 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
6553 {
6554 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
6555 }
6556
6557 /**
6558 * @brief Generate Capture/Compare 4 event.
6559 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
6560 * @param TIMx Timer instance
6561 * @retval None
6562 */
6563 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
6564 {
6565 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
6566 }
6567
6568 /**
6569 * @brief Generate commutation event.
6570 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
6571 * @param TIMx Timer instance
6572 * @retval None
6573 */
6574 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
6575 {
6576 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
6577 }
6578
6579 /**
6580 * @brief Generate trigger event.
6581 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
6582 * @param TIMx Timer instance
6583 * @retval None
6584 */
6585 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
6586 {
6587 SET_BIT(TIMx->EGR, TIM_EGR_TG);
6588 }
6589
6590 /**
6591 * @brief Generate break event.
6592 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
6593 * @param TIMx Timer instance
6594 * @retval None
6595 */
6596 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
6597 {
6598 SET_BIT(TIMx->EGR, TIM_EGR_BG);
6599 }
6600
6601 /**
6602 * @brief Generate break 2 event.
6603 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
6604 * @param TIMx Timer instance
6605 * @retval None
6606 */
6607 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
6608 {
6609 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
6610 }
6611
6612 /**
6613 * @}
6614 */
6615
6616 #if defined(USE_FULL_LL_DRIVER)
6617 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
6618 * @{
6619 */
6620
6621 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
6622 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
6623 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
6624 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6625 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
6626 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
6627 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
6628 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6629 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
6630 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6631 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
6632 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6633 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
6634 /**
6635 * @}
6636 */
6637 #endif /* USE_FULL_LL_DRIVER */
6638
6639 /**
6640 * @}
6641 */
6642
6643 /**
6644 * @}
6645 */
6646
6647 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
6648
6649 /**
6650 * @}
6651 */
6652
6653 #ifdef __cplusplus
6654 }
6655 #endif
6656
6657 #endif /* __STM32G4xx_LL_TIM_H */
6658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/