?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_ucpd.h
blob7c5eecc1b263f9d710ba19c4eebbc90574484438
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_ucpd.h
4 * @author MCD Application Team
5 * @brief Header file of UCPD LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32G4xx_LL_UCPD_H
22 #define STM32G4xx_LL_UCPD_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (UCPD1)
36
37 /** @defgroup UCPD_LL UCPD
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44
45 /* Exported types ------------------------------------------------------------*/
46 #if defined(USE_FULL_LL_DRIVER)
47 /** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
48 * @{
49 */
50
51 /**
52 * @brief UCPD Init structures definition
53 */
54 typedef struct
55 {
56 uint32_t psc_ucpdclk; /*!< Specifies the prescaler for the ucpd clock.
57 This parameter can be a value of @ref UCPD_LL_EC_PSC.
58 This feature can be modified afterwards using unitary function @ref LL_UCPD_SetPSCClk().*/
59
60 uint32_t transwin; /*!< Specifies the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) to achieve a legal
61 tTransitionWindow (set according to peripheral clock to define an interval of between 12 and 20 us).
62 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
63 This value can be modified afterwards using unitary function @ref LL_UCPD_SetTransWin().*/
64
65 uint32_t IfrGap; /*!< Specifies the definition of the clock divider (minus 1) in order to generate tInterframeGap
66 from the peripheral clock.
67 This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
68 This feature can be modified afterwards using unitary function @ref LL_UCPD_SetIfrGap().*/
69
70 uint32_t HbitClockDiv; /*!< Specifies the number of cycles (minus one) at UCPD peripheral for a half bit clock e.g. program 3
71 for a bit clock that takes 8 cycles of the peripheral clock "UCPD1_CLK"..
72 This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
73 This feature can be modified afterwards using unitary function @ref LL_UCPD_SetHbitClockDiv().*/
74
75 } LL_UCPD_InitTypeDef;
76
77 /**
78 * @}
79 */
80 #endif /* USE_FULL_LL_DRIVER */
81
82 /* Exported constants --------------------------------------------------------*/
83 /** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
84 * @{
85 */
86
87 /** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
88 * @brief Flags defines which can be used with LL_ucpd_ReadReg function
89 * @{
90 */
91 #define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
92 #define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
93 #define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
94 #define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
95 #define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
96 #define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
97 #define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
98 #define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
99 #define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
100 #define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
101 #define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
102 #define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
103 #define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
104 #define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
105 #define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
106 #define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
107 #define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
108 #define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
109
110 /**
111 * @}
112 */
113
114 /** @defgroup UCPD_LL_EC_IT IT Defines
115 * @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
116 * @{
117 */
118 #define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
119 #define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
120 #define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
121 #define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
122 #define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
123 #define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
124 #define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
125 #define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
126 #define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
127 #define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
128 #define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
129 #define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGEND /*!< Enable Rx message received */
130 #define LL_UCPD_IMR_RXERR UCPD_IMR_RXMSGENDIE /*!< Enable Rx error */
131 #define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
132 #define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
133 #define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
134 /**
135 * @}
136 */
137
138 /** @defgroup UCPD_LL_EC_ORDERSET orderset value
139 * @brief definition of the usual orderset
140 * @{
141 */
142 #define LL_UCPD_SYNC1 0x18u
143 #define LL_UCPD_SYNC2 0x11u
144 #define LL_UCPD_SYNC3 0x06u
145 #define LL_UCPD_RST1 0x07u
146 #define LL_UCPD_RST2 0x19u
147 #define LL_UCPD_EOP 0x0Du
148
149 #define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u))
150 #define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u))
151 #define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u))
152 #define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u ))
153 #define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u))
154 #define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u))
155 #define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u))
156 /**
157 * @}
158 */
159
160 /** @defgroup UCPD_LL_EC_MODE Role Mode
161 * @{
162 */
163 #define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
164 #define LL_UCPD_ROLE_SRC 0x0U
165 /**
166 * @}
167 */
168
169 /** @defgroup UCPD_LL_EC_RESISTOR resistor value
170 * @{
171 */
172 #define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
173 #define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
174 #define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
175 #define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
176 /**
177 * @}
178 */
179
180 /** @defgroup UCPD_LL_EC_CFG1_ORDERSET orderset configuration
181 * @{
182 */
183 #define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0
184 #define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1
185 #define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2
186 #define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3
187 #define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4
188 #define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5
189 #define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6
190 #define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7
191 #define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8
192 /**
193 * @}
194 */
195
196 /** @defgroup UCPD_LL_EC_CCxEVT ccxevt
197 * @{
198 */
199 #define LL_UCPD_SNK_CC1_VOPEN 0x00u
200 #define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0
201 #define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1
202 #define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1)
203
204 #define LL_UCPD_SNK_CC2_VOPEN 0x00u
205 #define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0
206 #define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1
207 #define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1)
208
209 #define LL_UCPD_SRC_CC1_VRA 0x0U
210 #define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0
211 #define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1
212
213 #define LL_UCPD_SRC_CC2_VRA 0x0U
214 #define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0
215 #define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1
216 /**
217 * @}
218 */
219
220 /** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
221 * @{
222 */
223 #define LL_UCPD_PSC_DIV1 0x0u
224 #define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0
225 #define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1
226 #define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0)
227 #define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2
228 /**
229 * @}
230 */
231
232 /** @defgroup UCPD_LL_EC_CCENABLE cc pin enable
233 * @{
234 */
235 #define LL_UCPD_CCENABLE_NONE 0x0U
236 #define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0
237 #define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1
238 #define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1)
239 /**
240 * @}
241 */
242
243 /** @defgroup UCPD_LL_EC_CCPIN cc pin selection
244 * @{
245 */
246 #define LL_UCPD_CCPIN_CC1 0x0U
247 #define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL
248 /**
249 * @}
250 */
251
252 /** @defgroup UCPD_LL_EC_RXMODE rx mode
253 * @{
254 */
255 #define LL_UCPD_RXMODE_NORMAL 0x0U
256 #define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE
257 /**
258 * @}
259 */
260
261 /** @defgroup UCPD_LL_EC_TXMODE tx mode
262 * @{
263 */
264 #define LL_UCPD_TXMODE_NORMAL 0x0U
265 #define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0
266 #define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1
267 /**
268 * @}
269 */
270
271 /** @defgroup UCPD_LL_EC_RXORDSET rx orderset
272 * @{
273 */
274 #define LL_UCPD_RXORDSET_SOP 0x0U
275 #define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0
276 #define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1
277 #define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1)
278 #define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2
279 #define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0)
280 #define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1)
281 #define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0)
282 /**
283 * @}
284 */
285
286 /**
287 * @}
288 */
289
290 /* Exported macro ------------------------------------------------------------*/
291 /** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
292 * @{
293 */
294
295 /** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
296 * @{
297 */
298
299 /**
300 * @brief Write a value in UCPD register
301 * @param __INSTANCE__ UCPD Instance
302 * @param __REG__ Register to be written
303 * @param __VALUE__ Value to be written in the register
304 * @retval None
305 */
306 #define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
307
308 /**
309 * @brief Read a value in UCPD register
310 * @param __INSTANCE__ UCPD Instance
311 * @param __REG__ Register to be read
312 * @retval Register value
313 */
314 #define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
315 /**
316 * @}
317 */
318
319 /**
320 * @}
321 */
322
323 /* Exported functions --------------------------------------------------------*/
324 /** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
325 * @{
326 */
327
328 /** @defgroup UCPD_LL_EF_Configuration Configuration
329 * @{
330 */
331
332 /** @defgroup UCPD_LL_EF_CFG1 CFG1 register
333 * @{
334 */
335 /**
336 * @brief Enable UCPD peripheral
337 * @rmtoll CFG1 UCPDEN LL_UCPD_Enable
338 * @param UCPDx UCPD Instance
339 * @retval None
340 */
341 __STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
342 {
343 SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
344 }
345
346 /**
347 * @brief Disable UCPD peripheral
348 * @note When disabling the UCPD, follow the procedure described in the Reference Manual.
349 * @rmtoll CFG1 UCPDEN LL_UCPD_Disable
350 * @param UCPDx UCPD Instance
351 * @retval None
352 */
353 __STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
354 {
355 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
356 }
357
358 /**
359 * @brief Check if UCPD peripheral is enabled
360 * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
361 * @param UCPDx UCPD Instance
362 * @retval State of bit (1 or 0).
363 */
364 __STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const * const UCPDx)
365 {
366 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
367 }
368
369 /**
370 * @brief Set the receiver ordered set detection enable
371 * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
372 * @param UCPDx UCPD Instance
373 * @param OrderSet This parameter can be combination of the following values:
374 * @arg @ref LL_UCPD_ORDERSET_SOP
375 * @arg @ref LL_UCPD_ORDERSET_SOP1
376 * @arg @ref LL_UCPD_ORDERSET_SOP2
377 * @arg @ref LL_UCPD_ORDERSET_HARDRST
378 * @arg @ref LL_UCPD_ORDERSET_CABLERST
379 * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
380 * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
381 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
382 * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
383 * @retval None
384 */
385 __STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
386 {
387 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
388 }
389
390 /**
391 * @brief Set the prescaler for ucpd clock
392 * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
393 * @param UCPDx UCPD Instance
394 * @param Psc This parameter can be one of the following values:
395 * @arg @ref LL_UCPD_PSC_DIV1
396 * @arg @ref LL_UCPD_PSC_DIV2
397 * @arg @ref LL_UCPD_PSC_DIV4
398 * @arg @ref LL_UCPD_PSC_DIV8
399 * @arg @ref LL_UCPD_PSC_DIV16
400 * @retval None
401 */
402 __STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
403 {
404 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
405 }
406
407 /**
408 * @brief Set the number of cycles (minus 1) of the half bit clock
409 * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
410 * @param UCPDx UCPD Instance
411 * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
412 * @retval None
413 */
414 __STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
415 {
416 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
417 }
418
419 /**
420 * @brief Set the clock divider value to generate an interframe gap
421 * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
422 * @param UCPDx UCPD Instance
423 * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
424 * @retval None
425 */
426 __STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
427 {
428 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
429 }
430
431 /**
432 * @brief Set the clock divider value to generate an interframe gap
433 * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
434 * @param UCPDx UCPD Instance
435 * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
436 * @retval None
437 */
438 __STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
439 {
440 MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
441 }
442
443 /**
444 * @}
445 */
446
447 /** @defgroup UCPD_LL_EF_CFG2 CFG2 register
448 * @{
449 */
450
451 /**
452 * @brief Enable the wakeup mode
453 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
454 * @param UCPDx UCPD Instance
455 * @retval None
456 */
457 __STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
458 {
459 SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
460 }
461
462 /**
463 * @brief Disable the wakeup mode
464 * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
465 * @param UCPDx UCPD Instance
466 * @retval None
467 */
468 __STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
469 {
470 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
471 }
472
473 /**
474 * @brief Force clock enable
475 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
476 * @param UCPDx UCPD Instance
477 * @retval None
478 */
479 __STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
480 {
481 SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
482 }
483
484 /**
485 * @brief Force clock disable
486 * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
487 * @param UCPDx UCPD Instance
488 * @retval None
489 */
490 __STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
491 {
492 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
493 }
494
495 /**
496 * @brief RxFilter enable
497 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
498 * @param UCPDx UCPD Instance
499 * @retval None
500 */
501 __STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
502 {
503 CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
504 }
505
506 /**
507 * @brief RxFilter disable
508 * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
509 * @param UCPDx UCPD Instance
510 * @retval None
511 */
512 __STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
513 {
514 SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
515 }
516
517 /**
518 * @}
519 */
520
521 /**
522 * @}
523 */
524
525 /** @defgroup UCPD_LL_EF_CR CR register
526 * @{
527 */
528 /**
529 * @brief Type C detector for CC2 enable
530 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
531 * @param UCPDx UCPD Instance
532 * @retval None
533 */
534 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
535 {
536 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
537 }
538
539 /**
540 * @brief Type C detector for CC2 disable
541 * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
542 * @param UCPDx UCPD Instance
543 * @retval None
544 */
545 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
546 {
547 SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
548 }
549
550 /**
551 * @brief Type C detector for CC1 enable
552 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
553 * @param UCPDx UCPD Instance
554 * @retval None
555 */
556 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
557 {
558 CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
559 }
560
561 /**
562 * @brief Type C detector for CC1 disable
563 * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
564 * @param UCPDx UCPD Instance
565 * @retval None
566 */
567 __STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
568 {
569 SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
570 }
571
572 /**
573 * @brief Source Vconn discharge enable
574 * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
575 * @param UCPDx UCPD Instance
576 * @retval None
577 */
578 __STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
579 {
580 SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
581 }
582
583 /**
584 * @brief Source Vconn discharge disable
585 * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
586 * @param UCPDx UCPD Instance
587 * @retval None
588 */
589 __STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
590 {
591 CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
592 }
593
594 /**
595 * @brief Signal Fast Role Swap request
596 * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
597 * @param UCPDx UCPD Instance
598 * @retval None
599 */
600 __STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
601 {
602 SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
603 }
604
605 /**
606 * @brief Fast Role swap RX detection enable
607 * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable
608 * @param UCPDx UCPD Instance
609 * @retval None
610 */
611 __STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
612 {
613 SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
614 }
615
616 /**
617 * @brief Fast Role swap RX detection disable
618 * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable
619 * @param UCPDx UCPD Instance
620 * @retval None
621 */
622 __STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
623 {
624 CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
625 }
626
627 /**
628 * @brief Set cc enable
629 * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
630 * @param UCPDx UCPD Instance
631 * @param CCEnable This parameter can be one of the following values:
632 * @arg @ref LL_UCPD_CCENABLE_NONE
633 * @arg @ref LL_UCPD_CCENABLE_CC1
634 * @arg @ref LL_UCPD_CCENABLE_CC2
635 * @arg @ref LL_UCPD_CCENABLE_CC1CC2
636 * @retval None
637 */
638 __STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
639 {
640 MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
641 }
642
643 /**
644 * @brief Set UCPD SNK role
645 * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
646 * @param UCPDx UCPD Instance
647 * @retval None
648 */
649 __STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
650 {
651 SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
652 }
653
654 /**
655 * @brief Set UCPD SRC role
656 * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
657 * @param UCPDx UCPD Instance
658 * @retval None
659 */
660 __STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
661 {
662 CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
663 }
664
665 /**
666 * @brief Get UCPD Role
667 * @rmtoll CR ANAMODE LL_UCPD_GetRole
668 * @param UCPDx UCPD Instance
669 * @retval Returned value can be one of the following values:
670 * @arg @ref LL_UCPD_ROLE_SNK
671 * @arg @ref LL_UCPD_ROLE_SRC
672 */
673 __STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const * const UCPDx)
674 {
675 return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
676 }
677
678 /**
679 * @brief Set Rp resistor
680 * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
681 * @param UCPDx UCPD Instance
682 * @param Resistor This parameter can be one of the following values:
683 * @arg @ref LL_UCPD_RESISTOR_DEFAULT
684 * @arg @ref LL_UCPD_RESISTOR_1_5A
685 * @arg @ref LL_UCPD_RESISTOR_3_0A
686 * @arg @ref LL_UCPD_RESISTOR_NONE
687 * @retval None
688 */
689 __STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
690 {
691 MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
692 }
693
694 /**
695 * @brief Set CC pin
696 * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
697 * @param UCPDx UCPD Instance
698 * @param CCPin This parameter can be one of the following values:
699 * @arg @ref LL_UCPD_CCPIN_CC1
700 * @arg @ref LL_UCPD_CCPIN_CC2
701 * @retval None
702 */
703 __STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
704 {
705 MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
706 }
707
708 /**
709 * @brief Rx enable
710 * @rmtoll CR PHYRXEN LL_UCPD_RxEnable
711 * @param UCPDx UCPD Instance
712 * @retval None
713 */
714 __STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
715 {
716 SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
717 }
718
719 /**
720 * @brief Rx disable
721 * @rmtoll CR PHYRXEN LL_UCPD_RxDisable
722 * @param UCPDx UCPD Instance
723 * @retval None
724 */
725 __STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
726 {
727 CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
728 }
729
730 /**
731 * @brief Set Rx mode
732 * @rmtoll CR RXMODE LL_UCPD_SetRxMode
733 * @param UCPDx UCPD Instance
734 * @param RxMode This parameter can be one of the following values:
735 * @arg @ref LL_UCPD_RXMODE_NORMAL
736 * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
737 * @retval None
738 */
739 __STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
740 {
741 MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
742 }
743
744 /**
745 * @brief Send Hard Reset
746 * @rmtoll CR TXHRST LL_UCPD_SendHardReset
747 * @param UCPDx UCPD Instance
748 * @retval None
749 */
750 __STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
751 {
752 SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
753 }
754
755 /**
756 * @brief Send message
757 * @rmtoll CR TXSEND LL_UCPD_SendMessage
758 * @param UCPDx UCPD Instance
759 * @retval None
760 */
761 __STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
762 {
763 SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
764 }
765
766 /**
767 * @brief Set Tx mode
768 * @rmtoll CR TXMODE LL_UCPD_SetTxMode
769 * @param UCPDx UCPD Instance
770 * @param TxMode This parameter can be one of the following values:
771 * @arg @ref LL_UCPD_TXMODE_NORMAL
772 * @arg @ref LL_UCPD_TXMODE_CABLE_RESET
773 * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
774 * @retval None
775 */
776 __STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
777 {
778 MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
779 }
780
781 /**
782 * @}
783 */
784
785 /** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
786 * @{
787 */
788
789 /**
790 * @brief Enable FRS interrupt
791 * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS
792 * @param UCPDx UCPD Instance
793 * @retval None
794 */
795 __STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
796 {
797 SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
798 }
799
800 /**
801 * @brief Enable type c event on CC2
802 * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
803 * @param UCPDx UCPD Instance
804 * @retval None
805 */
806 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
807 {
808 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
809 }
810
811 /**
812 * @brief Enable type c event on CC1
813 * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
814 * @param UCPDx UCPD Instance
815 * @retval None
816 */
817 __STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
818 {
819 SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
820 }
821
822 /**
823 * @brief Enable Rx message end interrupt
824 * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
825 * @param UCPDx UCPD Instance
826 * @retval None
827 */
828 __STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
829 {
830 SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
831 }
832
833 /**
834 * @brief Enable Rx overrun interrupt
835 * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
836 * @param UCPDx UCPD Instance
837 * @retval None
838 */
839 __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
840 {
841 SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
842 }
843
844 /**
845 * @brief Enable Rx hard resrt interrupt
846 * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
847 * @param UCPDx UCPD Instance
848 * @retval None
849 */
850 __STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
851 {
852 SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
853 }
854
855 /**
856 * @brief Enable Rx orderset interrupt
857 * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
858 * @param UCPDx UCPD Instance
859 * @retval None
860 */
861 __STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
862 {
863 SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
864 }
865
866 /**
867 * @brief Enable Rx non empty interrupt
868 * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
869 * @param UCPDx UCPD Instance
870 * @retval None
871 */
872 __STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
873 {
874 SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
875 }
876
877 /**
878 * @brief Enable TX underrun interrupt
879 * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
880 * @param UCPDx UCPD Instance
881 * @retval None
882 */
883 __STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
884 {
885 SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
886 }
887
888 /**
889 * @brief Enable hard reset sent interrupt
890 * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
891 * @param UCPDx UCPD Instance
892 * @retval None
893 */
894 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
895 {
896 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
897 }
898
899 /**
900 * @brief Enable hard reset discard interrupt
901 * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
902 * @param UCPDx UCPD Instance
903 * @retval None
904 */
905 __STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
906 {
907 SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
908 }
909
910 /**
911 * @brief Enable Tx message abort interrupt
912 * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
913 * @param UCPDx UCPD Instance
914 * @retval None
915 */
916 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
917 {
918 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
919 }
920
921 /**
922 * @brief Enable Tx message sent interrupt
923 * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
924 * @param UCPDx UCPD Instance
925 * @retval None
926 */
927 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
928 {
929 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
930 }
931
932 /**
933 * @brief Enable Tx message discarded interrupt
934 * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
935 * @param UCPDx UCPD Instance
936 * @retval None
937 */
938 __STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
939 {
940 SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
941 }
942
943 /**
944 * @brief Enable Tx data receive interrupt
945 * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
946 * @param UCPDx UCPD Instance
947 * @retval None
948 */
949 __STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
950 {
951 SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
952 }
953
954 /**
955 * @brief Disable FRS interrupt
956 * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
957 * @param UCPDx UCPD Instance
958 * @retval None
959 */
960 __STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
961 {
962 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
963 }
964
965 /**
966 * @brief Disable type c event on CC2
967 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
968 * @param UCPDx UCPD Instance
969 * @retval None
970 */
971 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
972 {
973 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
974 }
975
976 /**
977 * @brief Disable type c event on CC1
978 * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
979 * @param UCPDx UCPD Instance
980 * @retval None
981 */
982 __STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
983 {
984 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
985 }
986
987 /**
988 * @brief Disable Rx message end interrupt
989 * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
990 * @param UCPDx UCPD Instance
991 * @retval None
992 */
993 __STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
994 {
995 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
996 }
997
998 /**
999 * @brief Disable Rx overrun interrupt
1000 * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
1001 * @param UCPDx UCPD Instance
1002 * @retval None
1003 */
1004 __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
1005 {
1006 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
1007 }
1008
1009 /**
1010 * @brief Disable Rx hard resrt interrupt
1011 * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
1012 * @param UCPDx UCPD Instance
1013 * @retval None
1014 */
1015 __STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
1016 {
1017 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
1018 }
1019
1020 /**
1021 * @brief Disable Rx orderset interrupt
1022 * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
1023 * @param UCPDx UCPD Instance
1024 * @retval None
1025 */
1026 __STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
1027 {
1028 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
1029 }
1030
1031 /**
1032 * @brief Disable Rx non empty interrupt
1033 * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
1034 * @param UCPDx UCPD Instance
1035 * @retval None
1036 */
1037 __STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
1038 {
1039 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
1040 }
1041
1042 /**
1043 * @brief Disable TX underrun interrupt
1044 * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
1045 * @param UCPDx UCPD Instance
1046 * @retval None
1047 */
1048 __STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
1049 {
1050 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
1051 }
1052
1053 /**
1054 * @brief Disable hard reset sent interrupt
1055 * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
1056 * @param UCPDx UCPD Instance
1057 * @retval None
1058 */
1059 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1060 {
1061 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
1062 }
1063
1064 /**
1065 * @brief Disable hard reset discard interrupt
1066 * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
1067 * @param UCPDx UCPD Instance
1068 * @retval None
1069 */
1070 __STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1071 {
1072 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
1073 }
1074
1075 /**
1076 * @brief Disable Tx message abort interrupt
1077 * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
1078 * @param UCPDx UCPD Instance
1079 * @retval None
1080 */
1081 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
1082 {
1083 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
1084 }
1085
1086 /**
1087 * @brief Disable Tx message sent interrupt
1088 * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
1089 * @param UCPDx UCPD Instance
1090 * @retval None
1091 */
1092 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
1093 {
1094 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
1095 }
1096
1097 /**
1098 * @brief Disable Tx message discarded interrupt
1099 * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
1100 * @param UCPDx UCPD Instance
1101 * @retval None
1102 */
1103 __STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
1104 {
1105 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
1106 }
1107
1108 /**
1109 * @brief Disable Tx data receive interrupt
1110 * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
1111 * @param UCPDx UCPD Instance
1112 * @retval None
1113 */
1114 __STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
1115 {
1116 CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
1117 }
1118
1119 /**
1120 * @brief Check if FRS interrupt enabled
1121 * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
1122 * @param UCPDx UCPD Instance
1123 * @retval State of bit (1 or 0).
1124 */
1125 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const * const UCPDx)
1126 {
1127 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
1128 }
1129
1130 /**
1131 * @brief Check if type c event on CC2 enabled
1132 * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
1133 * @param UCPDx UCPD Instance
1134 * @retval State of bit (1 or 0).
1135 */
1136 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)
1137 {
1138 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
1139 }
1140
1141 /**
1142 * @brief Check if type c event on CC1 enabled
1143 * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
1144 * @param UCPDx UCPD Instance
1145 * @retval State of bit (1 or 0).
1146 */
1147 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)
1148 {
1149 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
1150 }
1151
1152 /**
1153 * @brief Check if Rx message end interrupt enabled
1154 * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
1155 * @param UCPDx UCPD Instance
1156 * @retval State of bit (1 or 0).
1157 */
1158 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const * const UCPDx)
1159 {
1160 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
1161 }
1162
1163 /**
1164 * @brief Check if Rx overrun interrupt enabled
1165 * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
1166 * @param UCPDx UCPD Instance
1167 * @retval State of bit (1 or 0).
1168 */
1169 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const * const UCPDx)
1170 {
1171 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
1172 }
1173
1174 /**
1175 * @brief Check if Rx hard resrt interrupt enabled
1176 * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
1177 * @param UCPDx UCPD Instance
1178 * @retval State of bit (1 or 0).
1179 */
1180 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const * const UCPDx)
1181 {
1182 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
1183 }
1184
1185 /**
1186 * @brief Check if Rx orderset interrupt enabled
1187 * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
1188 * @param UCPDx UCPD Instance
1189 * @retval State of bit (1 or 0).
1190 */
1191 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const * const UCPDx)
1192 {
1193 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
1194 }
1195
1196 /**
1197 * @brief Check if Rx non empty interrupt enabled
1198 * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
1199 * @param UCPDx UCPD Instance
1200 * @retval State of bit (1 or 0).
1201 */
1202 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const * const UCPDx)
1203 {
1204 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
1205 }
1206
1207 /**
1208 * @brief Check if TX underrun interrupt enabled
1209 * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
1210 * @param UCPDx UCPD Instance
1211 * @retval State of bit (1 or 0).
1212 */
1213 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const * const UCPDx)
1214 {
1215 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
1216 }
1217
1218 /**
1219 * @brief Check if hard reset sent interrupt enabled
1220 * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
1221 * @param UCPDx UCPD Instance
1222 * @retval State of bit (1 or 0).
1223 */
1224 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)
1225 {
1226 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
1227 }
1228
1229 /**
1230 * @brief Check if hard reset discard interrupt enabled
1231 * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
1232 * @param UCPDx UCPD Instance
1233 * @retval State of bit (1 or 0).
1234 */
1235 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)
1236 {
1237 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
1238 }
1239
1240 /**
1241 * @brief Check if Tx message abort interrupt enabled
1242 * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
1243 * @param UCPDx UCPD Instance
1244 * @retval State of bit (1 or 0).
1245 */
1246 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const * const UCPDx)
1247 {
1248 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
1249 }
1250
1251 /**
1252 * @brief Check if Tx message sent interrupt enabled
1253 * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
1254 * @param UCPDx UCPD Instance
1255 * @retval State of bit (1 or 0).
1256 */
1257 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const * const UCPDx)
1258 {
1259 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
1260 }
1261
1262 /**
1263 * @brief Check if Tx message discarded interrupt enabled
1264 * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
1265 * @param UCPDx UCPD Instance
1266 * @retval State of bit (1 or 0).
1267 */
1268 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const * const UCPDx)
1269 {
1270 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
1271 }
1272
1273 /**
1274 * @brief Check if Tx data receive interrupt enabled
1275 * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
1276 * @param UCPDx UCPD Instance
1277 * @retval State of bit (1 or 0).
1278 */
1279 __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const * const UCPDx)
1280 {
1281 return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
1282 }
1283
1284 /**
1285 * @}
1286 */
1287
1288 /** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
1289 * @{
1290 */
1291 /**
1292 * @brief Clear FRS interrupt
1293 * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
1294 * @param UCPDx UCPD Instance
1295 * @retval None
1296 */
1297 __STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
1298 {
1299 SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
1300 }
1301
1302 /**
1303 * @brief Clear type c event on CC2
1304 * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
1305 * @param UCPDx UCPD Instance
1306 * @retval None
1307 */
1308 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
1309 {
1310 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
1311 }
1312
1313 /**
1314 * @brief Clear type c event on CC1
1315 * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
1316 * @param UCPDx UCPD Instance
1317 * @retval None
1318 */
1319 __STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
1320 {
1321 SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
1322 }
1323
1324 /**
1325 * @brief Clear Rx message end interrupt
1326 * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
1327 * @param UCPDx UCPD Instance
1328 * @retval None
1329 */
1330 __STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
1331 {
1332 SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
1333 }
1334
1335 /**
1336 * @brief Clear Rx overrun interrupt
1337 * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
1338 * @param UCPDx UCPD Instance
1339 * @retval None
1340 */
1341 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
1342 {
1343 SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
1344 }
1345
1346 /**
1347 * @brief Clear Rx hard resrt interrupt
1348 * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
1349 * @param UCPDx UCPD Instance
1350 * @retval None
1351 */
1352 __STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
1353 {
1354 SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
1355 }
1356
1357 /**
1358 * @brief Clear Rx orderset interrupt
1359 * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
1360 * @param UCPDx UCPD Instance
1361 * @retval None
1362 */
1363 __STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
1364 {
1365 SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
1366 }
1367
1368 /**
1369 * @brief Clear TX underrun interrupt
1370 * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
1371 * @param UCPDx UCPD Instance
1372 * @retval None
1373 */
1374 __STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
1375 {
1376 SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
1377 }
1378
1379 /**
1380 * @brief Clear hard reset sent interrupt
1381 * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
1382 * @param UCPDx UCPD Instance
1383 * @retval None
1384 */
1385 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
1386 {
1387 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
1388 }
1389
1390 /**
1391 * @brief Clear hard reset discard interrupt
1392 * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
1393 * @param UCPDx UCPD Instance
1394 * @retval None
1395 */
1396 __STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
1397 {
1398 SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
1399 }
1400
1401 /**
1402 * @brief Clear Tx message abort interrupt
1403 * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
1404 * @param UCPDx UCPD Instance
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
1408 {
1409 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
1410 }
1411
1412 /**
1413 * @brief Clear Tx message sent interrupt
1414 * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
1415 * @param UCPDx UCPD Instance
1416 * @retval None
1417 */
1418 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
1419 {
1420 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
1421 }
1422
1423 /**
1424 * @brief Clear Tx message discarded interrupt
1425 * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
1426 * @param UCPDx UCPD Instance
1427 * @retval None
1428 */
1429 __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
1430 {
1431 SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
1432 }
1433
1434 /**
1435 * @}
1436 */
1437
1438 /** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
1439 * @{
1440 */
1441
1442 /**
1443 * @brief Check if FRS interrupt
1444 * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS
1445 * @param UCPDx UCPD Instance
1446 * @retval None
1447 */
1448 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const * const UCPDx)
1449 {
1450 return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
1451 }
1452
1453 /**
1454 * @brief Check if type c event on CC2
1455 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
1456 * @param UCPDx UCPD Instance
1457 * @retval None
1458 */
1459 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * const UCPDx)
1460 {
1461 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
1462 }
1463
1464 /**
1465 * @brief Check if type c event on CC1
1466 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
1467 * @param UCPDx UCPD Instance
1468 * @retval None
1469 */
1470 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * const UCPDx)
1471 {
1472 return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
1473 }
1474
1475 /**
1476 * @brief Check if Rx message end interrupt
1477 * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
1478 * @param UCPDx UCPD Instance
1479 * @retval None
1480 */
1481 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const * const UCPDx)
1482 {
1483 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
1484 }
1485
1486 /**
1487 * @brief Check if Rx overrun interrupt
1488 * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
1489 * @param UCPDx UCPD Instance
1490 * @retval None
1491 */
1492 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const * const UCPDx)
1493 {
1494 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
1495 }
1496
1497 /**
1498 * @brief Check if Rx hard resrt interrupt
1499 * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
1500 * @param UCPDx UCPD Instance
1501 * @retval None
1502 */
1503 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const * const UCPDx)
1504 {
1505 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
1506 }
1507
1508 /**
1509 * @brief Check if Rx orderset interrupt
1510 * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
1511 * @param UCPDx UCPD Instance
1512 * @retval State of bit (1 or 0).
1513 */
1514 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const * const UCPDx)
1515 {
1516 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
1517 }
1518
1519 /**
1520 * @brief Check if Rx non empty interrupt
1521 * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
1522 * @param UCPDx UCPD Instance
1523 * @retval State of bit (1 or 0).
1524 */
1525 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const * const UCPDx)
1526 {
1527 return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Check if TX underrun interrupt
1532 * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
1533 * @param UCPDx UCPD Instance
1534 * @retval State of bit (1 or 0).
1535 */
1536 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const * const UCPDx)
1537 {
1538 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
1539 }
1540
1541 /**
1542 * @brief Check if hard reset sent interrupt
1543 * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
1544 * @param UCPDx UCPD Instance
1545 * @retval State of bit (1 or 0).
1546 */
1547 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const * const UCPDx)
1548 {
1549 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
1550 }
1551
1552 /**
1553 * @brief Check if hard reset discard interrupt
1554 * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
1555 * @param UCPDx UCPD Instance
1556 * @retval State of bit (1 or 0).
1557 */
1558 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const * const UCPDx)
1559 {
1560 return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
1561 }
1562
1563 /**
1564 * @brief Check if Tx message abort interrupt
1565 * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
1566 * @param UCPDx UCPD Instance
1567 * @retval State of bit (1 or 0).
1568 */
1569 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const * const UCPDx)
1570 {
1571 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
1572 }
1573
1574 /**
1575 * @brief Check if Tx message sent interrupt
1576 * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
1577 * @param UCPDx UCPD Instance
1578 * @retval State of bit (1 or 0).
1579 */
1580 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const * const UCPDx)
1581 {
1582 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
1583 }
1584
1585 /**
1586 * @brief Check if Tx message discarded interrupt
1587 * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
1588 * @param UCPDx UCPD Instance
1589 * @retval State of bit (1 or 0).
1590 */
1591 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const * const UCPDx)
1592 {
1593 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
1594 }
1595
1596 /**
1597 * @brief Check if Tx data receive interrupt
1598 * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
1599 * @param UCPDx UCPD Instance
1600 * @retval State of bit (1 or 0).
1601 */
1602 __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const * const UCPDx)
1603 {
1604 return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
1605 }
1606
1607 /**
1608 * @brief return the vstate value for CC2
1609 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
1610 * @param UCPDx UCPD Instance
1611 * @retval val
1612 */
1613 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const * const UCPDx)
1614 {
1615 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
1616 }
1617
1618 /**
1619 * @brief return the vstate value for CC1
1620 * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
1621 * @param UCPDx UCPD Instance
1622 * @retval val
1623 */
1624 __STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const * const UCPDx)
1625 {
1626 return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
1627 }
1628
1629 /**
1630 * @}
1631 */
1632
1633
1634 /** @defgroup UCPD_LL_EF_DMA_Management DMA Management
1635 * @{
1636 */
1637
1638 /**
1639 * @brief Rx DMA Enable
1640 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
1641 * @param UCPDx UCPD Instance
1642 * @retval None
1643 */
1644 __STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
1645 {
1646 SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1647 }
1648
1649 /**
1650 * @brief Rx DMA Disable
1651 * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
1652 * @param UCPDx UCPD Instance
1653 * @retval None
1654 */
1655 __STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
1656 {
1657 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
1658 }
1659
1660 /**
1661 * @brief Tx DMA Enable
1662 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
1663 * @param UCPDx UCPD Instance
1664 * @retval None
1665 */
1666 __STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
1667 {
1668 SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1669 }
1670
1671 /**
1672 * @brief Tx DMA Disable
1673 * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
1674 * @param UCPDx UCPD Instance
1675 * @retval None
1676 */
1677 __STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
1678 {
1679 CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
1680 }
1681
1682 /**
1683 * @brief Check if DMA Tx is enabled
1684 * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
1685 * @param UCPDx UCPD Instance
1686 * @retval State of bit (1 or 0).
1687 */
1688 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const * const UCPDx)
1689 {
1690 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
1691 }
1692
1693 /**
1694 * @brief Check if DMA Rx is enabled
1695 * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
1696 * @param UCPDx UCPD Instance
1697 * @retval State of bit (1 or 0).
1698 */
1699 __STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const * const UCPDx)
1700 {
1701 return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
1702 }
1703
1704 /**
1705 * @}
1706 */
1707
1708 /** @defgroup UCPD_LL_EF_DATA_Management DATA Management
1709 * @{
1710 */
1711
1712 /**
1713 * @brief write the orderset for Tx message
1714 * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
1715 * @param UCPDx UCPD Instance
1716 * @param TxOrderSet one of the following value
1717 * @arg @ref LL_UCPD_ORDERED_SET_SOP
1718 * @arg @ref LL_UCPD_ORDERED_SET_SOP1
1719 * @arg @ref LL_UCPD_ORDERED_SET_SOP2
1720 * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
1721 * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
1722 * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
1723 * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
1724 * @retval None
1725 */
1726 __STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
1727 {
1728 WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
1729 }
1730
1731 /**
1732 * @brief write the Tx paysize
1733 * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
1734 * @param UCPDx UCPD Instance
1735 * @param TxPaySize
1736 * @retval None.
1737 */
1738 __STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
1739 {
1740 WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
1741 }
1742
1743 /**
1744 * @brief Write data
1745 * @rmtoll TXDR DR LL_UCPD_WriteData
1746 * @param UCPDx UCPD Instance
1747 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
1748 * @retval None.
1749 */
1750 __STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
1751 {
1752 WRITE_REG(UCPDx->TXDR, Data);
1753 }
1754
1755 /**
1756 * @brief read RX the orderset
1757 * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
1758 * @param UCPDx UCPD Instance
1759 * @retval RxOrderSet one of the following value
1760 * @arg @ref LL_UCPD_RXORDSET_SOP
1761 * @arg @ref LL_UCPD_RXORDSET_SOP1
1762 * @arg @ref LL_UCPD_RXORDSET_SOP2
1763 * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
1764 * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
1765 * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
1766 * @arg @ref LL_UCPD_RXORDSET_SOPEXT1
1767 * @arg @ref LL_UCPD_RXORDSET_SOPEXT2
1768 */
1769 __STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const * const UCPDx)
1770 {
1771 return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
1772 }
1773
1774 /**
1775 * @brief Read the Rx paysize
1776 * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_ReadRxPaySize
1777 * @param UCPDx UCPD Instance
1778 * @retval RXPaysize.
1779 */
1780 __STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const * const UCPDx)
1781 {
1782 return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
1783 }
1784
1785 /**
1786 * @brief Read data
1787 * @rmtoll TXDR RXDATA LL_UCPD_ReadData
1788 * @param UCPDx UCPD Instance
1789 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1790 */
1791 __STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const * const UCPDx)
1792 {
1793 return READ_REG(UCPDx->RXDR);
1794 }
1795
1796 /**
1797 * @brief Set Rx OrderSet Ext1
1798 * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
1799 * @param UCPDx UCPD Instance
1800 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1801 * @retval None
1802 */
1803 __STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1804 {
1805 WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
1806 }
1807
1808 /**
1809 * @brief Set Rx OrderSet Ext2
1810 * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
1811 * @param UCPDx UCPD Instance
1812 * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
1813 * @retval None
1814 */
1815 __STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
1816 {
1817 WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 #if defined(USE_FULL_LL_DRIVER)
1825 /** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
1826 * @{
1827 */
1828
1829 ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
1830 ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
1831 void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
1832
1833 /**
1834 * @}
1835 */
1836 #endif /* USE_FULL_LL_DRIVER */
1837
1838 /**
1839 * @}
1840 */
1841
1842 #endif /* defined (UCPD1) */
1843
1844 /**
1845 * @}
1846 */
1847
1848 /**
1849 * @}
1850 */
1851
1852 #ifdef __cplusplus
1853 }
1854 #endif
1855
1856 #endif /* STM32G4xx_LL_UCPD_H */
1857
1858 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/