lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dma.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_hal_dma.c
   4   * @author  MCD Application Team
   5   * @brief   DMA HAL module driver.
   6   *         This file provides firmware functions to manage the following
   7   *         functionalities of the Direct Memory Access (DMA) peripheral:
   8   *           + Initialization and de-initialization functions
   9   *           + IO operation functions
  10   *           + Peripheral State and errors functions
  11   @verbatim
  12   ==============================================================================
  13                         ##### How to use this driver #####
  14   ==============================================================================
  15   [..]
  16    (#) Enable and configure the peripheral to be connected to the DMA Channel
  17        (except for internal SRAM / FLASH memories: no initialization is
  18        necessary). Please refer to the Reference manual for connection between peripherals
  19        and DMA requests.
  20
  21    (#) For a given Channel, program the required configuration through the following parameters:
  22        Channel request, Transfer Direction, Source and Destination data formats,
  23        Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
  24        using HAL_DMA_Init() function.
  25
  26        Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
  27        thanks to:
  28       (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or  __HAL_RCC_DMA2_CLK_ENABLE() ;
  29       (##) DMAMUX1:      __HAL_RCC_DMAMUX1_CLK_ENABLE();
  30
  31    (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
  32        detection.
  33
  34    (#) Use HAL_DMA_Abort() function to abort the current transfer
  35
  36      -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
  37
  38      *** Polling mode IO operation ***
  39      =================================
  40     [..]
  41           (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
  42               address and destination address and the Length of data to be transferred
  43           (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
  44               case a fixed Timeout can be configured by User depending from his application.
  45
  46      *** Interrupt mode IO operation ***
  47      ===================================
  48     [..]
  49           (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
  50           (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
  51           (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
  52               Source address and destination address and the Length of data to be transferred.
  53               In this case the DMA interrupt is configured
  54           (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
  55           (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
  56               add his own function to register callbacks with HAL_DMA_RegisterCallback().
  57
  58      *** DMA HAL driver macros list ***
  59      =============================================
  60       [..]
  61        Below the list of macros in DMA HAL driver.
  62
  63        (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
  64        (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
  65        (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
  66        (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
  67        (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
  68        (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
  69        (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
  70
  71      [..]
  72       (@) You can refer to the DMA HAL driver header file for more useful macros
  73
  74   @endverbatim
  75   ******************************************************************************
  76   * @attention
  77   *
  78   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  79   * All rights reserved.</center></h2>
  80   *
  81   * This software component is licensed by ST under BSD 3-Clause license,
  82   * the "License"; You may not use this file except in compliance with the
  83   * License. You may obtain a copy of the License at:
  84   *                        opensource.org/licenses/BSD-3-Clause
  85   *
  86   ******************************************************************************
  87   */
  88
  89 /* Includes ------------------------------------------------------------------*/
  90 #include "stm32g4xx_hal.h"
  91
  92 /** @addtogroup STM32G4xx_HAL_Driver
  93   * @{
  94   */
  95
  96 /** @defgroup DMA DMA
  97   * @brief DMA HAL module driver
  98   * @{
  99   */
 100
 101 #ifdef HAL_DMA_MODULE_ENABLED
 102
 103 /* Private typedef -----------------------------------------------------------*/
 104 /* Private define ------------------------------------------------------------*/
 105 /* Private macro -------------------------------------------------------------*/
 106 /* Private variables ---------------------------------------------------------*/
 107 /* Private function prototypes -----------------------------------------------*/
 108 /** @defgroup DMA_Private_Functions DMA Private Functions
 109   * @{
 110   */
 111 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 112
 113 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
 114 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
 115
 116 /**
 117   * @}
 118   */
 119
 120 /* Exported functions ---------------------------------------------------------*/
 121
 122 /** @defgroup DMA_Exported_Functions DMA Exported Functions
 123   * @{
 124   */
 125
 126 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 127   *  @brief   Initialization and de-initialization functions
 128   *
 129 @verbatim
 130  ===============================================================================
 131              ##### Initialization and de-initialization functions  #####
 132  ===============================================================================
 133     [..]
 134     This section provides functions allowing to initialize the DMA Channel source
 135     and destination addresses, incrementation and data sizes, transfer direction,
 136     circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
 137     [..]
 138     The HAL_DMA_Init() function follows the DMA configuration procedures as described in
 139     reference manual.
 140
 141 @endverbatim
 142   * @{
 143   */
 144
 145 /**
 146   * @brief  Initialize the DMA according to the specified
 147   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
 148   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
 149   *               the configuration information for the specified DMA Channel.
 150   * @retval HAL status
 151   */
 152 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 153 {
 154   uint32_t tmp;
 155
 156   /* Check the DMA handle allocation */
 157   if (hdma == NULL)
 158   {
 159     return HAL_ERROR;
 160   }
 161
 162   /* Check the parameters */
 163   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
 164   assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
 165   assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
 166   assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
 167   assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
 168   assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
 169   assert_param(IS_DMA_MODE(hdma->Init.Mode));
 170   assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
 171
 172   assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
 173
 174   /* Compute the channel index */
 175   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 176   {
 177     /* DMA1 */
 178     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 179     hdma->DmaBaseAddress = DMA1;
 180   }
 181   else
 182   {
 183     /* DMA2 */
 184     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 185     hdma->DmaBaseAddress = DMA2;
 186   }
 187
 188   /* Change DMA peripheral state */
 189   hdma->State = HAL_DMA_STATE_BUSY;
 190
 191   /* Get the CR register value */
 192   tmp = hdma->Instance->CCR;
 193
 194   /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
 195   tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  |
 196                       DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   |
 197                       DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
 198
 199   /* Prepare the DMA Channel configuration */
 200   tmp |=  hdma->Init.Direction        |
 201           hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 202           hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 203           hdma->Init.Mode                | hdma->Init.Priority;
 204
 205   /* Write to DMA Channel CR register */
 206   hdma->Instance->CCR = tmp;
 207
 208   /* Initialize parameters for DMAMUX channel :
 209      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
 210   */
 211   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
 212
 213   if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
 214   {
 215     /* if memory to memory force the request to 0*/
 216     hdma->Init.Request = DMA_REQUEST_MEM2MEM;
 217   }
 218
 219   /* Set peripheral request  to DMAMUX channel */
 220   hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
 221
 222   /* Clear the DMAMUX synchro overrun flag */
 223   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 224
 225   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
 226   {
 227     /* Initialize parameters for DMAMUX request generator :
 228        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
 229     */
 230     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
 231
 232     /* Reset the DMAMUX request generator register*/
 233     hdma->DMAmuxRequestGen->RGCR = 0U;
 234
 235     /* Clear the DMAMUX request generator overrun flag */
 236     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 237   }
 238   else
 239   {
 240     hdma->DMAmuxRequestGen = 0U;
 241     hdma->DMAmuxRequestGenStatus = 0U;
 242     hdma->DMAmuxRequestGenStatusMask = 0U;
 243   }
 244
 245   /* Initialize the error code */
 246   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 247
 248   /* Initialize the DMA state*/
 249   hdma->State  = HAL_DMA_STATE_READY;
 250
 251   /* Allocate lock resource and initialize it */
 252   hdma->Lock = HAL_UNLOCKED;
 253
 254   return HAL_OK;
 255 }
 256
 257 /**
 258   * @brief  DeInitialize the DMA peripheral.
 259   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 260   *               the configuration information for the specified DMA Channel.
 261   * @retval HAL status
 262   */
 263 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 264 {
 265
 266   /* Check the DMA handle allocation */
 267   if (NULL == hdma)
 268   {
 269     return HAL_ERROR;
 270   }
 271
 272   /* Check the parameters */
 273   assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
 274
 275   /* Disable the selected DMA Channelx */
 276   __HAL_DMA_DISABLE(hdma);
 277
 278   /* Compute the channel index */
 279   if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 280   {
 281     /* DMA1 */
 282     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
 283     hdma->DmaBaseAddress = DMA1;
 284   }
 285   else
 286   {
 287     /* DMA2 */
 288     hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
 289     hdma->DmaBaseAddress = DMA2;
 290   }
 291
 292   /* Reset DMA Channel control register */
 293   hdma->Instance->CCR  = 0;
 294
 295   /* Clear all flags */
 296   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
 297
 298   /* Initialize parameters for DMAMUX channel :
 299      DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */
 300
 301   DMA_CalcDMAMUXChannelBaseAndMask(hdma);
 302
 303   /* Reset the DMAMUX channel that corresponds to the DMA channel */
 304   hdma->DMAmuxChannel->CCR = 0;
 305
 306   /* Clear the DMAMUX synchro overrun flag */
 307   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 308
 309   /* Reset Request generator parameters if any */
 310   if (((hdma->Init.Request >  0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
 311   {
 312     /* Initialize parameters for DMAMUX request generator :
 313        DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
 314     */
 315     DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
 316
 317     /* Reset the DMAMUX request generator register*/
 318     hdma->DMAmuxRequestGen->RGCR = 0U;
 319
 320     /* Clear the DMAMUX request generator overrun flag */
 321     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 322   }
 323
 324   hdma->DMAmuxRequestGen = 0U;
 325   hdma->DMAmuxRequestGenStatus = 0U;
 326   hdma->DMAmuxRequestGenStatusMask = 0U;
 327
 328   /* Clean callbacks */
 329   hdma->XferCpltCallback = NULL;
 330   hdma->XferHalfCpltCallback = NULL;
 331   hdma->XferErrorCallback = NULL;
 332   hdma->XferAbortCallback = NULL;
 333
 334   /* Initialize the error code */
 335   hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 336
 337   /* Initialize the DMA state */
 338   hdma->State = HAL_DMA_STATE_RESET;
 339
 340   /* Release Lock */
 341   __HAL_UNLOCK(hdma);
 342
 343   return HAL_OK;
 344 }
 345
 346 /**
 347   * @}
 348   */
 349
 350 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
 351   *  @brief   Input and Output operation functions
 352   *
 353 @verbatim
 354  ===============================================================================
 355                       #####  IO operation functions  #####
 356  ===============================================================================
 357     [..]  This section provides functions allowing to:
 358       (+) Configure the source, destination address and data length and Start DMA transfer
 359       (+) Configure the source, destination address and data length and
 360           Start DMA transfer with interrupt
 361       (+) Abort DMA transfer
 362       (+) Poll for transfer complete
 363       (+) Handle DMA interrupt request
 364
 365 @endverbatim
 366   * @{
 367   */
 368
 369 /**
 370   * @brief  Start the DMA Transfer.
 371   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 372   *               the configuration information for the specified DMA Channel.
 373   * @param  SrcAddress The source memory Buffer address
 374   * @param  DstAddress The destination memory Buffer address
 375   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
 376   * @retval HAL status
 377   */
 378 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 379 {
 380   HAL_StatusTypeDef status = HAL_OK;
 381
 382   /* Check the parameters */
 383   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
 384
 385   /* Process locked */
 386   __HAL_LOCK(hdma);
 387
 388   if (HAL_DMA_STATE_READY == hdma->State)
 389   {
 390     /* Change DMA peripheral state */
 391     hdma->State = HAL_DMA_STATE_BUSY;
 392     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 393
 394     /* Disable the peripheral */
 395     __HAL_DMA_DISABLE(hdma);
 396
 397     /* Configure the source, destination address and the data length & clear flags*/
 398     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 399
 400     /* Enable the Peripheral */
 401     __HAL_DMA_ENABLE(hdma);
 402   }
 403   else
 404   {
 405     /* Process Unlocked */
 406     __HAL_UNLOCK(hdma);
 407     status = HAL_BUSY;
 408   }
 409   return status;
 410 }
 411
 412 /**
 413   * @brief  Start the DMA Transfer with interrupt enabled.
 414   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 415   *               the configuration information for the specified DMA Channel.
 416   * @param  SrcAddress The source memory Buffer address
 417   * @param  DstAddress The destination memory Buffer address
 418   * @param  DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
 419   * @retval HAL status
 420   */
 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
 422                                    uint32_t DataLength)
 423 {
 424   HAL_StatusTypeDef status = HAL_OK;
 425
 426   /* Check the parameters */
 427   assert_param(IS_DMA_BUFFER_SIZE(DataLength));
 428
 429   /* Process locked */
 430   __HAL_LOCK(hdma);
 431
 432   if (HAL_DMA_STATE_READY == hdma->State)
 433   {
 434     /* Change DMA peripheral state */
 435     hdma->State = HAL_DMA_STATE_BUSY;
 436     hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 437
 438     /* Disable the peripheral */
 439     __HAL_DMA_DISABLE(hdma);
 440
 441     /* Configure the source, destination address and the data length & clear flags*/
 442     DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 443
 444     /* Enable the transfer complete interrupt */
 445     /* Enable the transfer Error interrupt */
 446     if (NULL != hdma->XferHalfCpltCallback)
 447     {
 448       /* Enable the Half transfer complete interrupt as well */
 449       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 450     }
 451     else
 452     {
 453       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 454       __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 455     }
 456
 457     /* Check if DMAMUX Synchronization is enabled*/
 458     if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
 459     {
 460       /* Enable DMAMUX sync overrun IT*/
 461       hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
 462     }
 463
 464     if (hdma->DMAmuxRequestGen != 0U)
 465     {
 466       /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
 467       /* enable the request gen overrun IT*/
 468       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
 469     }
 470
 471     /* Enable the Peripheral */
 472     __HAL_DMA_ENABLE(hdma);
 473   }
 474   else
 475   {
 476     /* Process Unlocked */
 477     __HAL_UNLOCK(hdma);
 478
 479     /* Remain BUSY */
 480     status = HAL_BUSY;
 481   }
 482   return status;
 483 }
 484
 485 /**
 486   * @brief  Abort the DMA Transfer.
 487   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 488   *               the configuration information for the specified DMA Channel.
 489     * @retval HAL status
 490   */
 491 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
 492 {
 493   HAL_StatusTypeDef status = HAL_OK;
 494
 495   if(hdma->State != HAL_DMA_STATE_BUSY)
 496   {
 497     /* no transfer ongoing */
 498     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 499
 500     status = HAL_ERROR;
 501   }
 502   else
 503   {
 504      /* Disable DMA IT */
 505      __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 506
 507      /* disable the DMAMUX sync overrun IT*/
 508      hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 509
 510      /* Disable the channel */
 511      __HAL_DMA_DISABLE(hdma);
 512
 513      /* Clear all flags */
 514      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
 515
 516      /* Clear the DMAMUX synchro overrun flag */
 517      hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 518
 519      if (hdma->DMAmuxRequestGen != 0U)
 520      {
 521        /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
 522        /* disable the request gen overrun IT*/
 523        hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 524
 525        /* Clear the DMAMUX request generator overrun flag */
 526        hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 527      }
 528   }
 529   /* Change the DMA state */
 530   hdma->State = HAL_DMA_STATE_READY;
 531
 532   /* Process Unlocked */
 533   __HAL_UNLOCK(hdma);
 534
 535   return status;
 536 }
 537
 538 /**
 539   * @brief  Aborts the DMA Transfer in Interrupt mode.
 540   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 541   *              the configuration information for the specified DMA Channel.
 542   * @retval HAL status
 543   */
 544 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
 545 {
 546   HAL_StatusTypeDef status = HAL_OK;
 547
 548   if (HAL_DMA_STATE_BUSY != hdma->State)
 549   {
 550     /* no transfer ongoing */
 551     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 552
 553     /* Change the DMA state */
 554     hdma->State = HAL_DMA_STATE_READY;
 555
 556     /* Process Unlocked */
 557     __HAL_UNLOCK(hdma);
 558
 559     status = HAL_ERROR;
 560   }
 561   else
 562   {
 563     /* Disable DMA IT */
 564     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 565
 566     /* Disable the channel */
 567     __HAL_DMA_DISABLE(hdma);
 568
 569     /* disable the DMAMUX sync overrun IT*/
 570     hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
 571
 572     /* Clear all flags */
 573     hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
 574
 575     /* Clear the DMAMUX synchro overrun flag */
 576     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 577
 578     if (hdma->DMAmuxRequestGen != 0U)
 579     {
 580       /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/
 581       /* disable the request gen overrun IT*/
 582       hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
 583
 584       /* Clear the DMAMUX request generator overrun flag */
 585       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 586     }
 587
 588     /* Change the DMA state */
 589     hdma->State = HAL_DMA_STATE_READY;
 590
 591     /* Process Unlocked */
 592     __HAL_UNLOCK(hdma);
 593
 594     /* Call User Abort callback */
 595     if (hdma->XferAbortCallback != NULL)
 596     {
 597       hdma->XferAbortCallback(hdma);
 598     }
 599   }
 600   return status;
 601 }
 602
 603 /**
 604   * @brief  Polling for transfer complete.
 605   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 606   *              the configuration information for the specified DMA Channel.
 607   * @param  CompleteLevel Specifies the DMA level complete.
 608   * @param  Timeout       Timeout duration.
 609   * @retval HAL status
 610   */
 611 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
 612                                           uint32_t Timeout)
 613 {
 614   uint32_t temp;
 615   uint32_t tickstart;
 616
 617   if (HAL_DMA_STATE_BUSY != hdma->State)
 618   {
 619     /* no transfer ongoing */
 620     hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 621     __HAL_UNLOCK(hdma);
 622     return HAL_ERROR;
 623   }
 624
 625   /* Polling mode not supported in circular mode */
 626   if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC))
 627   {
 628     hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
 629     return HAL_ERROR;
 630   }
 631
 632   /* Get the level transfer complete flag */
 633   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
 634   {
 635     /* Transfer Complete flag */
 636
 637     temp = (uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU);
 638   }
 639   else
 640   {
 641     /* Half Transfer Complete flag */
 642     temp = (uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU);
 643   }
 644
 645   /* Get tick */
 646   tickstart = HAL_GetTick();
 647
 648   while (0U == (hdma->DmaBaseAddress->ISR & temp))
 649   {
 650     if ((0U != (hdma->DmaBaseAddress->ISR & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU)))))
 651     {
 652       /* When a DMA transfer error occurs */
 653       /* A hardware clear of its EN bits is performed */
 654       /* Clear all flags */
 655       hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
 656
 657       /* Update error code */
 658       hdma->ErrorCode = HAL_DMA_ERROR_TE;
 659
 660       /* Change the DMA state */
 661       hdma->State = HAL_DMA_STATE_READY;
 662
 663       /* Process Unlocked */
 664       __HAL_UNLOCK(hdma);
 665
 666       return HAL_ERROR;
 667     }
 668     /* Check for the Timeout */
 669     if (Timeout != HAL_MAX_DELAY)
 670     {
 671       if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
 672       {
 673         /* Update error code */
 674         hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 675
 676         /* Change the DMA state */
 677         hdma->State = HAL_DMA_STATE_READY;
 678
 679         /* Process Unlocked */
 680         __HAL_UNLOCK(hdma);
 681
 682         return HAL_ERROR;
 683       }
 684     }
 685   }
 686
 687   /*Check for DMAMUX Request generator (if used) overrun status */
 688   if (hdma->DMAmuxRequestGen != 0U)
 689   {
 690     /* if using DMAMUX request generator Check for DMAMUX request generator overrun */
 691     if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
 692     {
 693       /* Disable the request gen overrun interrupt */
 694       hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
 695
 696       /* Clear the DMAMUX request generator overrun flag */
 697       hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
 698
 699       /* Update error code */
 700       hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
 701     }
 702   }
 703
 704   /* Check for DMAMUX Synchronization overrun */
 705   if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
 706   {
 707     /* Clear the DMAMUX synchro overrun flag */
 708     hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
 709
 710     /* Update error code */
 711     hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
 712   }
 713
 714   if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
 715   {
 716     /* Clear the transfer complete flag */
 717     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU));
 718
 719     /* The selected Channelx EN bit is cleared (DMA is disabled and
 720     all transfers are complete) */
 721     hdma->State = HAL_DMA_STATE_READY;
 722   }
 723   else
 724   {
 725     /* Clear the half transfer complete flag */
 726     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU));
 727   }
 728
 729   /* Process unlocked */
 730   __HAL_UNLOCK(hdma);
 731
 732   return HAL_OK;
 733 }
 734
 735 /**
 736   * @brief  Handle DMA interrupt request.
 737   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 738   *               the configuration information for the specified DMA Channel.
 739   * @retval None
 740   */
 741 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 742 {
 743   uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 744   uint32_t source_it = hdma->Instance->CCR;
 745
 746   /* Half Transfer Complete Interrupt management ******************************/
 747   if ((0U != (flag_it & ((uint32_t)DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1FU)))) && (0U != (source_it & DMA_IT_HT)))
 748   {
 749     /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
 750     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 751     {
 752       /* Disable the half transfer interrupt */
 753       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 754     }
 755     /* Clear the half transfer complete flag */
 756     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1FU));
 757
 758     /* DMA peripheral state is not updated in Half Transfer */
 759     /* but in Transfer Complete case */
 760
 761     if (hdma->XferHalfCpltCallback != NULL)
 762     {
 763       /* Half transfer callback */
 764       hdma->XferHalfCpltCallback(hdma);
 765     }
 766   }
 767   /* Transfer Complete Interrupt management ***********************************/
 768   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1FU))))
 769            && (0U != (source_it & DMA_IT_TC)))
 770   {
 771     if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 772     {
 773       /* Disable the transfer complete and error interrupt */
 774       __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 775
 776       /* Change the DMA state */
 777       hdma->State = HAL_DMA_STATE_READY;
 778     }
 779     /* Clear the transfer complete flag */
 780     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1FU));
 781
 782     /* Process Unlocked */
 783     __HAL_UNLOCK(hdma);
 784
 785     if (hdma->XferCpltCallback != NULL)
 786     {
 787       /* Transfer complete callback */
 788       hdma->XferCpltCallback(hdma);
 789     }
 790   }
 791   /* Transfer Error Interrupt management **************************************/
 792   else if ((0U != (flag_it & ((uint32_t)DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1FU))))
 793            && (0U != (source_it & DMA_IT_TE)))
 794   {
 795     /* When a DMA transfer error occurs */
 796     /* A hardware clear of its EN bits is performed */
 797     /* Disable ALL DMA IT */
 798     __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 799
 800     /* Clear all flags */
 801     hdma->DmaBaseAddress->IFCR = ((uint32_t)DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
 802
 803     /* Update error code */
 804     hdma->ErrorCode = HAL_DMA_ERROR_TE;
 805
 806     /* Change the DMA state */
 807     hdma->State = HAL_DMA_STATE_READY;
 808
 809     /* Process Unlocked */
 810     __HAL_UNLOCK(hdma);
 811
 812     if (hdma->XferErrorCallback != NULL)
 813     {
 814       /* Transfer error callback */
 815       hdma->XferErrorCallback(hdma);
 816     }
 817   }
 818   else
 819   {
 820     /* Nothing To Do */
 821   }
 822   return;
 823 }
 824
 825 /**
 826   * @brief  Register callbacks
 827   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
 828   *                               the configuration information for the specified DMA Channel.
 829   * @param  CallbackID           User Callback identifer
 830   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 831   * @param  pCallback            pointer to private callbacsk function which has pointer to
 832   *                               a DMA_HandleTypeDef structure as parameter.
 833   * @retval HAL status
 834   */
 835 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
 836 {
 837   HAL_StatusTypeDef status = HAL_OK;
 838
 839   /* Process locked */
 840   __HAL_LOCK(hdma);
 841
 842   if (HAL_DMA_STATE_READY == hdma->State)
 843   {
 844     switch (CallbackID)
 845     {
 846       case  HAL_DMA_XFER_CPLT_CB_ID:
 847         hdma->XferCpltCallback = pCallback;
 848         break;
 849
 850       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
 851         hdma->XferHalfCpltCallback = pCallback;
 852         break;
 853
 854       case  HAL_DMA_XFER_ERROR_CB_ID:
 855         hdma->XferErrorCallback = pCallback;
 856         break;
 857
 858       case  HAL_DMA_XFER_ABORT_CB_ID:
 859         hdma->XferAbortCallback = pCallback;
 860         break;
 861
 862       default:
 863         status = HAL_ERROR;
 864         break;
 865     }
 866   }
 867   else
 868   {
 869     status = HAL_ERROR;
 870   }
 871
 872   /* Release Lock */
 873   __HAL_UNLOCK(hdma);
 874
 875   return status;
 876 }
 877
 878 /**
 879   * @brief  UnRegister callbacks
 880   * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
 881   *                               the configuration information for the specified DMA Channel.
 882   * @param  CallbackID           User Callback identifer
 883   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 884   * @retval HAL status
 885   */
 886 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
 887 {
 888   HAL_StatusTypeDef status = HAL_OK;
 889
 890   /* Process locked */
 891   __HAL_LOCK(hdma);
 892
 893   if (HAL_DMA_STATE_READY == hdma->State)
 894   {
 895     switch (CallbackID)
 896     {
 897       case  HAL_DMA_XFER_CPLT_CB_ID:
 898         hdma->XferCpltCallback = NULL;
 899         break;
 900
 901       case  HAL_DMA_XFER_HALFCPLT_CB_ID:
 902         hdma->XferHalfCpltCallback = NULL;
 903         break;
 904
 905       case  HAL_DMA_XFER_ERROR_CB_ID:
 906         hdma->XferErrorCallback = NULL;
 907         break;
 908
 909       case  HAL_DMA_XFER_ABORT_CB_ID:
 910         hdma->XferAbortCallback = NULL;
 911         break;
 912
 913       case   HAL_DMA_XFER_ALL_CB_ID:
 914         hdma->XferCpltCallback = NULL;
 915         hdma->XferHalfCpltCallback = NULL;
 916         hdma->XferErrorCallback = NULL;
 917         hdma->XferAbortCallback = NULL;
 918         break;
 919
 920       default:
 921         status = HAL_ERROR;
 922         break;
 923     }
 924   }
 925   else
 926   {
 927     status = HAL_ERROR;
 928   }
 929
 930   /* Release Lock */
 931   __HAL_UNLOCK(hdma);
 932
 933   return status;
 934 }
 935
 936 /**
 937   * @}
 938   */
 939
 940
 941
 942 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
 943   *  @brief    Peripheral State and Errors functions
 944   *
 945 @verbatim
 946  ===============================================================================
 947             ##### Peripheral State and Errors functions #####
 948  ===============================================================================
 949     [..]
 950     This subsection provides functions allowing to
 951       (+) Check the DMA state
 952       (+) Get error code
 953
 954 @endverbatim
 955   * @{
 956   */
 957
 958 /**
 959   * @brief  Return the DMA hande state.
 960   * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 961   *               the configuration information for the specified DMA Channel.
 962   * @retval HAL state
 963   */
 964 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
 965 {
 966   /* Return DMA handle state */
 967   return hdma->State;
 968 }
 969
 970 /**
 971   * @brief  Return the DMA error code.
 972   * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
 973   *              the configuration information for the specified DMA Channel.
 974   * @retval DMA Error Code
 975   */
 976 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 977 {
 978   return hdma->ErrorCode;
 979 }
 980
 981 /**
 982   * @}
 983   */
 984
 985 /**
 986   * @}
 987   */
 988
 989 /** @addtogroup DMA_Private_Functions
 990   * @{
 991   */
 992
 993 /**
 994   * @brief  Sets the DMA Transfer parameter.
 995   * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
 996   *                     the configuration information for the specified DMA Channel.
 997   * @param  SrcAddress The source memory Buffer address
 998   * @param  DstAddress The destination memory Buffer address
 999   * @param  DataLength The length of data to be transferred from source to destination
1000   * @retval HAL status
1001   */
1002 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
1003 {
1004   /* Clear the DMAMUX synchro overrun flag */
1005   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
1006
1007   if (hdma->DMAmuxRequestGen != 0U)
1008   {
1009     /* Clear the DMAMUX request generator overrun flag */
1010     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
1011   }
1012
1013   /* Clear all flags */
1014   hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
1015
1016   /* Configure DMA Channel data length */
1017   hdma->Instance->CNDTR = DataLength;
1018
1019   /* Memory to Peripheral */
1020   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
1021   {
1022     /* Configure DMA Channel destination address */
1023     hdma->Instance->CPAR = DstAddress;
1024
1025     /* Configure DMA Channel source address */
1026     hdma->Instance->CMAR = SrcAddress;
1027   }
1028   /* Peripheral to Memory */
1029   else
1030   {
1031     /* Configure DMA Channel source address */
1032     hdma->Instance->CPAR = SrcAddress;
1033
1034     /* Configure DMA Channel destination address */
1035     hdma->Instance->CMAR = DstAddress;
1036   }
1037 }
1038
1039 /**
1040   * @brief  Updates the DMA handle with the DMAMUX  channel and status mask depending on stream number
1041   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
1042   *                     the configuration information for the specified DMA Stream.
1043   * @retval None
1044   */
1045 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
1046 {
1047   uint32_t dmamux_base_addr;
1048   uint32_t channel_number;
1049   DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
1050
1051   /* check if instance is not outside the DMA channel range */
1052   if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
1053   {
1054     /* DMA1 */
1055     DMAMUX1_ChannelBase = DMAMUX1_Channel0;
1056   }
1057   else
1058   {
1059     /* DMA2 */
1060 #if defined (STM32G474xx) || defined (STM32G473xx) || defined (STM32G471xx) || defined (STM32G484xx)
1061     DMAMUX1_ChannelBase = DMAMUX1_Channel8;
1062 #elif defined (STM32G431xx) || defined (STM32G441xx) || defined (STM32GBK1CB)
1063     DMAMUX1_ChannelBase = DMAMUX1_Channel6;
1064 #else
1065     DMAMUX1_ChannelBase = DMAMUX1_Channel7;
1066 #endif /* STM32G4x1xx) */
1067   }
1068   dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
1069   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1070   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
1071   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
1072   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
1073 }
1074
1075 /**
1076   * @brief  Updates the DMA handle with the DMAMUX  request generator params
1077   * @param  hdma        pointer to a DMA_HandleTypeDef structure that contains
1078   *                     the configuration information for the specified DMA Channel.
1079   * @retval None
1080   */
1081
1082 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
1083 {
1084   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
1085
1086   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
1087   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
1088
1089   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
1090
1091   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
1092 }
1093
1094 /**
1095   * @}
1096   */
1097
1098 /**
1099   * @}
1100   */
1101
1102 #endif /* HAL_DMA_MODULE_ENABLED */
1103 /**
1104   * @}
1105   */
1106
1107 /**
1108   * @}
1109   */
1110
1111 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/