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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Src / stm32g4xx_hal_hrtim.c
blobb8eb52723e0bcc391cd38ad9509a1b40f4ba0bb1
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_hrtim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the High Resolution Timer (HRTIM) peripheral:
8 * + HRTIM Initialization
9 * + DLL Calibration Start
10 * + Timer Time Base Unit Configuration
11 * + Simple Time Base Start/Stop
12 * + Simple Time Base Start/Stop Interrupt
13 * + Simple Time Base Start/Stop DMA Request
14 * + Simple Output Compare/PWM Channel Configuration
15 * + Simple Output Compare/PWM Channel Start/Stop Interrupt
16 * + Simple Output Compare/PWM Channel Start/Stop DMA Request
17 * + Simple Input Capture Channel Configuration
18 * + Simple Input Capture Channel Start/Stop Interrupt
19 * + Simple Input Capture Channel Start/Stop DMA Request
20 * + Simple One Pulse Channel Configuration
21 * + Simple One Pulse Channel Start/Stop Interrupt
22 * + HRTIM External Synchronization Configuration
23 * + HRTIM Burst Mode Controller Configuration
24 * + HRTIM Burst Mode Controller Enabling
25 * + HRTIM External Events Conditioning Configuration
26 * + HRTIM Faults Conditioning Configuration
27 * + HRTIM Faults Enabling
28 * + HRTIM ADC trigger Configuration
29 * + Waveform Timer Configuration
30 * + Waveform Event Filtering Configuration
31 * + Waveform Dead Time Insertion Configuration
32 * + Waveform Chopper Mode Configuration
33 * + Waveform Compare Unit Configuration
34 * + Waveform Capture Unit Configuration
35 * + Waveform Output Configuration
36 * + Waveform Counter Start/Stop
37 * + Waveform Counter Start/Stop Interrupt
38 * + Waveform Counter Start/Stop DMA Request
39 * + Waveform Output Enabling
40 * + Waveform Output Level Set/Get
41 * + Waveform Output State Get
42 * + Waveform Burst DMA Operation Configuration
43 * + Waveform Burst DMA Operation Start
44 * + Waveform Timer Counter Software Reset
45 * + Waveform Capture Software Trigger
46 * + Waveform Burst Mode Controller Software Trigger
47 * + Waveform Timer Pre-loadable Registers Update Enabling
48 * + Waveform Timer Pre-loadable Registers Software Update
49 * + Waveform Timer Delayed Protection Status Get
50 * + Waveform Timer Burst Status Get
51 * + Waveform Timer Push-Pull Status Get
52 * + Peripheral State Get
53 @verbatim
54 ==============================================================================
55 ##### Simple mode v.s. waveform mode #####
56 ==============================================================================
57 [..] The HRTIM HAL API is split into 2 categories:
58 (#)Simple functions: these functions allow for using a HRTIM timer as a
59 general purpose timer with high resolution capabilities.
60 HRTIM simple modes are managed through the set of functions named
61 HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
62 to the one defined for the TIM peripheral. When a HRTIM timer operates in
63 simple mode, only a very limited set of HRTIM features are used.
64 Following simple modes are proposed:
65 (++)Output compare mode,
66 (++)PWM output mode,
67 (++)Input capture mode,
68 (++)One pulse mode.
69 (#)Waveform functions: These functions allow taking advantage of the HRTIM
70 flexibility to produce numerous types of control signal. When a HRTIM timer
71 operates in waveform mode, all the HRTIM features are accessible without
72 any restriction. HRTIM waveform modes are managed through the set of
73 functions named HAL_HRTIM_Waveform<Function>
74 ##### How to use this driver #####
75 ==============================================================================
76 [..]
77 (#)Initialize the HRTIM low level resources by implementing the
78 HAL_HRTIM_MspInit() function:
79 (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
80 (##)Connect HRTIM pins to MCU I/Os
81 (+++) Enable the clock for the HRTIM GPIOs using the following
82 function: __HAL_RCC_GPIOx_CLK_ENABLE()
83 (+++) Configure these GPIO pins in Alternate Function mode using
84 HAL_GPIO_Init()
85 (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
86 (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
87 (+++)Initialize the DMA handle
88 (+++)Associate the initialized DMA handle to the appropriate DMA
89 handle of the HRTIM handle using __HAL_LINKDMA()
90 (+++)Initialize the DMA channel using HAL_DMA_Init()
91 (+++)Configure the priority and enable the NVIC for the transfer
92 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
93 and HAL_NVIC_EnableIRQ()
94 (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
95 (+++)Configure the priority and enable the NVIC for the concerned
96 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
97
98 (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
99 structure (field of the HRTIM handle) specifies which global interrupt of
100 whole HRTIM must be enabled (Burst mode period, System fault, Faults).
101 It also contains the HRTIM external synchronization configuration. HRTIM
102 can act as a master (generating a synchronization signal) or as a slave
103 (waiting for a trigger to be synchronized).
104
105 (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
106 calibration is executed periodically and compensate for potential voltage
107 and temperature drifts. DLL calibration period is specified by the
108 CalibrationRate argument.
109
110 (#)HRTIM timers cannot be used until the high resolution unit is ready. This
111 can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
112 HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
113 is still going on when timeout given as argument expires. DLL calibration
114 can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
115 In that case an interrupt is generated when the DLL calibration is completed.
116 Note that as DLL calibration is executed on a periodic basis an interrupt
117 will be generated at the end of every DLL calibration operation
118 (worst case: one interrupt every 14 micro seconds !).
119
120 (#) Configure HRTIM resources shared by all HRTIM timers
121 (##)Burst Mode Controller:
122 (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
123 controller: operating mode (continuous or one-shot mode), clock
124 (source, prescaler) , trigger(s), period, idle duration.
125 (##)External Events Conditioning:
126 (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
127 external event channel: source, polarity, edge-sensitivity.
128 External event can be used as triggers (timer reset, input
129 capture, burst mode, ADC triggers, delayed protection)
130 They can also be used to set or reset timer outputs. Up to
131 10 event channels are available.
132 (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
133 event sampling clock (used for digital filtering).
134 (##)Fault Conditioning:
135 (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
136 fault channel: source, polarity, edge-sensitivity. Fault
137 channels are used to disable the outputs in case of an
138 abnormal operation. Up to 6 fault channels are available.
139 (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
140 sampling clock (used for digital filtering).
141 (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
142 circuitry. By default all fault inputs are disabled.
143 (##)ADC trigger:
144 (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
145 the update of the ADC trigger register and the ADC trigger.
146 4 independent triggers are available to start both the regular
147 and the injected sequencers of the 2 ADCs
148
149 (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
150 function must be called whatever the HRTIM timer operating mode is
151 (simple v.s. waveform). It configures mainly:
152 (##)The HRTIM timer counter operating mode (continuous v.s. one shot)
153 (##)The HRTIM timer clock prescaler
154 (##)The HRTIM timer period
155 (##)The HRTIM timer repetition counter
156
157 *** If the HRTIM timer operates in simple mode ***
158 ===================================================
159 [..]
160 (#) Start or Stop simple timers
161 (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
162 HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
163 HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
164 (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
165 HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
166 HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
167 HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
168 (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
169 HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
170 HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
171 HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
172 (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
173 HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
174 HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
175 HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
176 (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
177 HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
178 HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
179
180 *** If the HRTIM timer operates in waveform mode ***
181 ====================================================
182 [..]
183 (#) Completes waveform timer configuration
184 (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
185 operating in wave form mode mainly consists in:
186 (+++)Enabling the HRTIM timer interrupts and DMA requests.
187 (+++)Enabling the half mode for the HRTIM timer.
188 (+++)Defining how the HRTIM timer reacts to external synchronization input.
189 (+++)Enabling the push-pull mode for the HRTIM timer.
190 (+++)Enabling the fault channels for the HRTIM timer.
191 (+++)Enabling the dead-time insertion for the HRTIM timer.
192 (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
193 on which the delayed protection are applied).
194 (+++)Specifying the HRTIM timer update and reset triggers.
195 (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
196 (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
197 event blanking and windowing circuitry of a HRTIM timer:
198 (+++)Blanking: to mask external events during a defined time period a defined time period
199 (+++)Windowing, to enable external events only during a defined time period
200 (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
201 unit for a HRTIM timer. Allows to generate a couple of
202 complementary signals from a single reference waveform,
203 with programmable delays between active state.
204 (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
205 the high-frequency carrier signal added on top of the timing
206 unit output. Chopper mode can be enabled or disabled for each
207 timer output separately (see HAL_HRTIM_WaveformOutputConfig()).
208 (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
209 controller. Allows having multiple HRTIM registers updated
210 with a single DMA request. The burst DMA operation is started
211 by calling HAL_HRTIM_BurstDMATransfer().
212 (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
213 of a HRTIM timer. This operation consists in setting the
214 compare value and possibly specifying the auto delayed mode
215 for compare units 2 and 4 (allows to have compare events
216 generated relatively to capture events). Note that when auto
217 delayed mode is needed, the capture unit associated to the
218 compare unit must be configured separately.
219 (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
220 of a HRTIM timer. This operation consists in specifying the
221 source(s) triggering the capture (timer register update event,
222 external event, timer output set/reset event, other HRTIM
223 timer related events).
224 (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
225 output mainly consists in:
226 (+++)Setting the output polarity (active high or active low),
227 (+++)Defining the set/reset crossbar for the output,
228 (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
229
230 (#) Set waveform timer output(s) level
231 (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
232 active or inactive level. For example, when deadtime insertion
233 is enabled it is necessary to force the output level by software
234 to have the outputs in a complementary state as soon as the RUN mode is entered.
235
236 (#) Enable or Disable waveform timer output(s)
237 (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
238
239 (#) Start or Stop waveform HRTIM timer(s).
240 (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
241 (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
242 (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
243 (#) Burst mode controller enabling:
244 (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
245 burst mode controller.
246
247 (#) Some HRTIM operations can be triggered by software:
248 (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
249 trigs the burst operation.
250 (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
251 capture of the HRTIM timer counter.
252 (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
253 update of the pre-loadable registers of the HRTIM timer
254 (++)HAL_HRTIM_SoftwareReset():calling this function resets the
255 HRTIM timer counter.
256
257 (#) Some functions can be used any time to retrieve HRTIM timer related
258 information
259 (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
260 capture register of the designated capture unit.
261 (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
262 (ACTIVE/INACTIVE) of the designated timer output.
263 (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
264 (IDLE/RUN/FAULT) of the designated timer output.
265 (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
266 (ACTIVE/INACTIVE) of the designated output when the delayed
267 protection was triggered.
268 (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
269 (ACTIVE/INACTIVE) of the burst mode controller.
270 (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
271 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
272 the push-pull status indicates on which output the signal is currently
273 active (e.g signal applied on output 1 and output 2 forced
274 inactive or vice versa).
275 (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
276 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
277 the idle push-pull status indicates during which period the
278 delayed protection request occurred (e.g. protection occurred
279 when the output 1 was active and output 2 forced inactive or
280 vice versa).
281
282 (#) Some functions can be used any time to retrieve actual HRTIM status
283 (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
284
285 *** Callback registration ***
286 =============================
287 [..]
288 The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
289 allows the user to configure dynamically the driver callbacks.
290 Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
291 to register an interrupt callback.
292
293 Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
294 (+) Fault1Callback : Fault 1 interrupt callback function
295 (+) Fault2Callback : Fault 2 interrupt callback function
296 (+) Fault3Callback : Fault 3 interrupt callback function
297 (+) Fault4Callback : Fault 4 interrupt callback function
298 (+) Fault5Callback : Fault 5 interrupt callback function
299 (+) Fault6Callback : Fault 6 interrupt callback function
300 (+) SystemFaultCallback : System fault interrupt callback function
301 (+) DLLCalibrationReadyCallback : DLL Ready interrupt callback function
302 (+) BurstModePeriodCallback : Burst mode period interrupt callback function
303 (+) SynchronizationEventCallback : Sync Input interrupt callback function
304 (+) ErrorCallback : DMA error callback function
305 (+) MspInitCallback : HRTIM MspInit callback function
306 (+) MspDeInitCallback : HRTIM MspInit callback function
307
308 Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
309 (+) RegistersUpdateCallback : Timer x Update interrupt callback function
310 (+) RepetitionEventCallback : Timer x Repetition interrupt callback function
311 (+) Compare1EventCallback : Timer x Compare 1 match interrupt callback function
312 (+) Compare2EventCallback : Timer x Compare 2 match interrupt callback function
313 (+) Compare3EventCallback : Timer x Compare 3 match interrupt callback function
314 (+) Compare4EventCallback : Timer x Compare 4 match interrupt callback function
315 (+) Capture1EventCallback : Timer x Capture 1 interrupts callback function
316 (+) Capture2EventCallback : Timer x Capture 2 interrupts callback function
317 (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
318 (+) CounterResetCallback : Timer x counter reset/roll-over interrupt callback function
319 (+) Output1SetCallback : Timer x output 1 set interrupt callback function
320 (+) Output1ResetCallback : Timer x output 1 reset interrupt callback function
321 (+) Output2SetCallback : Timer x output 2 set interrupt callback function
322 (+) Output2ResetCallback : Timer x output 2 reset interrupt callback function
323 (+) BurstDMATransferCallback : Timer x Burst DMA completed interrupt callback function
324
325 Both functions take as parameters the HAL peripheral handle, the Callback ID
326 and a pointer to the user callback function.
327
328 Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
329 to reset a callback to the default weak function. Both functions take as parameters
330 the HAL peripheral handle and the Callback ID.
331
332 By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
333 all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
334 Exception done for MspInit and MspDeInit functions that are reset to the legacy
335 weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
336 callbacks are null (not registered beforehand). If MspInit or MspDeInit are
337 not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
338 MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
339
340 Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
341 Exception done MspInit/MspDeInit functions that can be registered/unregistered
342 in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
343 (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
344 Then, the user first registers the MspInit/MspDeInit user callbacks
345 using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
346 or @ref HAL_HRTIM_Init() function.
347
348 When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
349 not defined, the callback registration feature is not available and all
350 callbacks are set to the corresponding weak functions.
351
352 @endverbatim
353
354 ******************************************************************************
355 * @attention
356 *
357 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
358 * All rights reserved.</center></h2>
359 *
360 * This software component is licensed by ST under BSD 3-Clause license,
361 * the "License"; You may not use this file except in compliance with the
362 * License. You may obtain a copy of the License at:
363 * opensource.org/licenses/BSD-3-Clause
364 *
365 ******************************************************************************
366 */
367
368 /* Includes ------------------------------------------------------------------*/
369 #include "stm32g4xx_hal.h"
370
371 /** @addtogroup STM32G4xx_HAL_Driver
372 * @{
373 */
374
375 #ifdef HAL_HRTIM_MODULE_ENABLED
376
377 #if defined(HRTIM1)
378
379 /** @defgroup HRTIM HRTIM
380 * @brief HRTIM HAL module driver
381 * @{
382 */
383
384 /* Private typedef -----------------------------------------------------------*/
385 /* Private define ------------------------------------------------------------*/
386 /** @defgroup HRTIM_Private_Defines HRTIM Private Define
387 * @{
388 */
389 #define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
390 HRTIM_FLTR_FLT2EN |\
391 HRTIM_FLTR_FLT3EN |\
392 HRTIM_FLTR_FLT4EN | \
393 HRTIM_FLTR_FLT5EN | \
394 HRTIM_FLTR_FLT6EN)
395
396 #define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
397 HRTIM_TIMUPDATETRIGGER_TIMER_A |\
398 HRTIM_TIMUPDATETRIGGER_TIMER_B |\
399 HRTIM_TIMUPDATETRIGGER_TIMER_C |\
400 HRTIM_TIMUPDATETRIGGER_TIMER_D |\
401 HRTIM_TIMUPDATETRIGGER_TIMER_E |\
402 HRTIM_TIMUPDATETRIGGER_TIMER_F)
403
404 #define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
405 (HRTIM_FAULTLOCK_READONLY << 8U) | \
406 (HRTIM_FAULTLOCK_READONLY << 16U) | \
407 (HRTIM_FAULTLOCK_READONLY << 24U))
408
409 #define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY) | \
410 (HRTIM_FAULTLOCK_READONLY << 8U))
411 /**
412 * @}
413 */
414
415 /* Private macro -------------------------------------------------------------*/
416 /* Private variables ---------------------------------------------------------*/
417 /** @defgroup HRTIM_Private_Variables HRTIM Private Variables
418 * @{
419 */
420 static uint32_t TimerIdxToTimerId[] =
421 {
422 HRTIM_TIMERID_TIMER_A,
423 HRTIM_TIMERID_TIMER_B,
424 HRTIM_TIMERID_TIMER_C,
425 HRTIM_TIMERID_TIMER_D,
426 HRTIM_TIMERID_TIMER_E,
427 HRTIM_TIMERID_TIMER_F,
428 HRTIM_TIMERID_MASTER,
429 };
430 /**
431 * @}
432 */
433
434 /* Private function prototypes -----------------------------------------------*/
435 /** @defgroup HRTIM_Private_Functions HRTIM Private Functions
436 * @{
437 */
438 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
439 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
440
441 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
442 uint32_t TimerIdx,
443 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
444
445 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
446 HRTIM_TimerCfgTypeDef * pTimerCfg);
447
448 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
449 uint32_t TimerIdx,
450 HRTIM_TimerCfgTypeDef * pTimerCfg);
451
452 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
453 uint32_t TimerIdx,
454 HRTIM_TimerCtlTypeDef * pTimerCtl);
455
456 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
457 uint32_t TimerIdx,
458 uint32_t pRollOverMode);
459
460
461 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
462 uint32_t TimerIdx,
463 uint32_t CaptureUnit,
464 uint32_t Event);
465
466 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
467 uint32_t TimerIdx,
468 uint32_t Output,
469 HRTIM_OutputCfgTypeDef * pOutputCfg);
470
471 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
472 uint32_t Event,
473 HRTIM_EventCfgTypeDef * pEventCfg);
474
475 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
476 uint32_t TimerIdx,
477 uint32_t Event);
478
479 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
480 uint32_t TimerIdx,
481 uint32_t OCChannel);
482
483 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
484 uint32_t TimerIdx,
485 uint32_t OCChannel);
486
487 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
488 uint32_t TimerIdx);
489
490 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
491 DMA_HandleTypeDef * hdma);
492
493 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
494 uint32_t TimerIdx);
495
496 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim);
497
498 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim);
499
500 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
501 uint32_t TimerIdx);
502
503 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
504
505 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
506
507 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
508
509 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
510 /**
511 * @}
512 */
513
514 /* Exported functions ---------------------------------------------------------*/
515 /** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
516 * @{
517 */
518
519 /** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
520 * @brief Initialization and Configuration functions
521 @verbatim
522 ===============================================================================
523 ##### Initialization and Time Base Configuration functions #####
524 ===============================================================================
525 [..] This section provides functions allowing to:
526 (+) Initialize a HRTIM instance
527 (+) De-initialize a HRTIM instance
528 (+) Initialize the HRTIM MSP
529 (+) De-initialize the HRTIM MSP
530 (+) Start the high-resolution unit (start DLL calibration)
531 (+) Check that the high resolution unit is ready (DLL calibration done)
532 (+) Configure the time base unit of a HRTIM timer
533
534 @endverbatim
535 * @{
536 */
537
538 /**
539 * @brief Initialize a HRTIM instance
540 * @param hhrtim pointer to HAL HRTIM handle
541 * @retval HAL status
542 */
543 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef * hhrtim)
544 {
545 uint8_t timer_idx;
546 uint32_t hrtim_mcr;
547
548 /* Check the HRTIM handle allocation */
549 if(hhrtim == NULL)
550 {
551 return HAL_ERROR;
552 }
553
554 /* Check the parameters */
555 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
556 assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptResquests));
557
558 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
559 if (hhrtim->State == HAL_HRTIM_STATE_RESET)
560 {
561 /* Initialize callback function pointers to their default values */
562 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
563 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
564 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
565 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
566 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
567 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
568 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
569 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
570 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
571 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
572 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
573 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
574 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
575 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
576 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
577 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
578 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
579 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
580 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
581 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
582 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
583 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
584 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
585 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
586 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
587 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
588
589 if (hhrtim->MspInitCallback == NULL)
590 {
591 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
592 }
593 }
594 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
595
596 /* Set the HRTIM state */
597 hhrtim->State = HAL_HRTIM_STATE_BUSY;
598
599 /* Initialize the DMA handles */
600 hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
601 hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
602 hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
603 hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
604 hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
605 hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
606 hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
607
608 /* HRTIM output synchronization configuration (if required) */
609 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
610 {
611 /* Check parameters */
612 assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
613 assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
614
615 /* The synchronization output initialization procedure must be done prior
616 to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
617 */
618 if (hhrtim->Instance == HRTIM1)
619 {
620 /* Enable the HRTIM peripheral clock */
621 __HAL_RCC_HRTIM1_CLK_ENABLE();
622 }
623
624 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
625
626 /* Set the event to be sent on the synchronization output */
627 hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
628 hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
629
630 /* Set the polarity of the synchronization output */
631 hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
632 hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
633
634 /* Update the HRTIM registers */
635 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
636 }
637
638 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
639 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
640 hhrtim->MspInitCallback(hhrtim);
641 #else
642 HAL_HRTIM_MspInit(hhrtim);
643 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
644
645 /* HRTIM input synchronization configuration (if required) */
646 if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
647 {
648 /* Check parameters */
649 assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
650
651 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
652
653 /* Set the synchronization input source */
654 hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
655 hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
656
657 /* Update the HRTIM registers */
658 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
659 }
660
661 /* Initialize the HRTIM state*/
662 hhrtim->State = HAL_HRTIM_STATE_READY;
663
664 /* Initialize the lock status of the HRTIM HAL API */
665 __HAL_UNLOCK(hhrtim);
666
667 /* Initialize timer related parameters */
668 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
669 timer_idx <= HRTIM_TIMERINDEX_MASTER ;
670 timer_idx++)
671 {
672 hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
673 hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
674 hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
675 hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
676 hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
677 hhrtim->TimerParam[timer_idx].DMASize = 0U;
678 }
679
680 return HAL_OK;
681 }
682
683 /**
684 * @brief De-initialize a HRTIM instance
685 * @param hhrtim pointer to HAL HRTIM handle
686 * @retval HAL status
687 */
688 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef * hhrtim)
689 {
690 /* Check the HRTIM handle allocation */
691 if(hhrtim == NULL)
692 {
693 return HAL_ERROR;
694 }
695
696 /* Check the parameters */
697 assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
698
699 /* Set the HRTIM state */
700 hhrtim->State = HAL_HRTIM_STATE_BUSY;
701
702 /* DeInit the low level hardware */
703 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
704 if (hhrtim->MspDeInitCallback == NULL)
705 {
706 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
707 }
708
709 hhrtim->MspDeInitCallback(hhrtim);
710 #else
711 HAL_HRTIM_MspDeInit(hhrtim);
712 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
713
714 hhrtim->State = HAL_HRTIM_STATE_READY;
715
716 return HAL_OK;
717 }
718
719 /**
720 * @brief MSP initialization for a HRTIM instance
721 * @param hhrtim pointer to HAL HRTIM handle
722 * @retval None
723 */
724 __weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef * hhrtim)
725 {
726 /* Prevent unused argument(s) compilation warning */
727 UNUSED(hhrtim);
728
729 /* NOTE: This function should not be modified, when the callback is needed,
730 the HAL_HRTIM_MspInit could be implemented in the user file
731 */
732 }
733
734 /**
735 * @brief MSP de-initialization of a HRTIM instance
736 * @param hhrtim pointer to HAL HRTIM handle
737 * @retval None
738 */
739 __weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef * hhrtim)
740 {
741 /* Prevent unused argument(s) compilation warning */
742 UNUSED(hhrtim);
743
744 /* NOTE: This function should not be modified, when the callback is needed,
745 the HAL_HRTIM_MspDeInit could be implemented in the user file
746 */
747 }
748
749 /**
750 * @brief Start the DLL calibration
751 * @param hhrtim pointer to HAL HRTIM handle
752 * @param CalibrationRate DLL calibration period
753 * This parameter can be one of the following values:
754 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
755 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
756 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
757 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
758 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
759 * @retval HAL status
760 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
761 * within the HAL_HRTIM_PollForDLLCalibration function, just before
762 * exiting the function.
763 */
764 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef * hhrtim,
765 uint32_t CalibrationRate)
766 {
767 /* Check the parameters */
768 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
769
770 /* Process Locked */
771 __HAL_LOCK(hhrtim);
772
773 hhrtim->State = HAL_HRTIM_STATE_BUSY;
774
775 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
776 {
777 /* One shot DLL calibration */
778 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
779 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
780 }
781 else
782 {
783 /* Periodic DLL calibration */
784 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
785 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
786 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
787 }
788
789 return HAL_OK;
790 }
791
792 /**
793 * @brief Start the DLL calibration.
794 * DLL ready interrupt is enabled
795 * @param hhrtim pointer to HAL HRTIM handle
796 * @param CalibrationRate DLL calibration period
797 * This parameter can be one of the following values:
798 * @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
799 * @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
800 * @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
801 * @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
802 * @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
803 * @retval HAL status
804 * @note This function locks the HRTIM instance. HRTIM instance is unlocked
805 * within the IRQ processing function when processing the DLL ready
806 * interrupt.
807 * @note If this function is called for periodic calibration, the DLLRDY
808 * interrupt is generated every time the calibration completes which
809 * will significantly increases the overall interrupt rate.
810 */
811 HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef * hhrtim,
812 uint32_t CalibrationRate)
813 {
814 /* Check the parameters */
815 assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
816
817 /* Process Locked */
818 __HAL_LOCK(hhrtim);
819
820 hhrtim->State = HAL_HRTIM_STATE_BUSY;
821
822 /* Enable DLL Ready interrupt flag */
823 __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
824
825 if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
826 {
827 /* One shot DLL calibration */
828 CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
829 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
830 }
831 else
832 {
833 /* Periodic DLL calibration */
834 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
835 MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
836 SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
837 }
838
839 return HAL_OK;
840 }
841
842 /**
843 * @brief Poll the DLL calibration ready flag and returns when the flag is
844 * set (DLL calibration completed) or upon timeout expiration.
845 * @param hhrtim pointer to HAL HRTIM handle
846 * @param Timeout Timeout duration in millisecond
847 * @retval HAL status
848 */
849 HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef * hhrtim,
850 uint32_t Timeout)
851 {
852 uint32_t tickstart;
853
854 tickstart = HAL_GetTick();
855
856 /* Check End of conversion flag */
857 while(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
858 {
859 if (Timeout != HAL_MAX_DELAY)
860 {
861 if(((HAL_GetTick()-tickstart) > Timeout) || (Timeout == 0U))
862 {
863 hhrtim->State = HAL_HRTIM_STATE_ERROR;
864 return HAL_TIMEOUT;
865 }
866 }
867 }
868
869 /* Set HRTIM State */
870 hhrtim->State = HAL_HRTIM_STATE_READY;
871
872 /* Process unlocked */
873 __HAL_UNLOCK(hhrtim);
874
875 return HAL_OK;
876 }
877
878 /**
879 * @brief Configure the time base unit of a timer
880 * @param hhrtim pointer to HAL HRTIM handle
881 * @param TimerIdx Timer index
882 * This parameter can be one of the following values:
883 * @arg HRTIM_TIMERINDEX_MASTER for master timer
884 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
885 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
886 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
887 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
888 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
889 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
890 * @param pTimeBaseCfg pointer to the time base configuration structure
891 * @note This function must be called prior starting the timer
892 * @note The time-base unit initialization parameters specify:
893 * The timer counter operating mode (continuous, one shot),
894 * The timer clock prescaler,
895 * The timer period,
896 * The timer repetition counter.
897 * @retval HAL status
898 */
899 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
900 uint32_t TimerIdx,
901 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
902 {
903 /* Check the parameters */
904 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
905 assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
906 assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
907
908 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
909 {
910 return HAL_BUSY;
911 }
912
913 /* Set the HRTIM state */
914 hhrtim->State = HAL_HRTIM_STATE_BUSY;
915
916 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
917 {
918 /* Configure master timer time base unit */
919 HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
920 }
921 else
922 {
923 /* Configure timing unit time base unit */
924 HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
925 }
926
927 /* Set HRTIM state */
928 hhrtim->State = HAL_HRTIM_STATE_READY;
929
930 return HAL_OK;
931 }
932
933 /**
934 * @}
935 */
936
937 /** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
938 * @brief Simple time base mode functions.
939 @verbatim
940 ===============================================================================
941 ##### Simple time base mode functions #####
942 ===============================================================================
943 [..] This section provides functions allowing to:
944 (+) Start simple time base
945 (+) Stop simple time base
946 (+) Start simple time base and enable interrupt
947 (+) Stop simple time base and disable interrupt
948 (+) Start simple time base and enable DMA transfer
949 (+) Stop simple time base and disable DMA transfer
950 -@- When a HRTIM timer operates in simple time base mode, the timer
951 counter counts from 0 to the period value.
952
953 @endverbatim
954 * @{
955 */
956
957 /**
958 * @brief Start the counter of a timer operating in simple time base mode.
959 * @param hhrtim pointer to HAL HRTIM handle
960 * @param TimerIdx Timer index.
961 * This parameter can be one of the following values:
962 * @arg HRTIM_TIMERINDEX_MASTER for master timer
963 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
964 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
965 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
966 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
967 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
968 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
969 * @retval HAL status
970 */
971 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef * hhrtim,
972 uint32_t TimerIdx)
973 {
974 /* Check the parameters */
975 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
976
977 /* Process Locked */
978 __HAL_LOCK(hhrtim);
979
980 hhrtim->State = HAL_HRTIM_STATE_BUSY;
981
982 /* Enable the timer counter */
983 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
984
985 hhrtim->State = HAL_HRTIM_STATE_READY;
986
987 /* Process Unlocked */
988 __HAL_UNLOCK(hhrtim);
989
990 return HAL_OK;
991 }
992
993 /**
994 * @brief Stop the counter of a timer operating in simple time base mode.
995 * @param hhrtim pointer to HAL HRTIM handle
996 * @param TimerIdx Timer index.
997 * This parameter can be one of the following values:
998 * @arg HRTIM_TIMERINDEX_MASTER for master timer
999 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1000 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1001 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1002 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1003 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1004 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1005 * @retval HAL status
1006 */
1007 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef * hhrtim,
1008 uint32_t TimerIdx)
1009 {
1010 /* Check the parameters */
1011 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1012
1013 /* Process Locked */
1014 __HAL_LOCK(hhrtim);
1015
1016 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1017
1018 /* Disable the timer counter */
1019 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1020
1021 hhrtim->State = HAL_HRTIM_STATE_READY;
1022
1023 /* Process Unlocked */
1024 __HAL_UNLOCK(hhrtim);
1025
1026 return HAL_OK;
1027 }
1028
1029 /**
1030 * @brief Start the counter of a timer operating in simple time base mode
1031 * (Timer repetition interrupt is enabled).
1032 * @param hhrtim pointer to HAL HRTIM handle
1033 * @param TimerIdx Timer index.
1034 * This parameter can be one of the following values:
1035 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1036 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1037 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1038 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1039 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1040 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1041 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1042 * @retval HAL status
1043 */
1044 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef * hhrtim,
1045 uint32_t TimerIdx)
1046 {
1047 /* Check the parameters */
1048 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1049
1050 /* Process Locked */
1051 __HAL_LOCK(hhrtim);
1052
1053 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1054
1055 /* Enable the repetition interrupt */
1056 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1057 {
1058 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1059 }
1060 else
1061 {
1062 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1063 }
1064
1065 /* Enable the timer counter */
1066 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1067
1068 hhrtim->State = HAL_HRTIM_STATE_READY;
1069
1070 /* Process Unlocked */
1071 __HAL_UNLOCK(hhrtim);
1072
1073 return HAL_OK;
1074 }
1075
1076 /**
1077 * @brief Stop the counter of a timer operating in simple time base mode
1078 * (Timer repetition interrupt is disabled).
1079 * @param hhrtim pointer to HAL HRTIM handle
1080 * @param TimerIdx Timer index.
1081 * This parameter can be one of the following values:
1082 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1083 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1084 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1085 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1086 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1087 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1088 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1089 * @retval HAL status
1090 */
1091 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef * hhrtim,
1092 uint32_t TimerIdx)
1093 {
1094 /* Check the parameters */
1095 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1096
1097 /* Process Locked */
1098 __HAL_LOCK(hhrtim);
1099
1100 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1101
1102 /* Disable the repetition interrupt */
1103 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1104 {
1105 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
1106 }
1107 else
1108 {
1109 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
1110 }
1111
1112 /* Disable the timer counter */
1113 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1114
1115 hhrtim->State = HAL_HRTIM_STATE_READY;
1116
1117 /* Process Unlocked */
1118 __HAL_UNLOCK(hhrtim);
1119
1120 return HAL_OK;
1121 }
1122
1123 /**
1124 * @brief Start the counter of a timer operating in simple time base mode
1125 * (Timer repetition DMA request is enabled).
1126 * @param hhrtim pointer to HAL HRTIM handle
1127 * @param TimerIdx Timer index.
1128 * This parameter can be one of the following values:
1129 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1130 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1131 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1132 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1133 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1134 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1135 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1136 * @param SrcAddr DMA transfer source address
1137 * @param DestAddr DMA transfer destination address
1138 * @param Length The length of data items (data size) to be transferred
1139 * from source to destination
1140 */
1141 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1142 uint32_t TimerIdx,
1143 uint32_t SrcAddr,
1144 uint32_t DestAddr,
1145 uint32_t Length)
1146 {
1147 DMA_HandleTypeDef * hdma;
1148
1149 /* Check the parameters */
1150 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1151
1152 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1153 {
1154 return HAL_BUSY;
1155 }
1156 if(hhrtim->State == HAL_HRTIM_STATE_READY)
1157 {
1158 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1159 {
1160 return HAL_ERROR;
1161 }
1162 else
1163 {
1164 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1165 }
1166 }
1167
1168 /* Process Locked */
1169 __HAL_LOCK(hhrtim);
1170
1171 /* Get the timer DMA handler */
1172 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1173
1174 if (hdma == NULL)
1175 {
1176 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1177
1178 /* Process Unlocked */
1179 __HAL_UNLOCK(hhrtim);
1180
1181 return HAL_ERROR;
1182 }
1183
1184 /* Set the DMA transfer completed callback */
1185 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1186 {
1187 hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
1188 }
1189 else
1190 {
1191 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1192 }
1193
1194 /* Set the DMA error callback */
1195 hdma->XferErrorCallback = HRTIM_DMAError ;
1196
1197 /* Enable the DMA channel */
1198 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1199 {
1200 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1201
1202 /* Process Unlocked */
1203 __HAL_UNLOCK(hhrtim);
1204
1205 return HAL_ERROR;
1206 }
1207
1208 /* Enable the timer repetition DMA request */
1209 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1210 {
1211 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1212 }
1213 else
1214 {
1215 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1216 }
1217
1218 /* Enable the timer counter */
1219 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1220
1221 hhrtim->State = HAL_HRTIM_STATE_READY;
1222
1223 /* Process Unlocked */
1224 __HAL_UNLOCK(hhrtim);
1225
1226 return HAL_OK;
1227 }
1228
1229 /**
1230 * @brief Stop the counter of a timer operating in simple time base mode
1231 * (Timer repetition DMA request is disabled).
1232 * @param hhrtim pointer to HAL HRTIM handle
1233 * @param TimerIdx Timer index.
1234 * This parameter can be one of the following values:
1235 * @arg HRTIM_TIMERINDEX_MASTER for master timer
1236 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1237 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1238 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1239 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1240 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1241 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1242 * @retval HAL status
1243 */
1244 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1245 uint32_t TimerIdx)
1246 {
1247 DMA_HandleTypeDef * hdma;
1248
1249 /* Check the parameters */
1250 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
1251
1252 /* Process Locked */
1253 __HAL_LOCK(hhrtim);
1254
1255 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
1256 {
1257 hhrtim->State = HAL_HRTIM_STATE_READY;
1258
1259 /* Disable the DMA */
1260 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
1261 {
1262 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1263 }
1264 /* Disable the timer repetition DMA request */
1265 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
1266 }
1267 else
1268 {
1269 /* Get the timer DMA handler */
1270 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1271
1272 if (hdma == NULL)
1273 {
1274 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1275 }
1276 else
1277 {
1278 hhrtim->State = HAL_HRTIM_STATE_READY;
1279
1280 /* Disable the DMA */
1281 if (HAL_DMA_Abort(hdma) != HAL_OK)
1282 {
1283 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1284 }
1285
1286 /* Disable the timer repetition DMA request */
1287 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
1288 }
1289 }
1290
1291 /* Disable the timer counter */
1292 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1293
1294 /* Process Unlocked */
1295 __HAL_UNLOCK(hhrtim);
1296
1297 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
1298 {
1299 return HAL_ERROR;
1300 }
1301 else
1302 {
1303 return HAL_OK;
1304 }
1305 }
1306
1307 /**
1308 * @}
1309 */
1310
1311 /** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
1312 * @brief Simple output compare functions
1313 @verbatim
1314 ===============================================================================
1315 ##### Simple output compare functions #####
1316 ===============================================================================
1317 [..] This section provides functions allowing to:
1318 (+) Configure simple output channel
1319 (+) Start simple output compare
1320 (+) Stop simple output compare
1321 (+) Start simple output compare and enable interrupt
1322 (+) Stop simple output compare and disable interrupt
1323 (+) Start simple output compare and enable DMA transfer
1324 (+) Stop simple output compare and disable DMA transfer
1325 -@- When a HRTIM timer operates in simple output compare mode
1326 the output level is set to a programmable value when a match
1327 is found between the compare register and the counter.
1328 Compare unit 1 is automatically associated to output 1
1329 Compare unit 2 is automatically associated to output 2
1330 @endverbatim
1331 * @{
1332 */
1333
1334 /**
1335 * @brief Configure an output in simple output compare mode
1336 * @param hhrtim pointer to HAL HRTIM handle
1337 * @param TimerIdx Timer index
1338 * This parameter can be one of the following values:
1339 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1340 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1341 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1342 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1343 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1344 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1345 * @param OCChannel Timer output
1346 * This parameter can be one of the following values:
1347 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1348 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1349 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1350 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1351 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1352 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1353 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1354 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1355 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1356 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1357 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1358 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1359 * @param pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
1360 * @note When the timer operates in simple output compare mode:
1361 * Output 1 is implicitly controlled by the compare unit 1
1362 * Output 2 is implicitly controlled by the compare unit 2
1363 * Output Set/Reset crossbar is set according to the selected output compare mode:
1364 * Toggle: SETxyR = RSTxyR = CMPy
1365 * Active: SETxyR = CMPy, RSTxyR = 0
1366 * Inactive: SETxy =0, RSTxy = CMPy
1367 * @retval HAL status
1368 */
1369 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef * hhrtim,
1370 uint32_t TimerIdx,
1371 uint32_t OCChannel,
1372 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg)
1373 {
1374 uint32_t CompareUnit = (uint32_t)RESET;
1375 HRTIM_OutputCfgTypeDef OutputCfg;
1376
1377 /* Check parameters */
1378 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1379 assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
1380 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
1381 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
1382 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
1383
1384 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
1385 {
1386 return HAL_BUSY;
1387 }
1388
1389 /* Set HRTIM state */
1390 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1391
1392 /* Configure timer compare unit */
1393 switch (OCChannel)
1394 {
1395 case HRTIM_OUTPUT_TA1:
1396 case HRTIM_OUTPUT_TB1:
1397 case HRTIM_OUTPUT_TC1:
1398 case HRTIM_OUTPUT_TD1:
1399 case HRTIM_OUTPUT_TE1:
1400 case HRTIM_OUTPUT_TF1:
1401 {
1402 CompareUnit = HRTIM_COMPAREUNIT_1;
1403 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
1404 break;
1405 }
1406 case HRTIM_OUTPUT_TA2:
1407 case HRTIM_OUTPUT_TB2:
1408 case HRTIM_OUTPUT_TC2:
1409 case HRTIM_OUTPUT_TD2:
1410 case HRTIM_OUTPUT_TE2:
1411 case HRTIM_OUTPUT_TF2:
1412 {
1413 CompareUnit = HRTIM_COMPAREUNIT_2;
1414 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
1415 break;
1416 }
1417 default:
1418 {
1419 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1420
1421 /* Process Unlocked */
1422 __HAL_UNLOCK(hhrtim);
1423
1424 break;
1425 }
1426 }
1427
1428 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1429 {
1430 return HAL_ERROR;
1431 }
1432
1433 /* Configure timer output */
1434 OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
1435 OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
1436 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
1437 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
1438 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
1439 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
1440
1441 switch (pSimpleOCChannelCfg->Mode)
1442 {
1443 case HRTIM_BASICOCMODE_TOGGLE:
1444 {
1445 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1446 {
1447 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1448 }
1449 else
1450 {
1451 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1452 }
1453 OutputCfg.ResetSource = OutputCfg.SetSource;
1454 break;
1455 }
1456
1457 case HRTIM_BASICOCMODE_ACTIVE:
1458 {
1459 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1460 {
1461 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
1462 }
1463 else
1464 {
1465 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
1466 }
1467 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
1468 break;
1469 }
1470
1471 case HRTIM_BASICOCMODE_INACTIVE:
1472 {
1473 if (CompareUnit == HRTIM_COMPAREUNIT_1)
1474 {
1475 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
1476 }
1477 else
1478 {
1479 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
1480 }
1481 OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
1482 break;
1483 }
1484
1485 default:
1486 {
1487 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1488
1489 /* Process Unlocked */
1490 __HAL_UNLOCK(hhrtim);
1491
1492 break;
1493 }
1494 }
1495
1496 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
1497 {
1498 return HAL_ERROR;
1499 }
1500
1501 HRTIM_OutputConfig(hhrtim,
1502 TimerIdx,
1503 OCChannel,
1504 &OutputCfg);
1505
1506 /* Set HRTIM state */
1507 hhrtim->State = HAL_HRTIM_STATE_READY;
1508
1509 return HAL_OK;
1510 }
1511
1512 /**
1513 * @brief Start the output compare signal generation on the designed timer output
1514 * @param hhrtim pointer to HAL HRTIM handle
1515 * @param TimerIdx Timer index
1516 * This parameter can be one of the following values:
1517 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1518 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1519 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1520 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1521 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1522 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1523 * @param OCChannel Timer output
1524 * This parameter can be one of the following values:
1525 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1526 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1527 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1528 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1529 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1530 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1531 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1532 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1533 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1534 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1535 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1536 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1537 * @retval HAL status
1538 */
1539 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef * hhrtim,
1540 uint32_t TimerIdx,
1541 uint32_t OCChannel)
1542 {
1543 /* Check the parameters */
1544 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1545
1546 /* Process Locked */
1547 __HAL_LOCK(hhrtim);
1548
1549 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1550
1551 /* Enable the timer output */
1552 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1553
1554 /* Enable the timer counter */
1555 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1556
1557 hhrtim->State = HAL_HRTIM_STATE_READY;
1558
1559 /* Process Unlocked */
1560 __HAL_UNLOCK(hhrtim);
1561
1562 return HAL_OK;
1563 }
1564
1565 /**
1566 * @brief Stop the output compare signal generation on the designed timer output
1567 * @param hhrtim pointer to HAL HRTIM handle
1568 * @param TimerIdx Timer index
1569 * This parameter can be one of the following values:
1570 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1571 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1572 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1573 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1574 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1575 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1576 * @param OCChannel Timer output
1577 * This parameter can be one of the following values:
1578 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1579 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1580 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1581 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1582 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1583 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1584 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1585 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1586 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1587 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1588 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1589 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1590 * @retval HAL status
1591 */
1592 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef * hhrtim,
1593 uint32_t TimerIdx,
1594 uint32_t OCChannel)
1595 {
1596 /* Check the parameters */
1597 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1598
1599 /* Process Locked */
1600 __HAL_LOCK(hhrtim);
1601
1602 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1603
1604 /* Disable the timer output */
1605 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1606
1607 /* Disable the timer counter */
1608 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1609
1610 hhrtim->State = HAL_HRTIM_STATE_READY;
1611
1612 /* Process Unlocked */
1613 __HAL_UNLOCK(hhrtim);
1614
1615 return HAL_OK;
1616 }
1617
1618 /**
1619 * @brief Start the output compare signal generation on the designed timer output
1620 * (Interrupt is enabled (see note note below)).
1621 * @param hhrtim pointer to HAL HRTIM handle
1622 * @param TimerIdx Timer index
1623 * This parameter can be one of the following values:
1624 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1625 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1626 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1627 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1628 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1629 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1630 * @param OCChannel Timer output
1631 * This parameter can be one of the following values:
1632 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1633 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1634 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1635 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1636 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1637 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1638 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1639 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1640 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1641 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1642 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1643 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1644 * @note Interrupt enabling depends on the chosen output compare mode
1645 * Output toggle: compare match interrupt is enabled
1646 * Output set active: output set interrupt is enabled
1647 * Output set inactive: output reset interrupt is enabled
1648 * @retval HAL status
1649 */
1650 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef * hhrtim,
1651 uint32_t TimerIdx,
1652 uint32_t OCChannel)
1653 {
1654 uint32_t interrupt;
1655
1656 /* Check the parameters */
1657 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1658
1659 /* Process Locked */
1660 __HAL_LOCK(hhrtim);
1661
1662 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1663
1664 /* Get the interrupt to enable (depends on the output compare mode) */
1665 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1666
1667 /* Enable the timer output */
1668 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1669
1670 /* Enable the timer interrupt (depends on the output compare mode) */
1671 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
1672
1673 /* Enable the timer counter */
1674 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1675
1676 hhrtim->State = HAL_HRTIM_STATE_READY;
1677
1678 /* Process Unlocked */
1679 __HAL_UNLOCK(hhrtim);
1680
1681 return HAL_OK;
1682 }
1683
1684 /**
1685 * @brief Stop the output compare signal generation on the designed timer output
1686 * (Interrupt is disabled).
1687 * @param hhrtim pointer to HAL HRTIM handle
1688 * @param TimerIdx Timer index
1689 * This parameter can be one of the following values:
1690 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1691 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1692 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1693 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1694 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1695 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1696 * @param OCChannel Timer output
1697 * This parameter can be one of the following values:
1698 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1699 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1700 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1701 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1702 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1703 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1704 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1705 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1706 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1707 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1708 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1709 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1710 * @retval HAL status
1711 */
1712 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef * hhrtim,
1713 uint32_t TimerIdx,
1714 uint32_t OCChannel)
1715 {
1716 uint32_t interrupt;
1717
1718 /* Check the parameters */
1719 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1720
1721 /* Process Locked */
1722 __HAL_LOCK(hhrtim);
1723
1724 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1725
1726 /* Disable the timer output */
1727 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1728
1729 /* Get the interrupt to disable (depends on the output compare mode) */
1730 interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
1731
1732 /* Disable the timer interrupt */
1733 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
1734
1735 /* Disable the timer counter */
1736 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1737
1738 hhrtim->State = HAL_HRTIM_STATE_READY;
1739
1740 /* Process Unlocked */
1741 __HAL_UNLOCK(hhrtim);
1742
1743 return HAL_OK;
1744 }
1745
1746 /**
1747 * @brief Start the output compare signal generation on the designed timer output
1748 * (DMA request is enabled (see note below)).
1749 * @param hhrtim pointer to HAL HRTIM handle
1750 * @param TimerIdx Timer index
1751 * This parameter can be one of the following values:
1752 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1753 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1754 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1755 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1756 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1757 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1758 * @param OCChannel Timer output
1759 * This parameter can be one of the following values:
1760 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1761 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1762 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1763 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1764 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1765 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1766 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1767 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1768 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1769 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1770 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1771 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1772 * @param SrcAddr DMA transfer source address
1773 * @param DestAddr DMA transfer destination address
1774 * @param Length The length of data items (data size) to be transferred
1775 * from source to destination
1776 * @note DMA request enabling depends on the chosen output compare mode
1777 * Output toggle: compare match DMA request is enabled
1778 * Output set active: output set DMA request is enabled
1779 * Output set inactive: output reset DMA request is enabled
1780 * @retval HAL status
1781 */
1782 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef * hhrtim,
1783 uint32_t TimerIdx,
1784 uint32_t OCChannel,
1785 uint32_t SrcAddr,
1786 uint32_t DestAddr,
1787 uint32_t Length)
1788 {
1789 DMA_HandleTypeDef * hdma;
1790 uint32_t dma_request;
1791
1792 /* Check the parameters */
1793 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1794
1795 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
1796 {
1797 return HAL_BUSY;
1798 }
1799 if((hhrtim->State == HAL_HRTIM_STATE_READY))
1800 {
1801 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
1802 {
1803 return HAL_ERROR;
1804 }
1805 else
1806 {
1807 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1808 }
1809 }
1810
1811 /* Process Locked */
1812 __HAL_LOCK(hhrtim);
1813
1814 /* Enable the timer output */
1815 hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
1816
1817 /* Get the DMA request to enable */
1818 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1819
1820 /* Get the timer DMA handler */
1821 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
1822
1823 if (hdma == NULL)
1824 {
1825 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1826
1827 /* Process Unlocked */
1828 __HAL_UNLOCK(hhrtim);
1829
1830 return HAL_ERROR;
1831 }
1832
1833 /* Set the DMA error callback */
1834 hdma->XferErrorCallback = HRTIM_DMAError ;
1835
1836 /* Set the DMA transfer completed callback */
1837 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
1838
1839 /* Enable the DMA channel */
1840 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
1841 {
1842 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1843
1844 /* Process Unlocked */
1845 __HAL_UNLOCK(hhrtim);
1846
1847 return HAL_ERROR;
1848 }
1849
1850 /* Enable the timer DMA request */
1851 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
1852
1853 /* Enable the timer counter */
1854 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1855
1856 hhrtim->State = HAL_HRTIM_STATE_READY;
1857
1858 /* Process Unlocked */
1859 __HAL_UNLOCK(hhrtim);
1860
1861 return HAL_OK;
1862 }
1863
1864 /**
1865 * @brief Stop the output compare signal generation on the designed timer output
1866 * (DMA request is disabled).
1867 * @param hhrtim pointer to HAL HRTIM handle
1868 * @param TimerIdx Timer index
1869 * This parameter can be one of the following values:
1870 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1871 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1872 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1873 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1874 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1875 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1876 * @param OCChannel Timer output
1877 * This parameter can be one of the following values:
1878 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1879 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1880 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1881 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1882 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1883 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1884 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1885 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1886 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1887 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1888 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1889 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1890 * @retval HAL status
1891 */
1892 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef * hhrtim,
1893 uint32_t TimerIdx,
1894 uint32_t OCChannel)
1895 {
1896 uint32_t dma_request;
1897
1898 /* Check the parameters */
1899 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
1900
1901 /* Process Locked */
1902 __HAL_LOCK(hhrtim);
1903
1904 hhrtim->State = HAL_HRTIM_STATE_BUSY;
1905
1906 /* Disable the timer output */
1907 hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
1908
1909 /* Get the timer DMA handler */
1910 /* Disable the DMA */
1911 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
1912 {
1913 hhrtim->State = HAL_HRTIM_STATE_ERROR;
1914
1915 /* Process Unlocked */
1916 __HAL_UNLOCK(hhrtim);
1917
1918 return HAL_ERROR;
1919 }
1920
1921 /* Get the DMA request to disable */
1922 dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
1923
1924 /* Disable the timer DMA request */
1925 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
1926
1927 /* Disable the timer counter */
1928 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
1929
1930 hhrtim->State = HAL_HRTIM_STATE_READY;
1931
1932 /* Process Unlocked */
1933 __HAL_UNLOCK(hhrtim);
1934
1935 return HAL_OK;
1936 }
1937
1938 /**
1939 * @}
1940 */
1941
1942 /** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
1943 * @brief Simple PWM output functions
1944 @verbatim
1945 ===============================================================================
1946 ##### Simple PWM output functions #####
1947 ===============================================================================
1948 [..] This section provides functions allowing to:
1949 (+) Configure simple PWM output channel
1950 (+) Start simple PWM output
1951 (+) Stop simple PWM output
1952 (+) Start simple PWM output and enable interrupt
1953 (+) Stop simple PWM output and disable interrupt
1954 (+) Start simple PWM output and enable DMA transfer
1955 (+) Stop simple PWM output and disable DMA transfer
1956 -@- When a HRTIM timer operates in simple PWM output mode
1957 the output level is set to a programmable value when a match is
1958 found between the compare register and the counter and reset when
1959 the timer period is reached. Duty cycle is determined by the
1960 comparison value.
1961 Compare unit 1 is automatically associated to output 1
1962 Compare unit 2 is automatically associated to output 2
1963 @endverbatim
1964 * @{
1965 */
1966
1967 /**
1968 * @brief Configure an output in simple PWM mode
1969 * @param hhrtim pointer to HAL HRTIM handle
1970 * @param TimerIdx Timer index
1971 * This parameter can be one of the following values:
1972 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
1973 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
1974 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
1975 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
1976 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
1977 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
1978 * @param PWMChannel Timer output
1979 * This parameter can be one of the following values:
1980 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
1981 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
1982 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
1983 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
1984 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
1985 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
1986 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
1987 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
1988 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
1989 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
1990 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
1991 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
1992 * @param pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
1993 * @note When the timer operates in simple PWM output mode:
1994 * Output 1 is implicitly controlled by the compare unit 1
1995 * Output 2 is implicitly controlled by the compare unit 2
1996 * Output Set/Reset crossbar is set as follows:
1997 * Output 1: SETx1R = CMP1, RSTx1R = PER
1998 * Output 2: SETx2R = CMP2, RST2R = PER
1999 * @note When Simple PWM mode is used the registers preload mechanism is
2000 * enabled (otherwise the behavior is not guaranteed).
2001 * @retval HAL status
2002 */
2003 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2004 uint32_t TimerIdx,
2005 uint32_t PWMChannel,
2006 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg)
2007 {
2008 HRTIM_OutputCfgTypeDef OutputCfg;
2009 uint32_t hrtim_timcr;
2010
2011 /* Check parameters */
2012 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2013 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
2014 assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
2015 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
2016
2017 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2018 {
2019 return HAL_BUSY;
2020 }
2021
2022 /* Process Locked */
2023 __HAL_LOCK(hhrtim);
2024
2025 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2026
2027 /* Configure timer compare unit */
2028 switch (PWMChannel)
2029 {
2030 case HRTIM_OUTPUT_TA1:
2031 case HRTIM_OUTPUT_TB1:
2032 case HRTIM_OUTPUT_TC1:
2033 case HRTIM_OUTPUT_TD1:
2034 case HRTIM_OUTPUT_TE1:
2035 case HRTIM_OUTPUT_TF1:
2036 {
2037 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
2038 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
2039 break;
2040 }
2041
2042 case HRTIM_OUTPUT_TA2:
2043 case HRTIM_OUTPUT_TB2:
2044 case HRTIM_OUTPUT_TC2:
2045 case HRTIM_OUTPUT_TD2:
2046 case HRTIM_OUTPUT_TE2:
2047 case HRTIM_OUTPUT_TF2:
2048 {
2049 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
2050 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
2051 break;
2052 }
2053 default:
2054 {
2055 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2056
2057 /* Process Unlocked */
2058 __HAL_UNLOCK(hhrtim);
2059
2060 break;
2061 }
2062 }
2063
2064 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2065 {
2066 return HAL_ERROR;
2067 }
2068
2069 /* Configure timer output */
2070 OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
2071 OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel& HRTIM_OUTR_IDLES1);
2072 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
2073 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
2074 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
2075 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
2076 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
2077
2078 HRTIM_OutputConfig(hhrtim,
2079 TimerIdx,
2080 PWMChannel,
2081 &OutputCfg);
2082
2083 /* Enable the registers preload mechanism */
2084 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
2085 hrtim_timcr |= HRTIM_TIMCR_PREEN;
2086 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
2087
2088 hhrtim->State = HAL_HRTIM_STATE_READY;
2089
2090 /* Process Unlocked */
2091 __HAL_UNLOCK(hhrtim);
2092
2093 return HAL_OK;
2094 }
2095
2096 /**
2097 * @brief Start the PWM output signal generation on the designed timer output
2098 * @param hhrtim pointer to HAL HRTIM handle
2099 * @param TimerIdx Timer index
2100 * This parameter can be one of the following values:
2101 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2102 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2103 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2104 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2105 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2106 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2107 * @param PWMChannel Timer output
2108 * This parameter can be one of the following values:
2109 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2110 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2111 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2112 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2113 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2114 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2115 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2116 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2117 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2118 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2119 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2120 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2121 * @retval HAL status
2122 */
2123 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef * hhrtim,
2124 uint32_t TimerIdx,
2125 uint32_t PWMChannel)
2126 {
2127 /* Check the parameters */
2128 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2129
2130 /* Process Locked */
2131 __HAL_LOCK(hhrtim);
2132
2133 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2134
2135 /* Enable the timer output */
2136 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2137
2138 /* Enable the timer counter */
2139 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2140
2141 hhrtim->State = HAL_HRTIM_STATE_READY;
2142
2143 /* Process Unlocked */
2144 __HAL_UNLOCK(hhrtim);
2145
2146 return HAL_OK;
2147 }
2148
2149 /**
2150 * @brief Stop the PWM output signal generation on the designed timer output
2151 * @param hhrtim pointer to HAL HRTIM handle
2152 * @param TimerIdx Timer index
2153 * This parameter can be one of the following values:
2154 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2155 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2156 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2157 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2158 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2159 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2160 * @param PWMChannel Timer output
2161 * This parameter can be one of the following values:
2162 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2163 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2164 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2165 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2166 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2167 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2168 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2169 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2170 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2171 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2172 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2173 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2174 * @retval HAL status
2175 */
2176 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef * hhrtim,
2177 uint32_t TimerIdx,
2178 uint32_t PWMChannel)
2179 {
2180 /* Check the parameters */
2181 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2182
2183 /* Process Locked */
2184 __HAL_LOCK(hhrtim);
2185
2186 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2187
2188 /* Disable the timer output */
2189 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2190
2191 /* Disable the timer counter */
2192 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2193
2194 hhrtim->State = HAL_HRTIM_STATE_READY;
2195
2196 /* Process Unlocked */
2197 __HAL_UNLOCK(hhrtim);
2198
2199 return HAL_OK;
2200 }
2201
2202 /**
2203 * @brief Start the PWM output signal generation on the designed timer output
2204 * (The compare interrupt is enabled).
2205 * @param hhrtim pointer to HAL HRTIM handle
2206 * @param TimerIdx Timer index
2207 * This parameter can be one of the following values:
2208 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2209 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2210 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2211 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2212 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2213 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2214 * @param PWMChannel Timer output
2215 * This parameter can be one of the following values:
2216 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2217 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2218 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2219 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2220 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2221 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2222 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2223 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2224 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2225 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2226 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2227 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2228 * @retval HAL status
2229 */
2230 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef * hhrtim,
2231 uint32_t TimerIdx,
2232 uint32_t PWMChannel)
2233 {
2234 /* Check the parameters */
2235 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2236
2237 /* Process Locked */
2238 __HAL_LOCK(hhrtim);
2239
2240 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2241
2242 /* Enable the timer output */
2243 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2244
2245 /* Enable the timer interrupt (depends on the PWM output) */
2246 switch (PWMChannel)
2247 {
2248 case HRTIM_OUTPUT_TA1:
2249 case HRTIM_OUTPUT_TB1:
2250 case HRTIM_OUTPUT_TC1:
2251 case HRTIM_OUTPUT_TD1:
2252 case HRTIM_OUTPUT_TE1:
2253 case HRTIM_OUTPUT_TF1:
2254 {
2255 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2256 break;
2257 }
2258
2259 case HRTIM_OUTPUT_TA2:
2260 case HRTIM_OUTPUT_TB2:
2261 case HRTIM_OUTPUT_TC2:
2262 case HRTIM_OUTPUT_TD2:
2263 case HRTIM_OUTPUT_TE2:
2264 case HRTIM_OUTPUT_TF2:
2265 {
2266 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2267 break;
2268 }
2269
2270 default:
2271 {
2272 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2273
2274 /* Process Unlocked */
2275 __HAL_UNLOCK(hhrtim);
2276
2277 break;
2278 }
2279 }
2280
2281 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2282 {
2283 return HAL_ERROR;
2284 }
2285
2286 /* Enable the timer counter */
2287 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2288
2289 hhrtim->State = HAL_HRTIM_STATE_READY;
2290
2291 /* Process Unlocked */
2292 __HAL_UNLOCK(hhrtim);
2293
2294 return HAL_OK;
2295 }
2296
2297 /**
2298 * @brief Stop the PWM output signal generation on the designed timer output
2299 * (The compare interrupt is disabled).
2300 * @param hhrtim pointer to HAL HRTIM handle
2301 * @param TimerIdx Timer index
2302 * This parameter can be one of the following values:
2303 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2304 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2305 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2306 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2307 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2308 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2309 * @param PWMChannel Timer output
2310 * This parameter can be one of the following values:
2311 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2312 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2313 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2314 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2315 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2316 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2317 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2318 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2319 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2320 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2321 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2322 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2323 * @retval HAL status
2324 */
2325 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef * hhrtim,
2326 uint32_t TimerIdx,
2327 uint32_t PWMChannel)
2328 {
2329 /* Check the parameters */
2330 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2331
2332 /* Process Locked */
2333 __HAL_LOCK(hhrtim);
2334
2335 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2336
2337 /* Disable the timer output */
2338 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2339
2340 /* Disable the timer interrupt (depends on the PWM output) */
2341 switch (PWMChannel)
2342 {
2343 case HRTIM_OUTPUT_TA1:
2344 case HRTIM_OUTPUT_TB1:
2345 case HRTIM_OUTPUT_TC1:
2346 case HRTIM_OUTPUT_TD1:
2347 case HRTIM_OUTPUT_TE1:
2348 case HRTIM_OUTPUT_TF1:
2349 {
2350 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
2351 break;
2352 }
2353
2354 case HRTIM_OUTPUT_TA2:
2355 case HRTIM_OUTPUT_TB2:
2356 case HRTIM_OUTPUT_TC2:
2357 case HRTIM_OUTPUT_TD2:
2358 case HRTIM_OUTPUT_TE2:
2359 case HRTIM_OUTPUT_TF2:
2360 {
2361 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
2362 break;
2363 }
2364
2365 default:
2366 {
2367 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2368
2369 /* Process Unlocked */
2370 __HAL_UNLOCK(hhrtim);
2371
2372 break;
2373 }
2374 }
2375
2376 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2377 {
2378 return HAL_ERROR;
2379 }
2380
2381 /* Disable the timer counter */
2382 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2383
2384 hhrtim->State = HAL_HRTIM_STATE_READY;
2385
2386 /* Process Unlocked */
2387 __HAL_UNLOCK(hhrtim);
2388
2389 return HAL_OK;
2390 }
2391
2392 /**
2393 * @brief Start the PWM output signal generation on the designed timer output
2394 * (The compare DMA request is enabled).
2395 * @param hhrtim pointer to HAL HRTIM handle
2396 * @param TimerIdx Timer index
2397 * This parameter can be one of the following values:
2398 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2399 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2400 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2401 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2402 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2403 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2404 * @param PWMChannel Timer output
2405 * This parameter can be one of the following values:
2406 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2407 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2408 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2409 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2410 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2411 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2412 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2413 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2414 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2415 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2416 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2417 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2418 * @param SrcAddr DMA transfer source address
2419 * @param DestAddr DMA transfer destination address
2420 * @param Length The length of data items (data size) to be transferred
2421 * from source to destination
2422 * @retval HAL status
2423 */
2424 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef * hhrtim,
2425 uint32_t TimerIdx,
2426 uint32_t PWMChannel,
2427 uint32_t SrcAddr,
2428 uint32_t DestAddr,
2429 uint32_t Length)
2430 {
2431 DMA_HandleTypeDef * hdma;
2432
2433 /* Check the parameters */
2434 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2435
2436 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
2437 {
2438 return HAL_BUSY;
2439 }
2440 if((hhrtim->State == HAL_HRTIM_STATE_READY))
2441 {
2442 if((SrcAddr == 0U ) || (DestAddr == 0U ) || (Length == 0U))
2443 {
2444 return HAL_ERROR;
2445 }
2446 else
2447 {
2448 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2449 }
2450 }
2451
2452 /* Process Locked */
2453 __HAL_LOCK(hhrtim);
2454
2455 /* Enable the timer output */
2456 hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
2457
2458 /* Get the timer DMA handler */
2459 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
2460
2461 if (hdma == NULL)
2462 {
2463 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2464
2465 /* Process Unlocked */
2466 __HAL_UNLOCK(hhrtim);
2467
2468 return HAL_ERROR;
2469 }
2470
2471 /* Set the DMA error callback */
2472 hdma->XferErrorCallback = HRTIM_DMAError ;
2473
2474 /* Set the DMA transfer completed callback */
2475 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
2476
2477 /* Enable the DMA channel */
2478 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
2479 {
2480 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2481
2482 /* Process Unlocked */
2483 __HAL_UNLOCK(hhrtim);
2484
2485 return HAL_ERROR;
2486 }
2487
2488 /* Enable the timer DMA request */
2489 switch (PWMChannel)
2490 {
2491 case HRTIM_OUTPUT_TA1:
2492 case HRTIM_OUTPUT_TB1:
2493 case HRTIM_OUTPUT_TC1:
2494 case HRTIM_OUTPUT_TD1:
2495 case HRTIM_OUTPUT_TE1:
2496 case HRTIM_OUTPUT_TF1:
2497 {
2498 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2499 break;
2500 }
2501
2502 case HRTIM_OUTPUT_TA2:
2503 case HRTIM_OUTPUT_TB2:
2504 case HRTIM_OUTPUT_TC2:
2505 case HRTIM_OUTPUT_TD2:
2506 case HRTIM_OUTPUT_TE2:
2507 case HRTIM_OUTPUT_TF2:
2508 {
2509 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2510 break;
2511 }
2512
2513 default:
2514 {
2515 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2516
2517 /* Process Unlocked */
2518 __HAL_UNLOCK(hhrtim);
2519
2520 break;
2521 }
2522 }
2523
2524 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2525 {
2526 return HAL_ERROR;
2527 }
2528
2529 /* Enable the timer counter */
2530 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2531
2532 hhrtim->State = HAL_HRTIM_STATE_READY;
2533
2534 /* Process Unlocked */
2535 __HAL_UNLOCK(hhrtim);
2536
2537 return HAL_OK;
2538 }
2539
2540 /**
2541 * @brief Stop the PWM output signal generation on the designed timer output
2542 * (The compare DMA request is disabled).
2543 * @param hhrtim pointer to HAL HRTIM handle
2544 * @param TimerIdx Timer index
2545 * This parameter can be one of the following values:
2546 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2547 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2548 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2549 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2550 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2551 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2552 * @param PWMChannel Timer output
2553 * This parameter can be one of the following values:
2554 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
2555 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
2556 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
2557 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
2558 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
2559 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
2560 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
2561 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
2562 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
2563 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
2564 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
2565 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
2566 * @retval HAL status
2567 */
2568 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef * hhrtim,
2569 uint32_t TimerIdx,
2570 uint32_t PWMChannel)
2571 {
2572 /* Check the parameters */
2573 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
2574
2575 /* Process Locked */
2576 __HAL_LOCK(hhrtim);
2577
2578 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2579
2580 /* Disable the timer output */
2581 hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
2582
2583 /* Get the timer DMA handler */
2584 /* Disable the DMA */
2585 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
2586 {
2587 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2588
2589 /* Process Unlocked */
2590 __HAL_UNLOCK(hhrtim);
2591
2592 return HAL_ERROR;
2593 }
2594
2595 /* Disable the timer DMA request */
2596 switch (PWMChannel)
2597 {
2598 case HRTIM_OUTPUT_TA1:
2599 case HRTIM_OUTPUT_TB1:
2600 case HRTIM_OUTPUT_TC1:
2601 case HRTIM_OUTPUT_TD1:
2602 case HRTIM_OUTPUT_TE1:
2603 case HRTIM_OUTPUT_TF1:
2604 {
2605 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
2606 break;
2607 }
2608
2609 case HRTIM_OUTPUT_TA2:
2610 case HRTIM_OUTPUT_TB2:
2611 case HRTIM_OUTPUT_TC2:
2612 case HRTIM_OUTPUT_TD2:
2613 case HRTIM_OUTPUT_TE2:
2614 case HRTIM_OUTPUT_TF2:
2615 {
2616 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
2617 break;
2618 }
2619
2620 default:
2621 {
2622 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2623
2624 /* Process Unlocked */
2625 __HAL_UNLOCK(hhrtim);
2626
2627 break;
2628 }
2629 }
2630
2631 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2632 {
2633 return HAL_ERROR;
2634 }
2635
2636 /* Disable the timer counter */
2637 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2638
2639 hhrtim->State = HAL_HRTIM_STATE_READY;
2640
2641 /* Process Unlocked */
2642 __HAL_UNLOCK(hhrtim);
2643
2644 return HAL_OK;
2645 }
2646
2647 /**
2648 * @}
2649 */
2650
2651 /** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
2652 * @brief Simple input capture functions
2653 @verbatim
2654 ===============================================================================
2655 ##### Simple input capture functions #####
2656 ===============================================================================
2657 [..] This section provides functions allowing to:
2658 (+) Configure simple input capture channel
2659 (+) Start simple input capture
2660 (+) Stop simple input capture
2661 (+) Start simple input capture and enable interrupt
2662 (+) Stop simple input capture and disable interrupt
2663 (+) Start simple input capture and enable DMA transfer
2664 (+) Stop simple input capture and disable DMA transfer
2665 -@- When a HRTIM timer operates in simple input capture mode
2666 the Capture Register (HRTIM_CPT1/2xR) is used to latch the
2667 value of the timer counter counter after a transition detected
2668 on a given external event input.
2669 @endverbatim
2670 * @{
2671 */
2672
2673 /**
2674 * @brief Configure a simple capture
2675 * @param hhrtim pointer to HAL HRTIM handle
2676 * @param TimerIdx Timer index
2677 * This parameter can be one of the following values:
2678 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2679 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2680 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2681 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2682 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2683 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2684 * @param CaptureChannel Capture unit
2685 * This parameter can be one of the following values:
2686 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2687 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2688 * @param pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
2689 * @note When the timer operates in simple capture mode the capture is trigerred
2690 * by the designated external event and GPIO input is implicitly used as event source.
2691 * The cature can be triggered by a rising edge, a falling edge or both
2692 * edges on event channel.
2693 * @retval HAL status
2694 */
2695 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef * hhrtim,
2696 uint32_t TimerIdx,
2697 uint32_t CaptureChannel,
2698 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg)
2699 {
2700 HRTIM_EventCfgTypeDef EventCfg;
2701
2702 /* Check parameters */
2703 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2704 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2705 assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
2706 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
2707 pSimpleCaptureChannelCfg->EventPolarity));
2708 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
2709 assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
2710 pSimpleCaptureChannelCfg->EventFilter));
2711
2712 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
2713 {
2714 return HAL_BUSY;
2715 }
2716
2717 /* Process Locked */
2718 __HAL_LOCK(hhrtim);
2719
2720 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2721
2722 /* Configure external event channel */
2723 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
2724 EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
2725 EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
2726 EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
2727 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
2728
2729 HRTIM_EventConfig(hhrtim,
2730 pSimpleCaptureChannelCfg->Event,
2731 &EventCfg);
2732
2733 /* Memorize capture trigger (will be configured when the capture is started */
2734 HRTIM_CaptureUnitConfig(hhrtim,
2735 TimerIdx,
2736 CaptureChannel,
2737 pSimpleCaptureChannelCfg->Event);
2738
2739 hhrtim->State = HAL_HRTIM_STATE_READY;
2740
2741 /* Process Unlocked */
2742 __HAL_UNLOCK(hhrtim);
2743
2744 return HAL_OK;
2745 }
2746
2747 /**
2748 * @brief Enable a simple capture on the designed capture unit
2749 * @param hhrtim pointer to HAL HRTIM handle
2750 * @param TimerIdx Timer index
2751 * This parameter can be one of the following values:
2752 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2753 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2754 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2755 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2756 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2757 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2758 * @param CaptureChannel Timer output
2759 * This parameter can be one of the following values:
2760 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2761 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2762 * @retval HAL status
2763 * @note The external event triggering the capture is available for all timing
2764 * units. It can be used directly and is active as soon as the timing
2765 * unit counter is enabled.
2766 */
2767 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef * hhrtim,
2768 uint32_t TimerIdx,
2769 uint32_t CaptureChannel)
2770 {
2771 /* Check the parameters */
2772 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2773 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2774
2775 /* Process Locked */
2776 __HAL_LOCK(hhrtim);
2777
2778 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2779
2780 /* Set the capture unit trigger */
2781 switch (CaptureChannel)
2782 {
2783 case HRTIM_CAPTUREUNIT_1:
2784 {
2785 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2786 break;
2787 }
2788
2789 case HRTIM_CAPTUREUNIT_2:
2790 {
2791 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2792 break;
2793 }
2794
2795 default:
2796 {
2797 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2798
2799 /* Process Unlocked */
2800 __HAL_UNLOCK(hhrtim);
2801
2802 break;
2803 }
2804 }
2805
2806 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2807 {
2808 return HAL_ERROR;
2809 }
2810
2811 /* Enable the timer counter */
2812 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2813
2814 hhrtim->State = HAL_HRTIM_STATE_READY;
2815
2816 /* Process Unlocked */
2817 __HAL_UNLOCK(hhrtim);
2818
2819 return HAL_OK;
2820 }
2821
2822 /**
2823 * @brief Disable a simple capture on the designed capture unit
2824 * @param hhrtim pointer to HAL HRTIM handle
2825 * @param TimerIdx Timer index
2826 * This parameter can be one of the following values:
2827 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2828 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2829 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2830 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2831 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2832 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2833 * @param CaptureChannel Timer output
2834 * This parameter can be one of the following values:
2835 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2836 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2837 * @retval HAL status
2838 */
2839 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef * hhrtim,
2840 uint32_t TimerIdx,
2841 uint32_t CaptureChannel)
2842 {
2843 uint32_t hrtim_cpt1cr;
2844 uint32_t hrtim_cpt2cr;
2845
2846 /* Check the parameters */
2847 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2848 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2849
2850 /* Process Locked */
2851 __HAL_LOCK(hhrtim);
2852
2853 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2854
2855 /* Set the capture unit trigger */
2856 switch (CaptureChannel)
2857 {
2858 case HRTIM_CAPTUREUNIT_1:
2859 {
2860 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
2861 break;
2862 }
2863
2864 case HRTIM_CAPTUREUNIT_2:
2865 {
2866 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
2867 break;
2868 }
2869
2870 default:
2871 {
2872 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2873
2874 /* Process Unlocked */
2875 __HAL_UNLOCK(hhrtim);
2876
2877 break;
2878 }
2879 }
2880
2881 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2882 {
2883 return HAL_ERROR;
2884 }
2885
2886 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
2887 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
2888
2889 /* Disable the timer counter */
2890 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
2891 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
2892 {
2893 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2894 }
2895
2896 hhrtim->State = HAL_HRTIM_STATE_READY;
2897
2898 /* Process Unlocked */
2899 __HAL_UNLOCK(hhrtim);
2900
2901 return HAL_OK;
2902 }
2903
2904 /**
2905 * @brief Enable a simple capture on the designed capture unit
2906 * (Capture interrupt is enabled).
2907 * @param hhrtim pointer to HAL HRTIM handle
2908 * @param TimerIdx Timer index
2909 * This parameter can be one of the following values:
2910 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2911 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2912 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2913 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2914 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2915 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2916 * @param CaptureChannel Timer output
2917 * This parameter can be one of the following values:
2918 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2919 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2920 * @retval HAL status
2921 */
2922 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef * hhrtim,
2923 uint32_t TimerIdx,
2924 uint32_t CaptureChannel)
2925 {
2926 /* Check the parameters */
2927 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
2928 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
2929
2930 /* Process Locked */
2931 __HAL_LOCK(hhrtim);
2932
2933 hhrtim->State = HAL_HRTIM_STATE_BUSY;
2934
2935 /* Set the capture unit trigger */
2936 switch (CaptureChannel)
2937 {
2938 case HRTIM_CAPTUREUNIT_1:
2939 {
2940 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
2941
2942 /* Enable the capture unit 1 interrupt */
2943 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
2944 break;
2945 }
2946
2947 case HRTIM_CAPTUREUNIT_2:
2948 {
2949 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
2950
2951 /* Enable the capture unit 2 interrupt */
2952 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
2953 break;
2954 }
2955
2956 default:
2957 {
2958 hhrtim->State = HAL_HRTIM_STATE_ERROR;
2959
2960 /* Process Unlocked */
2961 __HAL_UNLOCK(hhrtim);
2962
2963 break;
2964 }
2965 }
2966
2967 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
2968 {
2969 return HAL_ERROR;
2970 }
2971
2972 /* Enable the timer counter */
2973 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
2974
2975 hhrtim->State = HAL_HRTIM_STATE_READY;
2976
2977 /* Process Unlocked */
2978 __HAL_UNLOCK(hhrtim);
2979
2980 return HAL_OK;
2981 }
2982
2983 /**
2984 * @brief Disable a simple capture on the designed capture unit
2985 * (Capture interrupt is disabled).
2986 * @param hhrtim pointer to HAL HRTIM handle
2987 * @param TimerIdx Timer index
2988 * This parameter can be one of the following values:
2989 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
2990 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
2991 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
2992 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
2993 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
2994 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
2995 * @param CaptureChannel Timer output
2996 * This parameter can be one of the following values:
2997 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
2998 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
2999 * @retval HAL status
3000 */
3001 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef * hhrtim,
3002 uint32_t TimerIdx,
3003 uint32_t CaptureChannel)
3004 {
3005
3006 uint32_t hrtim_cpt1cr;
3007 uint32_t hrtim_cpt2cr;
3008
3009 /* Check the parameters */
3010 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3011 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3012
3013 /* Process Locked */
3014 __HAL_LOCK(hhrtim);
3015
3016 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3017
3018 /* Set the capture unit trigger */
3019 switch (CaptureChannel)
3020 {
3021 case HRTIM_CAPTUREUNIT_1:
3022 {
3023 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3024
3025 /* Disable the capture unit 1 interrupt */
3026 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
3027 break;
3028 }
3029
3030 case HRTIM_CAPTUREUNIT_2:
3031 {
3032 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3033
3034 /* Disable the capture unit 2 interrupt */
3035 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
3036 break;
3037 }
3038
3039 default:
3040 {
3041 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3042
3043 /* Process Unlocked */
3044 __HAL_UNLOCK(hhrtim);
3045
3046 break;
3047 }
3048 }
3049
3050 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3051 {
3052 return HAL_ERROR;
3053 }
3054
3055 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3056 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3057
3058 /* Disable the timer counter */
3059 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3060 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3061 {
3062 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3063 }
3064
3065 hhrtim->State = HAL_HRTIM_STATE_READY;
3066
3067 /* Process Unlocked */
3068 __HAL_UNLOCK(hhrtim);
3069
3070 return HAL_OK;
3071 }
3072
3073 /**
3074 * @brief Enable a simple capture on the designed capture unit
3075 * (Capture DMA request is enabled).
3076 * @param hhrtim pointer to HAL HRTIM handle
3077 * @param TimerIdx Timer index
3078 * This parameter can be one of the following values:
3079 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3080 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3081 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3082 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3083 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3084 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3085 * @param CaptureChannel Timer output
3086 * This parameter can be one of the following values:
3087 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3088 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3089 * @param SrcAddr DMA transfer source address
3090 * @param DestAddr DMA transfer destination address
3091 * @param Length The length of data items (data size) to be transferred
3092 * from source to destination
3093 * @retval HAL status
3094 */
3095 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef * hhrtim,
3096 uint32_t TimerIdx,
3097 uint32_t CaptureChannel,
3098 uint32_t SrcAddr,
3099 uint32_t DestAddr,
3100 uint32_t Length)
3101 {
3102 DMA_HandleTypeDef * hdma;
3103
3104 /* Check the parameters */
3105 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3106 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3107
3108 /* Process Locked */
3109 __HAL_LOCK(hhrtim);
3110
3111 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3112
3113 /* Get the timer DMA handler */
3114 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
3115
3116 if (hdma == NULL)
3117 {
3118 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3119
3120 /* Process Unlocked */
3121 __HAL_UNLOCK(hhrtim);
3122
3123 return HAL_ERROR;
3124 }
3125
3126 /* Set the DMA error callback */
3127 hdma->XferErrorCallback = HRTIM_DMAError ;
3128
3129 /* Set the DMA transfer completed callback */
3130 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
3131
3132 /* Enable the DMA channel */
3133 if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
3134 {
3135 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3136
3137 /* Process Unlocked */
3138 __HAL_UNLOCK(hhrtim);
3139
3140 return HAL_ERROR;
3141 }
3142
3143 switch (CaptureChannel)
3144 {
3145 case HRTIM_CAPTUREUNIT_1:
3146 {
3147 /* Set the capture unit trigger */
3148 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
3149
3150 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3151 break;
3152 }
3153
3154 case HRTIM_CAPTUREUNIT_2:
3155 {
3156 /* Set the capture unit trigger */
3157 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
3158
3159 /* Enable the timer DMA request */
3160 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3161 break;
3162 }
3163
3164 default:
3165 {
3166 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3167
3168 /* Process Unlocked */
3169 __HAL_UNLOCK(hhrtim);
3170
3171 break;
3172 }
3173 }
3174
3175 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3176 {
3177 return HAL_ERROR;
3178 }
3179
3180 /* Enable the timer counter */
3181 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3182
3183 hhrtim->State = HAL_HRTIM_STATE_READY;
3184
3185 /* Process Unlocked */
3186 __HAL_UNLOCK(hhrtim);
3187
3188 return HAL_OK;
3189 }
3190
3191 /**
3192 * @brief Disable a simple capture on the designed capture unit
3193 * (Capture DMA request is disabled).
3194 * @param hhrtim pointer to HAL HRTIM handle
3195 * @param TimerIdx Timer index
3196 * This parameter can be one of the following values:
3197 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3198 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3199 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3200 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3201 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3202 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3203 * @param CaptureChannel Timer output
3204 * This parameter can be one of the following values:
3205 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
3206 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
3207 * @retval HAL status
3208 */
3209 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef * hhrtim,
3210 uint32_t TimerIdx,
3211 uint32_t CaptureChannel)
3212 {
3213
3214 uint32_t hrtim_cpt1cr;
3215 uint32_t hrtim_cpt2cr;
3216
3217 /* Check the parameters */
3218 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
3219 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
3220
3221 /* Process Locked */
3222 __HAL_LOCK(hhrtim);
3223
3224 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3225
3226 /* Get the timer DMA handler */
3227 /* Disable the DMA */
3228 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
3229 {
3230 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3231
3232 /* Process Unlocked */
3233 __HAL_UNLOCK(hhrtim);
3234
3235 return HAL_ERROR;
3236 }
3237
3238 switch (CaptureChannel)
3239 {
3240 case HRTIM_CAPTUREUNIT_1:
3241 {
3242 /* Reset the capture unit trigger */
3243 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
3244
3245 /* Disable the capture unit 1 DMA request */
3246 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
3247 break;
3248 }
3249
3250 case HRTIM_CAPTUREUNIT_2:
3251 {
3252 /* Reset the capture unit trigger */
3253 hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
3254
3255 /* Disable the capture unit 2 DMA request */
3256 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
3257 break;
3258 }
3259
3260 default:
3261 {
3262 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3263
3264 /* Process Unlocked */
3265 __HAL_UNLOCK(hhrtim);
3266
3267 break;
3268 }
3269 }
3270
3271 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3272 {
3273 return HAL_ERROR;
3274 }
3275
3276 hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
3277 hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
3278
3279 /* Disable the timer counter */
3280 if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
3281 (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
3282 {
3283 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3284 }
3285
3286 hhrtim->State = HAL_HRTIM_STATE_READY;
3287
3288 /* Process Unlocked */
3289 __HAL_UNLOCK(hhrtim);
3290
3291 return HAL_OK;
3292 }
3293
3294 /**
3295 * @}
3296 */
3297
3298 /** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
3299 * @brief Simple one pulse functions
3300 @verbatim
3301 ===============================================================================
3302 ##### Simple one pulse functions #####
3303 ===============================================================================
3304 [..] This section provides functions allowing to:
3305 (+) Configure one pulse channel
3306 (+) Start one pulse generation
3307 (+) Stop one pulse generation
3308 (+) Start one pulse generation and enable interrupt
3309 (+) Stop one pulse generation and disable interrupt
3310 -@- When a HRTIM timer operates in simple one pulse mode
3311 the timer counter is started in response to transition detected
3312 on a given external event input to generate a pulse with a
3313 programmable length after a programmable delay.
3314 @endverbatim
3315 * @{
3316 */
3317
3318 /**
3319 * @brief Configure an output simple one pulse mode
3320 * @param hhrtim pointer to HAL HRTIM handle
3321 * @param TimerIdx Timer index
3322 * This parameter can be one of the following values:
3323 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3324 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3325 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3326 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3327 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3328 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3329 * @param OnePulseChannel Timer output
3330 * This parameter can be one of the following values:
3331 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3332 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3333 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3334 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3335 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3336 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3337 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3338 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3339 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3340 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3341 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3342 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3343 * @param pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
3344 * @note When the timer operates in simple one pulse mode:
3345 * the timer counter is implicitly started by the reset event,
3346 * the reset of the timer counter is triggered by the designated external event
3347 * GPIO input is implicitly used as event source,
3348 * Output 1 is implicitly controlled by the compare unit 1,
3349 * Output 2 is implicitly controlled by the compare unit 2.
3350 * Output Set/Reset crossbar is set as follows:
3351 * Output 1: SETx1R = CMP1, RSTx1R = PER
3352 * Output 2: SETx2R = CMP2, RST2R = PER
3353 * @retval HAL status
3354 * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
3355 * outputs, the reset event related configuration data provided in the
3356 * second call will override the reset event related configuration data
3357 * provided in the first call.
3358 */
3359 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef * hhrtim,
3360 uint32_t TimerIdx,
3361 uint32_t OnePulseChannel,
3362 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg)
3363 {
3364 HRTIM_OutputCfgTypeDef OutputCfg;
3365 HRTIM_EventCfgTypeDef EventCfg;
3366
3367 /* Check parameters */
3368 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3369 assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
3370 assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
3371 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
3372 assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
3373 assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
3374 pSimpleOnePulseChannelCfg->EventPolarity));
3375 assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
3376 assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
3377 pSimpleOnePulseChannelCfg->EventFilter));
3378
3379 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3380 {
3381 return HAL_BUSY;
3382 }
3383
3384 /* Process Locked */
3385 __HAL_LOCK(hhrtim);
3386
3387 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3388
3389 /* Configure timer compare unit */
3390 switch (OnePulseChannel)
3391 {
3392 case HRTIM_OUTPUT_TA1:
3393 case HRTIM_OUTPUT_TB1:
3394 case HRTIM_OUTPUT_TC1:
3395 case HRTIM_OUTPUT_TD1:
3396 case HRTIM_OUTPUT_TE1:
3397 case HRTIM_OUTPUT_TF1:
3398 {
3399 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
3400 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
3401 break;
3402 }
3403
3404 case HRTIM_OUTPUT_TA2:
3405 case HRTIM_OUTPUT_TB2:
3406 case HRTIM_OUTPUT_TC2:
3407 case HRTIM_OUTPUT_TD2:
3408 case HRTIM_OUTPUT_TE2:
3409 case HRTIM_OUTPUT_TF2:
3410 {
3411 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
3412 OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
3413 break;
3414 }
3415
3416 default:
3417 {
3418 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3419
3420 /* Process Unlocked */
3421 __HAL_UNLOCK(hhrtim);
3422
3423 break;
3424 }
3425 }
3426
3427 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3428 {
3429 return HAL_ERROR;
3430 }
3431
3432 /* Configure timer output */
3433 OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
3434 OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
3435 OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
3436 OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
3437 OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
3438 OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
3439 OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
3440
3441 HRTIM_OutputConfig(hhrtim,
3442 TimerIdx,
3443 OnePulseChannel,
3444 &OutputCfg);
3445
3446 /* Configure external event channel */
3447 EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
3448 EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
3449 EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
3450 EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity &HRTIM_EECR1_EE1SNS);
3451 EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
3452
3453 HRTIM_EventConfig(hhrtim,
3454 pSimpleOnePulseChannelCfg->Event,
3455 &EventCfg);
3456
3457 /* Configure the timer reset register */
3458 HRTIM_TIM_ResetConfig(hhrtim,
3459 TimerIdx,
3460 pSimpleOnePulseChannelCfg->Event);
3461
3462 hhrtim->State = HAL_HRTIM_STATE_READY;
3463
3464 /* Process Unlocked */
3465 __HAL_UNLOCK(hhrtim);
3466
3467 return HAL_OK;
3468 }
3469
3470 /**
3471 * @brief Enable the simple one pulse signal generation on the designed output
3472 * @param hhrtim pointer to HAL HRTIM handle
3473 * @param TimerIdx Timer index
3474 * This parameter can be one of the following values:
3475 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3476 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3477 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3478 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3479 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3480 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3481 * @param OnePulseChannel Timer output
3482 * This parameter can be one of the following values:
3483 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3484 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3485 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3486 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3487 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3488 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3489 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3490 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3491 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3492 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3493 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3494 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3495 * @retval HAL status
3496 */
3497 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef * hhrtim,
3498 uint32_t TimerIdx,
3499 uint32_t OnePulseChannel)
3500 {
3501 /* Check the parameters */
3502 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3503
3504 /* Process Locked */
3505 __HAL_LOCK(hhrtim);
3506
3507 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3508
3509 /* Enable the timer output */
3510 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3511
3512 /* Enable the timer counter */
3513 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3514
3515 hhrtim->State = HAL_HRTIM_STATE_READY;
3516
3517 /* Process Unlocked */
3518 __HAL_UNLOCK(hhrtim);
3519
3520 return HAL_OK;
3521 }
3522
3523 /**
3524 * @brief Disable the simple one pulse signal generation on the designed output
3525 * @param hhrtim pointer to HAL HRTIM handle
3526 * @param TimerIdx Timer index
3527 * This parameter can be one of the following values:
3528 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3529 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3530 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3531 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3532 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3533 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3534 * @param OnePulseChannel Timer output
3535 * This parameter can be one of the following values:
3536 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3537 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3538 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3539 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3540 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3541 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3542 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3543 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3544 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3545 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3546 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3547 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3548 * @retval HAL status
3549 */
3550 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef * hhrtim,
3551 uint32_t TimerIdx,
3552 uint32_t OnePulseChannel)
3553 {
3554 /* Check the parameters */
3555 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3556
3557 /* Process Locked */
3558 __HAL_LOCK(hhrtim);
3559
3560 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3561
3562 /* Disable the timer output */
3563 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3564
3565 /* Disable the timer counter */
3566 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3567
3568 hhrtim->State = HAL_HRTIM_STATE_READY;
3569
3570 /* Process Unlocked */
3571 __HAL_UNLOCK(hhrtim);
3572
3573 return HAL_OK;
3574 }
3575
3576 /**
3577 * @brief Enable the simple one pulse signal generation on the designed output
3578 * (The compare interrupt is enabled (pulse start)).
3579 * @param hhrtim pointer to HAL HRTIM handle
3580 * @param TimerIdx Timer index
3581 * This parameter can be one of the following values:
3582 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3583 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3584 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3585 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3586 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3587 * @arg HRTIM_TIMERINDEX_TIMER_F for timer E
3588 * @param OnePulseChannel Timer output
3589 * This parameter can be one of the following values:
3590 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3591 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3592 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3593 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3594 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3595 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3596 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3597 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3598 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3599 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3600 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3601 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3602 * @retval HAL status
3603 */
3604 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef * hhrtim,
3605 uint32_t TimerIdx,
3606 uint32_t OnePulseChannel)
3607 {
3608 /* Check the parameters */
3609 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3610
3611 /* Process Locked */
3612 __HAL_LOCK(hhrtim);
3613
3614 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3615
3616 /* Enable the timer output */
3617 hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
3618
3619 /* Enable the timer interrupt (depends on the OnePulse output) */
3620 switch (OnePulseChannel)
3621 {
3622 case HRTIM_OUTPUT_TA1:
3623 case HRTIM_OUTPUT_TB1:
3624 case HRTIM_OUTPUT_TC1:
3625 case HRTIM_OUTPUT_TD1:
3626 case HRTIM_OUTPUT_TE1:
3627 case HRTIM_OUTPUT_TF1:
3628 {
3629 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3630 break;
3631 }
3632
3633 case HRTIM_OUTPUT_TA2:
3634 case HRTIM_OUTPUT_TB2:
3635 case HRTIM_OUTPUT_TC2:
3636 case HRTIM_OUTPUT_TD2:
3637 case HRTIM_OUTPUT_TE2:
3638 case HRTIM_OUTPUT_TF2:
3639 {
3640 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3641 break;
3642 }
3643
3644 default:
3645 {
3646 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3647
3648 /* Process Unlocked */
3649 __HAL_UNLOCK(hhrtim);
3650
3651 break;
3652 }
3653 }
3654
3655 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3656 {
3657 return HAL_ERROR;
3658 }
3659
3660 /* Enable the timer counter */
3661 __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3662
3663 hhrtim->State = HAL_HRTIM_STATE_READY;
3664
3665 /* Process Unlocked */
3666 __HAL_UNLOCK(hhrtim);
3667
3668 return HAL_OK;
3669 }
3670
3671 /**
3672 * @brief Disable the simple one pulse signal generation on the designed output
3673 * (The compare interrupt is disabled).
3674 * @param hhrtim pointer to HAL HRTIM handle
3675 * @param TimerIdx Timer index
3676 * This parameter can be one of the following values:
3677 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
3678 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
3679 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
3680 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
3681 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
3682 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
3683 * @param OnePulseChannel Timer output
3684 * This parameter can be one of the following values:
3685 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
3686 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
3687 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
3688 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
3689 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
3690 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
3691 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
3692 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
3693 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
3694 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
3695 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
3696 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
3697 * @retval HAL status
3698 */
3699 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef * hhrtim,
3700 uint32_t TimerIdx,
3701 uint32_t OnePulseChannel)
3702 {
3703 /* Check the parameters */
3704 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
3705
3706 /* Process Locked */
3707 __HAL_LOCK(hhrtim);
3708
3709 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3710
3711 /* Disable the timer output */
3712 hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
3713
3714 /* Disable the timer interrupt (depends on the OnePulse output) */
3715 switch (OnePulseChannel)
3716 {
3717 case HRTIM_OUTPUT_TA1:
3718 case HRTIM_OUTPUT_TB1:
3719 case HRTIM_OUTPUT_TC1:
3720 case HRTIM_OUTPUT_TD1:
3721 case HRTIM_OUTPUT_TE1:
3722 case HRTIM_OUTPUT_TF1:
3723 {
3724 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
3725 break;
3726 }
3727
3728 case HRTIM_OUTPUT_TA2:
3729 case HRTIM_OUTPUT_TB2:
3730 case HRTIM_OUTPUT_TC2:
3731 case HRTIM_OUTPUT_TD2:
3732 case HRTIM_OUTPUT_TE2:
3733 case HRTIM_OUTPUT_TF2:
3734 {
3735 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
3736 break;
3737 }
3738
3739 default:
3740 {
3741 hhrtim->State = HAL_HRTIM_STATE_ERROR;
3742
3743 /* Process Unlocked */
3744 __HAL_UNLOCK(hhrtim);
3745
3746 break;
3747 }
3748 }
3749
3750 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
3751 {
3752 return HAL_ERROR;
3753 }
3754
3755 /* Disable the timer counter */
3756 __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
3757
3758 hhrtim->State = HAL_HRTIM_STATE_READY;
3759
3760 /* Process Unlocked */
3761 __HAL_UNLOCK(hhrtim);
3762
3763 return HAL_OK;
3764 }
3765
3766 /**
3767 * @}
3768 */
3769
3770 /** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
3771 * @brief HRTIM configuration functions
3772 @verbatim
3773 ===============================================================================
3774 ##### HRTIM configuration functions #####
3775 ===============================================================================
3776 [..] This section provides functions allowing to configure the HRTIM
3777 resources shared by all the HRTIM timers operating in waveform mode:
3778 (+) Configure the burst mode controller
3779 (+) Configure an external event conditioning
3780 (+) Configure the external events sampling clock
3781 (+) Configure a fault conditioning
3782 (+) Enable or disable fault inputs
3783 (+) Configure the faults sampling clock
3784 (+) Configure an ADC trigger
3785
3786 @endverbatim
3787 * @{
3788 */
3789
3790 /**
3791 * @brief Configure the burst mode feature of the HRTIM
3792 * @param hhrtim pointer to HAL HRTIM handle
3793 * @param pBurstModeCfg pointer to the burst mode configuration structure
3794 * @retval HAL status
3795 * @note This function must be called before starting the burst mode
3796 * controller
3797 */
3798 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef * hhrtim,
3799 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
3800 {
3801 uint32_t hrtim_bmcr;
3802
3803 /* Check parameters */
3804 assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
3805 assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
3806 assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
3807 assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
3808 assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
3809
3810 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3811 {
3812 return HAL_BUSY;
3813 }
3814
3815 /* Process Locked */
3816 __HAL_LOCK(hhrtim);
3817
3818 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3819
3820 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
3821
3822 /* Set the burst mode operating mode */
3823 hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
3824 hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
3825
3826 /* Set the burst mode clock source */
3827 hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
3828 hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
3829
3830 /* Set the burst mode prescaler */
3831 hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
3832 hrtim_bmcr |= pBurstModeCfg->Prescaler;
3833
3834 /* Enable/disable burst mode registers preload */
3835 hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
3836 hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
3837
3838 /* Set the burst mode trigger */
3839 hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
3840
3841 /* Set the burst mode compare value */
3842 hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
3843
3844 /* Set the burst mode period */
3845 hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
3846
3847 /* Update the HRTIM registers */
3848 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
3849
3850 hhrtim->State = HAL_HRTIM_STATE_READY;
3851
3852 /* Process Unlocked */
3853 __HAL_UNLOCK(hhrtim);
3854
3855 return HAL_OK;
3856 }
3857
3858 /**
3859 * @brief Configure the conditioning of an external event
3860 * @param hhrtim pointer to HAL HRTIM handle
3861 * @param Event external event to configure
3862 * This parameter can be one of the following values:
3863 * @arg HRTIM_EVENT_NONE: no external Event
3864 * @arg HRTIM_EVENT_1: External event 1
3865 * @arg HRTIM_EVENT_2: External event 2
3866 * @arg HRTIM_EVENT_3: External event 3
3867 * @arg HRTIM_EVENT_4: External event 4
3868 * @arg HRTIM_EVENT_5: External event 5
3869 * @arg HRTIM_EVENT_6: External event 6
3870 * @arg HRTIM_EVENT_7: External event 7
3871 * @arg HRTIM_EVENT_8: External event 8
3872 * @arg HRTIM_EVENT_9: External event 9
3873 * @arg HRTIM_EVENT_10: External event 10
3874 * @param pEventCfg pointer to the event conditioning configuration structure
3875 * @note This function must be called before starting the timer
3876 * @retval HAL status
3877 */
3878 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
3879 uint32_t Event,
3880 HRTIM_EventCfgTypeDef* pEventCfg)
3881 {
3882 /* Check parameters */
3883 assert_param(IS_HRTIM_EVENT(Event));
3884 assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
3885 assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
3886 assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
3887 assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
3888
3889 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3890 {
3891 return HAL_BUSY;
3892 }
3893
3894 /* Process Locked */
3895 __HAL_LOCK(hhrtim);
3896
3897 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3898
3899 /* Configure the event channel */
3900 HRTIM_EventConfig(hhrtim, Event, pEventCfg);
3901
3902 hhrtim->State = HAL_HRTIM_STATE_READY;
3903
3904 /* Process Unlocked */
3905 __HAL_UNLOCK(hhrtim);
3906
3907 return HAL_OK;
3908 }
3909
3910 /**
3911 * @brief Configure the external event conditioning block prescaler
3912 * @param hhrtim pointer to HAL HRTIM handle
3913 * @param Prescaler Prescaler value
3914 * This parameter can be one of the following values:
3915 * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
3916 * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
3917 * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
3918 * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
3919 * @note This function must be called before starting the timer
3920 * @retval HAL status
3921 */
3922 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
3923 uint32_t Prescaler)
3924 {
3925 /* Check parameters */
3926 assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
3927
3928 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3929 {
3930 return HAL_BUSY;
3931 }
3932
3933 /* Process Locked */
3934 __HAL_LOCK(hhrtim);
3935
3936 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3937
3938 /* Set the external event prescaler */
3939 MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
3940
3941 hhrtim->State = HAL_HRTIM_STATE_READY;
3942
3943 /* Process Unlocked */
3944 __HAL_UNLOCK(hhrtim);
3945
3946 return HAL_OK;
3947 }
3948
3949 /**
3950 * @brief Configure the conditioning of fault input
3951 * @param hhrtim pointer to HAL HRTIM handle
3952 * @param Fault fault input to configure
3953 * This parameter can be one of the following values:
3954 * @arg HRTIM_FAULT_1: Fault input 1
3955 * @arg HRTIM_FAULT_2: Fault input 2
3956 * @arg HRTIM_FAULT_3: Fault input 3
3957 * @arg HRTIM_FAULT_4: Fault input 4
3958 * @arg HRTIM_FAULT_5: Fault input 5
3959 * @arg HRTIM_FAULT_6: Fault input 6
3960 * @param pFaultCfg pointer to the fault conditioning configuration structure
3961 * @note This function must be called before starting the timer and before
3962 * enabling faults inputs
3963 * @retval HAL status
3964 */
3965 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef * hhrtim,
3966 uint32_t Fault,
3967 HRTIM_FaultCfgTypeDef* pFaultCfg)
3968 {
3969 uint32_t hrtim_fltinr1;
3970 uint32_t hrtim_fltinr2;
3971 uint32_t source0,source1;
3972
3973 /* Check parameters */
3974 assert_param(IS_HRTIM_FAULT(Fault));
3975 assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
3976 assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
3977 assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
3978 assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
3979
3980 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
3981 {
3982 return HAL_BUSY;
3983 }
3984
3985 /* Process Locked */
3986 __HAL_LOCK(hhrtim);
3987
3988 hhrtim->State = HAL_HRTIM_STATE_BUSY;
3989
3990 /* Configure fault channel */
3991 hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
3992 hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
3993
3994 source0 = (pFaultCfg->Source & 1U);
3995 source1 = ((pFaultCfg->Source & 2U) >> 1);
3996
3997 switch (Fault)
3998 {
3999 case HRTIM_FAULT_1:
4000 {
4001 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
4002 hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
4003 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos);
4004 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1);
4005 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT1SRC_1_Pos);
4006 hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
4007 hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
4008 break;
4009 }
4010
4011 case HRTIM_FAULT_2:
4012 {
4013 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
4014 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
4015 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos);
4016 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1);
4017 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT2SRC_1_Pos);
4018 hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
4019 hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
4020 break;
4021 }
4022
4023 case HRTIM_FAULT_3:
4024 {
4025 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
4026 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
4027 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos);
4028 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1);
4029 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT3SRC_1_Pos);
4030 hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
4031 hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
4032 break;
4033 }
4034
4035 case HRTIM_FAULT_4:
4036 {
4037 hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
4038 hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
4039 hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos);
4040 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1);
4041 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT4SRC_1_Pos);
4042 hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
4043 hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
4044 break;
4045 }
4046
4047 case HRTIM_FAULT_5:
4048 {
4049 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
4050 hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
4051 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos);
4052 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1);
4053 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT5SRC_1_Pos);
4054 hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
4055 hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
4056 break;
4057 }
4058
4059 case HRTIM_FAULT_6:
4060 {
4061 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK);
4062 hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P);
4063 hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos);
4064 hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1);
4065 hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT6SRC_1_Pos);
4066 hrtim_fltinr2 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR2_FLT6F);
4067 hrtim_fltinr2 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR2_FLT6LCK);
4068 break;
4069 }
4070
4071 default:
4072 {
4073 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4074
4075 /* Process Unlocked */
4076 __HAL_UNLOCK(hhrtim);
4077
4078 break;
4079 }
4080 }
4081
4082 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4083 {
4084 return HAL_ERROR;
4085 }
4086
4087 /* Update the HRTIM registers except LOCK bit */
4088 hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
4089 hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
4090
4091 /* Update the HRTIM registers LOCK bit */
4092 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1,(hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
4093 SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2,(hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
4094
4095 hhrtim->State = HAL_HRTIM_STATE_READY;
4096
4097 /* Process Unlocked */
4098 __HAL_UNLOCK(hhrtim);
4099
4100 return HAL_OK;
4101 }
4102
4103 /**
4104 * @brief Configure the fault conditioning block prescaler
4105 * @param hhrtim pointer to HAL HRTIM handle
4106 * @param Prescaler Prescaler value
4107 * This parameter can be one of the following values:
4108 * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
4109 * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
4110 * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
4111 * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
4112 * @retval HAL status
4113 * @note This function must be called before starting the timer and before
4114 * enabling faults inputs
4115 */
4116 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef * hhrtim,
4117 uint32_t Prescaler)
4118 {
4119 /* Check parameters */
4120 assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
4121
4122 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4123 {
4124 return HAL_BUSY;
4125 }
4126
4127 /* Process Locked */
4128 __HAL_LOCK(hhrtim);
4129
4130 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4131
4132 /* Set the external event prescaler */
4133 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
4134
4135 hhrtim->State = HAL_HRTIM_STATE_READY;
4136
4137 /* Process Unlocked */
4138 __HAL_UNLOCK(hhrtim);
4139
4140 return HAL_OK;
4141 }
4142
4143 /**
4144 * @brief Configure and Enable the blanking source of a Fault input
4145 * @param hhrtim pointer to HAL HRTIM handle
4146 * @param Fault fault input to configure
4147 * This parameter can be one of the following values:
4148 * @arg HRTIM_FAULT_1: Fault input 1
4149 * @arg HRTIM_FAULT_2: Fault input 2
4150 * @arg HRTIM_FAULT_3: Fault input 3
4151 * @arg HRTIM_FAULT_4: Fault input 4
4152 * @arg HRTIM_FAULT_5: Fault input 5
4153 * @arg HRTIM_FAULT_6: Fault input 6
4154 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4155 * @note This function automatically enables the Blanking on Fault
4156 * @note This function must be called when fault is not enabled
4157 * @retval HAL status
4158 */
4159 HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,
4160 uint32_t Fault,
4161 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
4162 {
4163 /* Check parameters */
4164 assert_param(IS_HRTIM_FAULT(Fault));
4165 assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource));
4166
4167 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4168 {
4169 return HAL_BUSY;
4170 }
4171
4172 /* Process Locked */
4173 __HAL_LOCK(hhrtim);
4174
4175 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4176
4177 switch (Fault)
4178 {
4179 case HRTIM_FAULT_1:
4180 {
4181 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4182 (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE),
4183 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) |
4184 HRTIM_FLTINR3_FLT1BLKE));
4185 break;
4186 }
4187 case HRTIM_FAULT_2:
4188 {
4189 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4190 (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE),
4191 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) |
4192 HRTIM_FLTINR3_FLT2BLKE));
4193 break;
4194 }
4195 case HRTIM_FAULT_3:
4196 {
4197 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4198 (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE),
4199 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) |
4200 HRTIM_FLTINR3_FLT3BLKE));
4201 break;
4202 }
4203 case HRTIM_FAULT_4:
4204 {
4205 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4206 (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE),
4207 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) |
4208 HRTIM_FLTINR3_FLT4BLKE));
4209 break;
4210 }
4211 case HRTIM_FAULT_5:
4212 {
4213 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4214 (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE),
4215 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) |
4216 HRTIM_FLTINR4_FLT5BLKE));
4217 break;
4218 }
4219 case HRTIM_FAULT_6:
4220 {
4221 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4222 (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE),
4223 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) |
4224 HRTIM_FLTINR4_FLT6BLKE));
4225 break;
4226 }
4227
4228 default:
4229 {
4230 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4231
4232 /* Process Unlocked */
4233 __HAL_UNLOCK(hhrtim);
4234
4235 break;
4236 }
4237 }
4238
4239 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4240 {
4241 return HAL_ERROR;
4242 }
4243
4244 hhrtim->State = HAL_HRTIM_STATE_READY;
4245
4246 /* Process Unlocked */
4247 __HAL_UNLOCK(hhrtim);
4248
4249 return HAL_OK;
4250 }
4251
4252 /**
4253 * @brief Configure the Fault Counter (Threshold and Reset Mode)
4254 * @param hhrtim pointer to HAL HRTIM handle
4255 * @param Fault fault input to configure
4256 * This parameter can be one of the following values:
4257 * @arg HRTIM_FAULT_1: Fault input 1
4258 * @arg HRTIM_FAULT_2: Fault input 2
4259 * @arg HRTIM_FAULT_3: Fault input 3
4260 * @arg HRTIM_FAULT_4: Fault input 4
4261 * @arg HRTIM_FAULT_5: Fault input 5
4262 * @arg HRTIM_FAULT_6: Fault input 6
4263 * @param pFaultBlkCfg: pointer to the fault conditioning configuration structure
4264 * @retval HAL status
4265 * @note A fault is considered valid when the number of
4266 * events is equal to the (FLTxCNT[3:0]+1) value
4267 *
4268 * @retval HAL status
4269 */
4270 HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,
4271 uint32_t Fault,
4272 HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg)
4273 {
4274 /* Check parameters */
4275 assert_param(IS_HRTIM_FAULT(Fault));
4276 assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold));
4277 assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode));
4278
4279 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4280 {
4281 return HAL_BUSY;
4282 }
4283
4284 /* Process Locked */
4285 __HAL_LOCK(hhrtim);
4286
4287 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4288
4289 switch (Fault)
4290 {
4291 case HRTIM_FAULT_1:
4292 {
4293 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4294 (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT),
4295 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) |
4296 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos));
4297 break;
4298 }
4299 case HRTIM_FAULT_2:
4300 {
4301 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4302 (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT),
4303 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) |
4304 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos));
4305 break;
4306 }
4307 case HRTIM_FAULT_3:
4308 {
4309 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4310 (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT),
4311 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) |
4312 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos));
4313 break;
4314 }
4315 case HRTIM_FAULT_4:
4316 {
4317 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
4318 (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT),
4319 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) |
4320 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos));
4321 break;
4322 }
4323 case HRTIM_FAULT_5:
4324 {
4325 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4326 (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT),
4327 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) |
4328 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos));
4329 break;
4330 }
4331 case HRTIM_FAULT_6:
4332 {
4333 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
4334 (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT),
4335 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) |
4336 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos));
4337 break;
4338 }
4339
4340 default:
4341 {
4342 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4343
4344 /* Process Unlocked */
4345 __HAL_UNLOCK(hhrtim);
4346
4347 break;
4348 }
4349 }
4350
4351 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4352 {
4353 return HAL_ERROR;
4354 }
4355
4356 hhrtim->State = HAL_HRTIM_STATE_READY;
4357
4358 /* Process Unlocked */
4359 __HAL_UNLOCK(hhrtim);
4360
4361 return HAL_OK;
4362 }
4363
4364 /**
4365 * @brief Reset the fault Counter Reset
4366 * @param hhrtim pointer to HAL HRTIM handle
4367 * @param Fault fault input to reset
4368 * This parameter can be one of the following values:
4369 * @arg HRTIM_FAULT_1: Fault input 1
4370 * @arg HRTIM_FAULT_2: Fault input 2
4371 * @arg HRTIM_FAULT_3: Fault input 3
4372 * @arg HRTIM_FAULT_4: Fault input 4
4373 * @arg HRTIM_FAULT_5: Fault input 5
4374 * @arg HRTIM_FAULT_6: Fault input 6
4375 * @retval HAL status
4376 */
4377 HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,
4378 uint32_t Fault)
4379 {
4380 /* Check parameters */
4381 assert_param(IS_HRTIM_FAULT(Fault));
4382
4383 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4384 {
4385 return HAL_BUSY;
4386 }
4387
4388 /* Process Locked */
4389 __HAL_LOCK(hhrtim);
4390
4391 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4392
4393 switch (Fault)
4394 {
4395 case HRTIM_FAULT_1:
4396 {
4397 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ;
4398 break;
4399 }
4400 case HRTIM_FAULT_2:
4401 {
4402 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ;
4403 break;
4404 }
4405 case HRTIM_FAULT_3:
4406 {
4407 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ;
4408 break;
4409 }
4410 case HRTIM_FAULT_4:
4411 {
4412 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ;
4413 break;
4414 }
4415 case HRTIM_FAULT_5:
4416 {
4417 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ;
4418 break;
4419 }
4420 case HRTIM_FAULT_6:
4421 {
4422 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ;
4423 break;
4424 }
4425
4426 default:
4427 {
4428 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4429
4430 /* Process Unlocked */
4431 __HAL_UNLOCK(hhrtim);
4432
4433 break;
4434 }
4435 }
4436
4437 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4438 {
4439 return HAL_ERROR;
4440 }
4441
4442 hhrtim->State = HAL_HRTIM_STATE_READY;
4443
4444 /* Process Unlocked */
4445 __HAL_UNLOCK(hhrtim);
4446
4447 return HAL_OK;
4448 }
4449
4450 /**
4451 * @brief Enable or disables the HRTIMx Fault mode.
4452 * @param hhrtim pointer to HAL HRTIM handle
4453 * @param Faults fault input(s) to enable or disable
4454 * This parameter can be any combination of the following values:
4455 * @arg HRTIM_FAULT_1: Fault input 1
4456 * @arg HRTIM_FAULT_2: Fault input 2
4457 * @arg HRTIM_FAULT_3: Fault input 3
4458 * @arg HRTIM_FAULT_4: Fault input 4
4459 * @arg HRTIM_FAULT_5: Fault input 5
4460 * @arg HRTIM_FAULT_6: Fault input 6
4461 * @param Enable Fault(s) enabling
4462 * This parameter can be one of the following values:
4463 * @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
4464 * @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
4465 * @retval None
4466 */
4467 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
4468 uint32_t Faults,
4469 uint32_t Enable)
4470 {
4471 /* Check parameters */
4472 assert_param(IS_HRTIM_FAULT(Faults));
4473 assert_param(IS_HRTIM_FAULTMODECTL(Enable));
4474
4475 if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
4476 {
4477 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
4478 }
4479 if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
4480 {
4481 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
4482 }
4483 if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
4484 {
4485 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
4486 }
4487 if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
4488 {
4489 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
4490 }
4491 if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
4492 {
4493 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
4494 }
4495 if ((Faults & HRTIM_FAULT_6) != (uint32_t)RESET)
4496 {
4497 MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT6E, ((Enable << 8U) & HRTIM_FLTINR2_FLT6E));
4498 }
4499 }
4500
4501 /**
4502 * @brief Configure both the ADC trigger register update source and the ADC
4503 * trigger source.
4504 * @param hhrtim pointer to HAL HRTIM handle
4505 * @param ADCTrigger ADC trigger to configure
4506 * This parameter can be one of the following values:
4507 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4508 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4509 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4510 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4511 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4512 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4513 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4514 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4515 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4516 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4517 * @param pADCTriggerCfg pointer to the ADC trigger configuration structure
4518 * for Trigger nb (1..4): pADCTriggerCfg->Trigger parameter
4519 * can be a combination of the following values
4520 * @arg HRTIM_ADCTRIGGEREVENT13_...
4521 * @arg HRTIM_ADCTRIGGEREVENT24_...
4522 * for Trigger nb (5..10): pADCTriggerCfg->Trigger parameter
4523 * can be one of the following values
4524 * @arg HRTIM_ADCTRIGGEREVENT579_...
4525 * @arg HRTIM_ADCTRIGGEREVENT6810_...
4526 * @retval HAL status
4527 * @note This function must be called before starting the timer
4528 */
4529 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef * hhrtim,
4530 uint32_t ADCTrigger,
4531 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
4532 {
4533 uint32_t hrtim_cr1;
4534 uint32_t hrtim_adcur;
4535
4536 /* Check parameters */
4537 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4538 assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
4539
4540 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4541 {
4542 return HAL_BUSY;
4543 }
4544
4545 /* Process Locked */
4546 __HAL_LOCK(hhrtim);
4547
4548 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4549
4550 /* Set the ADC trigger update source */
4551 hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
4552 hrtim_adcur = hhrtim->Instance->sCommonRegs.ADCUR;
4553
4554 switch (ADCTrigger)
4555 {
4556 case HRTIM_ADCTRIGGER_1:
4557 {
4558 hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
4559 hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
4560
4561 /* Set the ADC trigger 1 source */
4562 hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
4563 break;
4564 }
4565
4566 case HRTIM_ADCTRIGGER_2:
4567 {
4568 hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
4569 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
4570
4571 /* Set the ADC trigger 2 source */
4572 hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
4573 break;
4574 }
4575
4576 case HRTIM_ADCTRIGGER_3:
4577 {
4578 hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
4579 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
4580
4581 /* Set the ADC trigger 3 source */
4582 hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
4583 break;
4584 }
4585
4586 case HRTIM_ADCTRIGGER_4:
4587 {
4588 hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
4589 hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
4590
4591 /* Set the ADC trigger 4 source */
4592 hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
4593 break;
4594 }
4595
4596 case HRTIM_ADCTRIGGER_5:
4597 {
4598 hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC);
4599 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC);
4600
4601 /* Set the ADC trigger 5 source */
4602 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD5TRG);
4603 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD5TRG_Pos) & HRTIM_ADCER_AD5TRG);
4604 break;
4605 }
4606
4607 case HRTIM_ADCTRIGGER_6:
4608 {
4609 hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC);
4610 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC);
4611
4612 /* Set the ADC trigger 6 source */
4613 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD6TRG);
4614 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD6TRG_Pos) & HRTIM_ADCER_AD6TRG);
4615 break;
4616 }
4617
4618 case HRTIM_ADCTRIGGER_7:
4619 {
4620 hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC);
4621 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC);
4622
4623 /* Set the ADC trigger 7 source */
4624 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD7TRG);
4625 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD7TRG_Pos) & HRTIM_ADCER_AD7TRG);
4626 break;
4627 }
4628
4629 case HRTIM_ADCTRIGGER_8:
4630 {
4631 hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC);
4632 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC);
4633
4634 /* Set the ADC trigger 8 source */
4635 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD8TRG);
4636 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD8TRG_Pos) & HRTIM_ADCER_AD8TRG);
4637 break;
4638 }
4639
4640 case HRTIM_ADCTRIGGER_9:
4641 {
4642 hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC);
4643 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC);
4644
4645 /* Set the ADC trigger 9 source */
4646 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD9TRG);
4647 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD9TRG_Pos) & HRTIM_ADCER_AD9TRG);
4648 break;
4649 }
4650
4651 case HRTIM_ADCTRIGGER_10:
4652 {
4653 hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC);
4654 hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC);
4655
4656 /* Set the ADC trigger 10 source */
4657 hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD10TRG);
4658 hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD10TRG_Pos) & HRTIM_ADCER_AD10TRG);
4659 break;
4660 }
4661
4662 default:
4663 {
4664 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4665
4666 /* Process Unlocked */
4667 __HAL_UNLOCK(hhrtim);
4668
4669 break;
4670 }
4671 }
4672
4673 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4674 {
4675 return HAL_ERROR;
4676 }
4677
4678 /* Update the HRTIM registers */
4679 if (ADCTrigger < HRTIM_ADCTRIGGER_5)
4680 {
4681 hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
4682 }
4683 else
4684 {
4685 hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur;
4686 }
4687
4688 hhrtim->State = HAL_HRTIM_STATE_READY;
4689
4690 /* Process Unlocked */
4691 __HAL_UNLOCK(hhrtim);
4692
4693 return HAL_OK;
4694 }
4695
4696 /**
4697 * @brief Configure the ADC trigger postscaler register of the ADC
4698 * trigger source.
4699 * @param hhrtim pointer to HAL HRTIM handle
4700 * @param ADCTrigger ADC trigger to configure
4701 * This parameter can be one of the following values:
4702 * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
4703 * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
4704 * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
4705 * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
4706 * @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
4707 * @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
4708 * @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
4709 * @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
4710 * @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
4711 * @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
4712 * @param Postscaler value 0..1F
4713 * @retval HAL status
4714 * @note This function must be called before starting the timer
4715 */
4716 HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,
4717 uint32_t ADCTrigger,
4718 uint32_t Postscaler)
4719 {
4720 /* Check parameters */
4721 assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
4722
4723 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4724 {
4725 return HAL_BUSY;
4726 }
4727
4728 /* Process Locked */
4729 __HAL_LOCK(hhrtim);
4730
4731 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4732
4733 switch (ADCTrigger)
4734 {
4735 case HRTIM_ADCTRIGGER_1:
4736 {
4737 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC));
4738 break;
4739 }
4740
4741 case HRTIM_ADCTRIGGER_2:
4742 {
4743 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC));
4744 break;
4745 }
4746
4747 case HRTIM_ADCTRIGGER_3:
4748 {
4749 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC));
4750 break;
4751 }
4752
4753 case HRTIM_ADCTRIGGER_4:
4754 {
4755 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC));
4756 break;
4757 }
4758
4759 case HRTIM_ADCTRIGGER_5:
4760 {
4761 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC));
4762 break;
4763 }
4764
4765 case HRTIM_ADCTRIGGER_6:
4766 {
4767 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC));
4768 break;
4769 }
4770
4771 case HRTIM_ADCTRIGGER_7:
4772 {
4773 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC));
4774 break;
4775 }
4776
4777 case HRTIM_ADCTRIGGER_8:
4778 {
4779 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC));
4780 break;
4781 }
4782
4783 case HRTIM_ADCTRIGGER_9:
4784 {
4785 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC));
4786 break;
4787 }
4788
4789 case HRTIM_ADCTRIGGER_10:
4790 {
4791 MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC));
4792 break;
4793 }
4794
4795 default:
4796 {
4797 hhrtim->State = HAL_HRTIM_STATE_ERROR;
4798
4799 /* Process Unlocked */
4800 __HAL_UNLOCK(hhrtim);
4801
4802 break;
4803 }
4804 }
4805
4806 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
4807 {
4808 return HAL_ERROR;
4809 }
4810
4811 hhrtim->State = HAL_HRTIM_STATE_READY;
4812
4813 /* Process Unlocked */
4814 __HAL_UNLOCK(hhrtim);
4815
4816 return HAL_OK;
4817 }
4818
4819 /**
4820 * @brief Configure the ADC Roll-Over mode of the ADC
4821 * trigger source.
4822 * @param hhrtim pointer to HAL HRTIM handle
4823 * @param TimerIdx Timer index
4824 * This parameter can be one of the following values:
4825 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4826 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4827 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4828 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4829 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4830 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4831 * @param RollOverCfg This parameter can be a combination of all the following values:
4832 * @arg HRTIM_TIM_FEROM_BOTH or HRTIM_TIM_FEROM_CREST or HRTIM_TIM_FEROM_VALLEY
4833 * @arg HRTIM_TIM_BMROM_BOTH or HRTIM_TIM_BMROM_CREST or HRTIM_TIM_BMROM_VALLEY
4834 * @arg HRTIM_TIM_ADROM_BOTH or HRTIM_TIM_ADROM_CREST or HRTIM_TIM_ADROM_VALLEY
4835 * @arg HRTIM_TIM_OUTROM_BOTH or HRTIM_TIM_OUTROM_CREST or HRTIM_TIM_OUTROM_VALLEY
4836 * @arg HRTIM_TIM_ROM_BOTH or HRTIM_TIM_ROM_CREST or HRTIM_TIM_ROM_VALLEY
4837 * @note This function must be called before starting the timer
4838 */
4839 HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,
4840 uint32_t TimerIdx,
4841 uint32_t RollOverCfg)
4842 {
4843 /* Check parameters */
4844 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
4845 assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg));
4846
4847 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4848 {
4849 return HAL_BUSY;
4850 }
4851
4852 /* Process Locked */
4853 __HAL_LOCK(hhrtim);
4854
4855 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4856
4857 HRTIM_TimingUnitRollOver_Config(hhrtim,TimerIdx,RollOverCfg);
4858
4859 hhrtim->State = HAL_HRTIM_STATE_READY;
4860
4861 /* Process Unlocked */
4862 __HAL_UNLOCK(hhrtim);
4863
4864 return HAL_OK;
4865 }
4866
4867
4868 /**
4869 * @}
4870 */
4871
4872 /** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
4873 * @brief HRTIM timer configuration and control functions
4874 @verbatim
4875 ===============================================================================
4876 ##### HRTIM timer configuration and control functions #####
4877 ===============================================================================
4878 [..] This section provides functions used to configure and control a
4879 HRTIM timer operating in waveform mode:
4880 (+) Configure HRTIM timer general behavior
4881 (+) Configure HRTIM timer event filtering
4882 (+) Configure HRTIM timer deadtime insertion
4883 (+) Configure HRTIM timer chopper mode
4884 (+) Configure HRTIM timer burst DMA
4885 (+) Configure HRTIM timer compare unit
4886 (+) Configure HRTIM timer capture unit
4887 (+) Configure HRTIM timer output
4888 (+) Set HRTIM timer output level
4889 (+) Enable HRTIM timer output
4890 (+) Disable HRTIM timer output
4891 (+) Start HRTIM timer
4892 (+) Stop HRTIM timer
4893 (+) Start HRTIM timer and enable interrupt
4894 (+) Stop HRTIM timer and disable interrupt
4895 (+) Start HRTIM timer and enable DMA transfer
4896 (+) Stop HRTIM timer and disable DMA transfer
4897 (+) Enable or disable the burst mode controller
4898 (+) Start the burst mode controller (by software)
4899 (+) Trigger a Capture (by software)
4900 (+) Update the HRTIM timer preloadable registers (by software)
4901 (+) Reset the HRTIM timer counter (by software)
4902 (+) Start a burst DMA transfer
4903 (+) Enable timer register update
4904 (+) Disable timer register update
4905
4906 @endverbatim
4907 * @{
4908 */
4909
4910 /**
4911 * @brief Configure the general behavior of a timer operating in waveform mode
4912 * @param hhrtim pointer to HAL HRTIM handle
4913 * @param TimerIdx Timer index
4914 * This parameter can be one of the following values:
4915 * @arg HRTIM_TIMERINDEX_MASTER for master timer
4916 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
4917 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
4918 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
4919 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
4920 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
4921 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
4922 * @param pTimerCfg pointer to the timer configuration structure
4923 * @note When the timer operates in waveform mode, all the features supported by
4924 * the HRTIM are available without any limitation.
4925 * @retval HAL status
4926 * @note This function must be called before starting the timer
4927 */
4928 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef * hhrtim,
4929 uint32_t TimerIdx,
4930 HRTIM_TimerCfgTypeDef * pTimerCfg)
4931 {
4932 /* Check parameters */
4933 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
4934
4935 /* Relevant for all HRTIM timers, including the master */
4936 assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
4937 assert_param(IS_HRTIM_INTERLEAVEDMODE(pTimerCfg->InterleavedMode));
4938 assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
4939 assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
4940 assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
4941 assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
4942 assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
4943 assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
4944
4945 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
4946 {
4947 return HAL_BUSY;
4948 }
4949
4950 /* Process Locked */
4951 __HAL_LOCK(hhrtim);
4952
4953 hhrtim->State = HAL_HRTIM_STATE_BUSY;
4954
4955 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
4956 {
4957 /* Check parameters */
4958 assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
4959 assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
4960 assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
4961
4962 /* Configure master timer */
4963 HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
4964 }
4965 else
4966 {
4967 /* Check parameters */
4968 assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
4969 assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
4970 assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
4971 assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
4972 assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
4973 assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
4974 assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
4975 pTimerCfg->DeadTimeInsertion));
4976 assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
4977 pTimerCfg->DelayedProtectionMode));
4978 assert_param(IS_HRTIM_OUTPUTBALANCEDIDLE(pTimerCfg->BalancedIdleAutomaticResume));
4979 assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
4980 assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
4981 assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
4982 assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
4983
4984 /* Configure timing unit */
4985 HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
4986 }
4987
4988 /* Update timer parameters */
4989 hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
4990 hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
4991 hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
4992 hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
4993 hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
4994
4995 /* Force a software update */
4996 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
4997
4998 hhrtim->State = HAL_HRTIM_STATE_READY;
4999
5000 /* Process Unlocked */
5001 __HAL_UNLOCK(hhrtim);
5002
5003 return HAL_OK;
5004 }
5005
5006 /**
5007 * @brief Configure the general behavior of a timer operating in waveform mode
5008 * @param hhrtim pointer to HAL HRTIM handle
5009 * @param TimerIdx Timer index
5010 * This parameter can be one of the following values:
5011 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5012 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5013 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5014 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5015 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5016 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5017 * @param pTimerCtl pointer to the timer configuration structure
5018 * @note When the timer operates in waveform mode, all the features supported by
5019 * the HRTIM are available without any limitation.
5020 * @retval HAL status
5021 * @note This function must be called before starting the timer
5022 */
5023 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,
5024 uint32_t TimerIdx,
5025 HRTIM_TimerCtlTypeDef * pTimerCtl)
5026 {
5027 /* Check parameters */
5028 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5029 /* Relevant for all A..F HRTIM timers */
5030 assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode));
5031 assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf));
5032 assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3));
5033 assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
5034 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5035 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5036 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5037
5038 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5039 {
5040 return HAL_BUSY;
5041 }
5042
5043 /* Process Locked */
5044 __HAL_LOCK(hhrtim);
5045
5046 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5047
5048 /* Configure timing unit */
5049 HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
5050
5051 /* Force a software update */
5052 HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
5053
5054 hhrtim->State = HAL_HRTIM_STATE_READY;
5055
5056 /* Process Unlocked */
5057 __HAL_UNLOCK(hhrtim);
5058
5059 return HAL_OK;
5060 }
5061
5062 /**
5063 * @brief Configure the Dual Channel Dac behavior of a timer operating in waveform mode
5064 * @param hhrtim: pointer to HAL HRTIM handle
5065 * @param TimerIdx Timer index
5066 * This parameter can be one of the following values:
5067 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5068 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5069 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5070 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5071 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5072 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5073 * @param pTimerCtl pointer to the timer DualChannel Dac configuration structure
5074 * @note When the timer operates in waveform mode, all the features supported by
5075 * the HRTIM are available without any limitation.
5076 * @retval HAL status
5077 * @note This function must be called before starting the timer
5078 */
5079 HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,
5080 uint32_t TimerIdx,
5081 HRTIM_TimerCtlTypeDef * pTimerCtl)
5082 {
5083 assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
5084 assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
5085 assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
5086
5087 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5088 {
5089 return HAL_BUSY;
5090 }
5091
5092 /* Process Locked */
5093 __HAL_LOCK(hhrtim);
5094
5095 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5096 /* clear DCDS,DCDR,DCDE bits */
5097 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
5098 (HRTIM_TIMER_DCDE_ENABLED |
5099 HRTIM_TIMER_DCDS_OUT1RST |
5100 HRTIM_TIMER_DCDR_OUT1SET) );
5101
5102 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 ,
5103 (HRTIM_TIMER_DCDE_ENABLED |
5104 HRTIM_TIMER_DCDS_OUT1RST |
5105 HRTIM_TIMER_DCDR_OUT1SET),
5106 (pTimerCtl->DualChannelDacReset |
5107 pTimerCtl->DualChannelDacStep |
5108 pTimerCtl->DualChannelDacEnable));
5109
5110 hhrtim->State = HAL_HRTIM_STATE_READY;
5111
5112 /* Process Unlocked */
5113 __HAL_UNLOCK(hhrtim);
5114
5115 return HAL_OK;
5116 }
5117
5118 /**
5119 * @brief Configure the event filtering capabilities of a timer (blanking, windowing)
5120 * @param hhrtim pointer to HAL HRTIM handle
5121 * @param TimerIdx Timer index
5122 * This parameter can be one of the following values:
5123 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5124 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5125 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5126 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5127 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5128 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5129 * @param Event external event for which timer event filtering must be configured
5130 * This parameter can be one of the following values:
5131 * @arg HRTIM_EVENT_1: External event 1
5132 * @arg HRTIM_EVENT_2: External event 2
5133 * @arg HRTIM_EVENT_3: External event 3
5134 * @arg HRTIM_EVENT_4: External event 4
5135 * @arg HRTIM_EVENT_5: External event 5
5136 * @arg HRTIM_EVENT_6: External event 6
5137 * @arg HRTIM_EVENT_7: External event 7
5138 * @arg HRTIM_EVENT_8: External event 8
5139 * @arg HRTIM_EVENT_9: External event 9
5140 * @arg HRTIM_EVENT_10: External event 10
5141 * @param pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
5142 * @note This function must be called before starting the timer
5143 * @retval HAL status
5144 */
5145 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef * hhrtim,
5146 uint32_t TimerIdx,
5147 uint32_t Event,
5148 HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
5149 {
5150 /* Check parameters */
5151 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5152 assert_param(IS_HRTIM_EVENT(Event));
5153 assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx,pTimerEventFilteringCfg->Filter));
5154
5155 assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
5156
5157 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5158 {
5159 return HAL_BUSY;
5160 }
5161
5162 /* Process Locked */
5163 __HAL_LOCK(hhrtim);
5164
5165 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5166
5167 /* Configure timer event filtering capabilities */
5168 switch (Event)
5169 {
5170 case HRTIM_EVENT_NONE:
5171 {
5172 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
5173 CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
5174 break;
5175 }
5176
5177 case HRTIM_EVENT_1:
5178 {
5179 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
5180 break;
5181 }
5182
5183 case HRTIM_EVENT_2:
5184 {
5185 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
5186 break;
5187 }
5188
5189 case HRTIM_EVENT_3:
5190 {
5191 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
5192 break;
5193 }
5194
5195 case HRTIM_EVENT_4:
5196 {
5197 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
5198 break;
5199 }
5200
5201 case HRTIM_EVENT_5:
5202 {
5203 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
5204 break;
5205 }
5206
5207 case HRTIM_EVENT_6:
5208 {
5209 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH), (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) );
5210 break;
5211 }
5212
5213 case HRTIM_EVENT_7:
5214 {
5215 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U) );
5216 break;
5217 }
5218
5219 case HRTIM_EVENT_8:
5220 {
5221 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U) );
5222 break;
5223 }
5224
5225 case HRTIM_EVENT_9:
5226 {
5227 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U) );
5228 break;
5229 }
5230
5231 case HRTIM_EVENT_10:
5232 {
5233 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH), ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U) );
5234 break;
5235 }
5236
5237 default:
5238 {
5239 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5240
5241 /* Process Unlocked */
5242 __HAL_UNLOCK(hhrtim);
5243
5244 break;
5245 }
5246 }
5247
5248 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5249 {
5250 return HAL_ERROR;
5251 }
5252
5253 hhrtim->State = HAL_HRTIM_STATE_READY;
5254
5255 /* Process Unlocked */
5256 __HAL_UNLOCK(hhrtim);
5257
5258 return HAL_OK;
5259 }
5260
5261 /**
5262 * @brief Configure the external Event Counter A or B of a timer (source, threshold, reset mode)
5263 * but does not enable : call HAL_HRTIM_ExternalEventCounterEnable afterwards
5264 * @param hhrtim pointer to HAL HRTIM handle
5265 * @param TimerIdx Timer index
5266 * This parameter can be one of the following values:
5267 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5268 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5269 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5270 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5271 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5272 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5273 * @param EventCounter external event Counter A or B for which timer event must be configured
5274 * This parameter can be one of the following values:
5275 * @arg HRTIM_TIMEEVENT_A
5276 * @arg HRTIM_TIMEEVENT_B
5277 * @param pTimerExternalEventCfg: pointer to the timer external event configuration structure
5278 * @note This function must be called before starting the timer
5279 * @retval HAL status
5280 */
5281 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,
5282 uint32_t TimerIdx,
5283 uint32_t EventCounter,
5284 HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg)
5285 {
5286 uint32_t hrtim_eefr3;
5287
5288 /* Check parameters */
5289 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5290 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5291 assert_param(IS_HRTIM_TIMEEVENT_RESETMODE(pTimerExternalEventCfg->ResetMode));
5292 assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter));
5293 assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source));
5294
5295 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5296 {
5297 return HAL_BUSY;
5298 }
5299
5300 /* Process Locked */
5301 __HAL_LOCK(hhrtim);
5302
5303 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5304
5305 if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U)
5306 {
5307 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5308 { /* reset External EventCounter A */
5309 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U);
5310 }
5311 else
5312 {
5313 /* Set timer External EventCounter A configuration */
5314 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos;
5315 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos;
5316 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos;
5317 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5318
5319 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT) , hrtim_eefr3 );
5320 }
5321 }
5322
5323 if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U)
5324 {
5325 if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
5326 { /* reset External EventCounter B */
5327 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU);
5328 }
5329 else
5330 {
5331 /* Set timer External EventCounter B configuration */
5332 hrtim_eefr3 = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos;
5333 hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos;
5334 hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos;
5335 /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
5336
5337 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT) , hrtim_eefr3 );
5338 }
5339 }
5340 hhrtim->State = HAL_HRTIM_STATE_READY;
5341
5342 /* Process Unlocked */
5343 __HAL_UNLOCK(hhrtim);
5344
5345 return HAL_OK;
5346 }
5347
5348 /**
5349 * @brief Enable the external event Counter A or B of a timer
5350 * @param hhrtim: pointer to HAL HRTIM handle
5351 * @param TimerIdx: Timer index
5352 * This parameter can be one of the following values:
5353 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5354 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5355 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5356 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5357 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5358 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5359 * @param EventCounter external Event Counter A or B for which timer event must be configured
5360 * This parameter can be a one of the following values:
5361 * @arg HRTIM_TIMEEVENT_A
5362 * @arg HRTIM_TIMEEVENT_B
5363 * @note This function must be called before starting the timer
5364 * @retval HAL status
5365 */
5366 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,
5367 uint32_t TimerIdx,
5368 uint32_t EventCounter)
5369 {
5370 /* Check parameters */
5371 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5372 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5373
5374 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5375 {
5376 return HAL_BUSY;
5377 }
5378
5379 /* Process Locked */
5380 __HAL_LOCK(hhrtim);
5381
5382 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5383
5384 if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U)
5385 {
5386 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5387 }
5388 if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U)
5389 {
5390 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5391 }
5392
5393 hhrtim->State = HAL_HRTIM_STATE_READY;
5394
5395 /* Process Unlocked */
5396 __HAL_UNLOCK(hhrtim);
5397
5398 return HAL_OK;
5399 }
5400
5401 /**
5402 * @brief Disable the external event Counter A or B of a timer
5403 * @param hhrtim: pointer to HAL HRTIM handle
5404 * @param TimerIdx: Timer index
5405 * This parameter can be one of the following values:
5406 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5407 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5408 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5409 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5410 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5411 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5412 * @param EventCounter external event Counter A or B for which timer event must be configured
5413 * This parameter can be a one of the following values:
5414 * @arg HRTIM_TIMEEVENT_A
5415 * @arg HRTIM_TIMEEVENT_B
5416 * @retval HAL status
5417 */
5418 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,
5419 uint32_t TimerIdx,
5420 uint32_t EventCounter)
5421 {
5422 /* Check parameters */
5423 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5424 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5425
5426 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5427 {
5428 return HAL_BUSY;
5429 }
5430
5431 /* Process Locked */
5432 __HAL_LOCK(hhrtim);
5433
5434 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5435
5436 if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U)
5437 {
5438 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
5439 }
5440
5441 if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U)
5442 {
5443 CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
5444 }
5445
5446 hhrtim->State = HAL_HRTIM_STATE_READY;
5447
5448 /* Process Unlocked */
5449 __HAL_UNLOCK(hhrtim);
5450
5451 return HAL_OK;
5452 }
5453
5454 /**
5455 * @brief Reset the external event Counter A or B of a timer
5456 * @param hhrtim pointer to HAL HRTIM handle
5457 * @param TimerIdx Timer index
5458 * This parameter can be one of the following values:
5459 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5460 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5461 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5462 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5463 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5464 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5465 * @param EventCounter external event Counter A or B for which timer event must be configured
5466 * This parameter can be one of the following values:
5467 * @arg HRTIM_TIMEEVENT_A
5468 * @arg HRTIM_TIMEEVENT_B
5469 * @note This function must be called before starting the timer
5470 * @retval HAL status
5471 */
5472 HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,
5473 uint32_t TimerIdx,
5474 uint32_t EventCounter)
5475 {
5476 /* Check parameters */
5477 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5478 assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
5479
5480 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5481 {
5482 return HAL_BUSY;
5483 }
5484
5485 /* Process Locked */
5486 __HAL_LOCK(hhrtim);
5487
5488 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5489
5490 if ((EventCounter & HRTIM_TIMEEVENT_A) != 0U)
5491 {
5492 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES);
5493 }
5494 if ((EventCounter & HRTIM_TIMEEVENT_B) != 0U)
5495 {
5496 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,HRTIM_EEFR3_EEVBCRES);
5497 }
5498
5499 hhrtim->State = HAL_HRTIM_STATE_READY;
5500
5501 /* Process Unlocked */
5502 __HAL_UNLOCK(hhrtim);
5503
5504 return HAL_OK;
5505 }
5506
5507 /**
5508 * @brief Configure the dead-time insertion feature for a timer
5509 * @param hhrtim pointer to HAL HRTIM handle
5510 * @param TimerIdx Timer index
5511 * This parameter can be one of the following values:
5512 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5513 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5514 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5515 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5516 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5517 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5518 * @param pDeadTimeCfg pointer to the deadtime insertion configuration structure
5519 * @retval HAL status
5520 * @note This function must be called before starting the timer
5521 */
5522 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef * hhrtim,
5523 uint32_t TimerIdx,
5524 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
5525 {
5526 uint32_t hrtim_dtr;
5527
5528 /* Check parameters */
5529 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5530 assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
5531 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
5532 assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
5533 assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
5534 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
5535 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
5536 assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
5537
5538 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5539 {
5540 return HAL_BUSY;
5541 }
5542
5543 /* Process Locked */
5544 __HAL_LOCK(hhrtim);
5545
5546 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5547
5548 /* Set timer deadtime configuration */
5549 hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
5550 hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
5551 hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
5552 hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
5553 hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
5554 hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
5555 hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
5556 hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
5557 hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
5558
5559 /* Update the HRTIM registers */
5560 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
5561 HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
5562 HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
5563 HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
5564
5565 hhrtim->State = HAL_HRTIM_STATE_READY;
5566
5567 /* Process Unlocked */
5568 __HAL_UNLOCK(hhrtim);
5569
5570 return HAL_OK;
5571 }
5572
5573 /**
5574 * @brief Configure the chopper mode feature for a timer
5575 * @param hhrtim pointer to HAL HRTIM handle
5576 * @param TimerIdx Timer index
5577 * This parameter can be one of the following values:
5578 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5579 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5580 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5581 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5582 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5583 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5584 * @param pChopperModeCfg pointer to the chopper mode configuration structure
5585 * @retval HAL status
5586 * @note This function must be called before configuring the timer output(s)
5587 */
5588 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef * hhrtim,
5589 uint32_t TimerIdx,
5590 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
5591 {
5592 uint32_t hrtim_chpr;
5593
5594 /* Check parameters */
5595 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5596 assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
5597 assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
5598 assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
5599
5600 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5601 {
5602 return HAL_BUSY;
5603 }
5604
5605 /* Process Locked */
5606 __HAL_LOCK(hhrtim);
5607
5608 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5609
5610 /* Set timer choppe mode configuration */
5611 hrtim_chpr = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
5612 hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
5613 hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
5614
5615 /* Update the HRTIM registers */
5616 MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR, (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY |
5617 HRTIM_CHPR_STRPW) ,
5618 hrtim_chpr);
5619
5620 hhrtim->State = HAL_HRTIM_STATE_READY;
5621
5622 /* Process Unlocked */
5623 __HAL_UNLOCK(hhrtim);
5624
5625 return HAL_OK;
5626 }
5627
5628 /**
5629 * @brief Configure the burst DMA controller for a timer
5630 * @param hhrtim pointer to HAL HRTIM handle
5631 * @param TimerIdx Timer index
5632 * This parameter can be one of the following values:
5633 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5634 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5635 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5636 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5637 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5638 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5639 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5640 * @param RegistersToUpdate registers to be written by DMA
5641 * This parameter can be any combination of the following values:
5642 * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
5643 * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
5644 * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
5645 * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
5646 * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
5647 * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
5648 * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
5649 * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
5650 * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
5651 * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
5652 * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
5653 * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
5654 * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
5655 * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
5656 * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
5657 * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
5658 * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
5659 * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
5660 * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
5661 * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
5662 * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
5663 * @retval HAL status
5664 * @note This function must be called before starting the timer
5665 */
5666 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef * hhrtim,
5667 uint32_t TimerIdx,
5668 uint32_t RegistersToUpdate)
5669 {
5670 /* Check parameters */
5671 assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
5672
5673 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5674 {
5675 return HAL_BUSY;
5676 }
5677
5678 /* Process Locked */
5679 __HAL_LOCK(hhrtim);
5680
5681 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5682
5683 /* Set the burst DMA timer update register */
5684 switch (TimerIdx)
5685 {
5686 case HRTIM_TIMERINDEX_TIMER_A:
5687 {
5688 hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
5689 break;
5690 }
5691
5692 case HRTIM_TIMERINDEX_TIMER_B:
5693 {
5694 hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
5695 break;
5696 }
5697
5698 case HRTIM_TIMERINDEX_TIMER_C:
5699 {
5700 hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
5701 break;
5702 }
5703
5704 case HRTIM_TIMERINDEX_TIMER_D:
5705 {
5706 hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
5707 break;
5708 }
5709
5710 case HRTIM_TIMERINDEX_TIMER_E:
5711 {
5712 hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
5713 break;
5714 }
5715
5716 case HRTIM_TIMERINDEX_TIMER_F:
5717 {
5718 hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate;
5719 break;
5720 }
5721
5722 case HRTIM_TIMERINDEX_MASTER:
5723 {
5724 hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
5725 break;
5726 }
5727
5728 default:
5729 {
5730 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5731
5732 /* Process Unlocked */
5733 __HAL_UNLOCK(hhrtim);
5734
5735 break;
5736 }
5737 }
5738
5739 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5740 {
5741 return HAL_ERROR;
5742 }
5743
5744 hhrtim->State = HAL_HRTIM_STATE_READY;
5745
5746 /* Process Unlocked */
5747 __HAL_UNLOCK(hhrtim);
5748
5749 return HAL_OK;
5750 }
5751
5752 /**
5753 * @brief Configure the compare unit of a timer operating in waveform mode
5754 * @param hhrtim pointer to HAL HRTIM handle
5755 * @param TimerIdx Timer index
5756 * This parameter can be one of the following values:
5757 * @arg HRTIM_TIMERINDEX_MASTER for master timer
5758 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5759 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5760 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5761 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5762 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5763 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5764 * @param CompareUnit Compare unit to configure
5765 * This parameter can be one of the following values:
5766 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
5767 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
5768 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
5769 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
5770 * @param pCompareCfg pointer to the compare unit configuration structure
5771 * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
5772 * application has to configure separately the capture unit. Capture unit
5773 * to configure in that case depends on the compare unit auto delayed mode
5774 * is applied to (see below):
5775 * Auto delayed on output compare 2: capture unit 1 must be configured
5776 * Auto delayed on output compare 4: capture unit 2 must be configured
5777 * @retval HAL status
5778 * @note This function must be called before starting the timer
5779 */
5780 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef * hhrtim,
5781 uint32_t TimerIdx,
5782 uint32_t CompareUnit,
5783 HRTIM_CompareCfgTypeDef* pCompareCfg)
5784 {
5785 /* Check parameters */
5786 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
5787
5788 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5789 {
5790 return HAL_BUSY;
5791 }
5792
5793 /* Process Locked */
5794 __HAL_LOCK(hhrtim);
5795
5796 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5797
5798 /* Configure the compare unit */
5799 if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
5800 {
5801 switch (CompareUnit)
5802 {
5803 case HRTIM_COMPAREUNIT_1:
5804 {
5805 hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
5806 break;
5807 }
5808
5809 case HRTIM_COMPAREUNIT_2:
5810 {
5811 hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
5812 break;
5813 }
5814
5815 case HRTIM_COMPAREUNIT_3:
5816 {
5817 hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
5818 break;
5819 }
5820
5821 case HRTIM_COMPAREUNIT_4:
5822 {
5823 hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
5824 break;
5825 }
5826
5827 default:
5828 {
5829 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5830
5831 /* Process Unlocked */
5832 __HAL_UNLOCK(hhrtim);
5833
5834 break;
5835 }
5836 }
5837
5838 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5839 {
5840 return HAL_ERROR;
5841 }
5842
5843 }
5844 else
5845 {
5846 switch (CompareUnit)
5847 {
5848 case HRTIM_COMPAREUNIT_1:
5849 {
5850 /* Set the compare value */
5851 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
5852 break;
5853 }
5854
5855 case HRTIM_COMPAREUNIT_2:
5856 {
5857 /* Check parameters */
5858 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5859
5860 /* Set the compare value */
5861 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
5862
5863 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5864 {
5865 /* Configure auto-delayed mode */
5866 /* DELCMP2 bitfield must be reset when reprogrammed from one value */
5867 /* to the other to reinitialize properly the auto-delayed mechanism */
5868 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
5869 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
5870
5871 /* Set the compare value for timeout compare unit (if any) */
5872 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5873 {
5874 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5875 }
5876 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5877 {
5878 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5879 }
5880 else
5881 {
5882 /* nothing to do */
5883 }
5884 }
5885 break;
5886 }
5887
5888 case HRTIM_COMPAREUNIT_3:
5889 {
5890 /* Set the compare value */
5891 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
5892 break;
5893 }
5894
5895 case HRTIM_COMPAREUNIT_4:
5896 {
5897 /* Check parameters */
5898 assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
5899
5900 /* Set the compare value */
5901 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
5902
5903 if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
5904 {
5905 /* Configure auto-delayed mode */
5906 /* DELCMP4 bitfield must be reset when reprogrammed from one value */
5907 /* to the other to reinitialize properly the auto-delayed mechanism */
5908 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
5909 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
5910
5911 /* Set the compare value for timeout compare unit (if any) */
5912 if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
5913 {
5914 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
5915 }
5916 else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
5917 {
5918 hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
5919 }
5920 else
5921 {
5922 /* nothing to do */
5923 }
5924 }
5925 break;
5926 }
5927
5928 default:
5929 {
5930 hhrtim->State = HAL_HRTIM_STATE_ERROR;
5931
5932 /* Process Unlocked */
5933 __HAL_UNLOCK(hhrtim);
5934
5935 break;
5936 }
5937 }
5938
5939 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
5940 {
5941 return HAL_ERROR;
5942 }
5943
5944 }
5945 hhrtim->State = HAL_HRTIM_STATE_READY;
5946
5947 /* Process Unlocked */
5948 __HAL_UNLOCK(hhrtim);
5949
5950 return HAL_OK;
5951 }
5952
5953 /**
5954 * @brief Configure the capture unit of a timer operating in waveform mode
5955 * @param hhrtim pointer to HAL HRTIM handle
5956 * @param TimerIdx Timer index
5957 * This parameter can be one of the following values:
5958 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
5959 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
5960 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
5961 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
5962 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
5963 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
5964 * @param CaptureUnit Capture unit to configure
5965 * This parameter can be one of the following values:
5966 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
5967 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
5968 * @param pCaptureCfg pointer to the compare unit configuration structure
5969 * @retval HAL status
5970 * @note This function must be called before starting the timer
5971 */
5972 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef * hhrtim,
5973 uint32_t TimerIdx,
5974 uint32_t CaptureUnit,
5975 HRTIM_CaptureCfgTypeDef* pCaptureCfg)
5976 {
5977 uint32_t Trigger;
5978 uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32);
5979
5980 /* Check parameters */
5981 assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, (uint32_t)(pCaptureCfg->Trigger)));
5982 assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger));
5983 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
5984
5985 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
5986 {
5987 return HAL_BUSY;
5988 }
5989
5990 /* Process Locked */
5991 __HAL_LOCK(hhrtim);
5992
5993 hhrtim->State = HAL_HRTIM_STATE_BUSY;
5994
5995 /* TimerF_Trigger is valid for setting other Timers than Timer F */
5996 if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A)
5997 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TA1SET_Pos ); }
5998 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B)
5999 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TB1SET_Pos ); }
6000 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C)
6001 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TC1SET_Pos ); }
6002 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D)
6003 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TD1SET_Pos ); }
6004 else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E)
6005 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ( (TimerF_Trigger ) << HRTIM_CPT1CR_TE1SET_Pos ); }
6006 else
6007 { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); }
6008 /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */
6009
6010 /* Configure the capture unit */
6011
6012 switch (CaptureUnit)
6013 {
6014 case HRTIM_CAPTUREUNIT_1:
6015 {
6016 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger);
6017 break;
6018 }
6019
6020 case HRTIM_CAPTUREUNIT_2:
6021 {
6022 WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger);
6023 break;
6024 }
6025
6026 default:
6027 {
6028 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6029
6030 /* Process Unlocked */
6031 __HAL_UNLOCK(hhrtim);
6032
6033 break;
6034 }
6035 }
6036
6037 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6038 {
6039 return HAL_ERROR;
6040 }
6041
6042
6043 hhrtim->State = HAL_HRTIM_STATE_READY;
6044
6045 /* Process Unlocked */
6046 __HAL_UNLOCK(hhrtim);
6047
6048 return HAL_OK;
6049 }
6050
6051 /**
6052 * @brief Configure the output of a timer operating in waveform mode
6053 * @param hhrtim pointer to HAL HRTIM handle
6054 * @param TimerIdx Timer index
6055 * This parameter can be one of the following values:
6056 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6057 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6058 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6059 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6060 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6061 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6062 * @param Output Timer output
6063 * This parameter can be one of the following values:
6064 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6065 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6066 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6067 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6068 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6069 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6070 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6071 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6072 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6073 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6074 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6075 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6076 * @param pOutputCfg pointer to the timer output configuration structure
6077 * @retval HAL status
6078 * @note This function must be called before configuring the timer and after
6079 * configuring the deadtime insertion feature (if required).
6080 */
6081 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef * hhrtim,
6082 uint32_t TimerIdx,
6083 uint32_t Output,
6084 HRTIM_OutputCfgTypeDef * pOutputCfg)
6085 {
6086 /* Check parameters */
6087 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6088 assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
6089 assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
6090 assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
6091 assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
6092 assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
6093 assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
6094
6095 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6096 {
6097 return HAL_BUSY;
6098 }
6099
6100 /* Process Locked */
6101 __HAL_LOCK(hhrtim);
6102
6103 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6104
6105 /* Configure the timer output */
6106 HRTIM_OutputConfig(hhrtim,
6107 TimerIdx,
6108 Output,
6109 pOutputCfg);
6110
6111 hhrtim->State = HAL_HRTIM_STATE_READY;
6112
6113 /* Process Unlocked */
6114 __HAL_UNLOCK(hhrtim);
6115
6116 return HAL_OK;
6117 }
6118
6119 /**
6120 * @brief Force the timer output to its active or inactive state
6121 * @param hhrtim pointer to HAL HRTIM handle
6122 * @param TimerIdx Timer index
6123 * This parameter can be one of the following values:
6124 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6125 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6126 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6127 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6128 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6129 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6130 * @param Output Timer output
6131 * This parameter can be one of the following values:
6132 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6133 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6134 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6135 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6136 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6137 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6138 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6139 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6140 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6141 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6142 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6143 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6144 * @param OutputLevel indicates whether the output is forced to its active or inactive level
6145 * This parameter can be one of the following values:
6146 * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
6147 * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
6148 * @retval HAL status
6149 * @note The 'software set/reset trigger' bit in the output set/reset registers
6150 * is automatically reset by hardware
6151 */
6152 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
6153 uint32_t TimerIdx,
6154 uint32_t Output,
6155 uint32_t OutputLevel)
6156 {
6157 /* Check parameters */
6158 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
6159 assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
6160
6161 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6162 {
6163 return HAL_BUSY;
6164 }
6165
6166 /* Process Locked */
6167 __HAL_LOCK(hhrtim);
6168
6169 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6170
6171 /* Force timer output level */
6172 switch (Output)
6173 {
6174 case HRTIM_OUTPUT_TA1:
6175 case HRTIM_OUTPUT_TB1:
6176 case HRTIM_OUTPUT_TC1:
6177 case HRTIM_OUTPUT_TD1:
6178 case HRTIM_OUTPUT_TE1:
6179 case HRTIM_OUTPUT_TF1:
6180 {
6181 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6182 {
6183 /* Force output to its active state */
6184 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R,HRTIM_SET1R_SST);
6185 }
6186 else
6187 {
6188 /* Force output to its inactive state */
6189 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
6190 }
6191 break;
6192 }
6193
6194 case HRTIM_OUTPUT_TA2:
6195 case HRTIM_OUTPUT_TB2:
6196 case HRTIM_OUTPUT_TC2:
6197 case HRTIM_OUTPUT_TD2:
6198 case HRTIM_OUTPUT_TE2:
6199 case HRTIM_OUTPUT_TF2:
6200 {
6201 if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
6202 {
6203 /* Force output to its active state */
6204 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
6205 }
6206 else
6207 {
6208 /* Force output to its inactive state */
6209 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
6210 }
6211 break;
6212 }
6213
6214 default:
6215 {
6216 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6217
6218 /* Process Unlocked */
6219 __HAL_UNLOCK(hhrtim);
6220
6221 break;
6222 }
6223 }
6224
6225 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6226 {
6227 return HAL_ERROR;
6228 }
6229
6230 hhrtim->State = HAL_HRTIM_STATE_READY;
6231
6232 /* Process Unlocked */
6233 __HAL_UNLOCK(hhrtim);
6234
6235 return HAL_OK;
6236 }
6237
6238 /**
6239 * @brief Enable the generation of the waveform signal on the designated output(s)
6240 * Outputs can be combined (ORed) to allow for simultaneous output enabling.
6241 * @param hhrtim pointer to HAL HRTIM handle
6242 * @param OutputsToStart Timer output(s) to enable
6243 * This parameter can be any combination of the following values:
6244 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6245 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6246 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6247 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6248 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6249 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6250 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6251 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6252 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6253 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6254 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6255 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6256 * @retval HAL status
6257 */
6258 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef * hhrtim,
6259 uint32_t OutputsToStart)
6260 {
6261 /* Check the parameters */
6262 assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
6263
6264 /* Process Locked */
6265 __HAL_LOCK(hhrtim);
6266
6267 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6268
6269 /* Enable the HRTIM outputs */
6270 hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
6271
6272 hhrtim->State = HAL_HRTIM_STATE_READY;
6273
6274 /* Process Unlocked */
6275 __HAL_UNLOCK(hhrtim);
6276
6277 return HAL_OK;
6278 }
6279
6280 /**
6281 * @brief Disable the generation of the waveform signal on the designated output(s)
6282 * Outputs can be combined (ORed) to allow for simultaneous output disabling.
6283 * @param hhrtim pointer to HAL HRTIM handle
6284 * @param OutputsToStop Timer output(s) to disable
6285 * This parameter can be any combination of the following values:
6286 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
6287 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
6288 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
6289 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
6290 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
6291 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
6292 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
6293 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
6294 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
6295 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
6296 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
6297 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
6298 * @retval HAL status
6299 */
6300 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef * hhrtim,
6301 uint32_t OutputsToStop)
6302 {
6303 /* Check the parameters */
6304 assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
6305
6306 /* Process Locked */
6307 __HAL_LOCK(hhrtim);
6308
6309 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6310
6311 /* Enable the HRTIM outputs */
6312 hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
6313
6314 hhrtim->State = HAL_HRTIM_STATE_READY;
6315
6316 /* Process Unlocked */
6317 __HAL_UNLOCK(hhrtim);
6318
6319 return HAL_OK;
6320 }
6321
6322 /**
6323 * @brief Start the counter of the designated timer(s) operating in waveform mode
6324 * Timers can be combined (ORed) to allow for simultaneous counter start.
6325 * @param hhrtim pointer to HAL HRTIM handle
6326 * @param Timers Timer counter(s) to start
6327 * This parameter can be any combination of the following values:
6328 * @arg HRTIM_TIMERID_MASTER
6329 * @arg HRTIM_TIMERID_TIMER_A
6330 * @arg HRTIM_TIMERID_TIMER_B
6331 * @arg HRTIM_TIMERID_TIMER_C
6332 * @arg HRTIM_TIMERID_TIMER_D
6333 * @arg HRTIM_TIMERID_TIMER_E
6334 * @arg HRTIM_TIMERID_TIMER_F
6335 * @retval HAL status
6336 */
6337 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef * hhrtim,
6338 uint32_t Timers)
6339 {
6340 /* Check the parameters */
6341 assert_param(IS_HRTIM_TIMERID(Timers));
6342
6343 /* Process Locked */
6344 __HAL_LOCK(hhrtim);
6345
6346 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6347
6348 /* Enable timer(s) counter */
6349 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6350
6351 hhrtim->State = HAL_HRTIM_STATE_READY;
6352
6353 /* Process Unlocked */
6354 __HAL_UNLOCK(hhrtim);
6355
6356 return HAL_OK;
6357 }
6358
6359 /**
6360 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6361 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6362 * @param hhrtim pointer to HAL HRTIM handle
6363 * @param Timers Timer counter(s) to stop
6364 * This parameter can be any combination of the following values:
6365 * @arg HRTIM_TIMERID_MASTER
6366 * @arg HRTIM_TIMERID_A
6367 * @arg HRTIM_TIMERID_B
6368 * @arg HRTIM_TIMERID_C
6369 * @arg HRTIM_TIMERID_D
6370 * @arg HRTIM_TIMERID_E
6371 * @arg HRTIM_TIMERID_F
6372 * @retval HAL status
6373 * @note The counter of a timer is stopped only if all timer outputs are disabled
6374 */
6375 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef * hhrtim,
6376 uint32_t Timers)
6377 {
6378 /* Check the parameters */
6379 assert_param(IS_HRTIM_TIMERID(Timers));
6380
6381 /* Process Locked */
6382 __HAL_LOCK(hhrtim);
6383
6384 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6385
6386 /* Disable timer(s) counter */
6387 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6388
6389 hhrtim->State = HAL_HRTIM_STATE_READY;
6390
6391 /* Process Unlocked */
6392 __HAL_UNLOCK(hhrtim);
6393
6394 return HAL_OK;
6395 }
6396
6397 /**
6398 * @brief Start the counter of the designated timer(s) operating in waveform mode
6399 * Timers can be combined (ORed) to allow for simultaneous counter start.
6400 * @param hhrtim pointer to HAL HRTIM handle
6401 * @param Timers Timer counter(s) to start
6402 * This parameter can be any combination of the following values:
6403 * @arg HRTIM_TIMERID_MASTER
6404 * @arg HRTIM_TIMERID_A
6405 * @arg HRTIM_TIMERID_B
6406 * @arg HRTIM_TIMERID_C
6407 * @arg HRTIM_TIMERID_D
6408 * @arg HRTIM_TIMERID_E
6409 * @arg HRTIM_TIMERID_F
6410 * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
6411 * to the timers to start are enabled within this function.
6412 * Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
6413 * function.
6414 * @retval HAL status
6415 */
6416 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef * hhrtim,
6417 uint32_t Timers)
6418 {
6419 uint8_t timer_idx;
6420
6421 /* Check the parameters */
6422 assert_param(IS_HRTIM_TIMERID(Timers));
6423
6424 /* Process Locked */
6425 __HAL_LOCK(hhrtim);
6426
6427 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6428
6429 /* Enable HRTIM interrupts (if required) */
6430 __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
6431
6432 /* Enable master timer related interrupts (if required) */
6433 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6434 {
6435 __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
6436 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6437 }
6438
6439 /* Enable timing unit related interrupts (if required) */
6440 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6441 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6442 timer_idx++)
6443 {
6444 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6445 {
6446 __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
6447 timer_idx,
6448 hhrtim->TimerParam[timer_idx].InterruptRequests);
6449 }
6450 }
6451
6452 /* Enable timer(s) counter */
6453 hhrtim->Instance->sMasterRegs.MCR |= (Timers);
6454
6455 hhrtim->State = HAL_HRTIM_STATE_READY;
6456
6457 /* Process Unlocked */
6458 __HAL_UNLOCK(hhrtim);
6459
6460 return HAL_OK;}
6461
6462 /**
6463 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6464 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6465 * @param hhrtim pointer to HAL HRTIM handle
6466 * @param Timers Timer counter(s) to stop
6467 * This parameter can be any combination of the following values:
6468 * @arg HRTIM_TIMERID_MASTER
6469 * @arg HRTIM_TIMERID_A
6470 * @arg HRTIM_TIMERID_B
6471 * @arg HRTIM_TIMERID_C
6472 * @arg HRTIM_TIMERID_D
6473 * @arg HRTIM_TIMERID_E
6474 * @arg HRTIM_TIMERID_F
6475 * @retval HAL status
6476 * @note The counter of a timer is stopped only if all timer outputs are disabled
6477 * @note All enabled timer related interrupts are disabled.
6478 */
6479 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef * hhrtim,
6480 uint32_t Timers)
6481 {
6482 /* ++ WA */
6483 __IO uint32_t delai = (uint32_t)(0x17FU);
6484 /* -- WA */
6485
6486 uint8_t timer_idx;
6487
6488 /* Check the parameters */
6489 assert_param(IS_HRTIM_TIMERID(Timers));
6490
6491 /* Process Locked */
6492 __HAL_LOCK(hhrtim);
6493
6494 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6495
6496 /* Disable HRTIM interrupts (if required) */
6497 __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptResquests);
6498
6499 /* Disable master timer related interrupts (if required) */
6500 if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
6501 {
6502 /* Interrupts enable flag must be cleared one by one */
6503 __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
6504 }
6505
6506 /* Disable timing unit related interrupts (if required) */
6507 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6508 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6509 timer_idx++)
6510 {
6511 if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
6512 {
6513 __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
6514 }
6515 }
6516
6517 /* ++ WA */
6518 do { delai--; } while (delai != 0U);
6519 /* -- WA */
6520
6521 /* Disable timer(s) counter */
6522 hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
6523
6524 hhrtim->State = HAL_HRTIM_STATE_READY;
6525
6526 /* Process Unlocked */
6527 __HAL_UNLOCK(hhrtim);
6528
6529 return HAL_OK;
6530 }
6531
6532 /**
6533 * @brief Start the counter of the designated timer(s) operating in waveform mode
6534 * Timers can be combined (ORed) to allow for simultaneous counter start.
6535 * @param hhrtim pointer to HAL HRTIM handle
6536 * @param Timers Timer counter(s) to start
6537 * This parameter can be any combination of the following values:
6538 * @arg HRTIM_TIMERID_MASTER
6539 * @arg HRTIM_TIMERID_TIMER_A
6540 * @arg HRTIM_TIMERID_TIMER_B
6541 * @arg HRTIM_TIMERID_TIMER_C
6542 * @arg HRTIM_TIMERID_TIMER_D
6543 * @arg HRTIM_TIMERID_TIMER_E
6544 * @arg HRTIM_TIMERID_TIMER_F
6545 * @retval HAL status
6546 * @note This function enables the dma request(s) mentionned in the timer
6547 * configuration data structure for every timers to start.
6548 * @note The source memory address, the destination memory address and the
6549 * size of each DMA transfer are specified at timer configuration time
6550 * (see HAL_HRTIM_WaveformTimerConfig)
6551 */
6552 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef * hhrtim,
6553 uint32_t Timers)
6554 {
6555 uint8_t timer_idx;
6556 DMA_HandleTypeDef * hdma;
6557
6558 /* Check the parameters */
6559 assert_param(IS_HRTIM_TIMERID(Timers));
6560
6561 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
6562 {
6563 return HAL_BUSY;
6564 }
6565
6566 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6567
6568 /* Process Locked */
6569 __HAL_LOCK(hhrtim);
6570
6571 if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
6572 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6573 {
6574 /* Set the DMA error callback */
6575 hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
6576
6577 /* Set the DMA transfer completed callback */
6578 hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
6579
6580 /* Enable the DMA channel */
6581 if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
6582 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
6583 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
6584 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
6585 {
6586 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6587
6588 /* Process Unlocked */
6589 __HAL_UNLOCK(hhrtim);
6590
6591 return HAL_ERROR;
6592 }
6593
6594 /* Enable the timer DMA request */
6595 __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
6596 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6597 }
6598
6599 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6600 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6601 timer_idx++)
6602 {
6603 if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
6604 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6605 {
6606 /* Get the timer DMA handler */
6607 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
6608
6609 if (hdma == NULL)
6610 {
6611 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6612
6613 /* Process Unlocked */
6614 __HAL_UNLOCK(hhrtim);
6615
6616 return HAL_ERROR;
6617 }
6618
6619 /* Set the DMA error callback */
6620 hdma->XferErrorCallback = HRTIM_DMAError ;
6621
6622 /* Set the DMA transfer completed callback */
6623 hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
6624
6625 /* Enable the DMA channel */
6626 if (HAL_DMA_Start_IT(hdma,
6627 hhrtim->TimerParam[timer_idx].DMASrcAddress,
6628 hhrtim->TimerParam[timer_idx].DMADstAddress,
6629 hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
6630 {
6631 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6632
6633 /* Process Unlocked */
6634 __HAL_UNLOCK(hhrtim);
6635
6636 return HAL_ERROR;
6637 }
6638
6639 /* Enable the timer DMA request */
6640 __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
6641 timer_idx,
6642 hhrtim->TimerParam[timer_idx].DMARequests);
6643 }
6644 }
6645
6646 /* Enable the timer counter */
6647 __HAL_HRTIM_ENABLE(hhrtim, Timers);
6648
6649 hhrtim->State = HAL_HRTIM_STATE_READY;
6650
6651 /* Process Unlocked */
6652 __HAL_UNLOCK(hhrtim);
6653
6654 return HAL_OK;
6655 }
6656
6657 /**
6658 * @brief Stop the counter of the designated timer(s) operating in waveform mode
6659 * Timers can be combined (ORed) to allow for simultaneous counter stop.
6660 * @param hhrtim pointer to HAL HRTIM handle
6661 * @param Timers Timer counter(s) to stop
6662 * This parameter can be any combination of the following values:
6663 * @arg HRTIM_TIMERID_MASTER
6664 * @arg HRTIM_TIMERID_TIMER_A
6665 * @arg HRTIM_TIMERID_TIMER_B
6666 * @arg HRTIM_TIMERID_TIMER_C
6667 * @arg HRTIM_TIMERID_TIMER_D
6668 * @arg HRTIM_TIMERID_TIMER_E
6669 * @arg HRTIM_TIMERID_TIMER_F
6670 * @retval HAL status
6671 * @note The counter of a timer is stopped only if all timer outputs are disabled
6672 * @note All enabled timer related DMA requests are disabled.
6673 */
6674 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef * hhrtim,
6675 uint32_t Timers)
6676 {
6677 uint8_t timer_idx;
6678
6679 /* Check the parameters */
6680 assert_param(IS_HRTIM_TIMERID(Timers));
6681
6682 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6683
6684 if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
6685 (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
6686 {
6687 /* Disable the DMA */
6688 if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
6689 {
6690 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6691 }
6692 else
6693 {
6694 hhrtim->State = HAL_HRTIM_STATE_READY;
6695 /* Disable the DMA request(s) */
6696 __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
6697 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
6698 }
6699 }
6700
6701 for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
6702 timer_idx < HRTIM_TIMERINDEX_MASTER ;
6703 timer_idx++)
6704 {
6705 if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
6706 (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
6707 {
6708 /* Get the timer DMA handler */
6709 /* Disable the DMA */
6710 if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
6711 {
6712 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6713 }
6714 else
6715 {
6716 hhrtim->State = HAL_HRTIM_STATE_READY;
6717
6718 /* Disable the DMA request(s) */
6719 __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
6720 timer_idx,
6721 hhrtim->TimerParam[timer_idx].DMARequests);
6722 }
6723 }
6724 }
6725
6726 /* Disable the timer counter */
6727 __HAL_HRTIM_DISABLE(hhrtim, Timers);
6728
6729 if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
6730 {
6731 return HAL_ERROR;
6732 }
6733 else
6734 {
6735 return HAL_OK;
6736 }
6737 }
6738
6739 /**
6740 * @brief Enable or disables the HRTIM burst mode controller.
6741 * @param hhrtim pointer to HAL HRTIM handle
6742 * @param Enable Burst mode controller enabling
6743 * This parameter can be one of the following values:
6744 * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
6745 * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
6746 * @retval HAL status
6747 * @note This function must be called after starting the timer(s)
6748 */
6749 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef * hhrtim,
6750 uint32_t Enable)
6751 {
6752 /* Check parameters */
6753 assert_param(IS_HRTIM_BURSTMODECTL(Enable));
6754
6755 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6756 {
6757 return HAL_BUSY;
6758 }
6759
6760 /* Process Locked */
6761 __HAL_LOCK(hhrtim);
6762
6763 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6764
6765 /* Enable/Disable the burst mode controller */
6766 MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
6767
6768 hhrtim->State = HAL_HRTIM_STATE_READY;
6769
6770 /* Process Unlocked */
6771 __HAL_UNLOCK(hhrtim);
6772
6773 return HAL_OK;
6774 }
6775
6776 /**
6777 * @brief Trig the burst mode operation.
6778 * @param hhrtim pointer to HAL HRTIM handle
6779 * @retval HAL status
6780 */
6781 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
6782 {
6783 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6784 {
6785 return HAL_BUSY;
6786 }
6787
6788 /* Process Locked */
6789 __HAL_LOCK(hhrtim);
6790
6791 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6792
6793 /* Software trigger of the burst mode controller */
6794 SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
6795
6796 hhrtim->State = HAL_HRTIM_STATE_READY;
6797
6798 /* Process Unlocked */
6799 __HAL_UNLOCK(hhrtim);
6800
6801 return HAL_OK;
6802 }
6803
6804 /**
6805 * @brief Trig a software capture on the designed capture unit
6806 * @param hhrtim pointer to HAL HRTIM handle
6807 * @param TimerIdx Timer index
6808 * This parameter can be one of the following values:
6809 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
6810 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
6811 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
6812 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
6813 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
6814 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
6815 * @param CaptureUnit Capture unit to trig
6816 * This parameter can be one of the following values:
6817 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
6818 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
6819 * @retval HAL status
6820 * @note The 'software capture' bit in the capure configuration register is
6821 * automatically reset by hardware
6822 */
6823 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef * hhrtim,
6824 uint32_t TimerIdx,
6825 uint32_t CaptureUnit)
6826 {
6827 /* Check parameters */
6828 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
6829 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
6830
6831 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6832 {
6833 return HAL_BUSY;
6834 }
6835
6836 /* Process Locked */
6837 __HAL_LOCK(hhrtim);
6838
6839 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6840
6841 /* Force a software capture on concerned capture unit */
6842 switch (CaptureUnit)
6843 {
6844 case HRTIM_CAPTUREUNIT_1:
6845 {
6846 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
6847 break;
6848 }
6849
6850 case HRTIM_CAPTUREUNIT_2:
6851 {
6852 SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
6853 break;
6854 }
6855
6856 default:
6857 {
6858 hhrtim->State = HAL_HRTIM_STATE_ERROR;
6859
6860 /* Process Unlocked */
6861 __HAL_UNLOCK(hhrtim);
6862
6863 break;
6864 }
6865 }
6866
6867 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
6868 {
6869 return HAL_ERROR;
6870 }
6871
6872 hhrtim->State = HAL_HRTIM_STATE_READY;
6873
6874 /* Process Unlocked */
6875 __HAL_UNLOCK(hhrtim);
6876
6877 return HAL_OK;
6878 }
6879
6880 /**
6881 * @brief Trig the update of the registers of one or several timers
6882 * @param hhrtim pointer to HAL HRTIM handle
6883 * @param Timers timers concerned with the software register update
6884 * This parameter can be any combination of the following values:
6885 * @arg HRTIM_TIMERUPDATE_MASTER
6886 * @arg HRTIM_TIMERUPDATE_A
6887 * @arg HRTIM_TIMERUPDATE_B
6888 * @arg HRTIM_TIMERUPDATE_C
6889 * @arg HRTIM_TIMERUPDATE_D
6890 * @arg HRTIM_TIMERUPDATE_E
6891 * @arg HRTIM_TIMERUPDATE_F
6892 * @retval HAL status
6893 * @note The 'software update' bits in the HRTIM conrol register 2 register are
6894 * automatically reset by hardware
6895 */
6896 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef * hhrtim,
6897 uint32_t Timers)
6898 {
6899 /* Check parameters */
6900 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
6901
6902 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6903 {
6904 return HAL_BUSY;
6905 }
6906
6907 /* Process Locked */
6908 __HAL_LOCK(hhrtim);
6909
6910 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6911
6912 /* Force timer(s) registers update */
6913 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
6914
6915 hhrtim->State = HAL_HRTIM_STATE_READY;
6916
6917 /* Process Unlocked */
6918 __HAL_UNLOCK(hhrtim);
6919
6920 return HAL_OK;
6921 }
6922
6923 /**
6924 * @brief Swap the Timer outputs
6925 * @param hhrtim pointer to HAL HRTIM handle
6926 * @param Timers timers concerned with the software register update
6927 * This parameter can be any combination of the following values:
6928 * @arg HRTIM_TIMERSWAP_A
6929 * @arg HRTIM_TIMERSWAP_B
6930 * @arg HRTIM_TIMERSWAP_C
6931 * @arg HRTIM_TIMERSWAP_D
6932 * @arg HRTIM_TIMERSWAP_E
6933 * @arg HRTIM_TIMERSWAP_F
6934 * @retval HAL status
6935 * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1)
6936 */
6937 HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,
6938 uint32_t Timers)
6939 {
6940 /* Check parameters */
6941 assert_param(IS_HRTIM_TIMERSWAP(Timers));
6942
6943 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6944 {
6945 return HAL_BUSY;
6946 }
6947
6948 /* Process Locked */
6949 __HAL_LOCK(hhrtim);
6950
6951 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6952
6953 /* Force timer(s) registers update */
6954 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
6955
6956 hhrtim->State = HAL_HRTIM_STATE_READY;
6957
6958 /* Process Unlocked */
6959 __HAL_UNLOCK(hhrtim);
6960
6961 return HAL_OK;
6962 }
6963
6964 /**
6965 * @brief Trig the reset of one or several timers
6966 * @param hhrtim pointer to HAL HRTIM handle
6967 * @param Timers timers concerned with the software counter reset
6968 * This parameter can be any combination of the following values:
6969 * @arg HRTIM_TIMERRESET_MASTER
6970 * @arg HRTIM_TIMERRESET_TIMER_A
6971 * @arg HRTIM_TIMERRESET_TIMER_B
6972 * @arg HRTIM_TIMERRESET_TIMER_C
6973 * @arg HRTIM_TIMERRESET_TIMER_D
6974 * @arg HRTIM_TIMERRESET_TIMER_E
6975 * @arg HRTIM_TIMERRESET_TIMER_F
6976 * @retval HAL status
6977 * @note The 'software reset' bits in the HRTIM conrol register 2 are
6978 * automatically reset by hardware
6979 */
6980 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef * hhrtim,
6981 uint32_t Timers)
6982 {
6983 /* Check parameters */
6984 assert_param(IS_HRTIM_TIMERRESET(Timers));
6985
6986 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
6987 {
6988 return HAL_BUSY;
6989 }
6990
6991 /* Process Locked */
6992 __HAL_LOCK(hhrtim);
6993
6994 hhrtim->State = HAL_HRTIM_STATE_BUSY;
6995
6996 /* Force timer(s) registers reset */
6997 hhrtim->Instance->sCommonRegs.CR2 = Timers;
6998
6999 hhrtim->State = HAL_HRTIM_STATE_READY;
7000
7001 /* Process Unlocked */
7002 __HAL_UNLOCK(hhrtim);
7003
7004 return HAL_OK;
7005 }
7006
7007 /**
7008 * @brief Swap the output of one or several timers
7009 * @param hhrtim: pointer to HAL HRTIM handle
7010 * @param Timers: timers concerned with the software register update
7011 * This parameter can be any combination of the following values:
7012 * @arg HRTIM_TIMERSWAP_A
7013 * @arg HRTIM_TIMERSWAP_B
7014 * @arg HRTIM_TIMERSWAP_C
7015 * @arg HRTIM_TIMERSWAP_D
7016 * @arg HRTIM_TIMERSWAP_E
7017 * @arg HRTIM_TIMERSWAP_F
7018 * @retval HAL status
7019 */
7020 HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,
7021 uint32_t Timers)
7022 {
7023 /* Check parameters */
7024 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7025
7026 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7027 {
7028 return HAL_BUSY;
7029 }
7030
7031 /* Process Locked */
7032 __HAL_LOCK(hhrtim);
7033
7034 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7035
7036 /* Force timer(s) registers update */
7037 hhrtim->Instance->sCommonRegs.CR2 |= Timers;
7038
7039 hhrtim->State = HAL_HRTIM_STATE_READY;
7040
7041 /* Process Unlocked */
7042 __HAL_UNLOCK(hhrtim);
7043
7044 return HAL_OK;
7045 }
7046
7047 /**
7048 * @brief Un-swap the output of one or several timers
7049 * @param hhrtim: pointer to HAL HRTIM handle
7050 * @param Timers: timers concerned with the software register update
7051 * This parameter can be any combination of the following values:
7052 * @arg HRTIM_TIMERSWAP_A
7053 * @arg HRTIM_TIMERSWAP_B
7054 * @arg HRTIM_TIMERSWAP_C
7055 * @arg HRTIM_TIMERSWAP_D
7056 * @arg HRTIM_TIMERSWAP_E
7057 * @arg HRTIM_TIMERSWAP_F
7058 * @retval HAL status
7059 */
7060 HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,
7061 uint32_t Timers)
7062 {
7063 /* Check parameters */
7064 assert_param(IS_HRTIM_TIMERSWAP(Timers));
7065
7066 if(hhrtim->State == HAL_HRTIM_STATE_BUSY)
7067 {
7068 return HAL_BUSY;
7069 }
7070
7071 /* Process Locked */
7072 __HAL_LOCK(hhrtim);
7073
7074 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7075
7076 /* Force timer(s) registers update */
7077 hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers);
7078
7079 hhrtim->State = HAL_HRTIM_STATE_READY;
7080
7081 /* Process Unlocked */
7082 __HAL_UNLOCK(hhrtim);
7083
7084 return HAL_OK;
7085 }
7086
7087 /**
7088 * @brief Start a burst DMA operation to update HRTIM control registers content
7089 * @param hhrtim pointer to HAL HRTIM handle
7090 * @param TimerIdx Timer index
7091 * This parameter can be one of the following values:
7092 * @arg HRTIM_TIMERINDEX_MASTER for master timer
7093 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7094 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7095 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7096 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7097 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7098 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7099 * @param BurstBufferAddress address of the buffer the HRTIM control registers
7100 * content will be updated from.
7101 * @param BurstBufferLength size (in WORDS) of the burst buffer.
7102 * @retval HAL status
7103 * @note The TimerIdx parameter determines the dma channel to be used by the
7104 * DMA burst controller (see below)
7105 * HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
7106 * HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
7107 * HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
7108 * HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
7109 * HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
7110 * HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
7111 * HRTIM_TIMERINDEX_TIMER_F: DMA channel 8 is used by the DMA burst controller
7112 */
7113 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
7114 uint32_t TimerIdx,
7115 uint32_t BurstBufferAddress,
7116 uint32_t BurstBufferLength)
7117 {
7118 DMA_HandleTypeDef * hdma;
7119
7120 /* Check the parameters */
7121 assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
7122
7123 if((hhrtim->State == HAL_HRTIM_STATE_BUSY))
7124 {
7125 return HAL_BUSY;
7126 }
7127 if((hhrtim->State == HAL_HRTIM_STATE_READY))
7128 {
7129 if((BurstBufferAddress == 0U ) || (BurstBufferLength == 0U))
7130 {
7131 return HAL_ERROR;
7132 }
7133 else
7134 {
7135 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7136 }
7137 }
7138
7139 /* Process Locked */
7140 __HAL_LOCK(hhrtim);
7141
7142 /* Get the timer DMA handler */
7143 hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
7144
7145 if (hdma == NULL)
7146 {
7147 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7148
7149 /* Process Unlocked */
7150 __HAL_UNLOCK(hhrtim);
7151
7152 return HAL_ERROR;
7153 }
7154
7155 /* Set the DMA transfer completed callback */
7156 hdma->XferCpltCallback = HRTIM_BurstDMACplt;
7157
7158 /* Set the DMA error callback */
7159 hdma->XferErrorCallback = HRTIM_DMAError ;
7160
7161 /* Enable the DMA channel */
7162 if (HAL_DMA_Start_IT(hdma,
7163 BurstBufferAddress,
7164 (uint32_t)&(hhrtim->Instance->sCommonRegs.BDMADR),
7165 BurstBufferLength) != HAL_OK)
7166 {
7167 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7168
7169 /* Process Unlocked */
7170 __HAL_UNLOCK(hhrtim);
7171
7172 return HAL_ERROR;
7173 }
7174
7175 hhrtim->State = HAL_HRTIM_STATE_READY;
7176
7177 /* Process Unlocked */
7178 __HAL_UNLOCK(hhrtim);
7179
7180 return HAL_OK;
7181 }
7182
7183 /**
7184 * @brief Enable the transfer from preload to active registers for one
7185 * or several timing units (including master timer).
7186 * @param hhrtim pointer to HAL HRTIM handle
7187 * @param Timers Timer(s) concerned by the register preload enabling command
7188 * This parameter can be any combination of the following values:
7189 * @arg HRTIM_TIMERUPDATE_MASTER
7190 * @arg HRTIM_TIMERUPDATE_A
7191 * @arg HRTIM_TIMERUPDATE_B
7192 * @arg HRTIM_TIMERUPDATE_C
7193 * @arg HRTIM_TIMERUPDATE_D
7194 * @arg HRTIM_TIMERUPDATE_E
7195 * @arg HRTIM_TIMERUPDATE_E
7196 * @retval HAL status
7197 */
7198 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
7199 uint32_t Timers)
7200 {
7201 /* Check the parameters */
7202 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7203
7204 /* Process Locked */
7205 __HAL_LOCK(hhrtim);
7206
7207 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7208
7209 /* Enable timer(s) registers update */
7210 hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
7211
7212 hhrtim->State = HAL_HRTIM_STATE_READY;
7213
7214 /* Process Unlocked */
7215 __HAL_UNLOCK(hhrtim);
7216
7217 return HAL_OK;
7218 }
7219
7220 /**
7221 * @brief Disable the transfer from preload to active registers for one
7222 * or several timing units (including master timer).
7223 * @param hhrtim pointer to HAL HRTIM handle
7224 * @param Timers Timer(s) concerned by the register preload disabling command
7225 * This parameter can be any combination of the following values:
7226 * @arg HRTIM_TIMERUPDATE_MASTER
7227 * @arg HRTIM_TIMERUPDATE_A
7228 * @arg HRTIM_TIMERUPDATE_B
7229 * @arg HRTIM_TIMERUPDATE_C
7230 * @arg HRTIM_TIMERUPDATE_D
7231 * @arg HRTIM_TIMERUPDATE_E
7232 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7233 * @retval HAL status
7234 */
7235 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
7236 uint32_t Timers)
7237 {
7238 /* Check the parameters */
7239 assert_param(IS_HRTIM_TIMERUPDATE(Timers));
7240
7241 /* Process Locked */
7242 __HAL_LOCK(hhrtim);
7243
7244 hhrtim->State = HAL_HRTIM_STATE_BUSY;
7245
7246 /* Enable timer(s) registers update */
7247 hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
7248
7249 hhrtim->State = HAL_HRTIM_STATE_READY;
7250
7251 /* Process Unlocked */
7252 __HAL_UNLOCK(hhrtim);
7253
7254 return HAL_OK;
7255 }
7256
7257 /**
7258 * @}
7259 */
7260
7261 /** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
7262 * @brief Peripheral State functions
7263 @verbatim
7264 ===============================================================================
7265 ##### Peripheral State functions #####
7266 ===============================================================================
7267 [..] This section provides functions used to get HRTIM or HRTIM timer
7268 specific information:
7269 (+) Get HRTIM HAL state
7270 (+) Get captured value
7271 (+) Get HRTIM timer output level
7272 (+) Get HRTIM timer output state
7273 (+) Get delayed protection status
7274 (+) Get burst status
7275 (+) Get current push-pull status
7276 (+) Get idle push-pull status
7277
7278 @endverbatim
7279 * @{
7280 */
7281
7282 /**
7283 * @brief Return the HRTIM HAL state
7284 * @param hhrtim pointer to HAL HRTIM handle
7285 * @retval HAL state
7286 */
7287 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim)
7288 {
7289 /* Return HRTIM state */
7290 return hhrtim->State;
7291 }
7292
7293 /**
7294 * @brief Return actual value of the capture register of the designated capture unit
7295 * @param hhrtim pointer to HAL HRTIM handle
7296 * @param TimerIdx Timer index
7297 * This parameter can be one of the following values:
7298 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7299 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7300 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7301 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7302 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7303 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7304 * @param CaptureUnit Capture unit to trig
7305 * This parameter can be one of the following values:
7306 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7307 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7308 * @retval Captured value
7309 */
7310 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
7311 uint32_t TimerIdx,
7312 uint32_t CaptureUnit)
7313 {
7314 uint32_t captured_value;
7315
7316 /* Check parameters */
7317 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7318 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7319
7320 /* Read captured value */
7321 switch (CaptureUnit)
7322 {
7323 case HRTIM_CAPTUREUNIT_1:
7324 {
7325 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU;
7326 break;
7327 }
7328
7329 case HRTIM_CAPTUREUNIT_2:
7330 {
7331 captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU;
7332 break;
7333 }
7334
7335 default:
7336 {
7337 captured_value = 0xFFFFFFFFUL;
7338
7339 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7340
7341 /* Process Unlocked */
7342 __HAL_UNLOCK(hhrtim);
7343 break;
7344 }
7345
7346 }
7347
7348 return captured_value;
7349 }
7350
7351 /**
7352 * @brief Return actual value and direction of the capture register of the designated capture unit
7353 * @param hhrtim pointer to HAL HRTIM handle
7354 * @param TimerIdx Timer index
7355 * This parameter can be one of the following values:
7356 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7357 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7358 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7359 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7360 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7361 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7362 * @param CaptureUnit Capture unit to trig
7363 * This parameter can be one of the following values:
7364 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7365 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7366 * @retval captured value and direction structure
7367 */
7368 HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim,
7369 uint32_t TimerIdx,
7370 uint32_t CaptureUnit)
7371 {
7372 uint32_t tmp;
7373 HRTIM_CaptureValueTypeDef captured;
7374
7375 /* Check parameters */
7376 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7377 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7378
7379 /* Read captured value */
7380 switch (CaptureUnit)
7381 {
7382 case HRTIM_CAPTUREUNIT_1:
7383 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
7384 captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU;
7385 captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR)?1U:0U);
7386 break;
7387 case HRTIM_CAPTUREUNIT_2:
7388 tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
7389 captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU;
7390 captured.Dir = (((tmp & HRTIM_CPT2R_DIR ) == HRTIM_CPT2R_DIR)?1U:0U);
7391 break;
7392 default:
7393 captured.Value = 0xFFFFFFFFUL;
7394 captured.Dir = 0xFFFFFFFFUL;
7395 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7396
7397 /* Process Unlocked */
7398 __HAL_UNLOCK(hhrtim);
7399 break;
7400 }
7401
7402 return captured;
7403 }
7404
7405 /**
7406 * @brief Return actual direction of the capture register of the designated capture unit
7407 * @param hhrtim pointer to HAL HRTIM handle
7408 * @param TimerIdx Timer index
7409 * This parameter can be one of the following values:
7410 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7411 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7412 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7413 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7414 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7415 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7416 * @param CaptureUnit Capture unit to trig
7417 * This parameter can be one of the following values:
7418 * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
7419 * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
7420 * @retval captured direction
7421 * @arg This parameter is one HRTIM_Timer_UpDown_Mode :
7422 * @arg HRTIM_TIMERUPDOWNMODE_UP
7423 * @arg HRTIM_TIMERUPDOWNMODE_UPDOWN
7424 */
7425 uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim,
7426 uint32_t TimerIdx,
7427 uint32_t CaptureUnit)
7428 {
7429 uint32_t tmp;
7430
7431 /* Check parameters */
7432 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7433 assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
7434
7435 /* Read captured value */
7436 switch (CaptureUnit)
7437 {
7438 case HRTIM_CAPTUREUNIT_1:
7439 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR ) >> HRTIM_CPT1R_DIR_Pos);
7440 break;
7441 case HRTIM_CAPTUREUNIT_2:
7442 tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR ) >> HRTIM_CPT2R_DIR_Pos);
7443 break;
7444 default:
7445 tmp = 0xFFFFFFFFU;
7446 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7447
7448 /* Process Unlocked */
7449 __HAL_UNLOCK(hhrtim);
7450 break;
7451 }
7452
7453 return tmp;
7454 }
7455
7456
7457 /**
7458 * @brief Return actual level (active or inactive) of the designated output
7459 * @param hhrtim pointer to HAL HRTIM handle
7460 * @param TimerIdx Timer index
7461 * This parameter can be one of the following values:
7462 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7463 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7464 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7465 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7466 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7467 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7468 * @param Output Timer output
7469 * This parameter can be one of the following values:
7470 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7471 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7472 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7473 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7474 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7475 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7476 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7477 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7478 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7479 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7480 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7481 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7482 * @retval Output level
7483 * @note Returned output level is taken before the output stage (chopper,
7484 * polarity).
7485 */
7486 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef * hhrtim,
7487 uint32_t TimerIdx,
7488 uint32_t Output)
7489 {
7490 uint32_t output_level = (uint32_t)RESET;
7491
7492 /* Check parameters */
7493 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7494
7495 /* Read the output level */
7496 switch (Output)
7497 {
7498 case HRTIM_OUTPUT_TA1:
7499 case HRTIM_OUTPUT_TB1:
7500 case HRTIM_OUTPUT_TC1:
7501 case HRTIM_OUTPUT_TD1:
7502 case HRTIM_OUTPUT_TE1:
7503 case HRTIM_OUTPUT_TF1:
7504 {
7505 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
7506 {
7507 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7508 }
7509 else
7510 {
7511 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7512 }
7513 break;
7514 }
7515
7516 case HRTIM_OUTPUT_TA2:
7517 case HRTIM_OUTPUT_TB2:
7518 case HRTIM_OUTPUT_TC2:
7519 case HRTIM_OUTPUT_TD2:
7520 case HRTIM_OUTPUT_TE2:
7521 case HRTIM_OUTPUT_TF2:
7522 {
7523 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
7524 {
7525 output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
7526 }
7527 else
7528 {
7529 output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
7530 }
7531 break;
7532 }
7533
7534 default:
7535 {
7536 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7537
7538 /* Process Unlocked */
7539 __HAL_UNLOCK(hhrtim);
7540
7541 break;
7542 }
7543 }
7544
7545 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7546 {
7547 return (uint32_t)HAL_ERROR;
7548 }
7549
7550 return output_level;
7551 }
7552
7553 /**
7554 * @brief Return actual state (RUN, IDLE, FAULT) of the designated output
7555 * @param hhrtim pointer to HAL HRTIM handle
7556 * @param TimerIdx Timer index
7557 * This parameter can be one of the following values:
7558 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7559 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7560 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7561 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7562 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7563 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7564 * @param Output Timer output
7565 * This parameter can be one of the following values:
7566 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7567 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7568 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7569 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7570 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7571 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7572 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7573 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7574 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7575 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7576 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7577 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7578 * @retval Output state
7579 */
7580 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
7581 uint32_t TimerIdx,
7582 uint32_t Output)
7583 {
7584 uint32_t output_bit = (uint32_t)RESET;
7585 uint32_t output_state;
7586
7587 /* Check parameters */
7588 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7589
7590 /* Set output state according to output control status and output disable status */
7591 switch (Output)
7592 {
7593 case HRTIM_OUTPUT_TA1:
7594 {
7595 output_bit = HRTIM_OENR_TA1OEN;
7596 break;
7597 }
7598
7599 case HRTIM_OUTPUT_TA2:
7600 {
7601 output_bit = HRTIM_OENR_TA2OEN;
7602 break;
7603 }
7604
7605 case HRTIM_OUTPUT_TB1:
7606 {
7607 output_bit = HRTIM_OENR_TB1OEN;
7608 break;
7609 }
7610
7611 case HRTIM_OUTPUT_TB2:
7612 {
7613 output_bit = HRTIM_OENR_TB2OEN;
7614 break;
7615 }
7616
7617 case HRTIM_OUTPUT_TC1:
7618 {
7619 output_bit = HRTIM_OENR_TC1OEN;
7620 break;
7621 }
7622
7623 case HRTIM_OUTPUT_TC2:
7624 {
7625 output_bit = HRTIM_OENR_TC2OEN;
7626 break;
7627 }
7628
7629 case HRTIM_OUTPUT_TD1:
7630 {
7631 output_bit = HRTIM_OENR_TD1OEN;
7632 break;
7633 }
7634
7635 case HRTIM_OUTPUT_TD2:
7636 {
7637 output_bit = HRTIM_OENR_TD2OEN;
7638 break;
7639 }
7640
7641 case HRTIM_OUTPUT_TE1:
7642 {
7643 output_bit = HRTIM_OENR_TE1OEN;
7644 break;
7645 }
7646
7647 case HRTIM_OUTPUT_TE2:
7648 {
7649 output_bit = HRTIM_OENR_TE2OEN;
7650 break;
7651 }
7652
7653 case HRTIM_OUTPUT_TF1:
7654 {
7655 output_bit = HRTIM_OENR_TF1OEN;
7656 break;
7657 }
7658
7659 case HRTIM_OUTPUT_TF2:
7660 {
7661 output_bit = HRTIM_OENR_TF2OEN;
7662 break;
7663 }
7664
7665 default:
7666 {
7667 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7668
7669 /* Process Unlocked */
7670 __HAL_UNLOCK(hhrtim);
7671
7672 break;
7673 }
7674 }
7675
7676 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7677 {
7678 return (uint32_t)HAL_ERROR;
7679 }
7680
7681 if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
7682 {
7683 /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
7684 output_state = HRTIM_OUTPUTSTATE_RUN;
7685 }
7686 else
7687 {
7688 if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
7689 {
7690 /* Output is disabled: output in FAULT state */
7691 output_state = HRTIM_OUTPUTSTATE_FAULT;
7692 }
7693 else
7694 {
7695 /* Output is disabled: output in IDLE state */
7696 output_state = HRTIM_OUTPUTSTATE_IDLE;
7697 }
7698 }
7699
7700 return(output_state);
7701 }
7702
7703 /**
7704 * @brief Return the level (active or inactive) of the designated output
7705 * when the delayed protection was triggered.
7706 * @param hhrtim pointer to HAL HRTIM handle
7707 * @param TimerIdx Timer index
7708 * This parameter can be one of the following values:
7709 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7710 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7711 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7712 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7713 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7714 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7715 * @param Output Timer output
7716 * This parameter can be one of the following values:
7717 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
7718 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
7719 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
7720 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
7721 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
7722 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
7723 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
7724 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
7725 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
7726 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
7727 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
7728 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
7729 * @retval Delayed protection status
7730 */
7731 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef * hhrtim,
7732 uint32_t TimerIdx,
7733 uint32_t Output)
7734 {
7735 uint32_t delayed_protection_status = (uint32_t)RESET;
7736
7737 /* Check parameters */
7738 assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
7739
7740 /* Read the delayed protection status */
7741 switch (Output)
7742 {
7743 case HRTIM_OUTPUT_TA1:
7744 case HRTIM_OUTPUT_TB1:
7745 case HRTIM_OUTPUT_TC1:
7746 case HRTIM_OUTPUT_TD1:
7747 case HRTIM_OUTPUT_TE1:
7748 case HRTIM_OUTPUT_TF1:
7749 {
7750 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
7751 {
7752 /* Output 1 was active when the delayed idle protection was triggered */
7753 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7754 }
7755 else
7756 {
7757 /* Output 1 was inactive when the delayed idle protection was triggered */
7758 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7759 }
7760 break;
7761 }
7762
7763 case HRTIM_OUTPUT_TA2:
7764 case HRTIM_OUTPUT_TB2:
7765 case HRTIM_OUTPUT_TC2:
7766 case HRTIM_OUTPUT_TD2:
7767 case HRTIM_OUTPUT_TE2:
7768 case HRTIM_OUTPUT_TF2:
7769 {
7770 if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
7771 {
7772 /* Output 2 was active when the delayed idle protection was triggered */
7773 delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
7774 }
7775 else
7776 {
7777 /* Output 2 was inactive when the delayed idle protection was triggered */
7778 delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
7779 }
7780 break;
7781 }
7782
7783 default:
7784 {
7785 hhrtim->State = HAL_HRTIM_STATE_ERROR;
7786
7787 /* Process Unlocked */
7788 __HAL_UNLOCK(hhrtim);
7789
7790 break;
7791 }
7792 }
7793
7794 if(hhrtim->State == HAL_HRTIM_STATE_ERROR)
7795 {
7796 return (uint32_t)HAL_ERROR;
7797 }
7798
7799 return delayed_protection_status;
7800 }
7801
7802 /**
7803 * @brief Return the actual status (active or inactive) of the burst mode controller
7804 * @param hhrtim pointer to HAL HRTIM handle
7805 * @retval Burst mode controller status
7806 */
7807 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef * hhrtim)
7808 {
7809 uint32_t burst_mode_status;
7810
7811 /* Read burst mode status */
7812 burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
7813
7814 return burst_mode_status;
7815 }
7816
7817 /**
7818 * @brief Indicate on which output the signal is currently active (when the
7819 * push pull mode is enabled).
7820 * @param hhrtim pointer to HAL HRTIM handle
7821 * @param TimerIdx Timer index
7822 * This parameter can be one of the following values:
7823 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7824 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7825 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7826 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7827 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7828 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7829 * @retval Burst mode controller status
7830 */
7831 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef * hhrtim,
7832 uint32_t TimerIdx)
7833 {
7834 uint32_t current_pushpull_status;
7835
7836 /* Check the parameters */
7837 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7838
7839 /* Read current push pull status */
7840 current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
7841
7842 return current_pushpull_status;
7843 }
7844
7845
7846 /**
7847 * @brief Indicate on which output the signal was applied, in push-pull mode,
7848 balanced fault mode or delayed idle mode, when the protection was triggered.
7849 * @param hhrtim pointer to HAL HRTIM handle
7850 * @param TimerIdx Timer index
7851 * This parameter can be one of the following values:
7852 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
7853 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
7854 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
7855 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
7856 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
7857 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
7858 * @retval Idle Push Pull Status
7859 */
7860 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef * hhrtim,
7861 uint32_t TimerIdx)
7862 {
7863 uint32_t idle_pushpull_status;
7864
7865 /* Check the parameters */
7866 assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
7867
7868 /* Read current push pull status */
7869 idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
7870
7871 return idle_pushpull_status;
7872 }
7873
7874 /**
7875 * @}
7876 */
7877
7878 /** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
7879 * @brief Functions called when HRTIM generates an interrupt
7880 * 7 interrupts can be generated by the master timer:
7881 * - Master timer registers update
7882 * - Synchronization event received
7883 * - Master timer repetition event
7884 * - Master Compare 1 to 4 event
7885 * 14 interrupts can be generated by each timing unit:
7886 * - Delayed protection triggered
7887 * - Counter reset or roll-over event
7888 * - Output 1 and output 2 reset (transition active to inactive)
7889 * - Output 1 and output 2 set (transition inactive to active)
7890 * - Capture 1 and 2 events
7891 * - Timing unit registers update
7892 * - Repetition event
7893 * - Compare 1 to 4 event
7894 * 8 global interrupts are generated for the whole HRTIM:
7895 * - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
7896 * - DLL calibration done
7897 * - Burst mode period completed
7898 @verbatim
7899 ===============================================================================
7900 ##### HRTIM interrupts handling #####
7901 ===============================================================================
7902 [..]
7903 This subsection provides a set of functions allowing to manage the HRTIM
7904 interrupts:
7905 (+) HRTIM interrupt handler
7906 (+) Callback function called when Fault1 interrupt occurs
7907 (+) Callback function called when Fault2 interrupt occurs
7908 (+) Callback function called when Fault3 interrupt occurs
7909 (+) Callback function called when Fault4 interrupt occurs
7910 (+) Callback function called when Fault5 interrupt occurs
7911 (+) Callback function called when Fault6 interrupt occurs
7912 (+) Callback function called when system Fault interrupt occurs
7913 (+) Callback function called when DLL ready interrupt occurs
7914 (+) Callback function called when burst mode period interrupt occurs
7915 (+) Callback function called when synchronization input interrupt occurs
7916 (+) Callback function called when a timer register update interrupt occurs
7917 (+) Callback function called when a timer repetition interrupt occurs
7918 (+) Callback function called when a compare 1 match interrupt occurs
7919 (+) Callback function called when a compare 2 match interrupt occurs
7920 (+) Callback function called when a compare 3 match interrupt occurs
7921 (+) Callback function called when a compare 4 match interrupt occurs
7922 (+) Callback function called when a capture 1 interrupt occurs
7923 (+) Callback function called when a capture 2 interrupt occurs
7924 (+) Callback function called when a delayed protection interrupt occurs
7925 (+) Callback function called when a timer counter reset interrupt occurs
7926 (+) Callback function called when a timer output 1 set interrupt occurs
7927 (+) Callback function called when a timer output 1 reset interrupt occurs
7928 (+) Callback function called when a timer output 2 set interrupt occurs
7929 (+) Callback function called when a timer output 2 reset interrupt occurs
7930 (+) Callback function called when a timer output 2 reset interrupt occurs
7931 (+) Callback function called upon completion of a burst DMA transfer
7932 (+) HRTIM callback function registration
7933 (+) HRTIM callback function unregistration
7934 (+) HRTIM Timer x callback function registration
7935 (+) HRTIM Timer x callback function unregistration
7936
7937 @endverbatim
7938 * @{
7939 */
7940
7941 /**
7942 * @brief This function handles HRTIM interrupt request.
7943 * @param hhrtim pointer to HAL HRTIM handle
7944 * @param TimerIdx Timer index
7945 * This parameter can be any value of HRTIM_Timer_Index
7946 * @retval None
7947 */
7948 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef * hhrtim,
7949 uint32_t TimerIdx)
7950 {
7951 /* HRTIM interrupts handling */
7952 if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
7953 {
7954 HRTIM_HRTIM_ISR(hhrtim);
7955 }
7956 else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
7957 {
7958 /* Master related interrupts handling */
7959 HRTIM_Master_ISR(hhrtim);
7960 }
7961 else
7962 {
7963 /* Timing unit related interrupts handling */
7964 HRTIM_Timer_ISR(hhrtim, TimerIdx);
7965 }
7966
7967 }
7968
7969 /**
7970 * @brief Callback function invoked when a fault 1 interrupt occurred
7971 * @param hhrtim pointer to HAL HRTIM handle * @retval None
7972 * @retval None
7973 */
7974 __weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef * hhrtim)
7975 {
7976 /* Prevent unused argument(s) compilation warning */
7977 UNUSED(hhrtim);
7978
7979 /* NOTE : This function should not be modified, when the callback is needed,
7980 the HAL_HRTIM_Fault1Callback could be implemented in the user file
7981 */
7982 }
7983
7984 /**
7985 * @brief Callback function invoked when a fault 2 interrupt occurred
7986 * @param hhrtim pointer to HAL HRTIM handle
7987 * @retval None
7988 */
7989 __weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef * hhrtim)
7990 {
7991 /* Prevent unused argument(s) compilation warning */
7992 UNUSED(hhrtim);
7993
7994 /* NOTE : This function should not be modified, when the callback is needed,
7995 the HAL_HRTIM_Fault2Callback could be implemented in the user file
7996 */
7997 }
7998
7999 /**
8000 * @brief Callback function invoked when a fault 3 interrupt occurred
8001 * @param hhrtim pointer to HAL HRTIM handle
8002 * @retval None
8003 */
8004 __weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef * hhrtim)
8005 {
8006 /* Prevent unused argument(s) compilation warning */
8007 UNUSED(hhrtim);
8008
8009 /* NOTE : This function should not be modified, when the callback is needed,
8010 the HAL_HRTIM_Fault3Callback could be implemented in the user file
8011 */
8012 }
8013
8014 /**
8015 * @brief Callback function invoked when a fault 4 interrupt occurred
8016 * @param hhrtim pointer to HAL HRTIM handle
8017 * @retval None
8018 */
8019 __weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef * hhrtim)
8020 {
8021 /* Prevent unused argument(s) compilation warning */
8022 UNUSED(hhrtim);
8023
8024 /* NOTE : This function should not be modified, when the callback is needed,
8025 the HAL_HRTIM_Fault4Callback could be implemented in the user file
8026 */
8027 }
8028
8029 /**
8030 * @brief Callback function invoked when a fault 5 interrupt occurred
8031 * @param hhrtim pointer to HAL HRTIM handle
8032 * @retval None
8033 */
8034 __weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef * hhrtim)
8035 {
8036 /* Prevent unused argument(s) compilation warning */
8037 UNUSED(hhrtim);
8038
8039 /* NOTE : This function should not be modified, when the callback is needed,
8040 the HAL_HRTIM_Fault5Callback could be implemented in the user file
8041 */
8042 }
8043
8044 /**
8045 * @brief Callback function invoked when a fault 6 interrupt occurred
8046 * @param hhrtim pointer to HAL HRTIM handle
8047 * @retval None
8048 */
8049 __weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef * hhrtim)
8050 {
8051 /* Prevent unused argument(s) compilation warning */
8052 UNUSED(hhrtim);
8053
8054 /* NOTE : This function should not be modified, when the callback is needed,
8055 the HAL_HRTIM_Fault6Callback could be implemented in the user file
8056 */
8057 }
8058
8059 /**
8060 * @brief Callback function invoked when a system fault interrupt occurred
8061 * @param hhrtim pointer to HAL HRTIM handle
8062 * @retval None
8063 */
8064 __weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef * hhrtim)
8065 {
8066 /* Prevent unused argument(s) compilation warning */
8067 UNUSED(hhrtim);
8068
8069 /* NOTE : This function should not be modified, when the callback is needed,
8070 the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
8071 */
8072 }
8073
8074 /**
8075 * @brief Callback function invoked when the DLL calibration is completed
8076 * @param hhrtim pointer to HAL HRTIM handle
8077 * @retval None
8078 */
8079 __weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef * hhrtim)
8080 {
8081 /* Prevent unused argument(s) compilation warning */
8082 UNUSED(hhrtim);
8083
8084 /* NOTE : This function should not be modified, when the callback is needed,
8085 the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
8086 */
8087 }
8088
8089 /**
8090 * @brief Callback function invoked when the end of the burst mode period is reached
8091 * @param hhrtim pointer to HAL HRTIM handle
8092 * @retval None
8093 */
8094 __weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef * hhrtim)
8095 {
8096 /* Prevent unused argument(s) compilation warning */
8097 UNUSED(hhrtim);
8098
8099 /* NOTE : This function should not be modified, when the callback is needed,
8100 the HAL_HRTIM_BurstModeCallback could be implemented in the user file
8101 */
8102 }
8103
8104 /**
8105 * @brief Callback function invoked when a synchronization input event is received
8106 * @param hhrtim pointer to HAL HRTIM handle
8107 * @retval None
8108 */
8109 __weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef * hhrtim)
8110 {
8111 /* Prevent unused argument(s) compilation warning */
8112 UNUSED(hhrtim);
8113
8114 /* NOTE : This function should not be modified, when the callback is needed,
8115 the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
8116 */
8117 }
8118
8119 /**
8120 * @brief Callback function invoked when timer registers are updated
8121 * @param hhrtim pointer to HAL HRTIM handle
8122 * @param TimerIdx Timer index
8123 * This parameter can be one of the following values:
8124 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8125 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8126 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8127 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8128 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8129 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8130 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8131 * @retval None
8132 */
8133 __weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef * hhrtim,
8134 uint32_t TimerIdx)
8135 {
8136 /* Prevent unused argument(s) compilation warning */
8137 UNUSED(hhrtim);
8138 UNUSED(TimerIdx);
8139
8140 /* NOTE : This function should not be modified, when the callback is needed,
8141 the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
8142 */
8143 }
8144
8145 /**
8146 * @brief Callback function invoked when timer repetition period has elapsed
8147 * @param hhrtim pointer to HAL HRTIM handle
8148 * @param TimerIdx Timer index
8149 * This parameter can be one of the following values:
8150 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8151 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8152 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8153 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8154 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8155 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8156 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8157 * @retval None
8158 */
8159 __weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef * hhrtim,
8160 uint32_t TimerIdx)
8161 {
8162 /* Prevent unused argument(s) compilation warning */
8163 UNUSED(hhrtim);
8164 UNUSED(TimerIdx);
8165
8166 /* NOTE : This function should not be modified, when the callback is needed,
8167 the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
8168 */
8169 }
8170
8171 /**
8172 * @brief Callback function invoked when the timer counter matches the value
8173 * programmed in the compare 1 register
8174 * @param hhrtim pointer to HAL HRTIM handle
8175 * @param TimerIdx Timer index
8176 * This parameter can be one of the following values:
8177 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8178 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8179 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8180 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8181 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8182 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8183 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8184 * @retval None
8185 */
8186 __weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef * hhrtim,
8187 uint32_t TimerIdx)
8188 {
8189 /* Prevent unused argument(s) compilation warning */
8190 UNUSED(hhrtim);
8191 UNUSED(TimerIdx);
8192
8193 /* NOTE : This function should not be modified, when the callback is needed,
8194 the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
8195 */
8196 }
8197
8198 /**
8199 * @brief Callback function invoked when the timer counter matches the value
8200 * programmed in the compare 2 register
8201 * @param hhrtim pointer to HAL HRTIM handle
8202 * @retval None
8203 * @param TimerIdx Timer index
8204 * This parameter can be one of the following values:
8205 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8206 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8207 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8208 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8209 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8210 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8211 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8212 */
8213 __weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef * hhrtim,
8214 uint32_t TimerIdx)
8215 {
8216 /* Prevent unused argument(s) compilation warning */
8217 UNUSED(hhrtim);
8218 UNUSED(TimerIdx);
8219
8220 /* NOTE : This function should not be modified, when the callback is needed,
8221 the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
8222 */
8223 }
8224
8225 /**
8226 * @brief Callback function invoked when the timer counter matches the value
8227 * programmed in the compare 3 register
8228 * @param hhrtim pointer to HAL HRTIM handle
8229 * @param TimerIdx Timer index
8230 * This parameter can be one of the following values:
8231 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8232 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8233 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8234 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8235 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8236 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8237 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8238 * @retval None
8239 */
8240 __weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef * hhrtim,
8241 uint32_t TimerIdx)
8242 {
8243 /* Prevent unused argument(s) compilation warning */
8244 UNUSED(hhrtim);
8245 UNUSED(TimerIdx);
8246
8247 /* NOTE : This function should not be modified, when the callback is needed,
8248 the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
8249 */
8250 }
8251
8252 /**
8253 * @brief Callback function invoked when the timer counter matches the value
8254 * programmed in the compare 4 register.
8255 * @param hhrtim pointer to HAL HRTIM handle
8256 * @param TimerIdx Timer index
8257 * This parameter can be one of the following values:
8258 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8259 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8260 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8261 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8262 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8263 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8264 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8265 * @retval None
8266 */
8267 __weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef * hhrtim,
8268 uint32_t TimerIdx)
8269 {
8270 /* Prevent unused argument(s) compilation warning */
8271 UNUSED(hhrtim);
8272 UNUSED(TimerIdx);
8273
8274 /* NOTE : This function should not be modified, when the callback is needed,
8275 the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
8276 */
8277 }
8278
8279 /**
8280 * @brief Callback function invoked when the timer x capture 1 event occurs
8281 * @param hhrtim pointer to HAL HRTIM handle
8282 * @param TimerIdx Timer index
8283 * This parameter can be one of the following values:
8284 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8285 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8286 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8287 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8288 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8289 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8290 * @retval None
8291 */
8292 __weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef * hhrtim,
8293 uint32_t TimerIdx)
8294 {
8295 /* Prevent unused argument(s) compilation warning */
8296 UNUSED(hhrtim);
8297 UNUSED(TimerIdx);
8298
8299 /* NOTE : This function should not be modified, when the callback is needed,
8300 the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
8301 */
8302 }
8303
8304 /**
8305 * @brief Callback function invoked when the timer x capture 2 event occurs
8306 * @param hhrtim pointer to HAL HRTIM handle
8307 * @param TimerIdx Timer index
8308 * This parameter can be one of the following values:
8309 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8310 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8311 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8312 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8313 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8314 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8315 * @retval None
8316 */
8317 __weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef * hhrtim,
8318 uint32_t TimerIdx)
8319 {
8320 /* Prevent unused argument(s) compilation warning */
8321 UNUSED(hhrtim);
8322 UNUSED(TimerIdx);
8323
8324 /* NOTE : This function should not be modified, when the callback is needed,
8325 the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
8326 */
8327 }
8328
8329 /**
8330 * @brief Callback function invoked when the delayed idle or balanced idle mode is
8331 * entered.
8332 * @param hhrtim pointer to HAL HRTIM handle
8333 * @param TimerIdx Timer index
8334 * This parameter can be one of the following values:
8335 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8336 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8337 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8338 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8339 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8340 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8341 * @retval None
8342 */
8343 __weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef * hhrtim,
8344 uint32_t TimerIdx)
8345 {
8346 /* Prevent unused argument(s) compilation warning */
8347 UNUSED(hhrtim);
8348 UNUSED(TimerIdx);
8349
8350 /* NOTE : This function should not be modified, when the callback is needed,
8351 the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
8352 */
8353 }
8354
8355 /**
8356 * @brief Callback function invoked when the timer x counter reset/roll-over
8357 * event occurs.
8358 * @param hhrtim pointer to HAL HRTIM handle
8359 * @param TimerIdx Timer index
8360 * This parameter can be one of the following values:
8361 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8362 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8363 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8364 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8365 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8366 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8367 * @retval None
8368 */
8369 __weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef * hhrtim,
8370 uint32_t TimerIdx)
8371 {
8372 /* Prevent unused argument(s) compilation warning */
8373 UNUSED(hhrtim);
8374 UNUSED(TimerIdx);
8375
8376 /* NOTE : This function should not be modified, when the callback is needed,
8377 the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
8378 */
8379 }
8380
8381 /**
8382 * @brief Callback function invoked when the timer x output 1 is set
8383 * @param hhrtim pointer to HAL HRTIM handle
8384 * @param TimerIdx Timer index
8385 * This parameter can be one of the following values:
8386 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8387 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8388 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8389 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8390 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8391 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8392 * @retval None
8393 */
8394 __weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef * hhrtim,
8395 uint32_t TimerIdx)
8396 {
8397 /* Prevent unused argument(s) compilation warning */
8398 UNUSED(hhrtim);
8399 UNUSED(TimerIdx);
8400
8401 /* NOTE : This function should not be modified, when the callback is needed,
8402 the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
8403 */
8404 }
8405
8406 /**
8407 * @brief Callback function invoked when the timer x output 1 is reset
8408 * @param hhrtim pointer to HAL HRTIM handle
8409 * @param TimerIdx Timer index
8410 * This parameter can be one of the following values:
8411 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8412 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8413 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8414 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8415 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8416 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8417 * @retval None
8418 */
8419 __weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef * hhrtim,
8420 uint32_t TimerIdx)
8421 {
8422 /* Prevent unused argument(s) compilation warning */
8423 UNUSED(hhrtim);
8424 UNUSED(TimerIdx);
8425
8426 /* NOTE : This function should not be modified, when the callback is needed,
8427 the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
8428 */
8429 }
8430
8431 /**
8432 * @brief Callback function invoked when the timer x output 2 is set
8433 * @param hhrtim pointer to HAL HRTIM handle
8434 * @param TimerIdx Timer index
8435 * This parameter can be one of the following values:
8436 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8437 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8438 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8439 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8440 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8441 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8442 * @retval None
8443 */
8444 __weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef * hhrtim,
8445 uint32_t TimerIdx)
8446 {
8447 /* Prevent unused argument(s) compilation warning */
8448 UNUSED(hhrtim);
8449 UNUSED(TimerIdx);
8450
8451 /* NOTE : This function should not be modified, when the callback is needed,
8452 the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
8453 */
8454 }
8455
8456 /**
8457 * @brief Callback function invoked when the timer x output 2 is reset
8458 * @param hhrtim pointer to HAL HRTIM handle
8459 * @param TimerIdx Timer index
8460 * This parameter can be one of the following values:
8461 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8462 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8463 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8464 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8465 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8466 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8467 * @retval None
8468 */
8469 __weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef * hhrtim,
8470 uint32_t TimerIdx)
8471 {
8472 /* Prevent unused argument(s) compilation warning */
8473 UNUSED(hhrtim);
8474 UNUSED(TimerIdx);
8475
8476 /* NOTE : This function should not be modified, when the callback is needed,
8477 the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
8478 */
8479 }
8480
8481 /**
8482 * @brief Callback function invoked when a DMA burst transfer is completed
8483 * @param hhrtim pointer to HAL HRTIM handle
8484 * @param TimerIdx Timer index
8485 * This parameter can be one of the following values:
8486 * @arg HRTIM_TIMERINDEX_MASTER for master timer
8487 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
8488 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
8489 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
8490 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
8491 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
8492 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
8493 * @retval None
8494 */
8495 __weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef * hhrtim,
8496 uint32_t TimerIdx)
8497 {
8498 /* Prevent unused argument(s) compilation warning */
8499 UNUSED(hhrtim);
8500 UNUSED(TimerIdx);
8501
8502 /* NOTE : This function should not be modified, when the callback is needed,
8503 the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
8504 */
8505 }
8506
8507 /**
8508 * @brief Callback function invoked when a DMA error occurs
8509 * @param hhrtim pointer to HAL HRTIM handle
8510 * @retval None
8511 */
8512 __weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
8513 {
8514 /* Prevent unused argument(s) compilation warning */
8515 UNUSED(hhrtim);
8516
8517 /* NOTE : This function should not be modified, when the callback is needed,
8518 the HAL_HRTIM_ErrorCallback could be implemented in the user file
8519 */
8520 }
8521
8522 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
8523 /**
8524 * @brief HRTIM callback function registration
8525 * @param hhrtim pointer to HAL HRTIM handle
8526 * @param CallbackID ID of the HRTIM callback function to register
8527 * This parameter can be one of the following values:
8528 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8529 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8530 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8531 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8532 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8533 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8534 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8535 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8536 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8537 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8538 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8539 * @arg HAL_HRTIM_MSPINIT_CB_ID
8540 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8541 * @param pCallback Callback function pointer
8542 * @retval HAL status
8543 */
8544 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8545 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8546 pHRTIM_CallbackTypeDef pCallback)
8547 {
8548 HAL_StatusTypeDef status = HAL_OK;
8549
8550 if (pCallback == NULL)
8551 {
8552 /* Update the state */
8553 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8554
8555 return HAL_ERROR;
8556 }
8557
8558 /* Process locked */
8559 __HAL_LOCK(hhrtim);
8560
8561 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8562 {
8563 switch (CallbackID)
8564 {
8565 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8566 hhrtim->Fault1Callback = pCallback;
8567 break;
8568
8569 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8570 hhrtim->Fault2Callback = pCallback;
8571 break;
8572
8573 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8574 hhrtim->Fault3Callback = pCallback;
8575 break;
8576
8577 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8578 hhrtim->Fault4Callback = pCallback;
8579 break;
8580
8581 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8582 hhrtim->Fault5Callback = pCallback;
8583 break;
8584
8585 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8586 hhrtim->Fault6Callback = pCallback;
8587 break;
8588
8589 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8590 hhrtim->SystemFaultCallback = pCallback;
8591 break;
8592
8593 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8594 hhrtim->DLLCalibrationReadyCallback = pCallback;
8595 break;
8596
8597 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8598 hhrtim->BurstModePeriodCallback = pCallback;
8599 break;
8600
8601 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8602 hhrtim->SynchronizationEventCallback = pCallback;
8603 break;
8604
8605 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8606 hhrtim->ErrorCallback = pCallback;
8607 break;
8608
8609 case HAL_HRTIM_MSPINIT_CB_ID :
8610 hhrtim->MspInitCallback = pCallback;
8611 break;
8612
8613 case HAL_HRTIM_MSPDEINIT_CB_ID :
8614 hhrtim->MspDeInitCallback = pCallback;
8615 break;
8616
8617 default :
8618 /* Update the state */
8619 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8620
8621 /* Return error status */
8622 status = HAL_ERROR;
8623 break;
8624 }
8625 }
8626 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8627 {
8628 switch (CallbackID)
8629 {
8630 case HAL_HRTIM_MSPINIT_CB_ID :
8631 hhrtim->MspInitCallback = pCallback;
8632 break;
8633
8634 case HAL_HRTIM_MSPDEINIT_CB_ID :
8635 hhrtim->MspDeInitCallback = pCallback;
8636 break;
8637
8638 default :
8639 /* Update the state */
8640 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8641
8642 /* Return error status */
8643 status = HAL_ERROR;
8644 break;
8645 }
8646 }
8647 else
8648 {
8649 /* Update the state */
8650 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8651
8652 /* Return error status */
8653 status = HAL_ERROR;
8654 }
8655
8656 /* Release Lock */
8657 __HAL_UNLOCK(hhrtim);
8658
8659 return status;
8660 }
8661
8662 /**
8663 * @brief HRTIM callback function un-registration
8664 * @param hhrtim pointer to HAL HRTIM handle
8665 * @param CallbackID ID of the HRTIM callback function to unregister
8666 * This parameter can be one of the following values:
8667 * @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
8668 * @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
8669 * @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
8670 * @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
8671 * @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
8672 * @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
8673 * @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
8674 * @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
8675 * @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
8676 * @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
8677 * @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
8678 * @arg HAL_HRTIM_MSPINIT_CB_ID
8679 * @arg HAL_HRTIM_MSPDEINIT_CB_ID
8680 * @retval HAL status
8681 */
8682 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8683 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8684 {
8685 HAL_StatusTypeDef status = HAL_OK;
8686
8687 /* Process locked */
8688 __HAL_LOCK(hhrtim);
8689
8690 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8691 {
8692 switch (CallbackID)
8693 {
8694 case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
8695 hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
8696 break;
8697
8698 case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
8699 hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
8700 break;
8701
8702 case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
8703 hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
8704 break;
8705
8706 case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
8707 hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
8708 break;
8709
8710 case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
8711 hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
8712 break;
8713
8714 case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
8715 hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
8716 break;
8717
8718 case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
8719 hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
8720 break;
8721
8722 case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
8723 hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
8724 break;
8725
8726 case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
8727 hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
8728 break;
8729
8730 case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
8731 hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
8732 break;
8733
8734 case HAL_HRTIM_ERRORCALLBACK_CB_ID :
8735 hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
8736 break;
8737
8738 case HAL_HRTIM_MSPINIT_CB_ID :
8739 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8740 break;
8741
8742 case HAL_HRTIM_MSPDEINIT_CB_ID :
8743 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8744 break;
8745
8746 default :
8747 /* Update the state */
8748 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8749
8750 /* Return error status */
8751 status = HAL_ERROR;
8752 break;
8753 }
8754 }
8755 else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
8756 {
8757 switch (CallbackID)
8758 {
8759 case HAL_HRTIM_MSPINIT_CB_ID :
8760 hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
8761 break;
8762
8763 case HAL_HRTIM_MSPDEINIT_CB_ID :
8764 hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
8765 break;
8766
8767 default :
8768 /* Update the state */
8769 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8770
8771 /* Return error status */
8772 status = HAL_ERROR;
8773 break;
8774 }
8775 }
8776 else
8777 {
8778 /* Update the state */
8779 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8780
8781 /* Return error status */
8782 status = HAL_ERROR;
8783 }
8784
8785 /* Release Lock */
8786 __HAL_UNLOCK(hhrtim);
8787
8788 return status;
8789 }
8790
8791 /**
8792 * @brief HRTIM Timer x callback function registration
8793 * @param hhrtim pointer to HAL HRTIM handle
8794 * @param CallbackID ID of the HRTIM Timer x callback function to register
8795 * This parameter can be one of the following values:
8796 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8797 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8798 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8799 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8800 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8801 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8802 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8803 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8804 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8805 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8806 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8807 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8808 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8809 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8810 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8811 * @param pCallback Callback function pointer
8812 * @retval HAL status
8813 */
8814 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8815 HAL_HRTIM_CallbackIDTypeDef CallbackID,
8816 pHRTIM_TIMxCallbackTypeDef pCallback)
8817 {
8818 HAL_StatusTypeDef status = HAL_OK;
8819
8820 if (pCallback == NULL)
8821 {
8822 /* Update the state */
8823 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8824
8825 return HAL_ERROR;
8826 }
8827
8828 /* Process locked */
8829 __HAL_LOCK(hhrtim);
8830
8831 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8832 {
8833 switch (CallbackID)
8834 {
8835 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
8836 hhrtim->RegistersUpdateCallback = pCallback;
8837 break;
8838
8839 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
8840 hhrtim->RepetitionEventCallback = pCallback;
8841 break;
8842
8843 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
8844 hhrtim->Compare1EventCallback = pCallback;
8845 break;
8846
8847 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
8848 hhrtim->Compare2EventCallback = pCallback;
8849 break;
8850
8851 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
8852 hhrtim->Compare3EventCallback = pCallback;
8853 break;
8854
8855 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
8856 hhrtim->Compare4EventCallback = pCallback;
8857 break;
8858
8859 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
8860 hhrtim->Capture1EventCallback = pCallback;
8861 break;
8862
8863 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
8864 hhrtim->Capture2EventCallback = pCallback;
8865 break;
8866
8867 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
8868 hhrtim->DelayedProtectionCallback = pCallback;
8869 break;
8870
8871 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
8872 hhrtim->CounterResetCallback = pCallback;
8873 break;
8874
8875 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
8876 hhrtim->Output1SetCallback = pCallback;
8877 break;
8878
8879 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
8880 hhrtim->Output1ResetCallback = pCallback;
8881 break;
8882
8883 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
8884 hhrtim->Output2SetCallback = pCallback;
8885 break;
8886
8887 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
8888 hhrtim->Output2ResetCallback = pCallback;
8889 break;
8890
8891 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
8892 hhrtim->BurstDMATransferCallback = pCallback;
8893 break;
8894
8895 default :
8896 /* Update the state */
8897 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8898
8899 /* Return error status */
8900 status = HAL_ERROR;
8901 break;
8902 }
8903 }
8904 else
8905 {
8906 /* Update the state */
8907 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
8908
8909 /* Return error status */
8910 status = HAL_ERROR;
8911 }
8912
8913 /* Release Lock */
8914 __HAL_UNLOCK(hhrtim);
8915
8916 return status;
8917 }
8918
8919 /**
8920 * @brief HRTIM Timer x callback function un-registration
8921 * @param hhrtim pointer to HAL HRTIM handle
8922 * @param CallbackID ID of the HRTIM callback Timer x function to unregister
8923 * This parameter can be one of the following values:
8924 * @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
8925 * @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
8926 * @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
8927 * @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
8928 * @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
8929 * @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
8930 * @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
8931 * @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
8932 * @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
8933 * @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
8934 * @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
8935 * @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
8936 * @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
8937 * @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
8938 * @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
8939 * @retval HAL status
8940 */
8941 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
8942 HAL_HRTIM_CallbackIDTypeDef CallbackID)
8943 {
8944 HAL_StatusTypeDef status = HAL_OK;
8945
8946 /* Process locked */
8947 __HAL_LOCK(hhrtim);
8948
8949 if (HAL_HRTIM_STATE_READY == hhrtim->State)
8950 {
8951 switch (CallbackID)
8952 {
8953 case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
8954 hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
8955 break;
8956
8957 case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
8958 hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
8959 break;
8960
8961 case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
8962 hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
8963 break;
8964
8965 case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
8966 hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
8967 break;
8968
8969 case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
8970 hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
8971 break;
8972
8973 case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
8974 hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
8975 break;
8976
8977 case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
8978 hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
8979 break;
8980
8981 case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
8982 hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
8983 break;
8984
8985 case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
8986 hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
8987 break;
8988
8989 case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
8990 hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
8991 break;
8992
8993 case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
8994 hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
8995 break;
8996
8997 case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
8998 hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
8999 break;
9000
9001 case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
9002 hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
9003 break;
9004
9005 case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
9006 hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
9007 break;
9008
9009 case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
9010 hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
9011 break;
9012
9013 default :
9014 /* Update the state */
9015 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9016
9017 /* Return error status */
9018 status = HAL_ERROR;
9019 break;
9020 }
9021 }
9022 else
9023 {
9024 /* Update the state */
9025 hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
9026
9027 /* Return error status */
9028 status = HAL_ERROR;
9029 }
9030
9031 /* Release Lock */
9032 __HAL_UNLOCK(hhrtim);
9033
9034 return status;
9035 }
9036 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
9037 /**
9038 * @}
9039 */
9040
9041 /**
9042 * @}
9043 */
9044
9045 /** @addtogroup HRTIM_Private_Functions
9046 * @{
9047 */
9048
9049 /**
9050 * @brief Configure the master timer time base
9051 * @param hhrtim pointer to HAL HRTIM handle
9052 * @param pTimeBaseCfg pointer to the time base configuration structure
9053 * @retval None
9054 */
9055 static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef * hhrtim,
9056 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
9057 {
9058 uint32_t hrtim_mcr;
9059
9060 /* Configure master timer */
9061 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9062
9063 /* Set the prescaler ratio */
9064 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
9065 hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9066
9067 /* Set the operating mode */
9068 hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
9069 hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
9070
9071 /* Update the HRTIM registers */
9072 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9073 hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
9074 hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
9075 }
9076
9077 /**
9078 * @brief Configure timing unit (Timer A to Timer F) time base
9079 * @param hhrtim pointer to HAL HRTIM handle
9080 * @param TimerIdx Timer index
9081 * @param pTimeBaseCfg pointer to the time base configuration structure
9082 * @retval None
9083 */
9084 static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef * hhrtim,
9085 uint32_t TimerIdx ,
9086 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg)
9087 {
9088 uint32_t hrtim_timcr;
9089
9090 /* Configure master timing unit */
9091 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9092
9093 /* Set the prescaler ratio */
9094 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
9095 hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
9096
9097 /* Set the operating mode */
9098 hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
9099 hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
9100
9101 /* Update the HRTIM registers */
9102 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9103 hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
9104 hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
9105 }
9106
9107 /**
9108 * @brief Configure the master timer in waveform mode
9109 * @param hhrtim pointer to HAL HRTIM handle
9110 * @param pTimerCfg pointer to the timer configuration data structure
9111 * @retval None
9112 */
9113 static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
9114 HRTIM_TimerCfgTypeDef * pTimerCfg)
9115 {
9116 uint32_t hrtim_mcr;
9117 uint32_t hrtim_bmcr;
9118
9119 /* Configure master timer */
9120 hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
9121 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9122
9123 /* Enable/Disable the half mode */
9124 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9125 hrtim_mcr |= pTimerCfg->HalfModeEnable;
9126
9127 /* INTLVD bits are set to 00 */
9128 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9129 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9130 {
9131 /* INTLVD bits set to 00 */
9132 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9133 hrtim_mcr |= (HRTIM_MCR_HALF);
9134 }
9135 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9136 {
9137 hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
9138 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
9139 }
9140 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9141 {
9142 hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
9143 hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
9144 }
9145 else
9146 {
9147 hrtim_mcr &= ~(HRTIM_MCR_HALF);
9148 hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
9149 }
9150
9151 /* Enable/Disable the timer start upon synchronization event reception */
9152 hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
9153 hrtim_mcr |= pTimerCfg->StartOnSync;
9154
9155 /* Enable/Disable the timer reset upon synchronization event reception */
9156 hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
9157 hrtim_mcr |= pTimerCfg->ResetOnSync;
9158
9159 /* Enable/Disable the DAC synchronization event generation */
9160 hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
9161 hrtim_mcr |= pTimerCfg->DACSynchro;
9162
9163 /* Enable/Disable preload meachanism for timer registers */
9164 hrtim_mcr &= ~(HRTIM_MCR_PREEN);
9165 hrtim_mcr |= pTimerCfg->PreloadEnable;
9166
9167 /* Master timer registers update handling */
9168 hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
9169 hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
9170
9171 /* Enable/Disable registers update on repetition */
9172 hrtim_mcr &= ~(HRTIM_MCR_MREPU);
9173 hrtim_mcr |= pTimerCfg->RepetitionUpdate;
9174
9175 /* Set the timer burst mode */
9176 hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
9177 hrtim_bmcr |= pTimerCfg->BurstMode;
9178
9179 /* Update the HRTIM registers */
9180 hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
9181 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9182 }
9183
9184 /**
9185 * @brief Configure timing unit (Timer A to Timer F) in waveform mode
9186 * @param hhrtim pointer to HAL HRTIM handle
9187 * @param TimerIdx Timer index
9188 * @param pTimerCfg pointer to the timer configuration data structure
9189 * @retval None
9190 */
9191 static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef * hhrtim,
9192 uint32_t TimerIdx,
9193 HRTIM_TimerCfgTypeDef * pTimerCfg)
9194 {
9195 uint32_t hrtim_timcr;
9196 uint32_t hrtim_timfltr;
9197 uint32_t hrtim_timoutr;
9198 uint32_t hrtim_timrstr;
9199 uint32_t hrtim_bmcr;
9200
9201 /* UPDGAT bitfield must be reset before programming a new value */
9202 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
9203
9204 /* Configure timing unit (Timer A to Timer F) */
9205 hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
9206 hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
9207 hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9208 hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
9209
9210 /* Enable/Disable the half mode */
9211 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9212 hrtim_timcr |= pTimerCfg->HalfModeEnable;
9213
9214 if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED) || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
9215 {
9216 /* INTLVD bits set to 00 */
9217 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9218 hrtim_timcr |= (HRTIM_TIMCR_HALF);
9219 }
9220 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
9221 {
9222 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
9223 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
9224 }
9225 else if ( pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
9226 {
9227 hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
9228 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
9229 }
9230 else
9231 {
9232 hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
9233 hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
9234 }
9235
9236 /* Enable/Disable the timer start upon synchronization event reception */
9237 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
9238 hrtim_timcr |= pTimerCfg->StartOnSync;
9239
9240 /* Enable/Disable the timer reset upon synchronization event reception */
9241 hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
9242 hrtim_timcr |= pTimerCfg->ResetOnSync;
9243
9244 /* Enable/Disable the DAC synchronization event generation */
9245 hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
9246 hrtim_timcr |= pTimerCfg->DACSynchro;
9247
9248 /* Enable/Disable preload meachanism for timer registers */
9249 hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
9250 hrtim_timcr |= pTimerCfg->PreloadEnable;
9251
9252 /* Timing unit registers update handling */
9253 hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
9254 hrtim_timcr |= pTimerCfg->UpdateGating;
9255
9256 if (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT)
9257 {
9258 /* Timing unit Re-Synchronized Update */
9259 hrtim_timcr &= ~(HRTIM_TIMCR_RSYNCU);
9260 hrtim_timcr |= (pTimerCfg->ReSyncUpdate) << HRTIM_TIMCR_RSYNCU_Pos;
9261 }
9262
9263
9264 /* Enable/Disable registers update on repetition */
9265 hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
9266 if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
9267 {
9268 hrtim_timcr |= HRTIM_TIMCR_TREPU;
9269 }
9270
9271 /* Set the push-pull mode */
9272 hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
9273 hrtim_timcr |= pTimerCfg->PushPull;
9274
9275 /* Enable/Disable registers update on timer counter reset */
9276 hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
9277 hrtim_timcr |= pTimerCfg->ResetUpdate;
9278
9279 /* Set the timer update trigger */
9280 hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
9281 hrtim_timcr |= pTimerCfg->UpdateTrigger;
9282
9283 /* Enable/Disable the fault channel at timer level */
9284 hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
9285 hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
9286
9287 /* Lock/Unlock fault sources at timer level */
9288 hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
9289 hrtim_timfltr |= pTimerCfg->FaultLock;
9290
9291 /* Enable/Disable dead time insertion at timer level */
9292 hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
9293 hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
9294
9295 /* Enable/Disable delayed protection at timer level
9296 Delayed Idle is available whatever the timer operating mode (regular, push-pull)
9297 Balanced Idle is only available in push-pull mode
9298 */
9299 if ( ((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
9300 && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
9301 || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
9302 {
9303 hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
9304 hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
9305 }
9306
9307 /* Set the BIAR mode : one bit for both outputs */
9308 hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
9309 hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
9310
9311 /* Set the timer counter reset trigger */
9312 hrtim_timrstr = pTimerCfg->ResetTrigger;
9313
9314 /* Set the timer burst mode */
9315 switch (TimerIdx)
9316 {
9317 case HRTIM_TIMERINDEX_TIMER_A:
9318 {
9319 hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
9320 hrtim_bmcr |= ( pTimerCfg->BurstMode << 1U);
9321 break;
9322 }
9323
9324 case HRTIM_TIMERINDEX_TIMER_B:
9325 {
9326 hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
9327 hrtim_bmcr |= ( pTimerCfg->BurstMode << 2U);
9328 break;
9329 }
9330
9331 case HRTIM_TIMERINDEX_TIMER_C:
9332 {
9333 hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
9334 hrtim_bmcr |= ( pTimerCfg->BurstMode << 3U);
9335 break;
9336 }
9337
9338 case HRTIM_TIMERINDEX_TIMER_D:
9339 {
9340 hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
9341 hrtim_bmcr |= ( pTimerCfg->BurstMode << 4U);
9342 break;
9343 }
9344
9345 case HRTIM_TIMERINDEX_TIMER_E:
9346 {
9347 hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
9348 hrtim_bmcr |= ( pTimerCfg->BurstMode << 5U);
9349 break;
9350 }
9351
9352 case HRTIM_TIMERINDEX_TIMER_F:
9353 {
9354 hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
9355 hrtim_bmcr |= ( pTimerCfg->BurstMode << 6U);
9356 break;
9357 }
9358
9359 default:
9360 break;
9361 }
9362
9363 /* Update the HRTIM registers */
9364 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
9365 hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
9366 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
9367 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
9368 hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
9369 }
9370
9371 /**
9372 * @brief Control timing unit (timer A to timer F) in waveform mode
9373 * @param hhrtim pointer to HAL HRTIM handle
9374 * @param TimerIdx Timer index
9375 * @param pTimerCtl pointer to the timer configuration data structure
9376 * @retval None
9377 */
9378 static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef * hhrtim,
9379 uint32_t TimerIdx,
9380 HRTIM_TimerCtlTypeDef * pTimerCtl)
9381 {
9382 uint32_t hrtim_timcr2;
9383
9384 /* UPDGAT bitfield must be reset before programming a new value */
9385 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
9386
9387 /* Configure timing unit (Timer A to Timer F) */
9388 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9389
9390 /* Set the UpDown counting Mode */
9391 hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
9392 hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
9393
9394 /* Set the TrigHalf Mode : requires the counter to be disabled */
9395 hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
9396 hrtim_timcr2 |= pTimerCtl->TrigHalf;
9397
9398 /* define the compare event operating mode */
9399 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
9400 hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
9401
9402 /* define the compare event operating mode */
9403 hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
9404 hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
9405
9406 if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
9407 {
9408 /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
9409 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
9410 hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
9411
9412 /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
9413 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
9414 hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
9415
9416 /* Enable the DualChannel DAC trigger */
9417 hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
9418 hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
9419 }
9420 /* Update the HRTIM registers */
9421 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9422
9423 }
9424
9425 /**
9426 * @brief Configure timing RollOver Mode (Timer A to Timer F)
9427 * @param hhrtim pointer to HAL HRTIM handle
9428 * @param TimerIdx Timer index
9429 * @param pRollOverMode: a combination of the timer RollOver Mode configuration
9430 * @retval None
9431 */
9432 static void HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef * hhrtim,
9433 uint32_t TimerIdx,
9434 uint32_t pRollOverMode)
9435 {
9436 uint32_t hrtim_timcr2;
9437
9438 /* Configure timing unit (Timer A to Timer F) */
9439 hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
9440
9441 if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U)
9442 {
9443 /* xxROM bitfield must be reset before programming a new value */
9444 hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9445 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9446
9447 /* Update the HRTIM TIMxCR2 register */
9448 hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
9449 HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
9450
9451 hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
9452 }
9453 }
9454
9455 /**
9456 * @brief Configure a capture unit
9457 * @param hhrtim pointer to HAL HRTIM handle
9458 * @param TimerIdx Timer index
9459 * @param CaptureUnit Capture unit identifier
9460 * @param Event Event reference
9461 * @retval None
9462 */
9463 static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef * hhrtim,
9464 uint32_t TimerIdx,
9465 uint32_t CaptureUnit,
9466 uint32_t Event)
9467 {
9468 uint32_t CaptureTrigger = 0xFFFFFFFFU;
9469
9470 switch (Event)
9471 {
9472 case HRTIM_EVENT_1:
9473 {
9474 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
9475 break;
9476 }
9477
9478 case HRTIM_EVENT_2:
9479 {
9480 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
9481 break;
9482 }
9483
9484 case HRTIM_EVENT_3:
9485 {
9486 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
9487 break;
9488 }
9489
9490 case HRTIM_EVENT_4:
9491 {
9492 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
9493 break;
9494 }
9495
9496 case HRTIM_EVENT_5:
9497 {
9498 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
9499 break;
9500 }
9501
9502 case HRTIM_EVENT_6:
9503 {
9504 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
9505 break;
9506 }
9507
9508 case HRTIM_EVENT_7:
9509 {
9510 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
9511 break;
9512 }
9513
9514 case HRTIM_EVENT_8:
9515 {
9516 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
9517 break;
9518 }
9519
9520 case HRTIM_EVENT_9:
9521 {
9522 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
9523 break;
9524 }
9525
9526 case HRTIM_EVENT_10:
9527 {
9528 CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
9529 break;
9530 }
9531
9532 default:
9533 break;
9534 }
9535
9536 switch (CaptureUnit)
9537 {
9538 case HRTIM_CAPTUREUNIT_1:
9539 {
9540 hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
9541 break;
9542 }
9543
9544 case HRTIM_CAPTUREUNIT_2:
9545 {
9546 hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
9547 break;
9548 }
9549
9550 default:
9551 break;
9552 }
9553 }
9554
9555 /**
9556 * @brief Configure the output of a timing unit
9557 * @param hhrtim pointer to HAL HRTIM handle
9558 * @param TimerIdx Timer index
9559 * @param Output timing unit output identifier
9560 * @param pOutputCfg pointer to the output configuration data structure
9561 * @retval None
9562 */
9563 static void HRTIM_OutputConfig(HRTIM_HandleTypeDef * hhrtim,
9564 uint32_t TimerIdx,
9565 uint32_t Output,
9566 HRTIM_OutputCfgTypeDef * pOutputCfg)
9567 {
9568 uint32_t hrtim_outr;
9569 uint32_t hrtim_dtr;
9570
9571 uint32_t shift = 0U;
9572
9573 hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
9574 hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
9575
9576 switch (Output)
9577 {
9578 case HRTIM_OUTPUT_TA1:
9579 case HRTIM_OUTPUT_TB1:
9580 case HRTIM_OUTPUT_TC1:
9581 case HRTIM_OUTPUT_TD1:
9582 case HRTIM_OUTPUT_TE1:
9583 case HRTIM_OUTPUT_TF1:
9584 {
9585 /* Set the output set/reset crossbar */
9586 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
9587 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
9588 break;
9589 }
9590
9591 case HRTIM_OUTPUT_TA2:
9592 case HRTIM_OUTPUT_TB2:
9593 case HRTIM_OUTPUT_TC2:
9594 case HRTIM_OUTPUT_TD2:
9595 case HRTIM_OUTPUT_TE2:
9596 case HRTIM_OUTPUT_TF2:
9597 {
9598 /* Set the output set/reset crossbar */
9599 hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
9600 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
9601 shift = 16U;
9602 break;
9603 }
9604
9605 default:
9606 break;
9607 }
9608
9609 /* Clear output config */
9610 hrtim_outr &= ~((HRTIM_OUTR_POL1 |
9611 HRTIM_OUTR_IDLM1 |
9612 HRTIM_OUTR_IDLES1|
9613 HRTIM_OUTR_FAULT1|
9614 HRTIM_OUTR_CHP1 |
9615 HRTIM_OUTR_DIDL1) << shift);
9616
9617 /* Set the polarity */
9618 hrtim_outr |= (pOutputCfg->Polarity << shift);
9619
9620 /* Set the IDLE mode */
9621 hrtim_outr |= (pOutputCfg->IdleMode << shift);
9622
9623 /* Set the IDLE state */
9624 hrtim_outr |= (pOutputCfg->IdleLevel << shift);
9625
9626 /* Set the FAULT state */
9627 hrtim_outr |= (pOutputCfg->FaultLevel << shift);
9628
9629 /* Set the chopper mode */
9630 hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
9631
9632 /* Set the burst mode entry mode : deadtime insertion when entering the idle
9633 state during a burst mode operation is allowed only under the following
9634 conditions:
9635 - the outputs is active during the burst mode (IDLES=1U)
9636 - positive deadtimes (SDTR/SDTF set to 0U)
9637 */
9638 if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
9639 ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
9640 ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
9641 {
9642 hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
9643 }
9644
9645 /* Update HRTIM register */
9646 hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
9647 }
9648
9649 /**
9650 * @brief Configure an external event channel
9651 * @param hhrtim pointer to HAL HRTIM handle
9652 * @param Event Event channel identifier
9653 * @param pEventCfg pointer to the event channel configuration data structure
9654 * @retval None
9655 */
9656 static void HRTIM_EventConfig(HRTIM_HandleTypeDef * hhrtim,
9657 uint32_t Event,
9658 HRTIM_EventCfgTypeDef *pEventCfg)
9659 {
9660 uint32_t hrtim_eecr1;
9661 uint32_t hrtim_eecr2;
9662 uint32_t hrtim_eecr3;
9663
9664 /* Configure external event channel */
9665 hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
9666 hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
9667 hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
9668
9669 switch (Event)
9670 {
9671 case HRTIM_EVENT_NONE:
9672 {
9673 /* Update the HRTIM registers */
9674 hhrtim->Instance->sCommonRegs.EECR1 = 0U;
9675 hhrtim->Instance->sCommonRegs.EECR2 = 0U;
9676 hhrtim->Instance->sCommonRegs.EECR3 = 0U;
9677 break;
9678 }
9679
9680 case HRTIM_EVENT_1:
9681 {
9682 hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
9683 hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
9684 hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
9685 hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
9686 /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
9687 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9688 /* Update the HRTIM registers (EE1FAST bit) */
9689 hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
9690 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9691 break;
9692 }
9693
9694 case HRTIM_EVENT_2:
9695 {
9696 hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
9697 hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
9698 hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
9699 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
9700 /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
9701 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9702 /* Update the HRTIM registers (EE2FAST bit) */
9703 hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
9704 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9705 break;
9706 }
9707
9708 case HRTIM_EVENT_3:
9709 {
9710 hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
9711 hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
9712 hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
9713 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
9714 /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
9715 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9716 /* Update the HRTIM registers (EE3FAST bit) */
9717 hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
9718 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9719 break;
9720 }
9721
9722 case HRTIM_EVENT_4:
9723 {
9724 hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
9725 hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
9726 hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
9727 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
9728 /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
9729 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9730 /* Update the HRTIM registers (EE4FAST bit) */
9731 hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
9732 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9733 break;
9734 }
9735
9736 case HRTIM_EVENT_5:
9737 {
9738 hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
9739 hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
9740 hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
9741 hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
9742 /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
9743 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9744 /* Update the HRTIM registers (EE5FAST bit) */
9745 hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
9746 hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
9747 break;
9748 }
9749
9750 case HRTIM_EVENT_6:
9751 {
9752 hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
9753 hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
9754 hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
9755 hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
9756 hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
9757 hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
9758 /* Update the HRTIM registers */
9759 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9760 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9761 break;
9762 }
9763
9764 case HRTIM_EVENT_7:
9765 {
9766 hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
9767 hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
9768 hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
9769 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
9770 hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
9771 hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
9772 /* Update the HRTIM registers */
9773 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9774 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9775 break;
9776 }
9777
9778 case HRTIM_EVENT_8:
9779 {
9780 hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
9781 hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
9782 hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
9783 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
9784 hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
9785 hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F );
9786 /* Update the HRTIM registers */
9787 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9788 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9789 break;
9790 }
9791
9792 case HRTIM_EVENT_9:
9793 {
9794 hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
9795 hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
9796 hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
9797 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
9798 hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
9799 hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
9800 /* Update the HRTIM registers */
9801 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9802 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9803 break;
9804 }
9805
9806 case HRTIM_EVENT_10:
9807 {
9808 hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
9809 hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
9810 hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
9811 hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
9812 hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
9813 hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
9814 /* Update the HRTIM registers */
9815 hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
9816 hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
9817 break;
9818 }
9819
9820 default:
9821 break;
9822 }
9823 }
9824
9825 /**
9826 * @brief Configure the timer counter reset
9827 * @param hhrtim pointer to HAL HRTIM handle
9828 * @param TimerIdx Timer index
9829 * @param Event Event channel identifier
9830 * @retval None
9831 */
9832 static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef * hhrtim,
9833 uint32_t TimerIdx,
9834 uint32_t Event)
9835 {
9836 switch (Event)
9837 {
9838 case HRTIM_EVENT_1:
9839 {
9840 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
9841 break;
9842 }
9843
9844 case HRTIM_EVENT_2:
9845 {
9846 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
9847 break;
9848 }
9849
9850 case HRTIM_EVENT_3:
9851 {
9852 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
9853 break;
9854 }
9855
9856 case HRTIM_EVENT_4:
9857 {
9858 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
9859 break;
9860 }
9861
9862 case HRTIM_EVENT_5:
9863 {
9864 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
9865 break;
9866 }
9867
9868 case HRTIM_EVENT_6:
9869 {
9870 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
9871 break;
9872 }
9873
9874 case HRTIM_EVENT_7:
9875 {
9876 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
9877 break;
9878 }
9879
9880 case HRTIM_EVENT_8:
9881 {
9882 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
9883 break;
9884 }
9885
9886 case HRTIM_EVENT_9:
9887 {
9888 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
9889 break;
9890 }
9891
9892 case HRTIM_EVENT_10:
9893 {
9894 hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
9895 break;
9896 }
9897
9898 default:
9899 break;
9900 }
9901 }
9902
9903 /**
9904 * @brief Return the interrupt to enable or disable according to the
9905 * OC mode.
9906 * @param hhrtim pointer to HAL HRTIM handle
9907 * @param TimerIdx Timer index
9908 * @param OCChannel Timer output
9909 * This parameter can be one of the following values:
9910 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
9911 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
9912 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
9913 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
9914 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
9915 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
9916 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
9917 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
9918 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
9919 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
9920 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
9921 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
9922 * @retval Interrupt to enable or disable
9923 */
9924 static uint32_t HRTIM_GetITFromOCMode(HRTIM_HandleTypeDef * hhrtim,
9925 uint32_t TimerIdx,
9926 uint32_t OCChannel)
9927 {
9928 uint32_t hrtim_set;
9929 uint32_t hrtim_reset;
9930 uint32_t interrupt = 0U;
9931
9932 switch (OCChannel)
9933 {
9934 case HRTIM_OUTPUT_TA1:
9935 case HRTIM_OUTPUT_TB1:
9936 case HRTIM_OUTPUT_TC1:
9937 case HRTIM_OUTPUT_TD1:
9938 case HRTIM_OUTPUT_TE1:
9939 case HRTIM_OUTPUT_TF1:
9940 {
9941 /* Retreives actual OC mode and set interrupt accordingly */
9942 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
9943 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
9944
9945 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9946 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
9947 {
9948 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
9949 interrupt = HRTIM_TIM_IT_CMP1;
9950 }
9951 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
9952 (hrtim_reset == 0U))
9953 {
9954 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
9955 interrupt = HRTIM_TIM_IT_SET1;
9956 }
9957 else if ((hrtim_set == 0U) &&
9958 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
9959 {
9960 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
9961 interrupt = HRTIM_TIM_IT_RST1;
9962 }
9963 else
9964 {
9965 /* nothing to do */
9966 }
9967 break;
9968 }
9969
9970 case HRTIM_OUTPUT_TA2:
9971 case HRTIM_OUTPUT_TB2:
9972 case HRTIM_OUTPUT_TC2:
9973 case HRTIM_OUTPUT_TD2:
9974 case HRTIM_OUTPUT_TE2:
9975 case HRTIM_OUTPUT_TF2:
9976 {
9977 /* Retreives actual OC mode and set interrupt accordingly */
9978 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
9979 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
9980
9981 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
9982 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
9983 {
9984 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
9985 interrupt = HRTIM_TIM_IT_CMP2;
9986 }
9987 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
9988 (hrtim_reset == 0U))
9989 {
9990 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
9991 interrupt = HRTIM_TIM_IT_SET2;
9992 }
9993 else if ((hrtim_set == 0U) &&
9994 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
9995 {
9996 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
9997 interrupt = HRTIM_TIM_IT_RST2;
9998 }
9999 else
10000 {
10001 /* nothing to do */
10002 }
10003 break;
10004 }
10005
10006 default:
10007 break;
10008 }
10009
10010 return interrupt;
10011 }
10012
10013 /**
10014 * @brief Return the DMA request to enable or disable according to the
10015 * OC mode.
10016 * @param hhrtim pointer to HAL HRTIM handle
10017 * @param TimerIdx Timer index
10018 * @param OCChannel Timer output
10019 * This parameter can be one of the following values:
10020 * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
10021 * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
10022 * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
10023 * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
10024 * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
10025 * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
10026 * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
10027 * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
10028 * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
10029 * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
10030 * @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
10031 * @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
10032 * @retval DMA request to enable or disable
10033 */
10034 static uint32_t HRTIM_GetDMAFromOCMode(HRTIM_HandleTypeDef * hhrtim,
10035 uint32_t TimerIdx,
10036 uint32_t OCChannel)
10037 {
10038 uint32_t hrtim_set;
10039 uint32_t hrtim_reset;
10040 uint32_t dma_request = 0U;
10041
10042 switch (OCChannel)
10043 {
10044 case HRTIM_OUTPUT_TA1:
10045 case HRTIM_OUTPUT_TB1:
10046 case HRTIM_OUTPUT_TC1:
10047 case HRTIM_OUTPUT_TD1:
10048 case HRTIM_OUTPUT_TE1:
10049 case HRTIM_OUTPUT_TF1:
10050 {
10051 /* Retreives actual OC mode and set dma_request accordingly */
10052 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
10053 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
10054
10055 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10056 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10057 {
10058 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10059 dma_request = HRTIM_TIM_DMA_CMP1;
10060 }
10061 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
10062 (hrtim_reset == 0U))
10063 {
10064 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10065 dma_request = HRTIM_TIM_DMA_SET1;
10066 }
10067 else if ((hrtim_set == 0U) &&
10068 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
10069 {
10070 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10071 dma_request = HRTIM_TIM_DMA_RST1;
10072 }
10073 else
10074 {
10075 /* nothing to do */
10076 }
10077 break;
10078 }
10079
10080 case HRTIM_OUTPUT_TA2:
10081 case HRTIM_OUTPUT_TB2:
10082 case HRTIM_OUTPUT_TC2:
10083 case HRTIM_OUTPUT_TD2:
10084 case HRTIM_OUTPUT_TE2:
10085 case HRTIM_OUTPUT_TF2:
10086 {
10087 /* Retreives actual OC mode and set dma_request accordingly */
10088 hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
10089 hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
10090
10091 if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10092 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10093 {
10094 /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
10095 dma_request = HRTIM_TIM_DMA_CMP2;
10096 }
10097 else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
10098 (hrtim_reset == 0U))
10099 {
10100 /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
10101 dma_request = HRTIM_TIM_DMA_SET2;
10102 }
10103 else if ((hrtim_set == 0U) &&
10104 ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
10105 {
10106 /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
10107 dma_request = HRTIM_TIM_DMA_RST2;
10108 }
10109 else
10110 {
10111 /* nothing to do */
10112 }
10113 break;
10114 }
10115
10116 default:
10117 break;
10118 }
10119
10120 return dma_request;
10121 }
10122
10123 static DMA_HandleTypeDef * HRTIM_GetDMAHandleFromTimerIdx(HRTIM_HandleTypeDef * hhrtim,
10124 uint32_t TimerIdx)
10125 {
10126 DMA_HandleTypeDef * hdma = (DMA_HandleTypeDef *)NULL;
10127
10128 switch (TimerIdx)
10129 {
10130 case HRTIM_TIMERINDEX_MASTER:
10131 {
10132 hdma = hhrtim->hdmaMaster;
10133 break;
10134 }
10135
10136 case HRTIM_TIMERINDEX_TIMER_A:
10137 {
10138 hdma = hhrtim->hdmaTimerA;
10139 break;
10140 }
10141
10142 case HRTIM_TIMERINDEX_TIMER_B:
10143 {
10144 hdma = hhrtim->hdmaTimerB;
10145 break;
10146 }
10147
10148 case HRTIM_TIMERINDEX_TIMER_C:
10149 {
10150 hdma = hhrtim->hdmaTimerC;
10151 break;
10152 }
10153
10154 case HRTIM_TIMERINDEX_TIMER_D:
10155 {
10156 hdma = hhrtim->hdmaTimerD;
10157 break;
10158 }
10159
10160 case HRTIM_TIMERINDEX_TIMER_E:
10161 {
10162 hdma = hhrtim->hdmaTimerE;
10163 break;
10164 }
10165
10166 case HRTIM_TIMERINDEX_TIMER_F:
10167 {
10168 hdma = hhrtim->hdmaTimerF;
10169 break;
10170 }
10171
10172 default:
10173 break;
10174 }
10175
10176 return hdma;
10177 }
10178
10179 static uint32_t GetTimerIdxFromDMAHandle(HRTIM_HandleTypeDef * hhrtim,
10180 DMA_HandleTypeDef * hdma)
10181 {
10182 uint32_t timed_idx = 0xFFFFFFFFU;
10183
10184 if (hdma == hhrtim->hdmaMaster)
10185 {
10186 timed_idx = HRTIM_TIMERINDEX_MASTER;
10187 }
10188 else if (hdma == hhrtim->hdmaTimerA)
10189 {
10190 timed_idx = HRTIM_TIMERINDEX_TIMER_A;
10191 }
10192 else if (hdma == hhrtim->hdmaTimerB)
10193 {
10194 timed_idx = HRTIM_TIMERINDEX_TIMER_B;
10195 }
10196 else if (hdma == hhrtim->hdmaTimerC)
10197 {
10198 timed_idx = HRTIM_TIMERINDEX_TIMER_C;
10199 }
10200 else if (hdma == hhrtim->hdmaTimerD)
10201 {
10202 timed_idx = HRTIM_TIMERINDEX_TIMER_D;
10203 }
10204 else if (hdma == hhrtim->hdmaTimerE)
10205 {
10206 timed_idx = HRTIM_TIMERINDEX_TIMER_E;
10207 }
10208 else if (hdma == hhrtim->hdmaTimerF)
10209 {
10210 timed_idx = HRTIM_TIMERINDEX_TIMER_F;
10211 }
10212 else
10213 {
10214 /* nothing to do */
10215 }
10216 return timed_idx;
10217 }
10218
10219 /**
10220 * @brief Force an immediate transfer from the preload to the active
10221 * registers.
10222 * @param hhrtim pointer to HAL HRTIM handle
10223 * @param TimerIdx Timer index
10224 * @retval None
10225 */
10226 static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef * hhrtim,
10227 uint32_t TimerIdx)
10228 {
10229 switch (TimerIdx)
10230 {
10231 case HRTIM_TIMERINDEX_MASTER:
10232 {
10233 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
10234 break;
10235 }
10236
10237 case HRTIM_TIMERINDEX_TIMER_A:
10238 {
10239 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
10240 break;
10241 }
10242
10243 case HRTIM_TIMERINDEX_TIMER_B:
10244 {
10245 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
10246 break;
10247 }
10248
10249 case HRTIM_TIMERINDEX_TIMER_C:
10250 {
10251 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
10252 break;
10253 }
10254
10255 case HRTIM_TIMERINDEX_TIMER_D:
10256 {
10257 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
10258 break;
10259 }
10260
10261 case HRTIM_TIMERINDEX_TIMER_E:
10262 {
10263 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
10264 break;
10265 }
10266
10267 case HRTIM_TIMERINDEX_TIMER_F:
10268 {
10269 hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
10270 break;
10271 }
10272
10273 default:
10274 break;
10275 }
10276 }
10277
10278
10279 /**
10280 * @brief HRTIM interrupts service routine
10281 * @param hhrtim pointer to HAL HRTIM handle
10282 * @retval None
10283 */
10284 static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef * hhrtim)
10285 {
10286 /* Fault 1 event */
10287 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT1) != (uint32_t)RESET)
10288 {
10289 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT1) != RESET)
10290 {
10291 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
10292
10293 /* Invoke Fault 1 event callback */
10294 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10295 hhrtim->Fault1Callback(hhrtim);
10296 #else
10297 HAL_HRTIM_Fault1Callback(hhrtim);
10298 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10299 }
10300 }
10301
10302 /* Fault 2 event */
10303 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT2) != (uint32_t)RESET)
10304 {
10305 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT2) != RESET)
10306 {
10307 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
10308
10309 /* Invoke Fault 2 event callback */
10310 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10311 hhrtim->Fault2Callback(hhrtim);
10312 #else
10313 HAL_HRTIM_Fault2Callback(hhrtim);
10314 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10315 }
10316 }
10317
10318 /* Fault 3 event */
10319 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT3) != (uint32_t)RESET)
10320 {
10321 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT3) != RESET)
10322 {
10323 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
10324
10325 /* Invoke Fault 3 event callback */
10326 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10327 hhrtim->Fault3Callback(hhrtim);
10328 #else
10329 HAL_HRTIM_Fault3Callback(hhrtim);
10330 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10331 }
10332 }
10333
10334 /* Fault 4 event */
10335 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT4) != (uint32_t)RESET)
10336 {
10337 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT4) != RESET)
10338 {
10339 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
10340
10341 /* Invoke Fault 4 event callback */
10342 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10343 hhrtim->Fault4Callback(hhrtim);
10344 #else
10345 HAL_HRTIM_Fault4Callback(hhrtim);
10346 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10347 }
10348 }
10349
10350 /* Fault 5 event */
10351 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT5) != (uint32_t)RESET)
10352 {
10353 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT5) != RESET)
10354 {
10355 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
10356
10357 /* Invoke Fault 5 event callback */
10358 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10359 hhrtim->Fault5Callback(hhrtim);
10360 #else
10361 HAL_HRTIM_Fault5Callback(hhrtim);
10362 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10363 }
10364 }
10365
10366 /* Fault 6 event */
10367 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_FLT6) != (uint32_t)RESET)
10368 {
10369 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_FLT6) != RESET)
10370 {
10371 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
10372
10373 /* Invoke Fault 6 event callback */
10374 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10375 hhrtim->Fault6Callback(hhrtim);
10376 #else
10377 HAL_HRTIM_Fault6Callback(hhrtim);
10378 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10379 }
10380 }
10381
10382 /* System fault event */
10383 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
10384 {
10385 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_SYSFLT) != RESET)
10386 {
10387 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
10388
10389 /* Invoke System fault event callback */
10390 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10391 hhrtim->SystemFaultCallback(hhrtim);
10392 #else
10393 HAL_HRTIM_SystemFaultCallback(hhrtim);
10394 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10395 }
10396 }
10397 }
10398
10399 /**
10400 * @brief Master timer interrupts service routine
10401 * @param hhrtim pointer to HAL HRTIM handle
10402 * @retval None
10403 */
10404 static void HRTIM_Master_ISR(HRTIM_HandleTypeDef * hhrtim)
10405 {
10406 /* DLL calibration ready event */
10407 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
10408 {
10409 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_DLLRDY) != RESET)
10410 {
10411 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
10412
10413 /* Set HRTIM State */
10414 hhrtim->State = HAL_HRTIM_STATE_READY;
10415
10416 /* Process unlocked */
10417 __HAL_UNLOCK(hhrtim);
10418
10419 /* Invoke System fault event callback */
10420 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10421 hhrtim->DLLCalibrationReadyCallback(hhrtim);
10422 #else
10423 HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
10424 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10425 }
10426 }
10427
10428 /* Burst mode period event */
10429 if(__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_FLAG_BMPER) != (uint32_t)RESET)
10430 {
10431 if(__HAL_HRTIM_GET_ITSTATUS(hhrtim, HRTIM_IT_BMPER) != RESET)
10432 {
10433 __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
10434
10435 /* Invoke Burst mode period event callback */
10436 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10437 hhrtim->BurstModePeriodCallback(hhrtim);
10438 #else
10439 HAL_HRTIM_BurstModePeriodCallback(hhrtim);
10440 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10441 }
10442 }
10443
10444 /* Master timer compare 1 event */
10445 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
10446 {
10447 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP1) != RESET)
10448 {
10449 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
10450
10451 /* Invoke compare 1 event callback */
10452 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10453 hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10454 #else
10455 HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10456 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10457 }
10458 }
10459
10460 /* Master timer compare 2 event */
10461 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
10462 {
10463 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP2) != RESET)
10464 {
10465 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
10466
10467 /* Invoke compare 2 event callback */
10468 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10469 hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10470 #else
10471 HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10472 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10473 }
10474 }
10475
10476 /* Master timer compare 3 event */
10477 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
10478 {
10479 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP3) != RESET)
10480 {
10481 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
10482
10483 /* Invoke compare 3 event callback */
10484 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10485 hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10486 #else
10487 HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10488 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10489 }
10490 }
10491
10492 /* Master timer compare 4 event */
10493 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
10494 {
10495 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MCMP4) != RESET)
10496 {
10497 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
10498
10499 /* Invoke compare 4 event callback */
10500 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10501 hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10502 #else
10503 HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10504 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10505 }
10506 }
10507
10508 /* Master timer repetition event */
10509 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
10510 {
10511 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MREP) != RESET)
10512 {
10513 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
10514
10515 /* Invoke repetition event callback */
10516 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10517 hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10518 #else
10519 HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10520 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10521 }
10522 }
10523
10524 /* Synchronization input event */
10525 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
10526 {
10527 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_SYNC) != RESET)
10528 {
10529 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
10530
10531 /* Invoke synchronization event callback */
10532 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10533 hhrtim->SynchronizationEventCallback(hhrtim);
10534 #else
10535 HAL_HRTIM_SynchronizationEventCallback(hhrtim);
10536 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10537 }
10538 }
10539
10540 /* Master timer registers update event */
10541 if(__HAL_HRTIM_MASTER_GET_FLAG(hhrtim, HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
10542 {
10543 if(__HAL_HRTIM_MASTER_GET_ITSTATUS(hhrtim, HRTIM_MASTER_IT_MUPD) != RESET)
10544 {
10545 __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
10546
10547 /* Invoke registers update event callback */
10548 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10549 hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10550 #else
10551 HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
10552 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10553 }
10554 }
10555 }
10556
10557 /**
10558 * @brief Timer interrupts service routine
10559 * @param hhrtim pointer to HAL HRTIM handle
10560 * @param TimerIdx Timer index
10561 * This parameter can be one of the following values:
10562 * @arg HRTIM_TIMERINDEX_TIMER_A for timer A
10563 * @arg HRTIM_TIMERINDEX_TIMER_B for timer B
10564 * @arg HRTIM_TIMERINDEX_TIMER_C for timer C
10565 * @arg HRTIM_TIMERINDEX_TIMER_D for timer D
10566 * @arg HRTIM_TIMERINDEX_TIMER_E for timer E
10567 * @arg HRTIM_TIMERINDEX_TIMER_F for timer F
10568 * @retval None
10569 */
10570 static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef * hhrtim,
10571 uint32_t TimerIdx)
10572 {
10573 /* Timer compare 1 event */
10574 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
10575 {
10576 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1) != RESET)
10577 {
10578 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
10579
10580 /* Invoke compare 1 event callback */
10581 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10582 hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
10583 #else
10584 HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
10585 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10586 }
10587 }
10588
10589 /* Timer compare 2 event */
10590 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
10591 {
10592 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2) != RESET)
10593 {
10594 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
10595
10596 /* Invoke compare 2 event callback */
10597 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10598 hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
10599 #else
10600 HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
10601 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10602 }
10603 }
10604
10605 /* Timer compare 3 event */
10606 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
10607 {
10608 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3) != RESET)
10609 {
10610 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
10611
10612 /* Invoke compare 3 event callback */
10613 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10614 hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
10615 #else
10616 HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
10617 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10618 }
10619 }
10620
10621 /* Timer compare 4 event */
10622 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
10623 {
10624 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4) != RESET)
10625 {
10626 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
10627
10628 /* Invoke compare 4 event callback */
10629 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10630 hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
10631 #else
10632 HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
10633 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10634 }
10635 }
10636
10637 /* Timer repetition event */
10638 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
10639 {
10640 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_REP) != RESET)
10641 {
10642 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
10643
10644 /* Invoke repetition event callback */
10645 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10646 hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
10647 #else
10648 HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
10649 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10650 }
10651 }
10652
10653 /* Timer registers update event */
10654 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
10655 {
10656 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD) != RESET)
10657 {
10658 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
10659
10660 /* Invoke registers update event callback */
10661 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10662 hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
10663 #else
10664 HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
10665 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10666 }
10667 }
10668
10669 /* Timer capture 1 event */
10670 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
10671 {
10672 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1) != RESET)
10673 {
10674 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
10675
10676 /* Invoke capture 1 event callback */
10677 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10678 hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
10679 #else
10680 HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
10681 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10682 }
10683 }
10684
10685 /* Timer capture 2 event */
10686 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
10687 {
10688 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2) != RESET)
10689 {
10690 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
10691
10692 /* Invoke capture 2 event callback */
10693 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10694 hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
10695 #else
10696 HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
10697 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10698 }
10699 }
10700
10701 /* Timer output 1 set event */
10702 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
10703 {
10704 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1) != RESET)
10705 {
10706 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
10707
10708 /* Invoke output 1 set event callback */
10709 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10710 hhrtim->Output1SetCallback(hhrtim, TimerIdx);
10711 #else
10712 HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
10713 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10714 }
10715 }
10716
10717 /* Timer output 1 reset event */
10718 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
10719 {
10720 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1) != RESET)
10721 {
10722 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
10723
10724 /* Invoke output 1 reset event callback */
10725 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10726 hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
10727 #else
10728 HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
10729 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10730 }
10731 }
10732
10733 /* Timer output 2 set event */
10734 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
10735 {
10736 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2) != RESET)
10737 {
10738 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
10739
10740 /* Invoke output 2 set event callback */
10741 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10742 hhrtim->Output2SetCallback(hhrtim, TimerIdx);
10743 #else
10744 HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
10745 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10746 }
10747 }
10748
10749 /* Timer output 2 reset event */
10750 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
10751 {
10752 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2) != RESET)
10753 {
10754 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
10755
10756 /* Invoke output 2 reset event callback */
10757 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10758 hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
10759 #else
10760 HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
10761 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10762 }
10763 }
10764
10765 /* Timer reset event */
10766 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
10767 {
10768 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_RST) != RESET)
10769 {
10770 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
10771
10772 /* Invoke timer reset callback */
10773 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10774 hhrtim->CounterResetCallback(hhrtim, TimerIdx);
10775 #else
10776 HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
10777 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10778 }
10779 }
10780
10781 /* Delayed protection event */
10782 if(__HAL_HRTIM_TIMER_GET_FLAG(hhrtim, TimerIdx, HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
10783 {
10784 if(__HAL_HRTIM_TIMER_GET_ITSTATUS(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT) != RESET)
10785 {
10786 __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
10787
10788 /* Invoke delayed protection callback */
10789 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10790 hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
10791 #else
10792 HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
10793 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10794 }
10795 }
10796 }
10797
10798 /**
10799 * @brief DMA callback invoked upon master timer related DMA request completion
10800 * @param hdma pointer to DMA handle.
10801 * @retval None
10802 */
10803 static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
10804 {
10805 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10806
10807 if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
10808 {
10809 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10810 hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10811 #else
10812 HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10813 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10814 }
10815 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
10816 {
10817 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10818 hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10819 #else
10820 HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10821 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10822 }
10823 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
10824 {
10825 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10826 hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10827 #else
10828 HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10829 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10830 }
10831 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
10832 {
10833 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10834 hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10835 #else
10836 HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10837 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10838 }
10839 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
10840 {
10841 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10842 hrtim->SynchronizationEventCallback(hrtim);
10843 #else
10844 HAL_HRTIM_SynchronizationEventCallback(hrtim);
10845 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10846 }
10847 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
10848 {
10849 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10850 hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10851 #else
10852 HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10853 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10854 }
10855 else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
10856 {
10857 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10858 hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10859 #else
10860 HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
10861 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10862 }
10863 else
10864 {
10865 /* nothing to do */
10866 }
10867 }
10868
10869 /**
10870 * @brief DMA callback invoked upon timer A..F related DMA request completion
10871 * @param hdma pointer to DMA handle.
10872 * @retval None
10873 */
10874 static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
10875 {
10876 uint8_t timer_idx;
10877
10878 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
10879
10880 timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
10881
10882 if ( !IS_HRTIM_TIMING_UNIT(timer_idx) ) {return;}
10883
10884 if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
10885 {
10886 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10887 hrtim->Compare1EventCallback(hrtim, timer_idx);
10888 #else
10889 HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
10890 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10891 }
10892 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
10893 {
10894 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10895 hrtim->Compare2EventCallback(hrtim, timer_idx);
10896 #else
10897 HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
10898 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10899 }
10900 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
10901 {
10902 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10903 hrtim->Compare3EventCallback(hrtim, timer_idx);
10904 #else
10905 HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
10906 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10907 }
10908 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
10909 {
10910 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10911 hrtim->Compare4EventCallback(hrtim, timer_idx);
10912 #else
10913 HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
10914 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10915 }
10916 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
10917 {
10918 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10919 hrtim->RegistersUpdateCallback(hrtim, timer_idx);
10920 #else
10921 HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
10922 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10923 }
10924 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
10925 {
10926 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10927 hrtim->Capture1EventCallback(hrtim, timer_idx);
10928 #else
10929 HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
10930 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10931 }
10932 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
10933 {
10934 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10935 hrtim->Capture2EventCallback(hrtim, timer_idx);
10936 #else
10937 HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
10938 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10939 }
10940 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
10941 {
10942 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10943 hrtim->Output1SetCallback(hrtim, timer_idx);
10944 #else
10945 HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
10946 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10947 }
10948 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
10949 {
10950 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10951 hrtim->Output1ResetCallback(hrtim, timer_idx);
10952 #else
10953 HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
10954 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10955 }
10956 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
10957 {
10958 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10959 hrtim->Output2SetCallback(hrtim, timer_idx);
10960 #else
10961 HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
10962 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10963 }
10964 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
10965 {
10966 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10967 hrtim->Output2ResetCallback(hrtim, timer_idx);
10968 #else
10969 HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
10970 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10971 }
10972 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
10973 {
10974 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10975 hrtim->CounterResetCallback(hrtim, timer_idx);
10976 #else
10977 HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
10978 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10979 }
10980 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
10981 {
10982 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10983 hrtim->DelayedProtectionCallback(hrtim, timer_idx);
10984 #else
10985 HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
10986 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10987 }
10988 else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
10989 {
10990 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
10991 hrtim->RepetitionEventCallback(hrtim, timer_idx);
10992 #else
10993 HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
10994 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
10995 }
10996 else
10997 {
10998 /* nothing to do */
10999 }
11000 }
11001
11002 /**
11003 * @brief DMA error callback
11004 * @param hdma pointer to DMA handle.
11005 * @retval None
11006 */
11007 static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
11008 {
11009 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11010
11011 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11012 hrtim->ErrorCallback(hrtim);
11013 #else
11014 HAL_HRTIM_ErrorCallback(hrtim);
11015 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11016 }
11017
11018 /**
11019 * @brief DMA callback invoked upon burst DMA transfer completion
11020 * @param hdma pointer to DMA handle.
11021 * @retval None
11022 */
11023 static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
11024 {
11025 HRTIM_HandleTypeDef * hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef* )hdma)->Parent;
11026
11027 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
11028 hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11029 #else
11030 HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
11031 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
11032 }
11033
11034 /**
11035 * @}
11036 */
11037
11038 /**
11039 * @}
11040 */
11041
11042 #endif /* HRTIM1 */
11043
11044 #endif /* HAL_HRTIM_MODULE_ENABLED */
11045
11046 /**
11047 * @}
11048 */
11049
11050 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/