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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Src / stm32g4xx_hal_nand.c
blob41f78fed9d7e95ee1f5c81908cc9bd100ae84fef
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_nand.c
4 * @author MCD Application Team
5 * @brief NAND HAL module driver.
6 * This file provides a generic firmware to drive NAND memories mounted
7 * as external device.
8 *
9 @verbatim
10 ==============================================================================
11 ##### How to use this driver #####
12 ==============================================================================
13 [..]
14 This driver is a generic layered driver which contains a set of APIs used to
15 control NAND flash memories. It uses the FMC layer functions to interface
16 with NAND devices. This driver is used as follows:
17
18 (+) NAND flash memory configuration sequence using the function HAL_NAND_Init()
19 with control and timing parameters for both common and attribute spaces.
20
21 (+) Read NAND flash memory maker and device IDs using the function
22 HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef
23 structure declared by the function caller.
24
25 (+) Access NAND flash memory by read/write operations using the functions
26 HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(),
27 HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(),
28 HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(),
29 HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b()
30 to read/write page(s)/spare area(s). These functions use specific device
31 information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef
32 structure. The read/write address information is contained by the Nand_Address_Typedef
33 structure passed as parameter.
34
35 (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset().
36
37 (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block().
38 The erase block address information is contained in the Nand_Address_Typedef
39 structure passed as parameter.
40
41 (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status().
42
43 (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/
44 HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction
45 feature or the function HAL_NAND_GetECC() to get the ECC correction code.
46
47 (+) You can monitor the NAND device HAL state by calling the function
48 HAL_NAND_GetState()
49
50 [..]
51 (@) This driver is a set of generic APIs which handle standard NAND flash operations.
52 If a NAND flash device contains different operations and/or implementations,
53 it should be implemented separately.
54
55 *** Callback registration ***
56 =============================================
57 [..]
58 The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1
59 allows the user to configure dynamically the driver callbacks.
60
61 Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback,
62 it allows to register following callbacks:
63 (+) MspInitCallback : NAND MspInit.
64 (+) MspDeInitCallback : NAND MspDeInit.
65 This function takes as parameters the HAL peripheral handle, the Callback ID
66 and a pointer to the user callback function.
67
68 Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default
69 weak (surcharged) function. It allows to reset following callbacks:
70 (+) MspInitCallback : NAND MspInit.
71 (+) MspDeInitCallback : NAND MspDeInit.
72 This function) takes as parameters the HAL peripheral handle and the Callback ID.
73
74 By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET
75 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
76 Exception done for MspInit and MspDeInit callbacks that are respectively
77 reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init
78 and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand).
79 If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit
80 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
81
82 Callbacks can be registered/unregistered in READY state only.
83 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
84 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
85 during the Init/DeInit.
86 In that case first register the MspInit/MspDeInit user callbacks
87 using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit
88 or @ref HAL_NAND_Init function.
89
90 When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or
91 not defined, the callback registering feature is not available
92 and weak (surcharged) callbacks are used.
93
94 @endverbatim
95 ******************************************************************************
96 * @attention
97 *
98 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
99 * All rights reserved.</center></h2>
100 *
101 * This software component is licensed by ST under BSD 3-Clause license,
102 * the "License"; You may not use this file except in compliance with the
103 * License. You may obtain a copy of the License at:
104 * opensource.org/licenses/BSD-3-Clause
105 *
106 ******************************************************************************
107 */
108
109 /* Includes ------------------------------------------------------------------*/
110 #include "stm32g4xx_hal.h"
111
112 #if defined(FMC_BANK3)
113
114 /** @addtogroup STM32G4xx_HAL_Driver
115 * @{
116 */
117
118 #ifdef HAL_NAND_MODULE_ENABLED
119
120 /** @defgroup NAND NAND
121 * @brief NAND HAL module driver
122 * @{
123 */
124
125 /* Private typedef -----------------------------------------------------------*/
126 /* Private Constants ------------------------------------------------------------*/
127 /* Private macro -------------------------------------------------------------*/
128 /* Private variables ---------------------------------------------------------*/
129 /* Private function prototypes -----------------------------------------------*/
130 /* Exported functions ---------------------------------------------------------*/
131
132 /** @defgroup NAND_Exported_Functions NAND Exported Functions
133 * @{
134 */
135
136 /** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
137 * @brief Initialization and Configuration functions
138 *
139 @verbatim
140 ==============================================================================
141 ##### NAND Initialization and de-initialization functions #####
142 ==============================================================================
143 [..]
144 This section provides functions allowing to initialize/de-initialize
145 the NAND memory
146
147 @endverbatim
148 * @{
149 */
150
151 /**
152 * @brief Perform NAND memory Initialization sequence
153 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
154 * the configuration information for NAND module.
155 * @param ComSpace_Timing pointer to Common space timing structure
156 * @param AttSpace_Timing pointer to Attribute space timing structure
157 * @retval HAL status
158 */
159 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
160 {
161 /* Check the NAND handle state */
162 if (hnand == NULL)
163 {
164 return HAL_ERROR;
165 }
166
167 if (hnand->State == HAL_NAND_STATE_RESET)
168 {
169 /* Allocate lock resource and initialize it */
170 hnand->Lock = HAL_UNLOCKED;
171
172 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
173 if(hnand->MspInitCallback == NULL)
174 {
175 hnand->MspInitCallback = HAL_NAND_MspInit;
176 }
177 hnand->ItCallback = HAL_NAND_ITCallback;
178
179 /* Init the low level hardware */
180 hnand->MspInitCallback(hnand);
181 #else
182 /* Initialize the low level hardware (MSP) */
183 HAL_NAND_MspInit(hnand);
184 #endif
185 }
186
187 /* Initialize NAND control Interface */
188 (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init));
189
190 /* Initialize NAND common space timing Interface */
191 (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank);
192
193 /* Initialize NAND attribute space timing Interface */
194 (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank);
195
196 /* Enable the NAND device */
197 __FMC_NAND_ENABLE(hnand->Instance);
198
199 /* Update the NAND controller state */
200 hnand->State = HAL_NAND_STATE_READY;
201
202 return HAL_OK;
203 }
204
205 /**
206 * @brief Perform NAND memory De-Initialization sequence
207 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
208 * the configuration information for NAND module.
209 * @retval HAL status
210 */
211 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand)
212 {
213 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
214 if(hnand->MspDeInitCallback == NULL)
215 {
216 hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
217 }
218
219 /* DeInit the low level hardware */
220 hnand->MspDeInitCallback(hnand);
221 #else
222 /* Initialize the low level hardware (MSP) */
223 HAL_NAND_MspDeInit(hnand);
224 #endif
225
226 /* Configure the NAND registers with their reset values */
227 (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank);
228
229 /* Reset the NAND controller state */
230 hnand->State = HAL_NAND_STATE_RESET;
231
232 /* Release Lock */
233 __HAL_UNLOCK(hnand);
234
235 return HAL_OK;
236 }
237
238 /**
239 * @brief NAND MSP Init
240 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
241 * the configuration information for NAND module.
242 * @retval None
243 */
244 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand)
245 {
246 /* Prevent unused argument(s) compilation warning */
247 UNUSED(hnand);
248
249 /* NOTE : This function Should not be modified, when the callback is needed,
250 the HAL_NAND_MspInit could be implemented in the user file
251 */
252 }
253
254 /**
255 * @brief NAND MSP DeInit
256 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
257 * the configuration information for NAND module.
258 * @retval None
259 */
260 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand)
261 {
262 /* Prevent unused argument(s) compilation warning */
263 UNUSED(hnand);
264
265 /* NOTE : This function Should not be modified, when the callback is needed,
266 the HAL_NAND_MspDeInit could be implemented in the user file
267 */
268 }
269
270
271 /**
272 * @brief This function handles NAND device interrupt request.
273 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
274 * the configuration information for NAND module.
275 * @retval HAL status
276 */
277 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand)
278 {
279 /* Check NAND interrupt Rising edge flag */
280 if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE))
281 {
282 /* NAND interrupt callback*/
283 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
284 hnand->ItCallback(hnand);
285 #else
286 HAL_NAND_ITCallback(hnand);
287 #endif
288
289 /* Clear NAND interrupt Rising edge pending bit */
290 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE);
291 }
292
293 /* Check NAND interrupt Level flag */
294 if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL))
295 {
296 /* NAND interrupt callback*/
297 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
298 hnand->ItCallback(hnand);
299 #else
300 HAL_NAND_ITCallback(hnand);
301 #endif
302
303 /* Clear NAND interrupt Level pending bit */
304 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL);
305 }
306
307 /* Check NAND interrupt Falling edge flag */
308 if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE))
309 {
310 /* NAND interrupt callback*/
311 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
312 hnand->ItCallback(hnand);
313 #else
314 HAL_NAND_ITCallback(hnand);
315 #endif
316
317 /* Clear NAND interrupt Falling edge pending bit */
318 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE);
319 }
320
321 /* Check NAND interrupt FIFO empty flag */
322 if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT))
323 {
324 /* NAND interrupt callback*/
325 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
326 hnand->ItCallback(hnand);
327 #else
328 HAL_NAND_ITCallback(hnand);
329 #endif
330
331 /* Clear NAND interrupt FIFO empty pending bit */
332 __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT);
333 }
334
335 }
336
337 /**
338 * @brief NAND interrupt feature callback
339 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
340 * the configuration information for NAND module.
341 * @retval None
342 */
343 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
344 {
345 /* Prevent unused argument(s) compilation warning */
346 UNUSED(hnand);
347
348 /* NOTE : This function Should not be modified, when the callback is needed,
349 the HAL_NAND_ITCallback could be implemented in the user file
350 */
351 }
352
353 /**
354 * @}
355 */
356
357 /** @defgroup NAND_Exported_Functions_Group2 Input and Output functions
358 * @brief Input Output and memory control functions
359 *
360 @verbatim
361 ==============================================================================
362 ##### NAND Input and Output functions #####
363 ==============================================================================
364 [..]
365 This section provides functions allowing to use and control the NAND
366 memory
367
368 @endverbatim
369 * @{
370 */
371
372 /**
373 * @brief Read the NAND memory electronic signature
374 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
375 * the configuration information for NAND module.
376 * @param pNAND_ID NAND ID structure
377 * @retval HAL status
378 */
379 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
380 {
381 __IO uint32_t data = 0;
382 __IO uint32_t data1 = 0;
383 uint32_t deviceAddress;
384
385 /* Check the NAND controller state */
386 if (hnand->State == HAL_NAND_STATE_BUSY)
387 {
388 return HAL_BUSY;
389 }
390 else if (hnand->State == HAL_NAND_STATE_READY)
391 {
392 /* Process Locked */
393 __HAL_LOCK(hnand);
394
395 /* Update the NAND controller state */
396 hnand->State = HAL_NAND_STATE_BUSY;
397
398 /* Identify the device address */
399 deviceAddress = NAND_DEVICE;
400
401 /* Send Read ID command sequence */
402 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
403 __DSB();
404 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
405 __DSB();
406
407 /* Read the electronic signature from NAND flash */
408 if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
409 {
410 data = *(__IO uint32_t *)deviceAddress;
411
412 /* Return the data read */
413 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
414 pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
415 pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
416 pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
417 }
418 else
419 {
420 data = *(__IO uint32_t *)deviceAddress;
421 data1 = *((__IO uint32_t *)deviceAddress + 4);
422
423 /* Return the data read */
424 pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
425 pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
426 pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
427 pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
428 }
429
430 /* Update the NAND controller state */
431 hnand->State = HAL_NAND_STATE_READY;
432
433 /* Process unlocked */
434 __HAL_UNLOCK(hnand);
435 }
436 else
437 {
438 return HAL_ERROR;
439 }
440
441 return HAL_OK;
442 }
443
444 /**
445 * @brief NAND memory reset
446 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
447 * the configuration information for NAND module.
448 * @retval HAL status
449 */
450 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
451 {
452 uint32_t deviceAddress;
453
454 /* Check the NAND controller state */
455 if (hnand->State == HAL_NAND_STATE_BUSY)
456 {
457 return HAL_BUSY;
458 }
459 else if (hnand->State == HAL_NAND_STATE_READY)
460 {
461 /* Process Locked */
462 __HAL_LOCK(hnand);
463
464 /* Update the NAND controller state */
465 hnand->State = HAL_NAND_STATE_BUSY;
466
467 /* Identify the device address */
468 deviceAddress = NAND_DEVICE;
469
470 /* Send NAND reset command */
471 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = 0xFF;
472
473 /* Update the NAND controller state */
474 hnand->State = HAL_NAND_STATE_READY;
475
476 /* Process unlocked */
477 __HAL_UNLOCK(hnand);
478 }
479 else
480 {
481 return HAL_ERROR;
482 }
483
484 return HAL_OK;
485
486 }
487
488 /**
489 * @brief Configure the device: Enter the physical parameters of the device
490 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
491 * the configuration information for NAND module.
492 * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
493 * @retval HAL status
494 */
495 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
496 {
497 hnand->Config.PageSize = pDeviceConfig->PageSize;
498 hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize;
499 hnand->Config.BlockSize = pDeviceConfig->BlockSize;
500 hnand->Config.BlockNbr = pDeviceConfig->BlockNbr;
501 hnand->Config.PlaneSize = pDeviceConfig->PlaneSize;
502 hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr;
503 hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable;
504
505 return HAL_OK;
506 }
507
508
509 /**
510 * @brief Read Page(s) from NAND memory block (8-bits addressing)
511 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
512 * the configuration information for NAND module.
513 * @param pAddress pointer to NAND address structure
514 * @param pBuffer pointer to destination read buffer
515 * @param NumPageToRead number of pages to read from block
516 * @retval HAL status
517 */
518 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
519 {
520 uint32_t index;
521 uint32_t tickstart;
522 uint32_t deviceAddress, numPagesRead = 0U, nandAddress, nbpages = NumPageToRead;
523 uint8_t * buff = pBuffer;
524
525 /* Check the NAND controller state */
526 if (hnand->State == HAL_NAND_STATE_BUSY)
527 {
528 return HAL_BUSY;
529 }
530 else if (hnand->State == HAL_NAND_STATE_READY)
531 {
532 /* Process Locked */
533 __HAL_LOCK(hnand);
534
535 /* Update the NAND controller state */
536 hnand->State = HAL_NAND_STATE_BUSY;
537
538 /* Identify the device address */
539 deviceAddress = NAND_DEVICE;
540
541 /* NAND raw address calculation */
542 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
543
544 /* Page(s) read loop */
545 while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
546 {
547 /* Send read page command sequence */
548 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
549 __DSB();
550
551 /* Cards with page size <= 512 bytes */
552 if ((hnand->Config.PageSize) <= 512U)
553 {
554 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
555 {
556 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
557 __DSB();
558 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
559 __DSB();
560 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
561 __DSB();
562 }
563 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
564 {
565 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
566 __DSB();
567 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
568 __DSB();
569 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
570 __DSB();
571 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
572 __DSB();
573 }
574 }
575 else /* (hnand->Config.PageSize) > 512 */
576 {
577 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
578 {
579 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
580 __DSB();
581 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
582 __DSB();
583 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
584 __DSB();
585 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
586 __DSB();
587 }
588 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
589 {
590 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
591 __DSB();
592 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
593 __DSB();
594 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
595 __DSB();
596 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
597 __DSB();
598 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
599 __DSB();
600 }
601 }
602
603 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
604 __DSB();
605
606
607 if (hnand->Config.ExtraCommandEnable == ENABLE)
608 {
609 /* Get tick */
610 tickstart = HAL_GetTick();
611
612 /* Read status until NAND is ready */
613 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
614 {
615 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
616 {
617 /* Update the NAND controller state */
618 hnand->State = HAL_NAND_STATE_ERROR;
619
620 /* Process unlocked */
621 __HAL_UNLOCK(hnand);
622
623 return HAL_TIMEOUT;
624 }
625 }
626
627 /* Go back to read mode */
628 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
629 __DSB();
630 }
631
632 /* Get Data into Buffer */
633 for (index = 0U; index < hnand->Config.PageSize; index++)
634 {
635 *buff = *(uint8_t *)deviceAddress;
636 buff++;
637 }
638
639 /* Increment read pages number */
640 numPagesRead++;
641
642 /* Decrement pages to read */
643 nbpages--;
644
645 /* Increment the NAND address */
646 nandAddress = (uint32_t)(nandAddress + 1U);
647 }
648
649 /* Update the NAND controller state */
650 hnand->State = HAL_NAND_STATE_READY;
651
652 /* Process unlocked */
653 __HAL_UNLOCK(hnand);
654 }
655 else
656 {
657 return HAL_ERROR;
658 }
659
660 return HAL_OK;
661
662 }
663
664 /**
665 * @brief Read Page(s) from NAND memory block (16-bits addressing)
666 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
667 * the configuration information for NAND module.
668 * @param pAddress pointer to NAND address structure
669 * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
670 * @param NumPageToRead number of pages to read from block
671 * @retval HAL status
672 */
673 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
674 {
675 uint32_t index;
676 uint32_t tickstart;
677 uint32_t deviceAddress, numPagesRead = 0, nandAddress, nbpages = NumPageToRead;
678 uint16_t * buff = pBuffer;
679
680 /* Check the NAND controller state */
681 if (hnand->State == HAL_NAND_STATE_BUSY)
682 {
683 return HAL_BUSY;
684 }
685 else if (hnand->State == HAL_NAND_STATE_READY)
686 {
687 /* Process Locked */
688 __HAL_LOCK(hnand);
689
690 /* Update the NAND controller state */
691 hnand->State = HAL_NAND_STATE_BUSY;
692
693 /* Identify the device address */
694 deviceAddress = NAND_DEVICE;
695
696 /* NAND raw address calculation */
697 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
698
699 /* Page(s) read loop */
700 while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
701 {
702 /* Send read page command sequence */
703 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
704 __DSB();
705
706 /* Cards with page size <= 512 bytes */
707 if ((hnand->Config.PageSize) <= 512U)
708 {
709 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
710 {
711 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
712 __DSB();
713 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
714 __DSB();
715 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
716 __DSB();
717 }
718 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
719 {
720 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
721 __DSB();
722 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
723 __DSB();
724 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
725 __DSB();
726 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
727 __DSB();
728 }
729 }
730 else /* (hnand->Config.PageSize) > 512 */
731 {
732 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
733 {
734 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
735 __DSB();
736 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
737 __DSB();
738 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
739 __DSB();
740 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
741 __DSB();
742 }
743 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
744 {
745 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
746 __DSB();
747 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
748 __DSB();
749 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
750 __DSB();
751 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
752 __DSB();
753 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
754 __DSB();
755 }
756 }
757
758 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
759 __DSB();
760
761 if (hnand->Config.ExtraCommandEnable == ENABLE)
762 {
763 /* Get tick */
764 tickstart = HAL_GetTick();
765
766 /* Read status until NAND is ready */
767 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
768 {
769 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
770 {
771 /* Update the NAND controller state */
772 hnand->State = HAL_NAND_STATE_ERROR;
773
774 /* Process unlocked */
775 __HAL_UNLOCK(hnand);
776
777 return HAL_TIMEOUT;
778 }
779 }
780
781 /* Go back to read mode */
782 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
783 __DSB();
784 }
785
786 /* Get Data into Buffer */
787 for (index = 0U; index < hnand->Config.PageSize; index++)
788 {
789 *buff = *(uint16_t *)deviceAddress;
790 buff++;
791 }
792
793 /* Increment read pages number */
794 numPagesRead++;
795
796 /* Decrement pages to read */
797 nbpages--;
798
799 /* Increment the NAND address */
800 nandAddress = (uint32_t)(nandAddress + 1U);
801 }
802
803 /* Update the NAND controller state */
804 hnand->State = HAL_NAND_STATE_READY;
805
806 /* Process unlocked */
807 __HAL_UNLOCK(hnand);
808 }
809 else
810 {
811 return HAL_ERROR;
812 }
813
814 return HAL_OK;
815 }
816
817 /**
818 * @brief Write Page(s) to NAND memory block (8-bits addressing)
819 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
820 * the configuration information for NAND module.
821 * @param pAddress pointer to NAND address structure
822 * @param pBuffer pointer to source buffer to write
823 * @param NumPageToWrite number of pages to write to block
824 * @retval HAL status
825 */
826 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
827 {
828 uint32_t index;
829 uint32_t tickstart;
830 uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
831 uint8_t * buff = pBuffer;
832
833 /* Check the NAND controller state */
834 if (hnand->State == HAL_NAND_STATE_BUSY)
835 {
836 return HAL_BUSY;
837 }
838 else if (hnand->State == HAL_NAND_STATE_READY)
839 {
840 /* Process Locked */
841 __HAL_LOCK(hnand);
842
843 /* Update the NAND controller state */
844 hnand->State = HAL_NAND_STATE_BUSY;
845
846 /* Identify the device address */
847 deviceAddress = NAND_DEVICE;
848
849 /* NAND raw address calculation */
850 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
851
852 /* Page(s) write loop */
853 while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
854 {
855 /* Send write page command sequence */
856 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
857 __DSB();
858 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
859 __DSB();
860
861 /* Cards with page size <= 512 bytes */
862 if ((hnand->Config.PageSize) <= 512U)
863 {
864 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
865 {
866 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
867 __DSB();
868 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
869 __DSB();
870 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
871 __DSB();
872 }
873 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
874 {
875 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
876 __DSB();
877 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
878 __DSB();
879 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
880 __DSB();
881 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
882 __DSB();
883 }
884 }
885 else /* (hnand->Config.PageSize) > 512 */
886 {
887 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
888 {
889 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
890 __DSB();
891 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
892 __DSB();
893 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
894 __DSB();
895 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
896 __DSB();
897 }
898 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
899 {
900 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
901 __DSB();
902 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
903 __DSB();
904 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
905 __DSB();
906 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
907 __DSB();
908 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
909 __DSB();
910 }
911 }
912
913 /* Write data to memory */
914 for (index = 0U; index < hnand->Config.PageSize; index++)
915 {
916 *(__IO uint8_t *)deviceAddress = *buff;
917 buff++;
918 __DSB();
919 }
920
921 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
922 __DSB();
923
924 /* Get tick */
925 tickstart = HAL_GetTick();
926
927 /* Read status until NAND is ready */
928 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
929 {
930 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
931 {
932 /* Update the NAND controller state */
933 hnand->State = HAL_NAND_STATE_ERROR;
934
935 /* Process unlocked */
936 __HAL_UNLOCK(hnand);
937
938 return HAL_TIMEOUT;
939 }
940 }
941
942 /* Increment written pages number */
943 numPagesWritten++;
944
945 /* Decrement pages to write */
946 nbpages--;
947
948 /* Increment the NAND address */
949 nandAddress = (uint32_t)(nandAddress + 1U);
950 }
951
952 /* Update the NAND controller state */
953 hnand->State = HAL_NAND_STATE_READY;
954
955 /* Process unlocked */
956 __HAL_UNLOCK(hnand);
957 }
958 else
959 {
960 return HAL_ERROR;
961 }
962
963 return HAL_OK;
964 }
965
966 /**
967 * @brief Write Page(s) to NAND memory block (16-bits addressing)
968 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
969 * the configuration information for NAND module.
970 * @param pAddress pointer to NAND address structure
971 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
972 * @param NumPageToWrite number of pages to write to block
973 * @retval HAL status
974 */
975 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
976 {
977 uint32_t index;
978 uint32_t tickstart;
979 uint32_t deviceAddress, numPagesWritten = 0, nandAddress, nbpages = NumPageToWrite;
980 uint16_t * buff = pBuffer;
981
982 /* Check the NAND controller state */
983 if (hnand->State == HAL_NAND_STATE_BUSY)
984 {
985 return HAL_BUSY;
986 }
987 else if (hnand->State == HAL_NAND_STATE_READY)
988 {
989 /* Process Locked */
990 __HAL_LOCK(hnand);
991
992 /* Update the NAND controller state */
993 hnand->State = HAL_NAND_STATE_BUSY;
994
995 /* Identify the device address */
996 deviceAddress = NAND_DEVICE;
997
998 /* NAND raw address calculation */
999 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1000
1001 /* Page(s) write loop */
1002 while ((nbpages != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1003 {
1004 /* Send write page command sequence */
1005 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1006 __DSB();
1007 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1008 __DSB();
1009
1010 /* Cards with page size <= 512 bytes */
1011 if ((hnand->Config.PageSize) <= 512U)
1012 {
1013 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1014 {
1015 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1016 __DSB();
1017 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1018 __DSB();
1019 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1020 __DSB();
1021 }
1022 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1023 {
1024 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1025 __DSB();
1026 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1027 __DSB();
1028 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1029 __DSB();
1030 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1031 __DSB();
1032 }
1033 }
1034 else /* (hnand->Config.PageSize) > 512 */
1035 {
1036 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1037 {
1038 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1039 __DSB();
1040 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1041 __DSB();
1042 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1043 __DSB();
1044 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1045 __DSB();
1046 }
1047 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1048 {
1049 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1050 __DSB();
1051 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1052 __DSB();
1053 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1054 __DSB();
1055 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1056 __DSB();
1057 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1058 __DSB();
1059 }
1060 }
1061
1062 /* Write data to memory */
1063 for (index = 0U; index < hnand->Config.PageSize; index++)
1064 {
1065 *(__IO uint16_t *)deviceAddress = *buff;
1066 buff++;
1067 __DSB();
1068 }
1069
1070 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1071 __DSB();
1072
1073 /* Get tick */
1074 tickstart = HAL_GetTick();
1075
1076 /* Read status until NAND is ready */
1077 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1078 {
1079 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1080 {
1081 /* Update the NAND controller state */
1082 hnand->State = HAL_NAND_STATE_ERROR;
1083
1084 /* Process unlocked */
1085 __HAL_UNLOCK(hnand);
1086
1087 return HAL_TIMEOUT;
1088 }
1089 }
1090
1091 /* Increment written pages number */
1092 numPagesWritten++;
1093
1094 /* Decrement pages to write */
1095 nbpages--;
1096
1097 /* Increment the NAND address */
1098 nandAddress = (uint32_t)(nandAddress + 1U);
1099 }
1100
1101 /* Update the NAND controller state */
1102 hnand->State = HAL_NAND_STATE_READY;
1103
1104 /* Process unlocked */
1105 __HAL_UNLOCK(hnand);
1106 }
1107 else
1108 {
1109 return HAL_ERROR;
1110 }
1111
1112 return HAL_OK;
1113 }
1114
1115 /**
1116 * @brief Read Spare area(s) from NAND memory (8-bits addressing)
1117 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1118 * the configuration information for NAND module.
1119 * @param pAddress pointer to NAND address structure
1120 * @param pBuffer pointer to source buffer to write
1121 * @param NumSpareAreaToRead Number of spare area to read
1122 * @retval HAL status
1123 */
1124 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
1125 {
1126 uint32_t index;
1127 uint32_t tickstart;
1128 uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
1129 uint8_t * buff = pBuffer;
1130
1131 /* Check the NAND controller state */
1132 if (hnand->State == HAL_NAND_STATE_BUSY)
1133 {
1134 return HAL_BUSY;
1135 }
1136 else if (hnand->State == HAL_NAND_STATE_READY)
1137 {
1138 /* Process Locked */
1139 __HAL_LOCK(hnand);
1140
1141 /* Update the NAND controller state */
1142 hnand->State = HAL_NAND_STATE_BUSY;
1143
1144 /* Identify the device address */
1145 deviceAddress = NAND_DEVICE;
1146
1147 /* NAND raw address calculation */
1148 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1149
1150 /* Column in page address */
1151 columnAddress = COLUMN_ADDRESS(hnand);
1152
1153 /* Spare area(s) read loop */
1154 while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1155 {
1156 /* Cards with page size <= 512 bytes */
1157 if ((hnand->Config.PageSize) <= 512U)
1158 {
1159 /* Send read spare area command sequence */
1160 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1161 __DSB();
1162
1163 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1164 {
1165 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1166 __DSB();
1167 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1168 __DSB();
1169 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1170 __DSB();
1171 }
1172 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1173 {
1174 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1175 __DSB();
1176 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1177 __DSB();
1178 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1179 __DSB();
1180 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1181 __DSB();
1182 }
1183 }
1184 else /* (hnand->Config.PageSize) > 512 */
1185 {
1186 /* Send read spare area command sequence */
1187 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1188 __DSB();
1189
1190 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1191 {
1192 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1193 __DSB();
1194 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1195 __DSB();
1196 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1197 __DSB();
1198 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1199 __DSB();
1200 }
1201 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1202 {
1203 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1204 __DSB();
1205 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1206 __DSB();
1207 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1208 __DSB();
1209 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1210 __DSB();
1211 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1212 __DSB();
1213 }
1214 }
1215
1216 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1217 __DSB();
1218
1219 if (hnand->Config.ExtraCommandEnable == ENABLE)
1220 {
1221 /* Get tick */
1222 tickstart = HAL_GetTick();
1223
1224 /* Read status until NAND is ready */
1225 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1226 {
1227 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1228 {
1229 /* Update the NAND controller state */
1230 hnand->State = HAL_NAND_STATE_ERROR;
1231
1232 /* Process unlocked */
1233 __HAL_UNLOCK(hnand);
1234
1235 return HAL_TIMEOUT;
1236 }
1237 }
1238
1239 /* Go back to read mode */
1240 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
1241 __DSB();
1242 }
1243
1244 /* Get Data into Buffer */
1245 for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1246 {
1247 *buff = *(uint8_t *)deviceAddress;
1248 buff++;
1249 }
1250
1251 /* Increment read spare areas number */
1252 numSpareAreaRead++;
1253
1254 /* Decrement spare areas to read */
1255 nbspare--;
1256
1257 /* Increment the NAND address */
1258 nandAddress = (uint32_t)(nandAddress + 1U);
1259 }
1260
1261 /* Update the NAND controller state */
1262 hnand->State = HAL_NAND_STATE_READY;
1263
1264 /* Process unlocked */
1265 __HAL_UNLOCK(hnand);
1266 }
1267 else
1268 {
1269 return HAL_ERROR;
1270 }
1271
1272 return HAL_OK;
1273 }
1274
1275 /**
1276 * @brief Read Spare area(s) from NAND memory (16-bits addressing)
1277 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1278 * the configuration information for NAND module.
1279 * @param pAddress pointer to NAND address structure
1280 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
1281 * @param NumSpareAreaToRead Number of spare area to read
1282 * @retval HAL status
1283 */
1284 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
1285 {
1286 uint32_t index;
1287 uint32_t tickstart;
1288 uint32_t deviceAddress, numSpareAreaRead = 0, nandAddress, columnAddress, nbspare = NumSpareAreaToRead;
1289 uint16_t * buff = pBuffer;
1290
1291 /* Check the NAND controller state */
1292 if (hnand->State == HAL_NAND_STATE_BUSY)
1293 {
1294 return HAL_BUSY;
1295 }
1296 else if (hnand->State == HAL_NAND_STATE_READY)
1297 {
1298 /* Process Locked */
1299 __HAL_LOCK(hnand);
1300
1301 /* Update the NAND controller state */
1302 hnand->State = HAL_NAND_STATE_BUSY;
1303
1304 /* Identify the device address */
1305 deviceAddress = NAND_DEVICE;
1306
1307 /* NAND raw address calculation */
1308 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1309
1310 /* Column in page address */
1311 columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1312
1313 /* Spare area(s) read loop */
1314 while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1315 {
1316 /* Cards with page size <= 512 bytes */
1317 if ((hnand->Config.PageSize) <= 512U)
1318 {
1319 /* Send read spare area command sequence */
1320 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1321 __DSB();
1322
1323 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1324 {
1325 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1326 __DSB();
1327 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1328 __DSB();
1329 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1330 __DSB();
1331 }
1332 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1333 {
1334 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1335 __DSB();
1336 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1337 __DSB();
1338 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1339 __DSB();
1340 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1341 __DSB();
1342 }
1343 }
1344 else /* (hnand->Config.PageSize) > 512 */
1345 {
1346 /* Send read spare area command sequence */
1347 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1348 __DSB();
1349
1350 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1351 {
1352 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1353 __DSB();
1354 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1355 __DSB();
1356 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1357 __DSB();
1358 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1359 __DSB();
1360 }
1361 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1362 {
1363 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1364 __DSB();
1365 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1366 __DSB();
1367 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1368 __DSB();
1369 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1370 __DSB();
1371 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1372 __DSB();
1373 }
1374 }
1375
1376 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
1377 __DSB();
1378
1379 if (hnand->Config.ExtraCommandEnable == ENABLE)
1380 {
1381 /* Get tick */
1382 tickstart = HAL_GetTick();
1383
1384 /* Read status until NAND is ready */
1385 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1386 {
1387 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1388 {
1389 /* Update the NAND controller state */
1390 hnand->State = HAL_NAND_STATE_ERROR;
1391
1392 /* Process unlocked */
1393 __HAL_UNLOCK(hnand);
1394
1395 return HAL_TIMEOUT;
1396 }
1397 }
1398
1399 /* Go back to read mode */
1400 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = ((uint8_t)0x00U);
1401 __DSB();
1402 }
1403
1404 /* Get Data into Buffer */
1405 for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1406 {
1407 *buff = *(uint16_t *)deviceAddress;
1408 buff++;
1409 }
1410
1411 /* Increment read spare areas number */
1412 numSpareAreaRead++;
1413
1414 /* Decrement spare areas to read */
1415 nbspare--;
1416
1417 /* Increment the NAND address */
1418 nandAddress = (uint32_t)(nandAddress + 1U);
1419 }
1420
1421 /* Update the NAND controller state */
1422 hnand->State = HAL_NAND_STATE_READY;
1423
1424 /* Process unlocked */
1425 __HAL_UNLOCK(hnand);
1426 }
1427 else
1428 {
1429 return HAL_ERROR;
1430 }
1431
1432 return HAL_OK;
1433 }
1434
1435 /**
1436 * @brief Write Spare area(s) to NAND memory (8-bits addressing)
1437 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1438 * the configuration information for NAND module.
1439 * @param pAddress pointer to NAND address structure
1440 * @param pBuffer pointer to source buffer to write
1441 * @param NumSpareAreaTowrite number of spare areas to write to block
1442 * @retval HAL status
1443 */
1444 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
1445 {
1446 uint32_t index;
1447 uint32_t tickstart;
1448 uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
1449 uint8_t * buff = pBuffer;
1450
1451 /* Check the NAND controller state */
1452 if (hnand->State == HAL_NAND_STATE_BUSY)
1453 {
1454 return HAL_BUSY;
1455 }
1456 else if (hnand->State == HAL_NAND_STATE_READY)
1457 {
1458 /* Process Locked */
1459 __HAL_LOCK(hnand);
1460
1461 /* Update the NAND controller state */
1462 hnand->State = HAL_NAND_STATE_BUSY;
1463
1464 /* Identify the device address */
1465 deviceAddress = NAND_DEVICE;
1466
1467 /* Page address calculation */
1468 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1469
1470 /* Column in page address */
1471 columnAddress = COLUMN_ADDRESS(hnand);
1472
1473 /* Spare area(s) write loop */
1474 while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1475 {
1476 /* Cards with page size <= 512 bytes */
1477 if ((hnand->Config.PageSize) <= 512U)
1478 {
1479 /* Send write Spare area command sequence */
1480 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1481 __DSB();
1482 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1483 __DSB();
1484
1485 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1486 {
1487 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1488 __DSB();
1489 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1490 __DSB();
1491 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1492 __DSB();
1493 }
1494 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1495 {
1496 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1497 __DSB();
1498 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1499 __DSB();
1500 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1501 __DSB();
1502 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1503 __DSB();
1504 }
1505 }
1506 else /* (hnand->Config.PageSize) > 512 */
1507 {
1508 /* Send write Spare area command sequence */
1509 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1510 __DSB();
1511 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1512 __DSB();
1513
1514 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1515 {
1516 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1517 __DSB();
1518 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1519 __DSB();
1520 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1521 __DSB();
1522 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1523 __DSB();
1524 }
1525 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1526 {
1527 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1528 __DSB();
1529 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1530 __DSB();
1531 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1532 __DSB();
1533 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1534 __DSB();
1535 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1536 __DSB();
1537 }
1538 }
1539
1540 /* Write data to memory */
1541 for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1542 {
1543 *(__IO uint8_t *)deviceAddress = *buff;
1544 buff++;
1545 __DSB();
1546 }
1547
1548 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1549 __DSB();
1550
1551 /* Get tick */
1552 tickstart = HAL_GetTick();
1553
1554 /* Read status until NAND is ready */
1555 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1556 {
1557 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1558 {
1559 /* Update the NAND controller state */
1560 hnand->State = HAL_NAND_STATE_ERROR;
1561
1562 /* Process unlocked */
1563 __HAL_UNLOCK(hnand);
1564
1565 return HAL_TIMEOUT;
1566 }
1567 }
1568
1569 /* Increment written spare areas number */
1570 numSpareAreaWritten++;
1571
1572 /* Decrement spare areas to write */
1573 nbspare--;
1574
1575 /* Increment the NAND address */
1576 nandAddress = (uint32_t)(nandAddress + 1U);
1577 }
1578
1579 /* Update the NAND controller state */
1580 hnand->State = HAL_NAND_STATE_READY;
1581
1582 /* Process unlocked */
1583 __HAL_UNLOCK(hnand);
1584 }
1585 else
1586 {
1587 return HAL_ERROR;
1588 }
1589
1590 return HAL_OK;
1591 }
1592
1593 /**
1594 * @brief Write Spare area(s) to NAND memory (16-bits addressing)
1595 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1596 * the configuration information for NAND module.
1597 * @param pAddress pointer to NAND address structure
1598 * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
1599 * @param NumSpareAreaTowrite number of spare areas to write to block
1600 * @retval HAL status
1601 */
1602 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
1603 {
1604 uint32_t index;
1605 uint32_t tickstart;
1606 uint32_t deviceAddress, numSpareAreaWritten = 0, nandAddress, columnAddress, nbspare = NumSpareAreaTowrite;
1607 uint16_t * buff = pBuffer;
1608
1609 /* Check the NAND controller state */
1610 if (hnand->State == HAL_NAND_STATE_BUSY)
1611 {
1612 return HAL_BUSY;
1613 }
1614 else if (hnand->State == HAL_NAND_STATE_READY)
1615 {
1616 /* Process Locked */
1617 __HAL_LOCK(hnand);
1618
1619 /* Update the NAND controller state */
1620 hnand->State = HAL_NAND_STATE_BUSY;
1621
1622 /* Identify the device address */
1623 deviceAddress = NAND_DEVICE;
1624
1625 /* NAND raw address calculation */
1626 nandAddress = ARRAY_ADDRESS(pAddress, hnand);
1627
1628 /* Column in page address */
1629 columnAddress = (uint32_t)(COLUMN_ADDRESS(hnand) * 2U);
1630
1631 /* Spare area(s) write loop */
1632 while ((nbspare != 0U) && (nandAddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr))))
1633 {
1634 /* Cards with page size <= 512 bytes */
1635 if ((hnand->Config.PageSize) <= 512U)
1636 {
1637 /* Send write Spare area command sequence */
1638 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
1639 __DSB();
1640 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1641 __DSB();
1642
1643 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1644 {
1645 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1646 __DSB();
1647 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1648 __DSB();
1649 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1650 __DSB();
1651 }
1652 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1653 {
1654 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00U;
1655 __DSB();
1656 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1657 __DSB();
1658 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1659 __DSB();
1660 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1661 __DSB();
1662 }
1663 }
1664 else /* (hnand->Config.PageSize) > 512 */
1665 {
1666 /* Send write Spare area command sequence */
1667 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
1668 __DSB();
1669 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
1670 __DSB();
1671
1672 if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U)
1673 {
1674 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1675 __DSB();
1676 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1677 __DSB();
1678 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1679 __DSB();
1680 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1681 __DSB();
1682 }
1683 else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */
1684 {
1685 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnAddress);
1686 __DSB();
1687 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnAddress);
1688 __DSB();
1689 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
1690 __DSB();
1691 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
1692 __DSB();
1693 *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
1694 __DSB();
1695 }
1696 }
1697
1698 /* Write data to memory */
1699 for (index = 0U; index < hnand->Config.SpareAreaSize; index++)
1700 {
1701 *(__IO uint16_t *)deviceAddress = *buff;
1702 buff++;
1703 __DSB();
1704 }
1705
1706 *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
1707 __DSB();
1708
1709 /* Get tick */
1710 tickstart = HAL_GetTick();
1711
1712 /* Read status until NAND is ready */
1713 while (HAL_NAND_Read_Status(hnand) != NAND_READY)
1714 {
1715 if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT)
1716 {
1717 /* Update the NAND controller state */
1718 hnand->State = HAL_NAND_STATE_ERROR;
1719
1720 /* Process unlocked */
1721 __HAL_UNLOCK(hnand);
1722
1723 return HAL_TIMEOUT;
1724 }
1725 }
1726
1727 /* Increment written spare areas number */
1728 numSpareAreaWritten++;
1729
1730 /* Decrement spare areas to write */
1731 nbspare--;
1732
1733 /* Increment the NAND address */
1734 nandAddress = (uint32_t)(nandAddress + 1U);
1735 }
1736
1737 /* Update the NAND controller state */
1738 hnand->State = HAL_NAND_STATE_READY;
1739
1740 /* Process unlocked */
1741 __HAL_UNLOCK(hnand);
1742 }
1743 else
1744 {
1745 return HAL_ERROR;
1746 }
1747
1748 return HAL_OK;
1749 }
1750
1751 /**
1752 * @brief NAND memory Block erase
1753 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1754 * the configuration information for NAND module.
1755 * @param pAddress pointer to NAND address structure
1756 * @retval HAL status
1757 */
1758 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1759 {
1760 uint32_t DeviceAddress;
1761
1762 /* Check the NAND controller state */
1763 if (hnand->State == HAL_NAND_STATE_BUSY)
1764 {
1765 return HAL_BUSY;
1766 }
1767 else if (hnand->State == HAL_NAND_STATE_READY)
1768 {
1769 /* Process Locked */
1770 __HAL_LOCK(hnand);
1771
1772 /* Update the NAND controller state */
1773 hnand->State = HAL_NAND_STATE_BUSY;
1774
1775 /* Identify the device address */
1776 DeviceAddress = NAND_DEVICE;
1777
1778 /* Send Erase block command sequence */
1779 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
1780 __DSB();
1781 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1782 __DSB();
1783 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1784 __DSB();
1785 *(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
1786 __DSB();
1787
1788 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE1;
1789 __DSB();
1790
1791 /* Update the NAND controller state */
1792 hnand->State = HAL_NAND_STATE_READY;
1793
1794 /* Process unlocked */
1795 __HAL_UNLOCK(hnand);
1796 }
1797 else
1798 {
1799 return HAL_ERROR;
1800 }
1801
1802 return HAL_OK;
1803 }
1804
1805 /**
1806 * @brief Increment the NAND memory address
1807 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
1808 * the configuration information for NAND module.
1809 * @param pAddress pointer to NAND address structure
1810 * @retval The new status of the increment address operation. It can be:
1811 * - NAND_VALID_ADDRESS: When the new address is valid address
1812 * - NAND_INVALID_ADDRESS: When the new address is invalid address
1813 */
1814 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
1815 {
1816 uint32_t status = NAND_VALID_ADDRESS;
1817
1818 /* Increment page address */
1819 pAddress->Page++;
1820
1821 /* Check NAND address is valid */
1822 if (pAddress->Page == hnand->Config.BlockSize)
1823 {
1824 pAddress->Page = 0;
1825 pAddress->Block++;
1826
1827 if (pAddress->Block == hnand->Config.PlaneSize)
1828 {
1829 pAddress->Block = 0;
1830 pAddress->Plane++;
1831
1832 if (pAddress->Plane == (hnand->Config.PlaneNbr))
1833 {
1834 status = NAND_INVALID_ADDRESS;
1835 }
1836 }
1837 }
1838
1839 return (status);
1840 }
1841
1842 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
1843 /**
1844 * @brief Register a User NAND Callback
1845 * To be used instead of the weak (surcharged) predefined callback
1846 * @param hnand : NAND handle
1847 * @param CallbackId : ID of the callback to be registered
1848 * This parameter can be one of the following values:
1849 * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
1850 * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
1851 * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
1852 * @param pCallback : pointer to the Callback function
1853 * @retval status
1854 */
1855 HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback)
1856 {
1857 HAL_StatusTypeDef status = HAL_OK;
1858
1859 if(pCallback == NULL)
1860 {
1861 return HAL_ERROR;
1862 }
1863
1864 /* Process locked */
1865 __HAL_LOCK(hnand);
1866
1867 if(hnand->State == HAL_NAND_STATE_READY)
1868 {
1869 switch (CallbackId)
1870 {
1871 case HAL_NAND_MSP_INIT_CB_ID :
1872 hnand->MspInitCallback = pCallback;
1873 break;
1874 case HAL_NAND_MSP_DEINIT_CB_ID :
1875 hnand->MspDeInitCallback = pCallback;
1876 break;
1877 case HAL_NAND_IT_CB_ID :
1878 hnand->ItCallback = pCallback;
1879 break;
1880 default :
1881 /* update return status */
1882 status = HAL_ERROR;
1883 break;
1884 }
1885 }
1886 else if(hnand->State == HAL_NAND_STATE_RESET)
1887 {
1888 switch (CallbackId)
1889 {
1890 case HAL_NAND_MSP_INIT_CB_ID :
1891 hnand->MspInitCallback = pCallback;
1892 break;
1893 case HAL_NAND_MSP_DEINIT_CB_ID :
1894 hnand->MspDeInitCallback = pCallback;
1895 break;
1896 default :
1897 /* update return status */
1898 status = HAL_ERROR;
1899 break;
1900 }
1901 }
1902 else
1903 {
1904 /* update return status */
1905 status = HAL_ERROR;
1906 }
1907
1908 /* Release Lock */
1909 __HAL_UNLOCK(hnand);
1910 return status;
1911 }
1912
1913 /**
1914 * @brief Unregister a User NAND Callback
1915 * NAND Callback is redirected to the weak (surcharged) predefined callback
1916 * @param hnand : NAND handle
1917 * @param CallbackId : ID of the callback to be unregistered
1918 * This parameter can be one of the following values:
1919 * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID
1920 * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID
1921 * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID
1922 * @retval status
1923 */
1924 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId)
1925 {
1926 HAL_StatusTypeDef status = HAL_OK;
1927
1928 /* Process locked */
1929 __HAL_LOCK(hnand);
1930
1931 if(hnand->State == HAL_NAND_STATE_READY)
1932 {
1933 switch (CallbackId)
1934 {
1935 case HAL_NAND_MSP_INIT_CB_ID :
1936 hnand->MspInitCallback = HAL_NAND_MspInit;
1937 break;
1938 case HAL_NAND_MSP_DEINIT_CB_ID :
1939 hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
1940 break;
1941 case HAL_NAND_IT_CB_ID :
1942 hnand->ItCallback = HAL_NAND_ITCallback;
1943 break;
1944 default :
1945 /* update return status */
1946 status = HAL_ERROR;
1947 break;
1948 }
1949 }
1950 else if(hnand->State == HAL_NAND_STATE_RESET)
1951 {
1952 switch (CallbackId)
1953 {
1954 case HAL_NAND_MSP_INIT_CB_ID :
1955 hnand->MspInitCallback = HAL_NAND_MspInit;
1956 break;
1957 case HAL_NAND_MSP_DEINIT_CB_ID :
1958 hnand->MspDeInitCallback = HAL_NAND_MspDeInit;
1959 break;
1960 default :
1961 /* update return status */
1962 status = HAL_ERROR;
1963 break;
1964 }
1965 }
1966 else
1967 {
1968 /* update return status */
1969 status = HAL_ERROR;
1970 }
1971
1972 /* Release Lock */
1973 __HAL_UNLOCK(hnand);
1974 return status;
1975 }
1976 #endif
1977
1978 /**
1979 * @}
1980 */
1981
1982 /** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions
1983 * @brief management functions
1984 *
1985 @verbatim
1986 ==============================================================================
1987 ##### NAND Control functions #####
1988 ==============================================================================
1989 [..]
1990 This subsection provides a set of functions allowing to control dynamically
1991 the NAND interface.
1992
1993 @endverbatim
1994 * @{
1995 */
1996
1997
1998 /**
1999 * @brief Enables dynamically NAND ECC feature.
2000 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
2001 * the configuration information for NAND module.
2002 * @retval HAL status
2003 */
2004 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand)
2005 {
2006 /* Check the NAND controller state */
2007 if (hnand->State == HAL_NAND_STATE_BUSY)
2008 {
2009 return HAL_BUSY;
2010 }
2011 else if (hnand->State == HAL_NAND_STATE_READY)
2012 {
2013 /* Update the NAND state */
2014 hnand->State = HAL_NAND_STATE_BUSY;
2015
2016 /* Enable ECC feature */
2017 (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank);
2018
2019 /* Update the NAND state */
2020 hnand->State = HAL_NAND_STATE_READY;
2021 }
2022 else
2023 {
2024 return HAL_ERROR;
2025 }
2026
2027 return HAL_OK;
2028 }
2029
2030 /**
2031 * @brief Disables dynamically FMC_NAND ECC feature.
2032 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
2033 * the configuration information for NAND module.
2034 * @retval HAL status
2035 */
2036 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand)
2037 {
2038 /* Check the NAND controller state */
2039 if (hnand->State == HAL_NAND_STATE_BUSY)
2040 {
2041 return HAL_BUSY;
2042 }
2043 else if (hnand->State == HAL_NAND_STATE_READY)
2044 {
2045 /* Update the NAND state */
2046 hnand->State = HAL_NAND_STATE_BUSY;
2047
2048 /* Disable ECC feature */
2049 (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank);
2050
2051 /* Update the NAND state */
2052 hnand->State = HAL_NAND_STATE_READY;
2053 }
2054 else
2055 {
2056 return HAL_ERROR;
2057 }
2058
2059 return HAL_OK;
2060 }
2061
2062 /**
2063 * @brief Disables dynamically NAND ECC feature.
2064 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
2065 * the configuration information for NAND module.
2066 * @param ECCval pointer to ECC value
2067 * @param Timeout maximum timeout to wait
2068 * @retval HAL status
2069 */
2070 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
2071 {
2072 HAL_StatusTypeDef status;
2073
2074 /* Check the NAND controller state */
2075 if (hnand->State == HAL_NAND_STATE_BUSY)
2076 {
2077 return HAL_BUSY;
2078 }
2079 else if (hnand->State == HAL_NAND_STATE_READY)
2080 {
2081 /* Update the NAND state */
2082 hnand->State = HAL_NAND_STATE_BUSY;
2083
2084 /* Get NAND ECC value */
2085 status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout);
2086
2087 /* Update the NAND state */
2088 hnand->State = HAL_NAND_STATE_READY;
2089 }
2090 else
2091 {
2092 return HAL_ERROR;
2093 }
2094
2095 return status;
2096 }
2097
2098 /**
2099 * @}
2100 */
2101
2102
2103 /** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions
2104 * @brief Peripheral State functions
2105 *
2106 @verbatim
2107 ==============================================================================
2108 ##### NAND State functions #####
2109 ==============================================================================
2110 [..]
2111 This subsection permits to get in run-time the status of the NAND controller
2112 and the data flow.
2113
2114 @endverbatim
2115 * @{
2116 */
2117
2118 /**
2119 * @brief return the NAND state
2120 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
2121 * the configuration information for NAND module.
2122 * @retval HAL state
2123 */
2124 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand)
2125 {
2126 return hnand->State;
2127 }
2128
2129 /**
2130 * @brief NAND memory read status
2131 * @param hnand pointer to a NAND_HandleTypeDef structure that contains
2132 * the configuration information for NAND module.
2133 * @retval NAND status
2134 */
2135 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand)
2136 {
2137 uint32_t data;
2138 uint32_t DeviceAddress;
2139 UNUSED(hnand);
2140
2141 /* Identify the device address */
2142 DeviceAddress = NAND_DEVICE;
2143
2144 /* Send Read status operation command */
2145 *(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_STATUS;
2146
2147 /* Read status register data */
2148 data = *(__IO uint8_t *)DeviceAddress;
2149
2150 /* Return the status */
2151 if ((data & NAND_ERROR) == NAND_ERROR)
2152 {
2153 return NAND_ERROR;
2154 }
2155 else if ((data & NAND_READY) == NAND_READY)
2156 {
2157 return NAND_READY;
2158 }
2159 else
2160 {
2161 return NAND_BUSY;
2162 }
2163 }
2164
2165 /**
2166 * @}
2167 */
2168
2169 /**
2170 * @}
2171 */
2172
2173 /**
2174 * @}
2175 */
2176
2177 #endif /* HAL_NAND_MODULE_ENABLED */
2178
2179 /**
2180 * @}
2181 */
2182
2183 #endif /* FMC_BANK3 */
2184
2185 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/