?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Src / stm32g4xx_hal_spi.c
blob365b9f4aa814bc34d230ece0ff3f33d84ba6ceea
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_spi.c
4 * @author MCD Application Team
5 * @brief SPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### How to use this driver #####
16 ==============================================================================
17 [..]
18 The SPI HAL driver can be used as follows:
19
20 (#) Declare a SPI_HandleTypeDef handle structure, for example:
21 SPI_HandleTypeDef hspi;
22
23 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
24 (##) Enable the SPIx interface clock
25 (##) SPI pins configuration
26 (+++) Enable the clock for the SPI GPIOs
27 (+++) Configure these SPI pins as alternate function push-pull
28 (##) NVIC configuration if you need to use interrupt process
29 (+++) Configure the SPIx interrupt priority
30 (+++) Enable the NVIC SPI IRQ handle
31 (##) DMA Configuration if you need to use DMA process
32 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
33 (+++) Enable the DMAx clock
34 (+++) Configure the DMA handle parameters
35 (+++) Configure the DMA Tx or Rx Stream/Channel
36 (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle
37 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
38
39 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
40 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
41
42 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
43 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
44 by calling the customized HAL_SPI_MspInit() API.
45 [..]
46 Circular mode restriction:
47 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
48 (##) Master 2Lines RxOnly
49 (##) Master 1Line Rx
50 (#) The CRC feature is not managed when the DMA circular mode is enabled
51 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
52 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
53 [..]
54 Master Receive mode restriction:
55 (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
56 bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
57 does not initiate a new transfer the following procedure has to be respected:
58 (##) HAL_SPI_DeInit()
59 (##) HAL_SPI_Init()
60 [..]
61 Callback registration:
62
63 (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
64 allows the user to configure dynamically the driver callbacks.
65 Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
66
67 Function HAL_SPI_RegisterCallback() allows to register following callbacks:
68 (+) TxCpltCallback : SPI Tx Completed callback
69 (+) RxCpltCallback : SPI Rx Completed callback
70 (+) TxRxCpltCallback : SPI TxRx Completed callback
71 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
72 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
73 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
74 (+) ErrorCallback : SPI Error callback
75 (+) AbortCpltCallback : SPI Abort callback
76 (+) MspInitCallback : SPI Msp Init callback
77 (+) MspDeInitCallback : SPI Msp DeInit callback
78 This function takes as parameters the HAL peripheral handle, the Callback ID
79 and a pointer to the user callback function.
80
81
82 (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
83 weak function.
84 HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
85 and the Callback ID.
86 This function allows to reset following callbacks:
87 (+) TxCpltCallback : SPI Tx Completed callback
88 (+) RxCpltCallback : SPI Rx Completed callback
89 (+) TxRxCpltCallback : SPI TxRx Completed callback
90 (+) TxHalfCpltCallback : SPI Tx Half Completed callback
91 (+) RxHalfCpltCallback : SPI Rx Half Completed callback
92 (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
93 (+) ErrorCallback : SPI Error callback
94 (+) AbortCpltCallback : SPI Abort callback
95 (+) MspInitCallback : SPI Msp Init callback
96 (+) MspDeInitCallback : SPI Msp DeInit callback
97
98 By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
99 all callbacks are set to the corresponding weak functions:
100 examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
101 Exception done for MspInit and MspDeInit functions that are
102 reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
103 these callbacks are null (not registered beforehand).
104 If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
105 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
106
107 Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
108 Exception done MspInit/MspDeInit functions that can be registered/unregistered
109 in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
110 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
111 Then, the user first registers the MspInit/MspDeInit user callbacks
112 using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
113 or HAL_SPI_Init() function.
114
115 When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
116 not defined, the callback registering feature is not available
117 and weak (surcharged) callbacks are used.
118
119 [..]
120 Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
121 the following table resume the max SPI frequency reached with data size 8bits/16bits,
122 according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
123
124 @endverbatim
125
126 Additional table :
127
128 DataSize = SPI_DATASIZE_8BIT:
129 +----------------------------------------------------------------------------------------------+
130 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
131 | Process | Tranfert mode |---------------------|----------------------|----------------------|
132 | | | Master | Slave | Master | Slave | Master | Slave |
133 |==============================================================================================|
134 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
135 | X |----------------|----------|----------|-----------|----------|-----------|----------|
136 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
137 | R |----------------|----------|----------|-----------|----------|-----------|----------|
138 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
139 |=========|================|==========|==========|===========|==========|===========|==========|
140 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
141 | |----------------|----------|----------|-----------|----------|-----------|----------|
142 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
143 | X |----------------|----------|----------|-----------|----------|-----------|----------|
144 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
145 |=========|================|==========|==========|===========|==========|===========|==========|
146 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
147 | |----------------|----------|----------|-----------|----------|-----------|----------|
148 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
149 | X |----------------|----------|----------|-----------|----------|-----------|----------|
150 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
151 +----------------------------------------------------------------------------------------------+
152
153 DataSize = SPI_DATASIZE_16BIT:
154 +----------------------------------------------------------------------------------------------+
155 | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line |
156 | Process | Tranfert mode |---------------------|----------------------|----------------------|
157 | | | Master | Slave | Master | Slave | Master | Slave |
158 |==============================================================================================|
159 | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA |
160 | X |----------------|----------|----------|-----------|----------|-----------|----------|
161 | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA |
162 | R |----------------|----------|----------|-----------|----------|-----------|----------|
163 | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA |
164 |=========|================|==========|==========|===========|==========|===========|==========|
165 | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 |
166 | |----------------|----------|----------|-----------|----------|-----------|----------|
167 | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 |
168 | X |----------------|----------|----------|-----------|----------|-----------|----------|
169 | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 |
170 |=========|================|==========|==========|===========|==========|===========|==========|
171 | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 |
172 | |----------------|----------|----------|-----------|----------|-----------|----------|
173 | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 |
174 | X |----------------|----------|----------|-----------|----------|-----------|----------|
175 | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 |
176 +----------------------------------------------------------------------------------------------+
177 @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
178 SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
179 @note
180 (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
181 (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
182 (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
183
184 ******************************************************************************
185 * @attention
186 *
187 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
188 * All rights reserved.</center></h2>
189 *
190 * This software component is licensed by ST under BSD 3-Clause license,
191 * the "License"; You may not use this file except in compliance with the
192 * License. You may obtain a copy of the License at:
193 * opensource.org/licenses/BSD-3-Clause
194 *
195 ******************************************************************************
196 */
197
198 /* Includes ------------------------------------------------------------------*/
199 #include "stm32g4xx_hal.h"
200
201 /** @addtogroup STM32G4xx_HAL_Driver
202 * @{
203 */
204
205 /** @defgroup SPI SPI
206 * @brief SPI HAL module driver
207 * @{
208 */
209 #ifdef HAL_SPI_MODULE_ENABLED
210
211 /* Private typedef -----------------------------------------------------------*/
212 /* Private defines -----------------------------------------------------------*/
213 /** @defgroup SPI_Private_Constants SPI Private Constants
214 * @{
215 */
216 #define SPI_DEFAULT_TIMEOUT 100U
217 /**
218 * @}
219 */
220
221 /* Private macros ------------------------------------------------------------*/
222 /* Private variables ---------------------------------------------------------*/
223 /* Private function prototypes -----------------------------------------------*/
224 /** @defgroup SPI_Private_Functions SPI Private Functions
225 * @{
226 */
227 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
228 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
229 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
230 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
231 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
232 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
233 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
234 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
235 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
236 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
237 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
238 uint32_t Timeout, uint32_t Tickstart);
239 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
240 uint32_t Timeout, uint32_t Tickstart);
241 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
242 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
243 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 #if (USE_SPI_CRC != 0U)
250 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
251 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
252 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 #endif /* USE_SPI_CRC */
255 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
256 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
257 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
258 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
259 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
260 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
261 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 /**
263 * @}
264 */
265
266 /* Exported functions --------------------------------------------------------*/
267 /** @defgroup SPI_Exported_Functions SPI Exported Functions
268 * @{
269 */
270
271 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
272 * @brief Initialization and Configuration functions
273 *
274 @verbatim
275 ===============================================================================
276 ##### Initialization and de-initialization functions #####
277 ===============================================================================
278 [..] This subsection provides a set of functions allowing to initialize and
279 de-initialize the SPIx peripheral:
280
281 (+) User must implement HAL_SPI_MspInit() function in which he configures
282 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
283
284 (+) Call the function HAL_SPI_Init() to configure the selected device with
285 the selected configuration:
286 (++) Mode
287 (++) Direction
288 (++) Data Size
289 (++) Clock Polarity and Phase
290 (++) NSS Management
291 (++) BaudRate Prescaler
292 (++) FirstBit
293 (++) TIMode
294 (++) CRC Calculation
295 (++) CRC Polynomial if CRC enabled
296 (++) CRC Length, used only with Data8 and Data16
297 (++) FIFO reception threshold
298
299 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
300 of the selected SPIx peripheral.
301
302 @endverbatim
303 * @{
304 */
305
306 /**
307 * @brief Initialize the SPI according to the specified parameters
308 * in the SPI_InitTypeDef and initialize the associated handle.
309 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
310 * the configuration information for SPI module.
311 * @retval HAL status
312 */
313 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
314 {
315 uint32_t frxth;
316
317 /* Check the SPI handle allocation */
318 if (hspi == NULL)
319 {
320 return HAL_ERROR;
321 }
322
323 /* Check the parameters */
324 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
325 assert_param(IS_SPI_MODE(hspi->Init.Mode));
326 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
327 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
328 assert_param(IS_SPI_NSS(hspi->Init.NSS));
329 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
330 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
331 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
332 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
333 if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
334 {
335 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
336 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
337 }
338 #if (USE_SPI_CRC != 0U)
339 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
340 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
341 {
342 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
343 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
344 }
345 #else
346 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
347 #endif /* USE_SPI_CRC */
348
349 if (hspi->State == HAL_SPI_STATE_RESET)
350 {
351 /* Allocate lock resource and initialize it */
352 hspi->Lock = HAL_UNLOCKED;
353
354 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
355 /* Init the SPI Callback settings */
356 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
357 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
358 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
359 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
360 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
361 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
362 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
363 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
364
365 if (hspi->MspInitCallback == NULL)
366 {
367 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
368 }
369
370 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
371 hspi->MspInitCallback(hspi);
372 #else
373 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
374 HAL_SPI_MspInit(hspi);
375 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
376 }
377
378 hspi->State = HAL_SPI_STATE_BUSY;
379
380 /* Disable the selected SPI peripheral */
381 __HAL_SPI_DISABLE(hspi);
382
383 /* Align by default the rs fifo threshold on the data size */
384 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
385 {
386 frxth = SPI_RXFIFO_THRESHOLD_HF;
387 }
388 else
389 {
390 frxth = SPI_RXFIFO_THRESHOLD_QF;
391 }
392
393 /* CRC calculation is valid only for 16Bit and 8 Bit */
394 if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
395 {
396 /* CRC must be disabled */
397 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
398 }
399
400 /* Align the CRC Length on the data size */
401 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
402 {
403 /* CRC Length aligned on the data size : value set by default */
404 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
405 {
406 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
407 }
408 else
409 {
410 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
411 }
412 }
413
414 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
415 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
416 Communication speed, First bit and CRC calculation state */
417 WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction |
418 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
419 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation));
420 #if (USE_SPI_CRC != 0U)
421 /* Configure : CRC Length */
422 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
423 {
424 hspi->Instance->CR1 |= SPI_CR1_CRCL;
425 }
426 #endif /* USE_SPI_CRC */
427
428 /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
429 WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode |
430 hspi->Init.NSSPMode | hspi->Init.DataSize) | frxth);
431
432 #if (USE_SPI_CRC != 0U)
433 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
434 /* Configure : CRC Polynomial */
435 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
436 {
437 WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
438 }
439 #endif /* USE_SPI_CRC */
440
441 #if defined(SPI_I2SCFGR_I2SMOD)
442 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
443 CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
444 #endif /* SPI_I2SCFGR_I2SMOD */
445
446 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
447 hspi->State = HAL_SPI_STATE_READY;
448
449 return HAL_OK;
450 }
451
452 /**
453 * @brief De-Initialize the SPI peripheral.
454 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
455 * the configuration information for SPI module.
456 * @retval HAL status
457 */
458 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
459 {
460 /* Check the SPI handle allocation */
461 if (hspi == NULL)
462 {
463 return HAL_ERROR;
464 }
465
466 /* Check SPI Instance parameter */
467 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
468
469 hspi->State = HAL_SPI_STATE_BUSY;
470
471 /* Disable the SPI Peripheral Clock */
472 __HAL_SPI_DISABLE(hspi);
473
474 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
475 if (hspi->MspDeInitCallback == NULL)
476 {
477 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
478 }
479
480 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
481 hspi->MspDeInitCallback(hspi);
482 #else
483 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
484 HAL_SPI_MspDeInit(hspi);
485 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
486
487 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
488 hspi->State = HAL_SPI_STATE_RESET;
489
490 /* Release Lock */
491 __HAL_UNLOCK(hspi);
492
493 return HAL_OK;
494 }
495
496 /**
497 * @brief Initialize the SPI MSP.
498 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
499 * the configuration information for SPI module.
500 * @retval None
501 */
502 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
503 {
504 /* Prevent unused argument(s) compilation warning */
505 UNUSED(hspi);
506
507 /* NOTE : This function should not be modified, when the callback is needed,
508 the HAL_SPI_MspInit should be implemented in the user file
509 */
510 }
511
512 /**
513 * @brief De-Initialize the SPI MSP.
514 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
515 * the configuration information for SPI module.
516 * @retval None
517 */
518 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
519 {
520 /* Prevent unused argument(s) compilation warning */
521 UNUSED(hspi);
522
523 /* NOTE : This function should not be modified, when the callback is needed,
524 the HAL_SPI_MspDeInit should be implemented in the user file
525 */
526 }
527
528 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
529 /**
530 * @brief Register a User SPI Callback
531 * To be used instead of the weak predefined callback
532 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
533 * the configuration information for the specified SPI.
534 * @param CallbackID ID of the callback to be registered
535 * @param pCallback pointer to the Callback function
536 * @retval HAL status
537 */
538 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
539 pSPI_CallbackTypeDef pCallback)
540 {
541 HAL_StatusTypeDef status = HAL_OK;
542
543 if (pCallback == NULL)
544 {
545 /* Update the error code */
546 hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
547
548 return HAL_ERROR;
549 }
550 /* Process locked */
551 __HAL_LOCK(hspi);
552
553 if (HAL_SPI_STATE_READY == hspi->State)
554 {
555 switch (CallbackID)
556 {
557 case HAL_SPI_TX_COMPLETE_CB_ID :
558 hspi->TxCpltCallback = pCallback;
559 break;
560
561 case HAL_SPI_RX_COMPLETE_CB_ID :
562 hspi->RxCpltCallback = pCallback;
563 break;
564
565 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
566 hspi->TxRxCpltCallback = pCallback;
567 break;
568
569 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
570 hspi->TxHalfCpltCallback = pCallback;
571 break;
572
573 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
574 hspi->RxHalfCpltCallback = pCallback;
575 break;
576
577 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
578 hspi->TxRxHalfCpltCallback = pCallback;
579 break;
580
581 case HAL_SPI_ERROR_CB_ID :
582 hspi->ErrorCallback = pCallback;
583 break;
584
585 case HAL_SPI_ABORT_CB_ID :
586 hspi->AbortCpltCallback = pCallback;
587 break;
588
589 case HAL_SPI_MSPINIT_CB_ID :
590 hspi->MspInitCallback = pCallback;
591 break;
592
593 case HAL_SPI_MSPDEINIT_CB_ID :
594 hspi->MspDeInitCallback = pCallback;
595 break;
596
597 default :
598 /* Update the error code */
599 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
600
601 /* Return error status */
602 status = HAL_ERROR;
603 break;
604 }
605 }
606 else if (HAL_SPI_STATE_RESET == hspi->State)
607 {
608 switch (CallbackID)
609 {
610 case HAL_SPI_MSPINIT_CB_ID :
611 hspi->MspInitCallback = pCallback;
612 break;
613
614 case HAL_SPI_MSPDEINIT_CB_ID :
615 hspi->MspDeInitCallback = pCallback;
616 break;
617
618 default :
619 /* Update the error code */
620 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
621
622 /* Return error status */
623 status = HAL_ERROR;
624 break;
625 }
626 }
627 else
628 {
629 /* Update the error code */
630 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
631
632 /* Return error status */
633 status = HAL_ERROR;
634 }
635
636 /* Release Lock */
637 __HAL_UNLOCK(hspi);
638 return status;
639 }
640
641 /**
642 * @brief Unregister an SPI Callback
643 * SPI callback is redirected to the weak predefined callback
644 * @param hspi Pointer to a SPI_HandleTypeDef structure that contains
645 * the configuration information for the specified SPI.
646 * @param CallbackID ID of the callback to be unregistered
647 * @retval HAL status
648 */
649 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
650 {
651 HAL_StatusTypeDef status = HAL_OK;
652
653 /* Process locked */
654 __HAL_LOCK(hspi);
655
656 if (HAL_SPI_STATE_READY == hspi->State)
657 {
658 switch (CallbackID)
659 {
660 case HAL_SPI_TX_COMPLETE_CB_ID :
661 hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */
662 break;
663
664 case HAL_SPI_RX_COMPLETE_CB_ID :
665 hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */
666 break;
667
668 case HAL_SPI_TX_RX_COMPLETE_CB_ID :
669 hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */
670 break;
671
672 case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
673 hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
674 break;
675
676 case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
677 hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
678 break;
679
680 case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
681 hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
682 break;
683
684 case HAL_SPI_ERROR_CB_ID :
685 hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */
686 break;
687
688 case HAL_SPI_ABORT_CB_ID :
689 hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */
690 break;
691
692 case HAL_SPI_MSPINIT_CB_ID :
693 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
694 break;
695
696 case HAL_SPI_MSPDEINIT_CB_ID :
697 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
698 break;
699
700 default :
701 /* Update the error code */
702 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
703
704 /* Return error status */
705 status = HAL_ERROR;
706 break;
707 }
708 }
709 else if (HAL_SPI_STATE_RESET == hspi->State)
710 {
711 switch (CallbackID)
712 {
713 case HAL_SPI_MSPINIT_CB_ID :
714 hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */
715 break;
716
717 case HAL_SPI_MSPDEINIT_CB_ID :
718 hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */
719 break;
720
721 default :
722 /* Update the error code */
723 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
724
725 /* Return error status */
726 status = HAL_ERROR;
727 break;
728 }
729 }
730 else
731 {
732 /* Update the error code */
733 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
734
735 /* Return error status */
736 status = HAL_ERROR;
737 }
738
739 /* Release Lock */
740 __HAL_UNLOCK(hspi);
741 return status;
742 }
743 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
744 /**
745 * @}
746 */
747
748 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
749 * @brief Data transfers functions
750 *
751 @verbatim
752 ==============================================================================
753 ##### IO operation functions #####
754 ===============================================================================
755 [..]
756 This subsection provides a set of functions allowing to manage the SPI
757 data transfers.
758
759 [..] The SPI supports master and slave mode :
760
761 (#) There are two modes of transfer:
762 (++) Blocking mode: The communication is performed in polling mode.
763 The HAL status of all data processing is returned by the same function
764 after finishing transfer.
765 (++) No-Blocking mode: The communication is performed using Interrupts
766 or DMA, These APIs return the HAL status.
767 The end of the data processing will be indicated through the
768 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
769 using DMA mode.
770 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
771 will be executed respectively at the end of the transmit or Receive process
772 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
773
774 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
775 exist for 1Line (simplex) and 2Lines (full duplex) modes.
776
777 @endverbatim
778 * @{
779 */
780
781 /**
782 * @brief Transmit an amount of data in blocking mode.
783 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
784 * the configuration information for SPI module.
785 * @param pData pointer to data buffer
786 * @param Size amount of data to be sent
787 * @param Timeout Timeout duration
788 * @retval HAL status
789 */
790 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
791 {
792 uint32_t tickstart;
793 HAL_StatusTypeDef errorcode = HAL_OK;
794 uint16_t initial_TxXferCount;
795
796 /* Check Direction parameter */
797 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
798
799 /* Process Locked */
800 __HAL_LOCK(hspi);
801
802 /* Init tickstart for timeout management*/
803 tickstart = HAL_GetTick();
804 initial_TxXferCount = Size;
805
806 if (hspi->State != HAL_SPI_STATE_READY)
807 {
808 errorcode = HAL_BUSY;
809 goto error;
810 }
811
812 if ((pData == NULL) || (Size == 0U))
813 {
814 errorcode = HAL_ERROR;
815 goto error;
816 }
817
818 /* Set the transaction information */
819 hspi->State = HAL_SPI_STATE_BUSY_TX;
820 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
821 hspi->pTxBuffPtr = (uint8_t *)pData;
822 hspi->TxXferSize = Size;
823 hspi->TxXferCount = Size;
824
825 /*Init field not used in handle to zero */
826 hspi->pRxBuffPtr = (uint8_t *)NULL;
827 hspi->RxXferSize = 0U;
828 hspi->RxXferCount = 0U;
829 hspi->TxISR = NULL;
830 hspi->RxISR = NULL;
831
832 /* Configure communication direction : 1Line */
833 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
834 {
835 SPI_1LINE_TX(hspi);
836 }
837
838 #if (USE_SPI_CRC != 0U)
839 /* Reset CRC Calculation */
840 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
841 {
842 SPI_RESET_CRC(hspi);
843 }
844 #endif /* USE_SPI_CRC */
845
846 /* Check if the SPI is already enabled */
847 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
848 {
849 /* Enable SPI peripheral */
850 __HAL_SPI_ENABLE(hspi);
851 }
852
853 /* Transmit data in 16 Bit mode */
854 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
855 {
856 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
857 {
858 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
859 hspi->pTxBuffPtr += sizeof(uint16_t);
860 hspi->TxXferCount--;
861 }
862 /* Transmit data in 16 Bit mode */
863 while (hspi->TxXferCount > 0U)
864 {
865 /* Wait until TXE flag is set to send data */
866 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
867 {
868 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
869 hspi->pTxBuffPtr += sizeof(uint16_t);
870 hspi->TxXferCount--;
871 }
872 else
873 {
874 /* Timeout management */
875 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
876 {
877 errorcode = HAL_TIMEOUT;
878 goto error;
879 }
880 }
881 }
882 }
883 /* Transmit data in 8 Bit mode */
884 else
885 {
886 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
887 {
888 if (hspi->TxXferCount > 1U)
889 {
890 /* write on the data register in packing mode */
891 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
892 hspi->pTxBuffPtr += sizeof(uint16_t);
893 hspi->TxXferCount -= 2U;
894 }
895 else
896 {
897 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
898 hspi->pTxBuffPtr ++;
899 hspi->TxXferCount--;
900 }
901 }
902 while (hspi->TxXferCount > 0U)
903 {
904 /* Wait until TXE flag is set to send data */
905 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
906 {
907 if (hspi->TxXferCount > 1U)
908 {
909 /* write on the data register in packing mode */
910 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
911 hspi->pTxBuffPtr += sizeof(uint16_t);
912 hspi->TxXferCount -= 2U;
913 }
914 else
915 {
916 *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
917 hspi->pTxBuffPtr++;
918 hspi->TxXferCount--;
919 }
920 }
921 else
922 {
923 /* Timeout management */
924 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
925 {
926 errorcode = HAL_TIMEOUT;
927 goto error;
928 }
929 }
930 }
931 }
932 #if (USE_SPI_CRC != 0U)
933 /* Enable CRC Transmission */
934 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
935 {
936 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
937 }
938 #endif /* USE_SPI_CRC */
939
940 /* Check the end of the transaction */
941 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
942 {
943 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
944 }
945
946 /* Clear overrun flag in 2 Lines communication mode because received is not read */
947 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
948 {
949 __HAL_SPI_CLEAR_OVRFLAG(hspi);
950 }
951
952 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
953 {
954 errorcode = HAL_ERROR;
955 }
956
957 error:
958 hspi->State = HAL_SPI_STATE_READY;
959 /* Process Unlocked */
960 __HAL_UNLOCK(hspi);
961 return errorcode;
962 }
963
964 /**
965 * @brief Receive an amount of data in blocking mode.
966 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
967 * the configuration information for SPI module.
968 * @param pData pointer to data buffer
969 * @param Size amount of data to be received
970 * @param Timeout Timeout duration
971 * @retval HAL status
972 */
973 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
974 {
975 uint32_t tickstart;
976 HAL_StatusTypeDef errorcode = HAL_OK;
977
978 if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
979 {
980 hspi->State = HAL_SPI_STATE_BUSY_RX;
981 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
982 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
983 }
984
985 /* Process Locked */
986 __HAL_LOCK(hspi);
987
988 /* Init tickstart for timeout management*/
989 tickstart = HAL_GetTick();
990
991 if (hspi->State != HAL_SPI_STATE_READY)
992 {
993 errorcode = HAL_BUSY;
994 goto error;
995 }
996
997 if ((pData == NULL) || (Size == 0U))
998 {
999 errorcode = HAL_ERROR;
1000 goto error;
1001 }
1002
1003 /* Set the transaction information */
1004 hspi->State = HAL_SPI_STATE_BUSY_RX;
1005 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1006 hspi->pRxBuffPtr = (uint8_t *)pData;
1007 hspi->RxXferSize = Size;
1008 hspi->RxXferCount = Size;
1009
1010 /*Init field not used in handle to zero */
1011 hspi->pTxBuffPtr = (uint8_t *)NULL;
1012 hspi->TxXferSize = 0U;
1013 hspi->TxXferCount = 0U;
1014 hspi->RxISR = NULL;
1015 hspi->TxISR = NULL;
1016
1017 #if (USE_SPI_CRC != 0U)
1018 /* Reset CRC Calculation */
1019 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1020 {
1021 SPI_RESET_CRC(hspi);
1022 /* this is done to handle the CRCNEXT before the latest data */
1023 hspi->RxXferCount--;
1024 }
1025 #endif /* USE_SPI_CRC */
1026
1027 /* Set the Rx Fifo threshold */
1028 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1029 {
1030 /* Set RX Fifo threshold according the reception data length: 16bit */
1031 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1032 }
1033 else
1034 {
1035 /* Set RX Fifo threshold according the reception data length: 8bit */
1036 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1037 }
1038
1039 /* Configure communication direction: 1Line */
1040 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1041 {
1042 SPI_1LINE_RX(hspi);
1043 }
1044
1045 /* Check if the SPI is already enabled */
1046 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1047 {
1048 /* Enable SPI peripheral */
1049 __HAL_SPI_ENABLE(hspi);
1050 }
1051
1052 /* Receive data in 8 Bit mode */
1053 if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
1054 {
1055 /* Transfer loop */
1056 while (hspi->RxXferCount > 0U)
1057 {
1058 /* Check the RXNE flag */
1059 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1060 {
1061 /* read the received data */
1062 (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1063 hspi->pRxBuffPtr += sizeof(uint8_t);
1064 hspi->RxXferCount--;
1065 }
1066 else
1067 {
1068 /* Timeout management */
1069 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1070 {
1071 errorcode = HAL_TIMEOUT;
1072 goto error;
1073 }
1074 }
1075 }
1076 }
1077 else
1078 {
1079 /* Transfer loop */
1080 while (hspi->RxXferCount > 0U)
1081 {
1082 /* Check the RXNE flag */
1083 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1084 {
1085 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1086 hspi->pRxBuffPtr += sizeof(uint16_t);
1087 hspi->RxXferCount--;
1088 }
1089 else
1090 {
1091 /* Timeout management */
1092 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1093 {
1094 errorcode = HAL_TIMEOUT;
1095 goto error;
1096 }
1097 }
1098 }
1099 }
1100
1101 #if (USE_SPI_CRC != 0U)
1102 /* Handle the CRC Transmission */
1103 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1104 {
1105 /* freeze the CRC before the latest data */
1106 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1107
1108 /* Read the latest data */
1109 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1110 {
1111 /* the latest data has not been received */
1112 errorcode = HAL_TIMEOUT;
1113 goto error;
1114 }
1115
1116 /* Receive last data in 16 Bit mode */
1117 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1118 {
1119 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1120 }
1121 /* Receive last data in 8 Bit mode */
1122 else
1123 {
1124 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1125 }
1126
1127 /* Wait the CRC data */
1128 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1129 {
1130 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1131 errorcode = HAL_TIMEOUT;
1132 goto error;
1133 }
1134
1135 /* Read CRC to Flush DR and RXNE flag */
1136 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1137 {
1138 /* Read 16bit CRC */
1139 READ_REG(hspi->Instance->DR);
1140 }
1141 else
1142 {
1143 /* Read 8bit CRC */
1144 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1145
1146 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1147 {
1148 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1149 {
1150 /* Error on the CRC reception */
1151 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1152 errorcode = HAL_TIMEOUT;
1153 goto error;
1154 }
1155 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1156 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1157 }
1158 }
1159 }
1160 #endif /* USE_SPI_CRC */
1161
1162 /* Check the end of the transaction */
1163 if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1164 {
1165 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1166 }
1167
1168 #if (USE_SPI_CRC != 0U)
1169 /* Check if CRC error occurred */
1170 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1171 {
1172 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1173 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1174 }
1175 #endif /* USE_SPI_CRC */
1176
1177 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1178 {
1179 errorcode = HAL_ERROR;
1180 }
1181
1182 error :
1183 hspi->State = HAL_SPI_STATE_READY;
1184 __HAL_UNLOCK(hspi);
1185 return errorcode;
1186 }
1187
1188 /**
1189 * @brief Transmit and Receive an amount of data in blocking mode.
1190 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1191 * the configuration information for SPI module.
1192 * @param pTxData pointer to transmission data buffer
1193 * @param pRxData pointer to reception data buffer
1194 * @param Size amount of data to be sent and received
1195 * @param Timeout Timeout duration
1196 * @retval HAL status
1197 */
1198 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1199 uint32_t Timeout)
1200 {
1201 uint16_t initial_TxXferCount;
1202 uint16_t initial_RxXferCount;
1203 uint32_t tmp_mode;
1204 HAL_SPI_StateTypeDef tmp_state;
1205 uint32_t tickstart;
1206 #if (USE_SPI_CRC != 0U)
1207 uint32_t spi_cr1;
1208 uint32_t spi_cr2;
1209 #endif /* USE_SPI_CRC */
1210
1211 /* Variable used to alternate Rx and Tx during transfer */
1212 uint32_t txallowed = 1U;
1213 HAL_StatusTypeDef errorcode = HAL_OK;
1214
1215 /* Check Direction parameter */
1216 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1217
1218 /* Process Locked */
1219 __HAL_LOCK(hspi);
1220
1221 /* Init tickstart for timeout management*/
1222 tickstart = HAL_GetTick();
1223
1224 /* Init temporary variables */
1225 tmp_state = hspi->State;
1226 tmp_mode = hspi->Init.Mode;
1227 initial_TxXferCount = Size;
1228 initial_RxXferCount = Size;
1229 #if (USE_SPI_CRC != 0U)
1230 spi_cr1 = READ_REG(hspi->Instance->CR1);
1231 spi_cr2 = READ_REG(hspi->Instance->CR2);
1232 #endif /* USE_SPI_CRC */
1233
1234 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1235 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1236 {
1237 errorcode = HAL_BUSY;
1238 goto error;
1239 }
1240
1241 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1242 {
1243 errorcode = HAL_ERROR;
1244 goto error;
1245 }
1246
1247 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1248 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1249 {
1250 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1251 }
1252
1253 /* Set the transaction information */
1254 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1255 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1256 hspi->RxXferCount = Size;
1257 hspi->RxXferSize = Size;
1258 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1259 hspi->TxXferCount = Size;
1260 hspi->TxXferSize = Size;
1261
1262 /*Init field not used in handle to zero */
1263 hspi->RxISR = NULL;
1264 hspi->TxISR = NULL;
1265
1266 #if (USE_SPI_CRC != 0U)
1267 /* Reset CRC Calculation */
1268 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1269 {
1270 SPI_RESET_CRC(hspi);
1271 }
1272 #endif /* USE_SPI_CRC */
1273
1274 /* Set the Rx Fifo threshold */
1275 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U))
1276 {
1277 /* Set fiforxthreshold according the reception data length: 16bit */
1278 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1279 }
1280 else
1281 {
1282 /* Set fiforxthreshold according the reception data length: 8bit */
1283 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1284 }
1285
1286 /* Check if the SPI is already enabled */
1287 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1288 {
1289 /* Enable SPI peripheral */
1290 __HAL_SPI_ENABLE(hspi);
1291 }
1292
1293 /* Transmit and Receive data in 16 Bit mode */
1294 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1295 {
1296 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1297 {
1298 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1299 hspi->pTxBuffPtr += sizeof(uint16_t);
1300 hspi->TxXferCount--;
1301 }
1302 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1303 {
1304 /* Check TXE flag */
1305 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1306 {
1307 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1308 hspi->pTxBuffPtr += sizeof(uint16_t);
1309 hspi->TxXferCount--;
1310 /* Next Data is a reception (Rx). Tx not allowed */
1311 txallowed = 0U;
1312
1313 #if (USE_SPI_CRC != 0U)
1314 /* Enable CRC Transmission */
1315 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1316 {
1317 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1318 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1319 {
1320 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1321 }
1322 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1323 }
1324 #endif /* USE_SPI_CRC */
1325 }
1326
1327 /* Check RXNE flag */
1328 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1329 {
1330 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1331 hspi->pRxBuffPtr += sizeof(uint16_t);
1332 hspi->RxXferCount--;
1333 /* Next Data is a Transmission (Tx). Tx is allowed */
1334 txallowed = 1U;
1335 }
1336 if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
1337 {
1338 errorcode = HAL_TIMEOUT;
1339 goto error;
1340 }
1341 }
1342 }
1343 /* Transmit and Receive data in 8 Bit mode */
1344 else
1345 {
1346 if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1347 {
1348 if (hspi->TxXferCount > 1U)
1349 {
1350 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1351 hspi->pTxBuffPtr += sizeof(uint16_t);
1352 hspi->TxXferCount -= 2U;
1353 }
1354 else
1355 {
1356 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1357 hspi->pTxBuffPtr++;
1358 hspi->TxXferCount--;
1359 }
1360 }
1361 while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1362 {
1363 /* Check TXE flag */
1364 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1365 {
1366 if (hspi->TxXferCount > 1U)
1367 {
1368 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1369 hspi->pTxBuffPtr += sizeof(uint16_t);
1370 hspi->TxXferCount -= 2U;
1371 }
1372 else
1373 {
1374 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1375 hspi->pTxBuffPtr++;
1376 hspi->TxXferCount--;
1377 }
1378 /* Next Data is a reception (Rx). Tx not allowed */
1379 txallowed = 0U;
1380
1381 #if (USE_SPI_CRC != 0U)
1382 /* Enable CRC Transmission */
1383 if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1384 {
1385 /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */
1386 if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP))
1387 {
1388 SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM);
1389 }
1390 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1391 }
1392 #endif /* USE_SPI_CRC */
1393 }
1394
1395 /* Wait until RXNE flag is reset */
1396 if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1397 {
1398 if (hspi->RxXferCount > 1U)
1399 {
1400 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1401 hspi->pRxBuffPtr += sizeof(uint16_t);
1402 hspi->RxXferCount -= 2U;
1403 if (hspi->RxXferCount <= 1U)
1404 {
1405 /* Set RX Fifo threshold before to switch on 8 bit data size */
1406 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1407 }
1408 }
1409 else
1410 {
1411 (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1412 hspi->pRxBuffPtr++;
1413 hspi->RxXferCount--;
1414 }
1415 /* Next Data is a Transmission (Tx). Tx is allowed */
1416 txallowed = 1U;
1417 }
1418 if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1419 {
1420 errorcode = HAL_TIMEOUT;
1421 goto error;
1422 }
1423 }
1424 }
1425
1426 #if (USE_SPI_CRC != 0U)
1427 /* Read CRC from DR to close CRC calculation process */
1428 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1429 {
1430 /* Wait until TXE flag */
1431 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1432 {
1433 /* Error on the CRC reception */
1434 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1435 errorcode = HAL_TIMEOUT;
1436 goto error;
1437 }
1438 /* Read CRC */
1439 if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1440 {
1441 /* Read 16bit CRC */
1442 READ_REG(hspi->Instance->DR);
1443 }
1444 else
1445 {
1446 /* Read 8bit CRC */
1447 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1448
1449 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
1450 {
1451 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1452 {
1453 /* Error on the CRC reception */
1454 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1455 errorcode = HAL_TIMEOUT;
1456 goto error;
1457 }
1458 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
1459 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
1460 }
1461 }
1462 }
1463
1464 /* Check if CRC error occurred */
1465 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1466 {
1467 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1468 /* Clear CRC Flag */
1469 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1470
1471 errorcode = HAL_ERROR;
1472 }
1473 #endif /* USE_SPI_CRC */
1474
1475 /* Check the end of the transaction */
1476 if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1477 {
1478 errorcode = HAL_ERROR;
1479 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1480 }
1481
1482 error :
1483 hspi->State = HAL_SPI_STATE_READY;
1484 __HAL_UNLOCK(hspi);
1485 return errorcode;
1486 }
1487
1488 /**
1489 * @brief Transmit an amount of data in non-blocking mode with Interrupt.
1490 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1491 * the configuration information for SPI module.
1492 * @param pData pointer to data buffer
1493 * @param Size amount of data to be sent
1494 * @retval HAL status
1495 */
1496 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1497 {
1498 HAL_StatusTypeDef errorcode = HAL_OK;
1499
1500 /* Check Direction parameter */
1501 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1502
1503 /* Process Locked */
1504 __HAL_LOCK(hspi);
1505
1506 if ((pData == NULL) || (Size == 0U))
1507 {
1508 errorcode = HAL_ERROR;
1509 goto error;
1510 }
1511
1512 if (hspi->State != HAL_SPI_STATE_READY)
1513 {
1514 errorcode = HAL_BUSY;
1515 goto error;
1516 }
1517
1518 /* Set the transaction information */
1519 hspi->State = HAL_SPI_STATE_BUSY_TX;
1520 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1521 hspi->pTxBuffPtr = (uint8_t *)pData;
1522 hspi->TxXferSize = Size;
1523 hspi->TxXferCount = Size;
1524
1525 /* Init field not used in handle to zero */
1526 hspi->pRxBuffPtr = (uint8_t *)NULL;
1527 hspi->RxXferSize = 0U;
1528 hspi->RxXferCount = 0U;
1529 hspi->RxISR = NULL;
1530
1531 /* Set the function for IT treatment */
1532 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1533 {
1534 hspi->TxISR = SPI_TxISR_16BIT;
1535 }
1536 else
1537 {
1538 hspi->TxISR = SPI_TxISR_8BIT;
1539 }
1540
1541 /* Configure communication direction : 1Line */
1542 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1543 {
1544 SPI_1LINE_TX(hspi);
1545 }
1546
1547 #if (USE_SPI_CRC != 0U)
1548 /* Reset CRC Calculation */
1549 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1550 {
1551 SPI_RESET_CRC(hspi);
1552 }
1553 #endif /* USE_SPI_CRC */
1554
1555 /* Enable TXE and ERR interrupt */
1556 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1557
1558
1559 /* Check if the SPI is already enabled */
1560 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1561 {
1562 /* Enable SPI peripheral */
1563 __HAL_SPI_ENABLE(hspi);
1564 }
1565
1566 error :
1567 __HAL_UNLOCK(hspi);
1568 return errorcode;
1569 }
1570
1571 /**
1572 * @brief Receive an amount of data in non-blocking mode with Interrupt.
1573 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1574 * the configuration information for SPI module.
1575 * @param pData pointer to data buffer
1576 * @param Size amount of data to be sent
1577 * @retval HAL status
1578 */
1579 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1580 {
1581 HAL_StatusTypeDef errorcode = HAL_OK;
1582
1583 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1584 {
1585 hspi->State = HAL_SPI_STATE_BUSY_RX;
1586 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1587 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1588 }
1589
1590 /* Process Locked */
1591 __HAL_LOCK(hspi);
1592
1593 if (hspi->State != HAL_SPI_STATE_READY)
1594 {
1595 errorcode = HAL_BUSY;
1596 goto error;
1597 }
1598
1599 if ((pData == NULL) || (Size == 0U))
1600 {
1601 errorcode = HAL_ERROR;
1602 goto error;
1603 }
1604
1605 /* Set the transaction information */
1606 hspi->State = HAL_SPI_STATE_BUSY_RX;
1607 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1608 hspi->pRxBuffPtr = (uint8_t *)pData;
1609 hspi->RxXferSize = Size;
1610 hspi->RxXferCount = Size;
1611
1612 /* Init field not used in handle to zero */
1613 hspi->pTxBuffPtr = (uint8_t *)NULL;
1614 hspi->TxXferSize = 0U;
1615 hspi->TxXferCount = 0U;
1616 hspi->TxISR = NULL;
1617
1618 /* Check the data size to adapt Rx threshold and the set the function for IT treatment */
1619 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1620 {
1621 /* Set RX Fifo threshold according the reception data length: 16 bit */
1622 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1623 hspi->RxISR = SPI_RxISR_16BIT;
1624 }
1625 else
1626 {
1627 /* Set RX Fifo threshold according the reception data length: 8 bit */
1628 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1629 hspi->RxISR = SPI_RxISR_8BIT;
1630 }
1631
1632 /* Configure communication direction : 1Line */
1633 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1634 {
1635 SPI_1LINE_RX(hspi);
1636 }
1637
1638 #if (USE_SPI_CRC != 0U)
1639 /* Reset CRC Calculation */
1640 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1641 {
1642 hspi->CRCSize = 1U;
1643 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1644 {
1645 hspi->CRCSize = 2U;
1646 }
1647 SPI_RESET_CRC(hspi);
1648 }
1649 else
1650 {
1651 hspi->CRCSize = 0U;
1652 }
1653 #endif /* USE_SPI_CRC */
1654
1655 /* Enable TXE and ERR interrupt */
1656 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1657
1658 /* Note : The SPI must be enabled after unlocking current process
1659 to avoid the risk of SPI interrupt handle execution before current
1660 process unlock */
1661
1662 /* Check if the SPI is already enabled */
1663 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1664 {
1665 /* Enable SPI peripheral */
1666 __HAL_SPI_ENABLE(hspi);
1667 }
1668
1669 error :
1670 /* Process Unlocked */
1671 __HAL_UNLOCK(hspi);
1672 return errorcode;
1673 }
1674
1675 /**
1676 * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1677 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1678 * the configuration information for SPI module.
1679 * @param pTxData pointer to transmission data buffer
1680 * @param pRxData pointer to reception data buffer
1681 * @param Size amount of data to be sent and received
1682 * @retval HAL status
1683 */
1684 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1685 {
1686 uint32_t tmp_mode;
1687 HAL_SPI_StateTypeDef tmp_state;
1688 HAL_StatusTypeDef errorcode = HAL_OK;
1689
1690 /* Check Direction parameter */
1691 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1692
1693 /* Process locked */
1694 __HAL_LOCK(hspi);
1695
1696 /* Init temporary variables */
1697 tmp_state = hspi->State;
1698 tmp_mode = hspi->Init.Mode;
1699
1700 if (!((tmp_state == HAL_SPI_STATE_READY) || \
1701 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1702 {
1703 errorcode = HAL_BUSY;
1704 goto error;
1705 }
1706
1707 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1708 {
1709 errorcode = HAL_ERROR;
1710 goto error;
1711 }
1712
1713 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1714 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1715 {
1716 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1717 }
1718
1719 /* Set the transaction information */
1720 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1721 hspi->pTxBuffPtr = (uint8_t *)pTxData;
1722 hspi->TxXferSize = Size;
1723 hspi->TxXferCount = Size;
1724 hspi->pRxBuffPtr = (uint8_t *)pRxData;
1725 hspi->RxXferSize = Size;
1726 hspi->RxXferCount = Size;
1727
1728 /* Set the function for IT treatment */
1729 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1730 {
1731 hspi->RxISR = SPI_2linesRxISR_16BIT;
1732 hspi->TxISR = SPI_2linesTxISR_16BIT;
1733 }
1734 else
1735 {
1736 hspi->RxISR = SPI_2linesRxISR_8BIT;
1737 hspi->TxISR = SPI_2linesTxISR_8BIT;
1738 }
1739
1740 #if (USE_SPI_CRC != 0U)
1741 /* Reset CRC Calculation */
1742 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1743 {
1744 hspi->CRCSize = 1U;
1745 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
1746 {
1747 hspi->CRCSize = 2U;
1748 }
1749 SPI_RESET_CRC(hspi);
1750 }
1751 else
1752 {
1753 hspi->CRCSize = 0U;
1754 }
1755 #endif /* USE_SPI_CRC */
1756
1757 /* Check if packing mode is enabled and if there is more than 2 data to receive */
1758 if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U))
1759 {
1760 /* Set RX Fifo threshold according the reception data length: 16 bit */
1761 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1762 }
1763 else
1764 {
1765 /* Set RX Fifo threshold according the reception data length: 8 bit */
1766 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1767 }
1768
1769 /* Enable TXE, RXNE and ERR interrupt */
1770 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1771
1772 /* Check if the SPI is already enabled */
1773 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1774 {
1775 /* Enable SPI peripheral */
1776 __HAL_SPI_ENABLE(hspi);
1777 }
1778
1779 error :
1780 /* Process Unlocked */
1781 __HAL_UNLOCK(hspi);
1782 return errorcode;
1783 }
1784
1785 /**
1786 * @brief Transmit an amount of data in non-blocking mode with DMA.
1787 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1788 * the configuration information for SPI module.
1789 * @param pData pointer to data buffer
1790 * @param Size amount of data to be sent
1791 * @retval HAL status
1792 */
1793 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1794 {
1795 HAL_StatusTypeDef errorcode = HAL_OK;
1796
1797 /* Check tx dma handle */
1798 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1799
1800 /* Check Direction parameter */
1801 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1802
1803 /* Process Locked */
1804 __HAL_LOCK(hspi);
1805
1806 if (hspi->State != HAL_SPI_STATE_READY)
1807 {
1808 errorcode = HAL_BUSY;
1809 goto error;
1810 }
1811
1812 if ((pData == NULL) || (Size == 0U))
1813 {
1814 errorcode = HAL_ERROR;
1815 goto error;
1816 }
1817
1818 /* Set the transaction information */
1819 hspi->State = HAL_SPI_STATE_BUSY_TX;
1820 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1821 hspi->pTxBuffPtr = (uint8_t *)pData;
1822 hspi->TxXferSize = Size;
1823 hspi->TxXferCount = Size;
1824
1825 /* Init field not used in handle to zero */
1826 hspi->pRxBuffPtr = (uint8_t *)NULL;
1827 hspi->TxISR = NULL;
1828 hspi->RxISR = NULL;
1829 hspi->RxXferSize = 0U;
1830 hspi->RxXferCount = 0U;
1831
1832 /* Configure communication direction : 1Line */
1833 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1834 {
1835 SPI_1LINE_TX(hspi);
1836 }
1837
1838 #if (USE_SPI_CRC != 0U)
1839 /* Reset CRC Calculation */
1840 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1841 {
1842 SPI_RESET_CRC(hspi);
1843 }
1844 #endif /* USE_SPI_CRC */
1845
1846 /* Set the SPI TxDMA Half transfer complete callback */
1847 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1848
1849 /* Set the SPI TxDMA transfer complete callback */
1850 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1851
1852 /* Set the DMA error callback */
1853 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1854
1855 /* Set the DMA AbortCpltCallback */
1856 hspi->hdmatx->XferAbortCallback = NULL;
1857
1858 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1859 /* Packing mode is enabled only if the DMA setting is HALWORD */
1860 if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
1861 {
1862 /* Check the even/odd of the data size + crc if enabled */
1863 if ((hspi->TxXferCount & 0x1U) == 0U)
1864 {
1865 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1866 hspi->TxXferCount = (hspi->TxXferCount >> 1U);
1867 }
1868 else
1869 {
1870 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
1871 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
1872 }
1873 }
1874
1875 /* Enable the Tx DMA Stream/Channel */
1876 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1877 hspi->TxXferCount))
1878 {
1879 /* Update SPI error code */
1880 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1881 errorcode = HAL_ERROR;
1882
1883 hspi->State = HAL_SPI_STATE_READY;
1884 goto error;
1885 }
1886
1887 /* Check if the SPI is already enabled */
1888 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1889 {
1890 /* Enable SPI peripheral */
1891 __HAL_SPI_ENABLE(hspi);
1892 }
1893
1894 /* Enable the SPI Error Interrupt Bit */
1895 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1896
1897 /* Enable Tx DMA Request */
1898 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1899
1900 error :
1901 /* Process Unlocked */
1902 __HAL_UNLOCK(hspi);
1903 return errorcode;
1904 }
1905
1906 /**
1907 * @brief Receive an amount of data in non-blocking mode with DMA.
1908 * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1909 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
1910 * the configuration information for SPI module.
1911 * @param pData pointer to data buffer
1912 * @note When the CRC feature is enabled the pData Length must be Size + 1.
1913 * @param Size amount of data to be sent
1914 * @retval HAL status
1915 */
1916 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1917 {
1918 HAL_StatusTypeDef errorcode = HAL_OK;
1919
1920 /* Check rx dma handle */
1921 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1922
1923 if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1924 {
1925 hspi->State = HAL_SPI_STATE_BUSY_RX;
1926
1927 /* Check tx dma handle */
1928 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1929
1930 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1931 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1932 }
1933
1934 /* Process Locked */
1935 __HAL_LOCK(hspi);
1936
1937 if (hspi->State != HAL_SPI_STATE_READY)
1938 {
1939 errorcode = HAL_BUSY;
1940 goto error;
1941 }
1942
1943 if ((pData == NULL) || (Size == 0U))
1944 {
1945 errorcode = HAL_ERROR;
1946 goto error;
1947 }
1948
1949 /* Set the transaction information */
1950 hspi->State = HAL_SPI_STATE_BUSY_RX;
1951 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
1952 hspi->pRxBuffPtr = (uint8_t *)pData;
1953 hspi->RxXferSize = Size;
1954 hspi->RxXferCount = Size;
1955
1956 /*Init field not used in handle to zero */
1957 hspi->RxISR = NULL;
1958 hspi->TxISR = NULL;
1959 hspi->TxXferSize = 0U;
1960 hspi->TxXferCount = 0U;
1961
1962 /* Configure communication direction : 1Line */
1963 if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1964 {
1965 SPI_1LINE_RX(hspi);
1966 }
1967
1968 #if (USE_SPI_CRC != 0U)
1969 /* Reset CRC Calculation */
1970 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1971 {
1972 SPI_RESET_CRC(hspi);
1973 }
1974 #endif /* USE_SPI_CRC */
1975
1976
1977 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1978 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1979 {
1980 /* Set RX Fifo threshold according the reception data length: 16bit */
1981 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1982 }
1983 else
1984 {
1985 /* Set RX Fifo threshold according the reception data length: 8bit */
1986 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1987
1988 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
1989 {
1990 /* Set RX Fifo threshold according the reception data length: 16bit */
1991 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
1992
1993 if ((hspi->RxXferCount & 0x1U) == 0x0U)
1994 {
1995 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
1996 hspi->RxXferCount = hspi->RxXferCount >> 1U;
1997 }
1998 else
1999 {
2000 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2001 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2002 }
2003 }
2004 }
2005
2006 /* Set the SPI RxDMA Half transfer complete callback */
2007 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2008
2009 /* Set the SPI Rx DMA transfer complete callback */
2010 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2011
2012 /* Set the DMA error callback */
2013 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2014
2015 /* Set the DMA AbortCpltCallback */
2016 hspi->hdmarx->XferAbortCallback = NULL;
2017
2018 /* Enable the Rx DMA Stream/Channel */
2019 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2020 hspi->RxXferCount))
2021 {
2022 /* Update SPI error code */
2023 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2024 errorcode = HAL_ERROR;
2025
2026 hspi->State = HAL_SPI_STATE_READY;
2027 goto error;
2028 }
2029
2030 /* Check if the SPI is already enabled */
2031 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2032 {
2033 /* Enable SPI peripheral */
2034 __HAL_SPI_ENABLE(hspi);
2035 }
2036
2037 /* Enable the SPI Error Interrupt Bit */
2038 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2039
2040 /* Enable Rx DMA Request */
2041 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2042
2043 error:
2044 /* Process Unlocked */
2045 __HAL_UNLOCK(hspi);
2046 return errorcode;
2047 }
2048
2049 /**
2050 * @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
2051 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2052 * the configuration information for SPI module.
2053 * @param pTxData pointer to transmission data buffer
2054 * @param pRxData pointer to reception data buffer
2055 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
2056 * @param Size amount of data to be sent
2057 * @retval HAL status
2058 */
2059 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
2060 uint16_t Size)
2061 {
2062 uint32_t tmp_mode;
2063 HAL_SPI_StateTypeDef tmp_state;
2064 HAL_StatusTypeDef errorcode = HAL_OK;
2065
2066 /* Check rx & tx dma handles */
2067 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
2068 assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
2069
2070 /* Check Direction parameter */
2071 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
2072
2073 /* Process locked */
2074 __HAL_LOCK(hspi);
2075
2076 /* Init temporary variables */
2077 tmp_state = hspi->State;
2078 tmp_mode = hspi->Init.Mode;
2079
2080 if (!((tmp_state == HAL_SPI_STATE_READY) ||
2081 ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
2082 {
2083 errorcode = HAL_BUSY;
2084 goto error;
2085 }
2086
2087 if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
2088 {
2089 errorcode = HAL_ERROR;
2090 goto error;
2091 }
2092
2093 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
2094 if (hspi->State != HAL_SPI_STATE_BUSY_RX)
2095 {
2096 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
2097 }
2098
2099 /* Set the transaction information */
2100 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2101 hspi->pTxBuffPtr = (uint8_t *)pTxData;
2102 hspi->TxXferSize = Size;
2103 hspi->TxXferCount = Size;
2104 hspi->pRxBuffPtr = (uint8_t *)pRxData;
2105 hspi->RxXferSize = Size;
2106 hspi->RxXferCount = Size;
2107
2108 /* Init field not used in handle to zero */
2109 hspi->RxISR = NULL;
2110 hspi->TxISR = NULL;
2111
2112 #if (USE_SPI_CRC != 0U)
2113 /* Reset CRC Calculation */
2114 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2115 {
2116 SPI_RESET_CRC(hspi);
2117 }
2118 #endif /* USE_SPI_CRC */
2119
2120 /* Reset the threshold bit */
2121 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX);
2122
2123 /* The packing mode management is enabled by the DMA settings according the spi data size */
2124 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
2125 {
2126 /* Set fiforxthreshold according the reception data length: 16bit */
2127 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2128 }
2129 else
2130 {
2131 /* Set RX Fifo threshold according the reception data length: 8bit */
2132 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2133
2134 if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2135 {
2136 if ((hspi->TxXferSize & 0x1U) == 0x0U)
2137 {
2138 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2139 hspi->TxXferCount = hspi->TxXferCount >> 1U;
2140 }
2141 else
2142 {
2143 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
2144 hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U;
2145 }
2146 }
2147
2148 if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
2149 {
2150 /* Set RX Fifo threshold according the reception data length: 16bit */
2151 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
2152
2153 if ((hspi->RxXferCount & 0x1U) == 0x0U)
2154 {
2155 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2156 hspi->RxXferCount = hspi->RxXferCount >> 1U;
2157 }
2158 else
2159 {
2160 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
2161 hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U;
2162 }
2163 }
2164 }
2165
2166 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
2167 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
2168 {
2169 /* Set the SPI Rx DMA Half transfer complete callback */
2170 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
2171 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
2172 }
2173 else
2174 {
2175 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
2176 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
2177 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
2178 }
2179
2180 /* Set the DMA error callback */
2181 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
2182
2183 /* Set the DMA AbortCpltCallback */
2184 hspi->hdmarx->XferAbortCallback = NULL;
2185
2186 /* Enable the Rx DMA Stream/Channel */
2187 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
2188 hspi->RxXferCount))
2189 {
2190 /* Update SPI error code */
2191 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2192 errorcode = HAL_ERROR;
2193
2194 hspi->State = HAL_SPI_STATE_READY;
2195 goto error;
2196 }
2197
2198 /* Enable Rx DMA Request */
2199 SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2200
2201 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
2202 is performed in DMA reception complete callback */
2203 hspi->hdmatx->XferHalfCpltCallback = NULL;
2204 hspi->hdmatx->XferCpltCallback = NULL;
2205 hspi->hdmatx->XferErrorCallback = NULL;
2206 hspi->hdmatx->XferAbortCallback = NULL;
2207
2208 /* Enable the Tx DMA Stream/Channel */
2209 if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
2210 hspi->TxXferCount))
2211 {
2212 /* Update SPI error code */
2213 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2214 errorcode = HAL_ERROR;
2215
2216 hspi->State = HAL_SPI_STATE_READY;
2217 goto error;
2218 }
2219
2220 /* Check if the SPI is already enabled */
2221 if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
2222 {
2223 /* Enable SPI peripheral */
2224 __HAL_SPI_ENABLE(hspi);
2225 }
2226 /* Enable the SPI Error Interrupt Bit */
2227 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
2228
2229 /* Enable Tx DMA Request */
2230 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2231
2232 error :
2233 /* Process Unlocked */
2234 __HAL_UNLOCK(hspi);
2235 return errorcode;
2236 }
2237
2238 /**
2239 * @brief Abort ongoing transfer (blocking mode).
2240 * @param hspi SPI handle.
2241 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2242 * started in Interrupt or DMA mode.
2243 * This procedure performs following operations :
2244 * - Disable SPI Interrupts (depending of transfer direction)
2245 * - Disable the DMA transfer in the peripheral register (if enabled)
2246 * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2247 * - Set handle State to READY
2248 * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2249 * @retval HAL status
2250 */
2251 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2252 {
2253 HAL_StatusTypeDef errorcode;
2254 __IO uint32_t count;
2255 __IO uint32_t resetcount;
2256
2257 /* Initialized local variable */
2258 errorcode = HAL_OK;
2259 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2260 count = resetcount;
2261
2262 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2263 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2264
2265 /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2266 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2267 {
2268 hspi->TxISR = SPI_AbortTx_ISR;
2269 /* Wait HAL_SPI_STATE_ABORT state */
2270 do
2271 {
2272 if (count == 0U)
2273 {
2274 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2275 break;
2276 }
2277 count--;
2278 } while (hspi->State != HAL_SPI_STATE_ABORT);
2279 /* Reset Timeout Counter */
2280 count = resetcount;
2281 }
2282
2283 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2284 {
2285 hspi->RxISR = SPI_AbortRx_ISR;
2286 /* Wait HAL_SPI_STATE_ABORT state */
2287 do
2288 {
2289 if (count == 0U)
2290 {
2291 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2292 break;
2293 }
2294 count--;
2295 } while (hspi->State != HAL_SPI_STATE_ABORT);
2296 /* Reset Timeout Counter */
2297 count = resetcount;
2298 }
2299
2300 /* Disable the SPI DMA Tx request if enabled */
2301 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2302 {
2303 /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2304 if (hspi->hdmatx != NULL)
2305 {
2306 /* Set the SPI DMA Abort callback :
2307 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2308 hspi->hdmatx->XferAbortCallback = NULL;
2309
2310 /* Abort DMA Tx Handle linked to SPI Peripheral */
2311 if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2312 {
2313 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2314 }
2315
2316 /* Disable Tx DMA Request */
2317 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2318
2319 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2320 {
2321 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2322 }
2323
2324 /* Disable SPI Peripheral */
2325 __HAL_SPI_DISABLE(hspi);
2326
2327 /* Empty the FRLVL fifo */
2328 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2329 {
2330 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2331 }
2332 }
2333 }
2334
2335 /* Disable the SPI DMA Rx request if enabled */
2336 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2337 {
2338 /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2339 if (hspi->hdmarx != NULL)
2340 {
2341 /* Set the SPI DMA Abort callback :
2342 will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2343 hspi->hdmarx->XferAbortCallback = NULL;
2344
2345 /* Abort DMA Rx Handle linked to SPI Peripheral */
2346 if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2347 {
2348 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2349 }
2350
2351 /* Disable peripheral */
2352 __HAL_SPI_DISABLE(hspi);
2353
2354 /* Control the BSY flag */
2355 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2356 {
2357 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2358 }
2359
2360 /* Empty the FRLVL fifo */
2361 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
2362 {
2363 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2364 }
2365
2366 /* Disable Rx DMA Request */
2367 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2368 }
2369 }
2370 /* Reset Tx and Rx transfer counters */
2371 hspi->RxXferCount = 0U;
2372 hspi->TxXferCount = 0U;
2373
2374 /* Check error during Abort procedure */
2375 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2376 {
2377 /* return HAL_Error in case of error during Abort procedure */
2378 errorcode = HAL_ERROR;
2379 }
2380 else
2381 {
2382 /* Reset errorCode */
2383 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2384 }
2385
2386 /* Clear the Error flags in the SR register */
2387 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2388 __HAL_SPI_CLEAR_FREFLAG(hspi);
2389
2390 /* Restore hspi->state to ready */
2391 hspi->State = HAL_SPI_STATE_READY;
2392
2393 return errorcode;
2394 }
2395
2396 /**
2397 * @brief Abort ongoing transfer (Interrupt mode).
2398 * @param hspi SPI handle.
2399 * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2400 * started in Interrupt or DMA mode.
2401 * This procedure performs following operations :
2402 * - Disable SPI Interrupts (depending of transfer direction)
2403 * - Disable the DMA transfer in the peripheral register (if enabled)
2404 * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2405 * - Set handle State to READY
2406 * - At abort completion, call user abort complete callback
2407 * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
2408 * considered as completed only when user abort complete callback is executed (not when exiting function).
2409 * @retval HAL status
2410 */
2411 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2412 {
2413 HAL_StatusTypeDef errorcode;
2414 uint32_t abortcplt ;
2415 __IO uint32_t count;
2416 __IO uint32_t resetcount;
2417
2418 /* Initialized local variable */
2419 errorcode = HAL_OK;
2420 abortcplt = 1U;
2421 resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2422 count = resetcount;
2423
2424 /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2425 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2426
2427 /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2428 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2429 {
2430 hspi->TxISR = SPI_AbortTx_ISR;
2431 /* Wait HAL_SPI_STATE_ABORT state */
2432 do
2433 {
2434 if (count == 0U)
2435 {
2436 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2437 break;
2438 }
2439 count--;
2440 } while (hspi->State != HAL_SPI_STATE_ABORT);
2441 /* Reset Timeout Counter */
2442 count = resetcount;
2443 }
2444
2445 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2446 {
2447 hspi->RxISR = SPI_AbortRx_ISR;
2448 /* Wait HAL_SPI_STATE_ABORT state */
2449 do
2450 {
2451 if (count == 0U)
2452 {
2453 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2454 break;
2455 }
2456 count--;
2457 } while (hspi->State != HAL_SPI_STATE_ABORT);
2458 /* Reset Timeout Counter */
2459 count = resetcount;
2460 }
2461
2462 /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2463 before any call to DMA Abort functions */
2464 /* DMA Tx Handle is valid */
2465 if (hspi->hdmatx != NULL)
2466 {
2467 /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2468 Otherwise, set it to NULL */
2469 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2470 {
2471 hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2472 }
2473 else
2474 {
2475 hspi->hdmatx->XferAbortCallback = NULL;
2476 }
2477 }
2478 /* DMA Rx Handle is valid */
2479 if (hspi->hdmarx != NULL)
2480 {
2481 /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2482 Otherwise, set it to NULL */
2483 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2484 {
2485 hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2486 }
2487 else
2488 {
2489 hspi->hdmarx->XferAbortCallback = NULL;
2490 }
2491 }
2492
2493 /* Disable the SPI DMA Tx request if enabled */
2494 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2495 {
2496 /* Abort the SPI DMA Tx Stream/Channel */
2497 if (hspi->hdmatx != NULL)
2498 {
2499 /* Abort DMA Tx Handle linked to SPI Peripheral */
2500 if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2501 {
2502 hspi->hdmatx->XferAbortCallback = NULL;
2503 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2504 }
2505 else
2506 {
2507 abortcplt = 0U;
2508 }
2509 }
2510 }
2511 /* Disable the SPI DMA Rx request if enabled */
2512 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2513 {
2514 /* Abort the SPI DMA Rx Stream/Channel */
2515 if (hspi->hdmarx != NULL)
2516 {
2517 /* Abort DMA Rx Handle linked to SPI Peripheral */
2518 if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK)
2519 {
2520 hspi->hdmarx->XferAbortCallback = NULL;
2521 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2522 }
2523 else
2524 {
2525 abortcplt = 0U;
2526 }
2527 }
2528 }
2529
2530 if (abortcplt == 1U)
2531 {
2532 /* Reset Tx and Rx transfer counters */
2533 hspi->RxXferCount = 0U;
2534 hspi->TxXferCount = 0U;
2535
2536 /* Check error during Abort procedure */
2537 if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2538 {
2539 /* return HAL_Error in case of error during Abort procedure */
2540 errorcode = HAL_ERROR;
2541 }
2542 else
2543 {
2544 /* Reset errorCode */
2545 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2546 }
2547
2548 /* Clear the Error flags in the SR register */
2549 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2550 __HAL_SPI_CLEAR_FREFLAG(hspi);
2551
2552 /* Restore hspi->State to Ready */
2553 hspi->State = HAL_SPI_STATE_READY;
2554
2555 /* As no DMA to be aborted, call directly user Abort complete callback */
2556 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2557 hspi->AbortCpltCallback(hspi);
2558 #else
2559 HAL_SPI_AbortCpltCallback(hspi);
2560 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2561 }
2562
2563 return errorcode;
2564 }
2565
2566 /**
2567 * @brief Pause the DMA Transfer.
2568 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2569 * the configuration information for the specified SPI module.
2570 * @retval HAL status
2571 */
2572 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2573 {
2574 /* Process Locked */
2575 __HAL_LOCK(hspi);
2576
2577 /* Disable the SPI DMA Tx & Rx requests */
2578 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2579
2580 /* Process Unlocked */
2581 __HAL_UNLOCK(hspi);
2582
2583 return HAL_OK;
2584 }
2585
2586 /**
2587 * @brief Resume the DMA Transfer.
2588 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2589 * the configuration information for the specified SPI module.
2590 * @retval HAL status
2591 */
2592 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2593 {
2594 /* Process Locked */
2595 __HAL_LOCK(hspi);
2596
2597 /* Enable the SPI DMA Tx & Rx requests */
2598 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2599
2600 /* Process Unlocked */
2601 __HAL_UNLOCK(hspi);
2602
2603 return HAL_OK;
2604 }
2605
2606 /**
2607 * @brief Stop the DMA Transfer.
2608 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2609 * the configuration information for the specified SPI module.
2610 * @retval HAL status
2611 */
2612 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2613 {
2614 HAL_StatusTypeDef errorcode = HAL_OK;
2615 /* The Lock is not implemented on this API to allow the user application
2616 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2617 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2618 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2619 */
2620
2621 /* Abort the SPI DMA tx Stream/Channel */
2622 if (hspi->hdmatx != NULL)
2623 {
2624 if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2625 {
2626 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2627 errorcode = HAL_ERROR;
2628 }
2629 }
2630 /* Abort the SPI DMA rx Stream/Channel */
2631 if (hspi->hdmarx != NULL)
2632 {
2633 if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2634 {
2635 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2636 errorcode = HAL_ERROR;
2637 }
2638 }
2639
2640 /* Disable the SPI DMA Tx & Rx requests */
2641 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2642 hspi->State = HAL_SPI_STATE_READY;
2643 return errorcode;
2644 }
2645
2646 /**
2647 * @brief Handle SPI interrupt request.
2648 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2649 * the configuration information for the specified SPI module.
2650 * @retval None
2651 */
2652 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2653 {
2654 uint32_t itsource = hspi->Instance->CR2;
2655 uint32_t itflag = hspi->Instance->SR;
2656
2657 /* SPI in mode Receiver ----------------------------------------------------*/
2658 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2659 (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2660 {
2661 hspi->RxISR(hspi);
2662 return;
2663 }
2664
2665 /* SPI in mode Transmitter -------------------------------------------------*/
2666 if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2667 {
2668 hspi->TxISR(hspi);
2669 return;
2670 }
2671
2672 /* SPI in Error Treatment --------------------------------------------------*/
2673 if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2674 || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2675 {
2676 /* SPI Overrun error interrupt occurred ----------------------------------*/
2677 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2678 {
2679 if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2680 {
2681 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2682 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2683 }
2684 else
2685 {
2686 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2687 return;
2688 }
2689 }
2690
2691 /* SPI Mode Fault error interrupt occurred -------------------------------*/
2692 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2693 {
2694 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2695 __HAL_SPI_CLEAR_MODFFLAG(hspi);
2696 }
2697
2698 /* SPI Frame error interrupt occurred ------------------------------------*/
2699 if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2700 {
2701 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2702 __HAL_SPI_CLEAR_FREFLAG(hspi);
2703 }
2704
2705 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2706 {
2707 /* Disable all interrupts */
2708 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2709
2710 hspi->State = HAL_SPI_STATE_READY;
2711 /* Disable the SPI DMA requests if enabled */
2712 if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2713 {
2714 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2715
2716 /* Abort the SPI DMA Rx channel */
2717 if (hspi->hdmarx != NULL)
2718 {
2719 /* Set the SPI DMA Abort callback :
2720 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2721 hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2722 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2723 {
2724 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2725 }
2726 }
2727 /* Abort the SPI DMA Tx channel */
2728 if (hspi->hdmatx != NULL)
2729 {
2730 /* Set the SPI DMA Abort callback :
2731 will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2732 hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2733 if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2734 {
2735 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2736 }
2737 }
2738 }
2739 else
2740 {
2741 /* Call user error callback */
2742 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2743 hspi->ErrorCallback(hspi);
2744 #else
2745 HAL_SPI_ErrorCallback(hspi);
2746 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2747 }
2748 }
2749 return;
2750 }
2751 }
2752
2753 /**
2754 * @brief Tx Transfer completed callback.
2755 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2756 * the configuration information for SPI module.
2757 * @retval None
2758 */
2759 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2760 {
2761 /* Prevent unused argument(s) compilation warning */
2762 UNUSED(hspi);
2763
2764 /* NOTE : This function should not be modified, when the callback is needed,
2765 the HAL_SPI_TxCpltCallback should be implemented in the user file
2766 */
2767 }
2768
2769 /**
2770 * @brief Rx Transfer completed callback.
2771 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2772 * the configuration information for SPI module.
2773 * @retval None
2774 */
2775 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2776 {
2777 /* Prevent unused argument(s) compilation warning */
2778 UNUSED(hspi);
2779
2780 /* NOTE : This function should not be modified, when the callback is needed,
2781 the HAL_SPI_RxCpltCallback should be implemented in the user file
2782 */
2783 }
2784
2785 /**
2786 * @brief Tx and Rx Transfer completed callback.
2787 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2788 * the configuration information for SPI module.
2789 * @retval None
2790 */
2791 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2792 {
2793 /* Prevent unused argument(s) compilation warning */
2794 UNUSED(hspi);
2795
2796 /* NOTE : This function should not be modified, when the callback is needed,
2797 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2798 */
2799 }
2800
2801 /**
2802 * @brief Tx Half Transfer completed callback.
2803 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2804 * the configuration information for SPI module.
2805 * @retval None
2806 */
2807 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2808 {
2809 /* Prevent unused argument(s) compilation warning */
2810 UNUSED(hspi);
2811
2812 /* NOTE : This function should not be modified, when the callback is needed,
2813 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2814 */
2815 }
2816
2817 /**
2818 * @brief Rx Half Transfer completed callback.
2819 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2820 * the configuration information for SPI module.
2821 * @retval None
2822 */
2823 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2824 {
2825 /* Prevent unused argument(s) compilation warning */
2826 UNUSED(hspi);
2827
2828 /* NOTE : This function should not be modified, when the callback is needed,
2829 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2830 */
2831 }
2832
2833 /**
2834 * @brief Tx and Rx Half Transfer callback.
2835 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2836 * the configuration information for SPI module.
2837 * @retval None
2838 */
2839 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2840 {
2841 /* Prevent unused argument(s) compilation warning */
2842 UNUSED(hspi);
2843
2844 /* NOTE : This function should not be modified, when the callback is needed,
2845 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2846 */
2847 }
2848
2849 /**
2850 * @brief SPI error callback.
2851 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2852 * the configuration information for SPI module.
2853 * @retval None
2854 */
2855 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2856 {
2857 /* Prevent unused argument(s) compilation warning */
2858 UNUSED(hspi);
2859
2860 /* NOTE : This function should not be modified, when the callback is needed,
2861 the HAL_SPI_ErrorCallback should be implemented in the user file
2862 */
2863 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2864 and user can use HAL_SPI_GetError() API to check the latest error occurred
2865 */
2866 }
2867
2868 /**
2869 * @brief SPI Abort Complete callback.
2870 * @param hspi SPI handle.
2871 * @retval None
2872 */
2873 __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2874 {
2875 /* Prevent unused argument(s) compilation warning */
2876 UNUSED(hspi);
2877
2878 /* NOTE : This function should not be modified, when the callback is needed,
2879 the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2880 */
2881 }
2882
2883 /**
2884 * @}
2885 */
2886
2887 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2888 * @brief SPI control functions
2889 *
2890 @verbatim
2891 ===============================================================================
2892 ##### Peripheral State and Errors functions #####
2893 ===============================================================================
2894 [..]
2895 This subsection provides a set of functions allowing to control the SPI.
2896 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2897 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2898 @endverbatim
2899 * @{
2900 */
2901
2902 /**
2903 * @brief Return the SPI handle state.
2904 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2905 * the configuration information for SPI module.
2906 * @retval SPI state
2907 */
2908 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2909 {
2910 /* Return SPI handle state */
2911 return hspi->State;
2912 }
2913
2914 /**
2915 * @brief Return the SPI error code.
2916 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
2917 * the configuration information for SPI module.
2918 * @retval SPI error code in bitmap format
2919 */
2920 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2921 {
2922 /* Return SPI ErrorCode */
2923 return hspi->ErrorCode;
2924 }
2925
2926 /**
2927 * @}
2928 */
2929
2930 /**
2931 * @}
2932 */
2933
2934 /** @addtogroup SPI_Private_Functions
2935 * @brief Private functions
2936 * @{
2937 */
2938
2939 /**
2940 * @brief DMA SPI transmit process complete callback.
2941 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2942 * the configuration information for the specified DMA module.
2943 * @retval None
2944 */
2945 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2946 {
2947 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2948 uint32_t tickstart;
2949
2950 /* Init tickstart for timeout management*/
2951 tickstart = HAL_GetTick();
2952
2953 /* DMA Normal Mode */
2954 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2955 {
2956 /* Disable ERR interrupt */
2957 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2958
2959 /* Disable Tx DMA Request */
2960 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2961
2962 /* Check the end of the transaction */
2963 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2964 {
2965 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2966 }
2967
2968 /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2969 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2970 {
2971 __HAL_SPI_CLEAR_OVRFLAG(hspi);
2972 }
2973
2974 hspi->TxXferCount = 0U;
2975 hspi->State = HAL_SPI_STATE_READY;
2976
2977 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2978 {
2979 /* Call user error callback */
2980 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2981 hspi->ErrorCallback(hspi);
2982 #else
2983 HAL_SPI_ErrorCallback(hspi);
2984 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2985 return;
2986 }
2987 }
2988 /* Call user Tx complete callback */
2989 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2990 hspi->TxCpltCallback(hspi);
2991 #else
2992 HAL_SPI_TxCpltCallback(hspi);
2993 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2994 }
2995
2996 /**
2997 * @brief DMA SPI receive process complete callback.
2998 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
2999 * the configuration information for the specified DMA module.
3000 * @retval None
3001 */
3002 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
3003 {
3004 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3005 uint32_t tickstart;
3006
3007 /* Init tickstart for timeout management*/
3008 tickstart = HAL_GetTick();
3009
3010 /* DMA Normal Mode */
3011 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3012 {
3013 /* Disable ERR interrupt */
3014 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3015
3016 #if (USE_SPI_CRC != 0U)
3017 /* CRC handling */
3018 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3019 {
3020 /* Wait until RXNE flag */
3021 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3022 {
3023 /* Error on the CRC reception */
3024 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3025 }
3026 /* Read CRC */
3027 if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
3028 {
3029 /* Read 16bit CRC */
3030 READ_REG(hspi->Instance->DR);
3031 }
3032 else
3033 {
3034 /* Read 8bit CRC */
3035 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3036
3037 if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
3038 {
3039 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3040 {
3041 /* Error on the CRC reception */
3042 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3043 }
3044 /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */
3045 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3046 }
3047 }
3048 }
3049 #endif /* USE_SPI_CRC */
3050
3051 /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
3052 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3053
3054 /* Check the end of the transaction */
3055 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3056 {
3057 hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
3058 }
3059
3060 hspi->RxXferCount = 0U;
3061 hspi->State = HAL_SPI_STATE_READY;
3062
3063 #if (USE_SPI_CRC != 0U)
3064 /* Check if CRC error occurred */
3065 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3066 {
3067 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3068 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3069 }
3070 #endif /* USE_SPI_CRC */
3071
3072 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3073 {
3074 /* Call user error callback */
3075 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3076 hspi->ErrorCallback(hspi);
3077 #else
3078 HAL_SPI_ErrorCallback(hspi);
3079 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3080 return;
3081 }
3082 }
3083 /* Call user Rx complete callback */
3084 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3085 hspi->RxCpltCallback(hspi);
3086 #else
3087 HAL_SPI_RxCpltCallback(hspi);
3088 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3089 }
3090
3091 /**
3092 * @brief DMA SPI transmit receive process complete callback.
3093 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3094 * the configuration information for the specified DMA module.
3095 * @retval None
3096 */
3097 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3098 {
3099 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3100 uint32_t tickstart;
3101
3102 /* Init tickstart for timeout management*/
3103 tickstart = HAL_GetTick();
3104
3105 /* DMA Normal Mode */
3106 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
3107 {
3108 /* Disable ERR interrupt */
3109 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3110
3111 #if (USE_SPI_CRC != 0U)
3112 /* CRC handling */
3113 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3114 {
3115 if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
3116 {
3117 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT,
3118 tickstart) != HAL_OK)
3119 {
3120 /* Error on the CRC reception */
3121 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3122 }
3123 /* Read CRC to Flush DR and RXNE flag */
3124 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3125 }
3126 else
3127 {
3128 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3129 {
3130 /* Error on the CRC reception */
3131 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3132 }
3133 /* Read CRC to Flush DR and RXNE flag */
3134 READ_REG(hspi->Instance->DR);
3135 }
3136 }
3137 #endif /* USE_SPI_CRC */
3138
3139 /* Check the end of the transaction */
3140 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3141 {
3142 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3143 }
3144
3145 /* Disable Rx/Tx DMA Request */
3146 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3147
3148 hspi->TxXferCount = 0U;
3149 hspi->RxXferCount = 0U;
3150 hspi->State = HAL_SPI_STATE_READY;
3151
3152 #if (USE_SPI_CRC != 0U)
3153 /* Check if CRC error occurred */
3154 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
3155 {
3156 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3157 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3158 }
3159 #endif /* USE_SPI_CRC */
3160
3161 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3162 {
3163 /* Call user error callback */
3164 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3165 hspi->ErrorCallback(hspi);
3166 #else
3167 HAL_SPI_ErrorCallback(hspi);
3168 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3169 return;
3170 }
3171 }
3172 /* Call user TxRx complete callback */
3173 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3174 hspi->TxRxCpltCallback(hspi);
3175 #else
3176 HAL_SPI_TxRxCpltCallback(hspi);
3177 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3178 }
3179
3180 /**
3181 * @brief DMA SPI half transmit process complete callback.
3182 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3183 * the configuration information for the specified DMA module.
3184 * @retval None
3185 */
3186 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
3187 {
3188 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3189
3190 /* Call user Tx half complete callback */
3191 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3192 hspi->TxHalfCpltCallback(hspi);
3193 #else
3194 HAL_SPI_TxHalfCpltCallback(hspi);
3195 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3196 }
3197
3198 /**
3199 * @brief DMA SPI half receive process complete callback
3200 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3201 * the configuration information for the specified DMA module.
3202 * @retval None
3203 */
3204 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
3205 {
3206 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3207
3208 /* Call user Rx half complete callback */
3209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3210 hspi->RxHalfCpltCallback(hspi);
3211 #else
3212 HAL_SPI_RxHalfCpltCallback(hspi);
3213 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3214 }
3215
3216 /**
3217 * @brief DMA SPI half transmit receive process complete callback.
3218 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3219 * the configuration information for the specified DMA module.
3220 * @retval None
3221 */
3222 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
3223 {
3224 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3225
3226 /* Call user TxRx half complete callback */
3227 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3228 hspi->TxRxHalfCpltCallback(hspi);
3229 #else
3230 HAL_SPI_TxRxHalfCpltCallback(hspi);
3231 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3232 }
3233
3234 /**
3235 * @brief DMA SPI communication error callback.
3236 * @param hdma pointer to a DMA_HandleTypeDef structure that contains
3237 * the configuration information for the specified DMA module.
3238 * @retval None
3239 */
3240 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
3241 {
3242 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3243
3244 /* Stop the disable DMA transfer on SPI side */
3245 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
3246
3247 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
3248 hspi->State = HAL_SPI_STATE_READY;
3249 /* Call user error callback */
3250 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3251 hspi->ErrorCallback(hspi);
3252 #else
3253 HAL_SPI_ErrorCallback(hspi);
3254 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3255 }
3256
3257 /**
3258 * @brief DMA SPI communication abort callback, when initiated by HAL services on Error
3259 * (To be called at end of DMA Abort procedure following error occurrence).
3260 * @param hdma DMA handle.
3261 * @retval None
3262 */
3263 static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3264 {
3265 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3266 hspi->RxXferCount = 0U;
3267 hspi->TxXferCount = 0U;
3268
3269 /* Call user error callback */
3270 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3271 hspi->ErrorCallback(hspi);
3272 #else
3273 HAL_SPI_ErrorCallback(hspi);
3274 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3275 }
3276
3277 /**
3278 * @brief DMA SPI Tx communication abort callback, when initiated by user
3279 * (To be called at end of DMA Tx Abort procedure following user abort request).
3280 * @note When this callback is executed, User Abort complete call back is called only if no
3281 * Abort still ongoing for Rx DMA Handle.
3282 * @param hdma DMA handle.
3283 * @retval None
3284 */
3285 static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3286 {
3287 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3288
3289 hspi->hdmatx->XferAbortCallback = NULL;
3290
3291 /* Disable Tx DMA Request */
3292 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3293
3294 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3295 {
3296 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3297 }
3298
3299 /* Disable SPI Peripheral */
3300 __HAL_SPI_DISABLE(hspi);
3301
3302 /* Empty the FRLVL fifo */
3303 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3304 {
3305 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3306 }
3307
3308 /* Check if an Abort process is still ongoing */
3309 if (hspi->hdmarx != NULL)
3310 {
3311 if (hspi->hdmarx->XferAbortCallback != NULL)
3312 {
3313 return;
3314 }
3315 }
3316
3317 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3318 hspi->RxXferCount = 0U;
3319 hspi->TxXferCount = 0U;
3320
3321 /* Check no error during Abort procedure */
3322 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3323 {
3324 /* Reset errorCode */
3325 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3326 }
3327
3328 /* Clear the Error flags in the SR register */
3329 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3330 __HAL_SPI_CLEAR_FREFLAG(hspi);
3331
3332 /* Restore hspi->State to Ready */
3333 hspi->State = HAL_SPI_STATE_READY;
3334
3335 /* Call user Abort complete callback */
3336 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3337 hspi->AbortCpltCallback(hspi);
3338 #else
3339 HAL_SPI_AbortCpltCallback(hspi);
3340 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3341 }
3342
3343 /**
3344 * @brief DMA SPI Rx communication abort callback, when initiated by user
3345 * (To be called at end of DMA Rx Abort procedure following user abort request).
3346 * @note When this callback is executed, User Abort complete call back is called only if no
3347 * Abort still ongoing for Tx DMA Handle.
3348 * @param hdma DMA handle.
3349 * @retval None
3350 */
3351 static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3352 {
3353 SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3354
3355 /* Disable SPI Peripheral */
3356 __HAL_SPI_DISABLE(hspi);
3357
3358 hspi->hdmarx->XferAbortCallback = NULL;
3359
3360 /* Disable Rx DMA Request */
3361 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3362
3363 /* Control the BSY flag */
3364 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3365 {
3366 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3367 }
3368
3369 /* Empty the FRLVL fifo */
3370 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3371 {
3372 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
3373 }
3374
3375 /* Check if an Abort process is still ongoing */
3376 if (hspi->hdmatx != NULL)
3377 {
3378 if (hspi->hdmatx->XferAbortCallback != NULL)
3379 {
3380 return;
3381 }
3382 }
3383
3384 /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3385 hspi->RxXferCount = 0U;
3386 hspi->TxXferCount = 0U;
3387
3388 /* Check no error during Abort procedure */
3389 if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3390 {
3391 /* Reset errorCode */
3392 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3393 }
3394
3395 /* Clear the Error flags in the SR register */
3396 __HAL_SPI_CLEAR_OVRFLAG(hspi);
3397 __HAL_SPI_CLEAR_FREFLAG(hspi);
3398
3399 /* Restore hspi->State to Ready */
3400 hspi->State = HAL_SPI_STATE_READY;
3401
3402 /* Call user Abort complete callback */
3403 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3404 hspi->AbortCpltCallback(hspi);
3405 #else
3406 HAL_SPI_AbortCpltCallback(hspi);
3407 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3408 }
3409
3410 /**
3411 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3412 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3413 * the configuration information for SPI module.
3414 * @retval None
3415 */
3416 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3417 {
3418 /* Receive data in packing mode */
3419 if (hspi->RxXferCount > 1U)
3420 {
3421 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3422 hspi->pRxBuffPtr += sizeof(uint16_t);
3423 hspi->RxXferCount -= 2U;
3424 if (hspi->RxXferCount == 1U)
3425 {
3426 /* Set RX Fifo threshold according the reception data length: 8bit */
3427 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3428 }
3429 }
3430 /* Receive data in 8 Bit mode */
3431 else
3432 {
3433 *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3434 hspi->pRxBuffPtr++;
3435 hspi->RxXferCount--;
3436 }
3437
3438 /* Check end of the reception */
3439 if (hspi->RxXferCount == 0U)
3440 {
3441 #if (USE_SPI_CRC != 0U)
3442 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3443 {
3444 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
3445 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
3446 return;
3447 }
3448 #endif /* USE_SPI_CRC */
3449
3450 /* Disable RXNE and ERR interrupt */
3451 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3452
3453 if (hspi->TxXferCount == 0U)
3454 {
3455 SPI_CloseRxTx_ISR(hspi);
3456 }
3457 }
3458 }
3459
3460 #if (USE_SPI_CRC != 0U)
3461 /**
3462 * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3463 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3464 * the configuration information for SPI module.
3465 * @retval None
3466 */
3467 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3468 {
3469 /* Read 8bit CRC to flush Data Regsiter */
3470 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3471
3472 hspi->CRCSize--;
3473
3474 /* Check end of the reception */
3475 if (hspi->CRCSize == 0U)
3476 {
3477 /* Disable RXNE and ERR interrupt */
3478 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3479
3480 if (hspi->TxXferCount == 0U)
3481 {
3482 SPI_CloseRxTx_ISR(hspi);
3483 }
3484 }
3485 }
3486 #endif /* USE_SPI_CRC */
3487
3488 /**
3489 * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3490 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3491 * the configuration information for SPI module.
3492 * @retval None
3493 */
3494 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3495 {
3496 /* Transmit data in packing Bit mode */
3497 if (hspi->TxXferCount >= 2U)
3498 {
3499 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3500 hspi->pTxBuffPtr += sizeof(uint16_t);
3501 hspi->TxXferCount -= 2U;
3502 }
3503 /* Transmit data in 8 Bit mode */
3504 else
3505 {
3506 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3507 hspi->pTxBuffPtr++;
3508 hspi->TxXferCount--;
3509 }
3510
3511 /* Check the end of the transmission */
3512 if (hspi->TxXferCount == 0U)
3513 {
3514 #if (USE_SPI_CRC != 0U)
3515 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3516 {
3517 /* Set CRC Next Bit to send CRC */
3518 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3519 /* Disable TXE interrupt */
3520 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3521 return;
3522 }
3523 #endif /* USE_SPI_CRC */
3524
3525 /* Disable TXE interrupt */
3526 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3527
3528 if (hspi->RxXferCount == 0U)
3529 {
3530 SPI_CloseRxTx_ISR(hspi);
3531 }
3532 }
3533 }
3534
3535 /**
3536 * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3537 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3538 * the configuration information for SPI module.
3539 * @retval None
3540 */
3541 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3542 {
3543 /* Receive data in 16 Bit mode */
3544 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3545 hspi->pRxBuffPtr += sizeof(uint16_t);
3546 hspi->RxXferCount--;
3547
3548 if (hspi->RxXferCount == 0U)
3549 {
3550 #if (USE_SPI_CRC != 0U)
3551 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3552 {
3553 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
3554 return;
3555 }
3556 #endif /* USE_SPI_CRC */
3557
3558 /* Disable RXNE interrupt */
3559 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3560
3561 if (hspi->TxXferCount == 0U)
3562 {
3563 SPI_CloseRxTx_ISR(hspi);
3564 }
3565 }
3566 }
3567
3568 #if (USE_SPI_CRC != 0U)
3569 /**
3570 * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3571 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3572 * the configuration information for SPI module.
3573 * @retval None
3574 */
3575 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3576 {
3577 /* Read 16bit CRC to flush Data Regsiter */
3578 READ_REG(hspi->Instance->DR);
3579
3580 /* Disable RXNE interrupt */
3581 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3582
3583 SPI_CloseRxTx_ISR(hspi);
3584 }
3585 #endif /* USE_SPI_CRC */
3586
3587 /**
3588 * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3589 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3590 * the configuration information for SPI module.
3591 * @retval None
3592 */
3593 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3594 {
3595 /* Transmit data in 16 Bit mode */
3596 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3597 hspi->pTxBuffPtr += sizeof(uint16_t);
3598 hspi->TxXferCount--;
3599
3600 /* Enable CRC Transmission */
3601 if (hspi->TxXferCount == 0U)
3602 {
3603 #if (USE_SPI_CRC != 0U)
3604 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3605 {
3606 /* Set CRC Next Bit to send CRC */
3607 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3608 /* Disable TXE interrupt */
3609 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3610 return;
3611 }
3612 #endif /* USE_SPI_CRC */
3613
3614 /* Disable TXE interrupt */
3615 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3616
3617 if (hspi->RxXferCount == 0U)
3618 {
3619 SPI_CloseRxTx_ISR(hspi);
3620 }
3621 }
3622 }
3623
3624 #if (USE_SPI_CRC != 0U)
3625 /**
3626 * @brief Manage the CRC 8-bit receive in Interrupt context.
3627 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3628 * the configuration information for SPI module.
3629 * @retval None
3630 */
3631 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3632 {
3633 /* Read 8bit CRC to flush Data Register */
3634 READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
3635
3636 hspi->CRCSize--;
3637
3638 if (hspi->CRCSize == 0U)
3639 {
3640 SPI_CloseRx_ISR(hspi);
3641 }
3642 }
3643 #endif /* USE_SPI_CRC */
3644
3645 /**
3646 * @brief Manage the receive 8-bit in Interrupt context.
3647 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3648 * the configuration information for SPI module.
3649 * @retval None
3650 */
3651 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3652 {
3653 *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3654 hspi->pRxBuffPtr++;
3655 hspi->RxXferCount--;
3656
3657 #if (USE_SPI_CRC != 0U)
3658 /* Enable CRC Transmission */
3659 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3660 {
3661 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3662 }
3663 #endif /* USE_SPI_CRC */
3664
3665 if (hspi->RxXferCount == 0U)
3666 {
3667 #if (USE_SPI_CRC != 0U)
3668 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3669 {
3670 hspi->RxISR = SPI_RxISR_8BITCRC;
3671 return;
3672 }
3673 #endif /* USE_SPI_CRC */
3674 SPI_CloseRx_ISR(hspi);
3675 }
3676 }
3677
3678 #if (USE_SPI_CRC != 0U)
3679 /**
3680 * @brief Manage the CRC 16-bit receive in Interrupt context.
3681 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3682 * the configuration information for SPI module.
3683 * @retval None
3684 */
3685 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3686 {
3687 /* Read 16bit CRC to flush Data Register */
3688 READ_REG(hspi->Instance->DR);
3689
3690 /* Disable RXNE and ERR interrupt */
3691 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3692
3693 SPI_CloseRx_ISR(hspi);
3694 }
3695 #endif /* USE_SPI_CRC */
3696
3697 /**
3698 * @brief Manage the 16-bit receive in Interrupt context.
3699 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3700 * the configuration information for SPI module.
3701 * @retval None
3702 */
3703 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3704 {
3705 *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3706 hspi->pRxBuffPtr += sizeof(uint16_t);
3707 hspi->RxXferCount--;
3708
3709 #if (USE_SPI_CRC != 0U)
3710 /* Enable CRC Transmission */
3711 if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3712 {
3713 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3714 }
3715 #endif /* USE_SPI_CRC */
3716
3717 if (hspi->RxXferCount == 0U)
3718 {
3719 #if (USE_SPI_CRC != 0U)
3720 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3721 {
3722 hspi->RxISR = SPI_RxISR_16BITCRC;
3723 return;
3724 }
3725 #endif /* USE_SPI_CRC */
3726 SPI_CloseRx_ISR(hspi);
3727 }
3728 }
3729
3730 /**
3731 * @brief Handle the data 8-bit transmit in Interrupt mode.
3732 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3733 * the configuration information for SPI module.
3734 * @retval None
3735 */
3736 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3737 {
3738 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3739 hspi->pTxBuffPtr++;
3740 hspi->TxXferCount--;
3741
3742 if (hspi->TxXferCount == 0U)
3743 {
3744 #if (USE_SPI_CRC != 0U)
3745 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3746 {
3747 /* Enable CRC Transmission */
3748 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3749 }
3750 #endif /* USE_SPI_CRC */
3751 SPI_CloseTx_ISR(hspi);
3752 }
3753 }
3754
3755 /**
3756 * @brief Handle the data 16-bit transmit in Interrupt mode.
3757 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3758 * the configuration information for SPI module.
3759 * @retval None
3760 */
3761 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3762 {
3763 /* Transmit data in 16 Bit mode */
3764 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3765 hspi->pTxBuffPtr += sizeof(uint16_t);
3766 hspi->TxXferCount--;
3767
3768 if (hspi->TxXferCount == 0U)
3769 {
3770 #if (USE_SPI_CRC != 0U)
3771 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3772 {
3773 /* Enable CRC Transmission */
3774 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3775 }
3776 #endif /* USE_SPI_CRC */
3777 SPI_CloseTx_ISR(hspi);
3778 }
3779 }
3780
3781 /**
3782 * @brief Handle SPI Communication Timeout.
3783 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3784 * the configuration information for SPI module.
3785 * @param Flag SPI flag to check
3786 * @param State flag state to check
3787 * @param Timeout Timeout duration
3788 * @param Tickstart tick start value
3789 * @retval HAL status
3790 */
3791 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3792 uint32_t Timeout, uint32_t Tickstart)
3793 {
3794 while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3795 {
3796 if (Timeout != HAL_MAX_DELAY)
3797 {
3798 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3799 {
3800 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3801 on both master and slave sides in order to resynchronize the master
3802 and slave for their respective CRC calculation */
3803
3804 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3805 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3806
3807 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3808 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3809 {
3810 /* Disable SPI peripheral */
3811 __HAL_SPI_DISABLE(hspi);
3812 }
3813
3814 /* Reset CRC Calculation */
3815 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3816 {
3817 SPI_RESET_CRC(hspi);
3818 }
3819
3820 hspi->State = HAL_SPI_STATE_READY;
3821
3822 /* Process Unlocked */
3823 __HAL_UNLOCK(hspi);
3824
3825 return HAL_TIMEOUT;
3826 }
3827 }
3828 }
3829
3830 return HAL_OK;
3831 }
3832
3833 /**
3834 * @brief Handle SPI FIFO Communication Timeout.
3835 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3836 * the configuration information for SPI module.
3837 * @param Fifo Fifo to check
3838 * @param State Fifo state to check
3839 * @param Timeout Timeout duration
3840 * @param Tickstart tick start value
3841 * @retval HAL status
3842 */
3843 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
3844 uint32_t Timeout, uint32_t Tickstart)
3845 {
3846 while ((hspi->Instance->SR & Fifo) != State)
3847 {
3848 if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
3849 {
3850 /* Read 8bit CRC to flush Data Register */
3851 READ_REG(*((__IO uint8_t *)&hspi->Instance->DR));
3852 }
3853
3854 if (Timeout != HAL_MAX_DELAY)
3855 {
3856 if (((HAL_GetTick() - Tickstart) >= Timeout) || (Timeout == 0U))
3857 {
3858 /* Disable the SPI and reset the CRC: the CRC value should be cleared
3859 on both master and slave sides in order to resynchronize the master
3860 and slave for their respective CRC calculation */
3861
3862 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3863 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3864
3865 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3866 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3867 {
3868 /* Disable SPI peripheral */
3869 __HAL_SPI_DISABLE(hspi);
3870 }
3871
3872 /* Reset CRC Calculation */
3873 if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3874 {
3875 SPI_RESET_CRC(hspi);
3876 }
3877
3878 hspi->State = HAL_SPI_STATE_READY;
3879
3880 /* Process Unlocked */
3881 __HAL_UNLOCK(hspi);
3882
3883 return HAL_TIMEOUT;
3884 }
3885 }
3886 }
3887
3888 return HAL_OK;
3889 }
3890
3891 /**
3892 * @brief Handle the check of the RX transaction complete.
3893 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3894 * the configuration information for SPI module.
3895 * @param Timeout Timeout duration
3896 * @param Tickstart tick start value
3897 * @retval HAL status
3898 */
3899 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3900 {
3901 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3902 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3903 {
3904 /* Disable SPI peripheral */
3905 __HAL_SPI_DISABLE(hspi);
3906 }
3907
3908 /* Control the BSY flag */
3909 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3910 {
3911 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3912 return HAL_TIMEOUT;
3913 }
3914
3915 if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3916 || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3917 {
3918 /* Empty the FRLVL fifo */
3919 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3920 {
3921 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3922 return HAL_TIMEOUT;
3923 }
3924 }
3925 return HAL_OK;
3926 }
3927
3928 /**
3929 * @brief Handle the check of the RXTX or TX transaction complete.
3930 * @param hspi SPI handle
3931 * @param Timeout Timeout duration
3932 * @param Tickstart tick start value
3933 * @retval HAL status
3934 */
3935 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3936 {
3937 /* Control if the TX fifo is empty */
3938 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3939 {
3940 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3941 return HAL_TIMEOUT;
3942 }
3943
3944 /* Control the BSY flag */
3945 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3946 {
3947 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3948 return HAL_TIMEOUT;
3949 }
3950
3951 /* Control if the RX fifo is empty */
3952 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK)
3953 {
3954 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3955 return HAL_TIMEOUT;
3956 }
3957
3958 return HAL_OK;
3959 }
3960
3961 /**
3962 * @brief Handle the end of the RXTX transaction.
3963 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
3964 * the configuration information for SPI module.
3965 * @retval None
3966 */
3967 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3968 {
3969 uint32_t tickstart;
3970
3971 /* Init tickstart for timeout managment*/
3972 tickstart = HAL_GetTick();
3973
3974 /* Disable ERR interrupt */
3975 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3976
3977 /* Check the end of the transaction */
3978 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3979 {
3980 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3981 }
3982
3983 #if (USE_SPI_CRC != 0U)
3984 /* Check if CRC error occurred */
3985 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3986 {
3987 hspi->State = HAL_SPI_STATE_READY;
3988 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3989 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3990 /* Call user error callback */
3991 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3992 hspi->ErrorCallback(hspi);
3993 #else
3994 HAL_SPI_ErrorCallback(hspi);
3995 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3996 }
3997 else
3998 {
3999 #endif /* USE_SPI_CRC */
4000 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4001 {
4002 if (hspi->State == HAL_SPI_STATE_BUSY_RX)
4003 {
4004 hspi->State = HAL_SPI_STATE_READY;
4005 /* Call user Rx complete callback */
4006 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4007 hspi->RxCpltCallback(hspi);
4008 #else
4009 HAL_SPI_RxCpltCallback(hspi);
4010 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4011 }
4012 else
4013 {
4014 hspi->State = HAL_SPI_STATE_READY;
4015 /* Call user TxRx complete callback */
4016 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4017 hspi->TxRxCpltCallback(hspi);
4018 #else
4019 HAL_SPI_TxRxCpltCallback(hspi);
4020 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4021 }
4022 }
4023 else
4024 {
4025 hspi->State = HAL_SPI_STATE_READY;
4026 /* Call user error callback */
4027 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4028 hspi->ErrorCallback(hspi);
4029 #else
4030 HAL_SPI_ErrorCallback(hspi);
4031 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4032 }
4033 #if (USE_SPI_CRC != 0U)
4034 }
4035 #endif /* USE_SPI_CRC */
4036 }
4037
4038 /**
4039 * @brief Handle the end of the RX transaction.
4040 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4041 * the configuration information for SPI module.
4042 * @retval None
4043 */
4044 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
4045 {
4046 /* Disable RXNE and ERR interrupt */
4047 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
4048
4049 /* Check the end of the transaction */
4050 if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4051 {
4052 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4053 }
4054 hspi->State = HAL_SPI_STATE_READY;
4055
4056 #if (USE_SPI_CRC != 0U)
4057 /* Check if CRC error occurred */
4058 if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
4059 {
4060 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
4061 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
4062 /* Call user error callback */
4063 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4064 hspi->ErrorCallback(hspi);
4065 #else
4066 HAL_SPI_ErrorCallback(hspi);
4067 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4068 }
4069 else
4070 {
4071 #endif /* USE_SPI_CRC */
4072 if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
4073 {
4074 /* Call user Rx complete callback */
4075 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4076 hspi->RxCpltCallback(hspi);
4077 #else
4078 HAL_SPI_RxCpltCallback(hspi);
4079 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4080 }
4081 else
4082 {
4083 /* Call user error callback */
4084 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4085 hspi->ErrorCallback(hspi);
4086 #else
4087 HAL_SPI_ErrorCallback(hspi);
4088 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4089 }
4090 #if (USE_SPI_CRC != 0U)
4091 }
4092 #endif /* USE_SPI_CRC */
4093 }
4094
4095 /**
4096 * @brief Handle the end of the TX transaction.
4097 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4098 * the configuration information for SPI module.
4099 * @retval None
4100 */
4101 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
4102 {
4103 uint32_t tickstart;
4104
4105 /* Init tickstart for timeout management*/
4106 tickstart = HAL_GetTick();
4107
4108 /* Disable TXE and ERR interrupt */
4109 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
4110
4111 /* Check the end of the transaction */
4112 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
4113 {
4114 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
4115 }
4116
4117 /* Clear overrun flag in 2 Lines communication mode because received is not read */
4118 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
4119 {
4120 __HAL_SPI_CLEAR_OVRFLAG(hspi);
4121 }
4122
4123 hspi->State = HAL_SPI_STATE_READY;
4124 if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
4125 {
4126 /* Call user error callback */
4127 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4128 hspi->ErrorCallback(hspi);
4129 #else
4130 HAL_SPI_ErrorCallback(hspi);
4131 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4132 }
4133 else
4134 {
4135 /* Call user Rx complete callback */
4136 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
4137 hspi->TxCpltCallback(hspi);
4138 #else
4139 HAL_SPI_TxCpltCallback(hspi);
4140 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
4141 }
4142 }
4143
4144 /**
4145 * @brief Handle abort a Rx transaction.
4146 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4147 * the configuration information for SPI module.
4148 * @retval None
4149 */
4150 static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
4151 {
4152 __IO uint32_t count;
4153
4154 /* Disable SPI Peripheral */
4155 __HAL_SPI_DISABLE(hspi);
4156
4157 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4158
4159 /* Disable RXNEIE interrupt */
4160 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4161
4162 /* Check RXNEIE is disabled */
4163 do
4164 {
4165 if (count == 0U)
4166 {
4167 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4168 break;
4169 }
4170 count--;
4171 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4172
4173 /* Control the BSY flag */
4174 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4175 {
4176 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4177 }
4178
4179 /* Empty the FRLVL fifo */
4180 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4181 {
4182 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4183 }
4184
4185 hspi->State = HAL_SPI_STATE_ABORT;
4186 }
4187
4188 /**
4189 * @brief Handle abort a Tx or Rx/Tx transaction.
4190 * @param hspi pointer to a SPI_HandleTypeDef structure that contains
4191 * the configuration information for SPI module.
4192 * @retval None
4193 */
4194 static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
4195 {
4196 __IO uint32_t count;
4197
4198 count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
4199
4200 /* Disable TXEIE interrupt */
4201 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
4202
4203 /* Check TXEIE is disabled */
4204 do
4205 {
4206 if (count == 0U)
4207 {
4208 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4209 break;
4210 }
4211 count--;
4212 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
4213
4214 if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4215 {
4216 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4217 }
4218
4219 /* Disable SPI Peripheral */
4220 __HAL_SPI_DISABLE(hspi);
4221
4222 /* Empty the FRLVL fifo */
4223 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4224 {
4225 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4226 }
4227
4228 /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */
4229 if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
4230 {
4231 /* Disable RXNEIE interrupt */
4232 CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE));
4233
4234 /* Check RXNEIE is disabled */
4235 do
4236 {
4237 if (count == 0U)
4238 {
4239 SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
4240 break;
4241 }
4242 count--;
4243 } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
4244
4245 /* Control the BSY flag */
4246 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4247 {
4248 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4249 }
4250
4251 /* Empty the FRLVL fifo */
4252 if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
4253 {
4254 hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
4255 }
4256 }
4257 hspi->State = HAL_SPI_STATE_ABORT;
4258 }
4259
4260 /**
4261 * @}
4262 */
4263
4264 #endif /* HAL_SPI_MODULE_ENABLED */
4265
4266 /**
4267 * @}
4268 */
4269
4270 /**
4271 * @}
4272 */
4273
4274 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/