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Merge pull request #11189 from klutvott123/move-telemetry-displayport-init
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Src / stm32g4xx_ll_adc.c
blob0dc7b51b8cb1661ada8c64c04c56d73d02c8660c
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19 #if defined(USE_FULL_LL_DRIVER)
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32g4xx_ll_adc.h"
23 #include "stm32g4xx_ll_bus.h"
24
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif
30
31 /** @addtogroup STM32G4xx_LL_Driver
32 * @{
33 */
34
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
36
37 /** @addtogroup ADC_LL ADC
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @addtogroup ADC_LL_Private_Constants
45 * @{
46 */
47
48 /* Definitions of ADC hardware constraints delays */
49 /* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
50 /* not timeout values: */
51 /* Timeout values for ADC operations are dependent to device clock */
52 /* configuration (system clock versus ADC clock), */
53 /* and therefore must be defined in user application. */
54 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
55 /* values definition. */
56 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
57 /* of device clock setting. */
58 /* In user application, ADC timeout values should be defined with */
59 /* temporal values, in function of device clock settings. */
60 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
61 /* - ADC clock from synchronous clock with AHB prescaler 512, */
62 /* ADC prescaler 4. */
63 /* Ratio max = 512 *4 = 2048 */
64 /* - ADC clock from asynchronous clock (PLLP) with prescaler 256. */
65 /* Highest CPU clock PLL (PLLR). */
66 /* Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256 */
67 /* = 3968 */
68 /* Unit: CPU cycles. */
69 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST (3968UL)
70 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
71 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
72
73 /**
74 * @}
75 */
76
77 /* Private macros ------------------------------------------------------------*/
78
79 /** @addtogroup ADC_LL_Private_Macros
80 * @{
81 */
82
83 /* Check of parameters for configuration of ADC hierarchical scope: */
84 /* common to several ADC instances. */
85 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
86 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
87 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
88 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
89 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
90 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \
91 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \
92 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6) \
93 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8) \
94 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10) \
95 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12) \
96 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16) \
97 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32) \
98 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64) \
99 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128) \
100 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256) \
101 )
102
103 /* Check of parameters for configuration of ADC hierarchical scope: */
104 /* ADC instance. */
105 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
106 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
107 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
108 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
109 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
110 )
111
112 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
113 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
114 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
115 )
116
117 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
118 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
119 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
120 )
121
122 /* Check of parameters for configuration of ADC hierarchical scope: */
123 /* ADC group regular */
124 #if defined(STM32G474xx) || defined(STM32G484xx)
125 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
126 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
127 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
128 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
129 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
130 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
131 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
132 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
133 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
134 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
135 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
136 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
137 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
138 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \
139 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \
140 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \
141 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
150 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
151 && ( \
152 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \
159 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
160 ) \
161 ) \
162 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
163 && ( \
164 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
165 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
170 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) \
171 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) \
172 ) \
173 ) \
174 )
175 #elif defined(STM32G473xx)
176 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
177 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
182 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
183 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
184 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
185 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
186 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
187 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
188 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
189 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO) \
190 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) \
191 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1) \
192 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
193 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
194 && ( \
195 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
196 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
197 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
198 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
199 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
200 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2) \
201 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3) \
202 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
203 ) \
204 ) \
205 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
206 && ( \
207 ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1) \
208 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
209 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
210 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1) \
211 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
212 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2) \
213 ) \
214 ) \
215 )
216 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
217 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
218 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
219 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
220 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
221 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
222 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
223 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
224 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
225 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
226 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
227 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
228 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
229 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
230 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
231 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO) \
232 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
233 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
234 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
235 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT) \
236 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
237 )
238 #endif
239
240 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
241 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
242 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
243 )
244
245 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
246 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
247 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
248 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
249 )
250
251 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
252 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
253 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
254 )
255
256 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
257 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
258 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
259 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
260 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
261 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
262 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
263 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
264 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
265 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
266 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
267 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
268 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
269 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
270 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
271 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
272 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
273 )
274
275 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
276 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
277 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
278 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
279 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
280 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
281 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
282 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
283 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
284 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
285 )
286
287 /* Check of parameters for configuration of ADC hierarchical scope: */
288 /* ADC group injected */
289 #if defined(STM32G474xx) || defined(STM32G484xx)
290 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
291 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
292 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
293 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
294 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
295 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
296 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
297 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
298 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
299 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
300 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
301 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
302 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
303 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
304 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \
305 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \
306 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
307 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
308 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) \
309 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) \
310 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) \
311 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) \
312 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) \
313 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) \
314 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
315 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
316 && ( \
317 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
318 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
319 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
320 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
321 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
322 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \
323 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
324 ) \
325 ) \
326 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
327 && ( \
328 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
329 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
330 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
331 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
332 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
333 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) \
334 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) \
335 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
336 ) \
337 ) \
338 )
339 #elif defined(STM32G473xx)
340 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
341 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
342 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
343 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
344 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
345 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
346 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
347 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
348 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
349 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
350 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
351 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
352 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
353 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
354 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) \
355 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) \
356 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
357 || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
358 && ( \
359 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
360 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
361 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
362 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
363 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
364 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4) \
365 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
366 ) \
367 ) \
368 || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
369 && ( \
370 ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3) \
371 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
372 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4) \
373 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
374 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
375 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) \
376 ) \
377 ) \
378 )
379 #elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
380 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
381 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
382 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
383 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
384 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
385 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
386 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
387 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
388 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
389 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
390 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
391 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
392 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
393 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \
394 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
395 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
396 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
397 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
398 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1) \
399 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) \
400 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
401 )
402 #endif
403
404 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
405 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
406 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
407 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
408 )
409
410 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
411 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
412 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
413 )
414
415 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
416 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
417 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
418 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
419 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
420 )
421
422 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
423 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
424 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
425 )
426
427 #if defined(ADC_MULTIMODE_SUPPORT)
428 /* Check of parameters for configuration of ADC hierarchical scope: */
429 /* multimode. */
430 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
431 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
432 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
433 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
434 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
435 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
436 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
437 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
438 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
439 )
440
441 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
442 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
443 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
444 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
445 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
446 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
447 )
448
449 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
450 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
451 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
452 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
453 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
454 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
455 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
456 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
457 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
458 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
459 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
460 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
461 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
462 )
463
464 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
465 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
466 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
467 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
468 )
469
470 #endif /* ADC_MULTIMODE_SUPPORT */
471 /**
472 * @}
473 */
474
475
476 /* Private function prototypes -----------------------------------------------*/
477
478 /* Exported functions --------------------------------------------------------*/
479 /** @addtogroup ADC_LL_Exported_Functions
480 * @{
481 */
482
483 /** @addtogroup ADC_LL_EF_Init
484 * @{
485 */
486
487 /**
488 * @brief De-initialize registers of all ADC instances belonging to
489 * the same ADC common instance to their default reset values.
490 * @note This function is performing a hard reset, using high level
491 * clock source RCC ADC reset.
492 * Caution: On this STM32 serie, if several ADC instances are available
493 * on the selected device, RCC ADC reset will reset
494 * all ADC instances belonging to the common ADC instance.
495 * To de-initialize only 1 ADC instance, use
496 * function @ref LL_ADC_DeInit().
497 * @param ADCxy_COMMON ADC common instance
498 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
499 * @retval An ErrorStatus enumeration value:
500 * - SUCCESS: ADC common registers are de-initialized
501 * - ERROR: not applicable
502 */
503 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
504 {
505 /* Check the parameters */
506 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
507
508 if (ADCxy_COMMON == ADC12_COMMON)
509 {
510 /* Force reset of ADC clock (core clock) */
511 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
512
513 /* Release reset of ADC clock (core clock) */
514 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
515 }
516 #if defined(ADC345_COMMON)
517 else
518 {
519 /* Force reset of ADC clock (core clock) */
520 LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
521
522 /* Release reset of ADC clock (core clock) */
523 LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
524 }
525 #endif
526
527 return SUCCESS;
528 }
529
530 /**
531 * @brief Initialize some features of ADC common parameters
532 * (all ADC instances belonging to the same ADC common instance)
533 * and multimode (for devices with several ADC instances available).
534 * @note The setting of ADC common parameters is conditioned to
535 * ADC instances state:
536 * All ADC instances belonging to the same ADC common instance
537 * must be disabled.
538 * @param ADCxy_COMMON ADC common instance
539 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
540 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
541 * @retval An ErrorStatus enumeration value:
542 * - SUCCESS: ADC common registers are initialized
543 * - ERROR: ADC common registers are not initialized
544 */
545 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
546 {
547 ErrorStatus status = SUCCESS;
548
549 /* Check the parameters */
550 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
551 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
552
553 #if defined(ADC_MULTIMODE_SUPPORT)
554 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
555 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
556 {
557 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
558 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
559 }
560 #endif /* ADC_MULTIMODE_SUPPORT */
561
562 /* Note: Hardware constraint (refer to description of functions */
563 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
564 /* On this STM32 serie, setting of these features is conditioned to */
565 /* ADC state: */
566 /* All ADC instances of the ADC common group must be disabled. */
567 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
568 {
569 /* Configuration of ADC hierarchical scope: */
570 /* - common to several ADC */
571 /* (all ADC instances belonging to the same ADC common instance) */
572 /* - Set ADC clock (conversion clock) */
573 /* - multimode (if several ADC instances available on the */
574 /* selected device) */
575 /* - Set ADC multimode configuration */
576 /* - Set ADC multimode DMA transfer */
577 /* - Set ADC multimode: delay between 2 sampling phases */
578 #if defined(ADC_MULTIMODE_SUPPORT)
579 if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
580 {
581 MODIFY_REG(ADCxy_COMMON->CCR,
582 ADC_CCR_CKMODE
583 | ADC_CCR_PRESC
584 | ADC_CCR_DUAL
585 | ADC_CCR_MDMA
586 | ADC_CCR_DELAY
587 ,
588 ADC_CommonInitStruct->CommonClock
589 | ADC_CommonInitStruct->Multimode
590 | ADC_CommonInitStruct->MultiDMATransfer
591 | ADC_CommonInitStruct->MultiTwoSamplingDelay
592 );
593 }
594 else
595 {
596 MODIFY_REG(ADCxy_COMMON->CCR,
597 ADC_CCR_CKMODE
598 | ADC_CCR_PRESC
599 | ADC_CCR_DUAL
600 | ADC_CCR_MDMA
601 | ADC_CCR_DELAY
602 ,
603 ADC_CommonInitStruct->CommonClock
604 | LL_ADC_MULTI_INDEPENDENT
605 );
606 }
607 #else
608 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
609 #endif
610 }
611 else
612 {
613 /* Initialization error: One or several ADC instances belonging to */
614 /* the same ADC common instance are not disabled. */
615 status = ERROR;
616 }
617
618 return status;
619 }
620
621 /**
622 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
623 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
624 * whose fields will be set to default values.
625 * @retval None
626 */
627 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
628 {
629 /* Set ADC_CommonInitStruct fields to default values */
630 /* Set fields of ADC common */
631 /* (all ADC instances belonging to the same ADC common instance) */
632 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
633
634 #if defined(ADC_MULTIMODE_SUPPORT)
635 /* Set fields of ADC multimode */
636 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
637 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
638 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
639 #endif /* ADC_MULTIMODE_SUPPORT */
640 }
641
642 /**
643 * @brief De-initialize registers of the selected ADC instance
644 * to their default reset values.
645 * @note To reset all ADC instances quickly (perform a hard reset),
646 * use function @ref LL_ADC_CommonDeInit().
647 * @note If this functions returns error status, it means that ADC instance
648 * is in an unknown state.
649 * In this case, perform a hard reset using high level
650 * clock source RCC ADC reset.
651 * Caution: On this STM32 serie, if several ADC instances are available
652 * on the selected device, RCC ADC reset will reset
653 * all ADC instances belonging to the common ADC instance.
654 * Refer to function @ref LL_ADC_CommonDeInit().
655 * @param ADCx ADC instance
656 * @retval An ErrorStatus enumeration value:
657 * - SUCCESS: ADC registers are de-initialized
658 * - ERROR: ADC registers are not de-initialized
659 */
660 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
661 {
662 ErrorStatus status = SUCCESS;
663
664 __IO uint32_t timeout_cpu_cycles = 0UL;
665
666 /* Check the parameters */
667 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
668
669 /* Disable ADC instance if not already disabled. */
670 if (LL_ADC_IsEnabled(ADCx) == 1UL)
671 {
672 /* Set ADC group regular trigger source to SW start to ensure to not */
673 /* have an external trigger event occurring during the conversion stop */
674 /* ADC disable process. */
675 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
676
677 /* Stop potential ADC conversion on going on ADC group regular. */
678 if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
679 {
680 if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
681 {
682 LL_ADC_REG_StopConversion(ADCx);
683 }
684 }
685
686 /* Set ADC group injected trigger source to SW start to ensure to not */
687 /* have an external trigger event occurring during the conversion stop */
688 /* ADC disable process. */
689 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
690
691 /* Stop potential ADC conversion on going on ADC group injected. */
692 if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
693 {
694 if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
695 {
696 LL_ADC_INJ_StopConversion(ADCx);
697 }
698 }
699
700 /* Wait for ADC conversions are effectively stopped */
701 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
702 while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
703 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
704 {
705 timeout_cpu_cycles--;
706 if (timeout_cpu_cycles == 0UL)
707 {
708 /* Time-out error */
709 status = ERROR;
710 break;
711 }
712 }
713
714 /* Flush group injected contexts queue (register JSQR): */
715 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
716 /* contexts queue is maintained with the last active context). */
717 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
718
719 /* Disable the ADC instance */
720 LL_ADC_Disable(ADCx);
721
722 /* Wait for ADC instance is effectively disabled */
723 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
724 while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
725 {
726 timeout_cpu_cycles--;
727 if (timeout_cpu_cycles == 0UL)
728 {
729 /* Time-out error */
730 status = ERROR;
731 break;
732 }
733 }
734 }
735
736 /* Check whether ADC state is compliant with expected state */
737 if (READ_BIT(ADCx->CR,
738 (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
739 | ADC_CR_ADDIS | ADC_CR_ADEN)
740 )
741 == 0UL)
742 {
743 /* ========== Reset ADC registers ========== */
744 /* Reset register IER */
745 CLEAR_BIT(ADCx->IER,
746 (LL_ADC_IT_ADRDY
747 | LL_ADC_IT_EOC
748 | LL_ADC_IT_EOS
749 | LL_ADC_IT_OVR
750 | LL_ADC_IT_EOSMP
751 | LL_ADC_IT_JEOC
752 | LL_ADC_IT_JEOS
753 | LL_ADC_IT_JQOVF
754 | LL_ADC_IT_AWD1
755 | LL_ADC_IT_AWD2
756 | LL_ADC_IT_AWD3
757 )
758 );
759
760 /* Reset register ISR */
761 SET_BIT(ADCx->ISR,
762 (LL_ADC_FLAG_ADRDY
763 | LL_ADC_FLAG_EOC
764 | LL_ADC_FLAG_EOS
765 | LL_ADC_FLAG_OVR
766 | LL_ADC_FLAG_EOSMP
767 | LL_ADC_FLAG_JEOC
768 | LL_ADC_FLAG_JEOS
769 | LL_ADC_FLAG_JQOVF
770 | LL_ADC_FLAG_AWD1
771 | LL_ADC_FLAG_AWD2
772 | LL_ADC_FLAG_AWD3
773 )
774 );
775
776 /* Reset register CR */
777 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
778 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
779 /* access mode "read-set": no direct reset applicable. */
780 /* - Reset Calibration mode to default setting (single ended). */
781 /* - Disable ADC internal voltage regulator. */
782 /* - Enable ADC deep power down. */
783 /* Note: ADC internal voltage regulator disable and ADC deep power */
784 /* down enable are conditioned to ADC state disabled: */
785 /* already done above. */
786 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
787 SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
788
789 /* Reset register CFGR */
790 MODIFY_REG(ADCx->CFGR,
791 (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
792 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
793 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
794 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
795 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
796 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN),
797 ADC_CFGR_JQDIS
798 );
799
800 /* Reset register CFGR2 */
801 CLEAR_BIT(ADCx->CFGR2,
802 (ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
803 | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
804 | ADC_CFGR2_GCOMP
805 | ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
806 );
807
808 /* Reset register SMPR1 */
809 CLEAR_BIT(ADCx->SMPR1,
810 (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
811 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
812 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
813 );
814
815 /* Reset register SMPR2 */
816 CLEAR_BIT(ADCx->SMPR2,
817 (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
818 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
819 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
820 );
821
822 /* Reset register TR1 */
823 MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
824
825 /* Reset register TR2 */
826 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
827
828 /* Reset register TR3 */
829 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
830
831 /* Reset register SQR1 */
832 CLEAR_BIT(ADCx->SQR1,
833 (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
834 | ADC_SQR1_SQ1 | ADC_SQR1_L)
835 );
836
837 /* Reset register SQR2 */
838 CLEAR_BIT(ADCx->SQR2,
839 (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
840 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
841 );
842
843 /* Reset register SQR3 */
844 CLEAR_BIT(ADCx->SQR3,
845 (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
846 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
847 );
848
849 /* Reset register SQR4 */
850 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
851
852 /* Reset register JSQR */
853 CLEAR_BIT(ADCx->JSQR,
854 (ADC_JSQR_JL
855 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
856 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
857 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1)
858 );
859
860 /* Reset register DR */
861 /* Note: bits in access mode read only, no direct reset applicable */
862
863 /* Reset register OFR1 */
864 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
865 /* Reset register OFR2 */
866 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
867 /* Reset register OFR3 */
868 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
869 /* Reset register OFR4 */
870 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
871
872 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
873 /* Note: bits in access mode read only, no direct reset applicable */
874
875 /* Reset register AWD2CR */
876 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
877
878 /* Reset register AWD3CR */
879 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
880
881 /* Reset register DIFSEL */
882 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
883
884 /* Reset register CALFACT */
885 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
886
887 /* Reset register GCOMP */
888 CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
889 }
890 else
891 {
892 /* ADC instance is in an unknown state */
893 /* Need to performing a hard reset of ADC instance, using high level */
894 /* clock source RCC ADC reset. */
895 /* Caution: On this STM32 serie, if several ADC instances are available */
896 /* on the selected device, RCC ADC reset will reset */
897 /* all ADC instances belonging to the common ADC instance. */
898 /* Caution: On this STM32 serie, if several ADC instances are available */
899 /* on the selected device, RCC ADC reset will reset */
900 /* all ADC instances belonging to the common ADC instance. */
901 status = ERROR;
902 }
903
904 return status;
905 }
906
907 /**
908 * @brief Initialize some features of ADC instance.
909 * @note These parameters have an impact on ADC scope: ADC instance.
910 * Affects both group regular and group injected (availability
911 * of ADC group injected depends on STM32 families).
912 * Refer to corresponding unitary functions into
913 * @ref ADC_LL_EF_Configuration_ADC_Instance .
914 * @note The setting of these parameters by function @ref LL_ADC_Init()
915 * is conditioned to ADC state:
916 * ADC instance must be disabled.
917 * This condition is applied to all ADC features, for efficiency
918 * and compatibility over all STM32 families. However, the different
919 * features can be set under different ADC state conditions
920 * (setting possible with ADC enabled without conversion on going,
921 * ADC enabled with conversion on going, ...)
922 * Each feature can be updated afterwards with a unitary function
923 * and potentially with ADC in a different state than disabled,
924 * refer to description of each function for setting
925 * conditioned to ADC state.
926 * @note After using this function, some other features must be configured
927 * using LL unitary functions.
928 * The minimum configuration remaining to be done is:
929 * - Set ADC group regular or group injected sequencer:
930 * map channel on the selected sequencer rank.
931 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
932 * - Set ADC channel sampling time
933 * Refer to function LL_ADC_SetChannelSamplingTime();
934 * @param ADCx ADC instance
935 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
936 * @retval An ErrorStatus enumeration value:
937 * - SUCCESS: ADC registers are initialized
938 * - ERROR: ADC registers are not initialized
939 */
940 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
941 {
942 ErrorStatus status = SUCCESS;
943
944 /* Check the parameters */
945 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
946
947 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
948 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
949 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
950
951 /* Note: Hardware constraint (refer to description of this function): */
952 /* ADC instance must be disabled. */
953 if (LL_ADC_IsEnabled(ADCx) == 0UL)
954 {
955 /* Configuration of ADC hierarchical scope: */
956 /* - ADC instance */
957 /* - Set ADC data resolution */
958 /* - Set ADC conversion data alignment */
959 /* - Set ADC low power mode */
960 MODIFY_REG(ADCx->CFGR,
961 ADC_CFGR_RES
962 | ADC_CFGR_ALIGN
963 | ADC_CFGR_AUTDLY
964 ,
965 ADC_InitStruct->Resolution
966 | ADC_InitStruct->DataAlignment
967 | ADC_InitStruct->LowPowerMode
968 );
969
970 }
971 else
972 {
973 /* Initialization error: ADC instance is not disabled. */
974 status = ERROR;
975 }
976 return status;
977 }
978
979 /**
980 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
981 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
982 * whose fields will be set to default values.
983 * @retval None
984 */
985 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
986 {
987 /* Set ADC_InitStruct fields to default values */
988 /* Set fields of ADC instance */
989 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
990 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
991 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
992
993 }
994
995 /**
996 * @brief Initialize some features of ADC group regular.
997 * @note These parameters have an impact on ADC scope: ADC group regular.
998 * Refer to corresponding unitary functions into
999 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1000 * (functions with prefix "REG").
1001 * @note The setting of these parameters by function @ref LL_ADC_Init()
1002 * is conditioned to ADC state:
1003 * ADC instance must be disabled.
1004 * This condition is applied to all ADC features, for efficiency
1005 * and compatibility over all STM32 families. However, the different
1006 * features can be set under different ADC state conditions
1007 * (setting possible with ADC enabled without conversion on going,
1008 * ADC enabled with conversion on going, ...)
1009 * Each feature can be updated afterwards with a unitary function
1010 * and potentially with ADC in a different state than disabled,
1011 * refer to description of each function for setting
1012 * conditioned to ADC state.
1013 * @note After using this function, other features must be configured
1014 * using LL unitary functions.
1015 * The minimum configuration remaining to be done is:
1016 * - Set ADC group regular or group injected sequencer:
1017 * map channel on the selected sequencer rank.
1018 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1019 * - Set ADC channel sampling time
1020 * Refer to function LL_ADC_SetChannelSamplingTime();
1021 * @param ADCx ADC instance
1022 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1023 * @retval An ErrorStatus enumeration value:
1024 * - SUCCESS: ADC registers are initialized
1025 * - ERROR: ADC registers are not initialized
1026 */
1027 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1028 {
1029 ErrorStatus status = SUCCESS;
1030
1031 /* Check the parameters */
1032 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1033 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
1034 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1035 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1036 {
1037 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1038 }
1039 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1040 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1041 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
1042
1043 /* Note: Hardware constraint (refer to description of this function): */
1044 /* ADC instance must be disabled. */
1045 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1046 {
1047 /* Configuration of ADC hierarchical scope: */
1048 /* - ADC group regular */
1049 /* - Set ADC group regular trigger source */
1050 /* - Set ADC group regular sequencer length */
1051 /* - Set ADC group regular sequencer discontinuous mode */
1052 /* - Set ADC group regular continuous mode */
1053 /* - Set ADC group regular conversion data transfer: no transfer or */
1054 /* transfer by DMA, and DMA requests mode */
1055 /* - Set ADC group regular overrun behavior */
1056 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1057 /* setting of trigger source to SW start. */
1058 if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1059 {
1060 MODIFY_REG(ADCx->CFGR,
1061 ADC_CFGR_EXTSEL
1062 | ADC_CFGR_EXTEN
1063 | ADC_CFGR_DISCEN
1064 | ADC_CFGR_DISCNUM
1065 | ADC_CFGR_CONT
1066 | ADC_CFGR_DMAEN
1067 | ADC_CFGR_DMACFG
1068 | ADC_CFGR_OVRMOD
1069 ,
1070 ADC_REG_InitStruct->TriggerSource
1071 | ADC_REG_InitStruct->SequencerDiscont
1072 | ADC_REG_InitStruct->ContinuousMode
1073 | ADC_REG_InitStruct->DMATransfer
1074 | ADC_REG_InitStruct->Overrun
1075 );
1076 }
1077 else
1078 {
1079 MODIFY_REG(ADCx->CFGR,
1080 ADC_CFGR_EXTSEL
1081 | ADC_CFGR_EXTEN
1082 | ADC_CFGR_DISCEN
1083 | ADC_CFGR_DISCNUM
1084 | ADC_CFGR_CONT
1085 | ADC_CFGR_DMAEN
1086 | ADC_CFGR_DMACFG
1087 | ADC_CFGR_OVRMOD
1088 ,
1089 ADC_REG_InitStruct->TriggerSource
1090 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1091 | ADC_REG_InitStruct->ContinuousMode
1092 | ADC_REG_InitStruct->DMATransfer
1093 | ADC_REG_InitStruct->Overrun
1094 );
1095 }
1096
1097 /* Set ADC group regular sequencer length and scan direction */
1098 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1099 }
1100 else
1101 {
1102 /* Initialization error: ADC instance is not disabled. */
1103 status = ERROR;
1104 }
1105 return status;
1106 }
1107
1108 /**
1109 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1110 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1111 * whose fields will be set to default values.
1112 * @retval None
1113 */
1114 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1115 {
1116 /* Set ADC_REG_InitStruct fields to default values */
1117 /* Set fields of ADC group regular */
1118 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1119 /* setting of trigger source to SW start. */
1120 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1121 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1122 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1123 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1124 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1125 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1126 }
1127
1128 /**
1129 * @brief Initialize some features of ADC group injected.
1130 * @note These parameters have an impact on ADC scope: ADC group injected.
1131 * Refer to corresponding unitary functions into
1132 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1133 * (functions with prefix "INJ").
1134 * @note The setting of these parameters by function @ref LL_ADC_Init()
1135 * is conditioned to ADC state:
1136 * ADC instance must be disabled.
1137 * This condition is applied to all ADC features, for efficiency
1138 * and compatibility over all STM32 families. However, the different
1139 * features can be set under different ADC state conditions
1140 * (setting possible with ADC enabled without conversion on going,
1141 * ADC enabled with conversion on going, ...)
1142 * Each feature can be updated afterwards with a unitary function
1143 * and potentially with ADC in a different state than disabled,
1144 * refer to description of each function for setting
1145 * conditioned to ADC state.
1146 * @note After using this function, other features must be configured
1147 * using LL unitary functions.
1148 * The minimum configuration remaining to be done is:
1149 * - Set ADC group injected sequencer:
1150 * map channel on the selected sequencer rank.
1151 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1152 * - Set ADC channel sampling time
1153 * Refer to function LL_ADC_SetChannelSamplingTime();
1154 * @param ADCx ADC instance
1155 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1156 * @retval An ErrorStatus enumeration value:
1157 * - SUCCESS: ADC registers are initialized
1158 * - ERROR: ADC registers are not initialized
1159 */
1160 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1161 {
1162 ErrorStatus status = SUCCESS;
1163
1164 /* Check the parameters */
1165 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1166 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
1167 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1168 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1169 {
1170 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1171 }
1172 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1173
1174 /* Note: Hardware constraint (refer to description of this function): */
1175 /* ADC instance must be disabled. */
1176 if (LL_ADC_IsEnabled(ADCx) == 0UL)
1177 {
1178 /* Configuration of ADC hierarchical scope: */
1179 /* - ADC group injected */
1180 /* - Set ADC group injected trigger source */
1181 /* - Set ADC group injected sequencer length */
1182 /* - Set ADC group injected sequencer discontinuous mode */
1183 /* - Set ADC group injected conversion trigger: independent or */
1184 /* from ADC group regular */
1185 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1186 /* setting of trigger source to SW start. */
1187 if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1188 {
1189 MODIFY_REG(ADCx->CFGR,
1190 ADC_CFGR_JDISCEN
1191 | ADC_CFGR_JAUTO
1192 ,
1193 ADC_INJ_InitStruct->SequencerDiscont
1194 | ADC_INJ_InitStruct->TrigAuto
1195 );
1196 }
1197 else
1198 {
1199 MODIFY_REG(ADCx->CFGR,
1200 ADC_CFGR_JDISCEN
1201 | ADC_CFGR_JAUTO
1202 ,
1203 LL_ADC_REG_SEQ_DISCONT_DISABLE
1204 | ADC_INJ_InitStruct->TrigAuto
1205 );
1206 }
1207
1208 MODIFY_REG(ADCx->JSQR,
1209 ADC_JSQR_JEXTSEL
1210 | ADC_JSQR_JEXTEN
1211 | ADC_JSQR_JL
1212 ,
1213 ADC_INJ_InitStruct->TriggerSource
1214 | ADC_INJ_InitStruct->SequencerLength
1215 );
1216 }
1217 else
1218 {
1219 /* Initialization error: ADC instance is not disabled. */
1220 status = ERROR;
1221 }
1222 return status;
1223 }
1224
1225 /**
1226 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1227 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1228 * whose fields will be set to default values.
1229 * @retval None
1230 */
1231 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1232 {
1233 /* Set ADC_INJ_InitStruct fields to default values */
1234 /* Set fields of ADC group injected */
1235 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1236 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1237 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1238 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1239 }
1240
1241 /**
1242 * @}
1243 */
1244
1245 /**
1246 * @}
1247 */
1248
1249 /**
1250 * @}
1251 */
1252
1253 #endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
1254
1255 /**
1256 * @}
1257 */
1258
1259 #endif /* USE_FULL_LL_DRIVER */
1260
1261 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/