lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_dma.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_dma.c
   4   * @author  MCD Application Team
   5   * @brief   DMA LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 #if defined(USE_FULL_LL_DRIVER)
  21
  22 /* Includes ------------------------------------------------------------------*/
  23 #include "stm32g4xx_ll_dma.h"
  24 #include "stm32g4xx_ll_bus.h"
  25 #ifdef  USE_FULL_ASSERT
  26 #include "stm32_assert.h"
  27 #else
  28 #define assert_param(expr) ((void)0U)
  29 #endif /* USE_FULL_ASSERT */
  30
  31 /** @addtogroup STM32G4xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined (DMA1) || defined (DMA2)
  36
  37 /** @defgroup DMA_LL DMA
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45 /** @addtogroup DMA_LL_Private_Macros
  46   * @{
  47   */
  48 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
  49                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
  50                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
  51
  52 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
  53                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR))
  54
  55 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
  56                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
  57
  58 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
  59                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
  60
  61 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
  62                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
  63                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
  64
  65 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
  66                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
  67                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
  68
  69 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
  70
  71 #define IS_LL_DMA_PERIPHREQUEST(__VALUE__)      ((__VALUE__) <= 115U)
  72
  73 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
  74                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
  75                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
  76                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
  77
  78 #if defined (DMA1_Channel8)
  79 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
  80                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
  81                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
  82                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
  83                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
  84                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
  85                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
  86                                                               ((CHANNEL) == LL_DMA_CHANNEL_7) || \
  87                                                               ((CHANNEL) == LL_DMA_CHANNEL_8))) || \
  88                                                             (((INSTANCE) == DMA2) && \
  89                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
  90                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
  91                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
  92                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
  93                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
  94                                                               ((CHANNEL) == LL_DMA_CHANNEL_6) || \
  95                                                               ((CHANNEL) == LL_DMA_CHANNEL_7) || \
  96                                                               ((CHANNEL) == LL_DMA_CHANNEL_8))))
  97 #elif defined (DMA1_Channel6)
  98 #define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL)  ((((INSTANCE) == DMA1) && \
  99                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 100                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 101                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 102                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 103                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 104                                                               ((CHANNEL) == LL_DMA_CHANNEL_6))) || \
 105                                                             (((INSTANCE) == DMA2) && \
 106                                                              (((CHANNEL) == LL_DMA_CHANNEL_1) || \
 107                                                               ((CHANNEL) == LL_DMA_CHANNEL_2) || \
 108                                                               ((CHANNEL) == LL_DMA_CHANNEL_3) || \
 109                                                               ((CHANNEL) == LL_DMA_CHANNEL_4) || \
 110                                                               ((CHANNEL) == LL_DMA_CHANNEL_5) || \
 111                                                               ((CHANNEL) == LL_DMA_CHANNEL_6))))
 112 #endif /* DMA1_Channel8 */
 113 /**
 114   * @}
 115   */
 116
 117 /* Private function prototypes -----------------------------------------------*/
 118
 119 /* Exported functions --------------------------------------------------------*/
 120 /** @addtogroup DMA_LL_Exported_Functions
 121   * @{
 122   */
 123
 124 /** @addtogroup DMA_LL_EF_Init
 125   * @{
 126   */
 127
 128 /**
 129   * @brief  De-initialize the DMA registers to their default reset values.
 130   * @param  DMAx DMAx Instance
 131   * @param  Channel This parameter can be one of the following values:
 132   *         @arg @ref LL_DMA_CHANNEL_1
 133   *         @arg @ref LL_DMA_CHANNEL_2
 134   *         @arg @ref LL_DMA_CHANNEL_3
 135   *         @arg @ref LL_DMA_CHANNEL_4
 136   *         @arg @ref LL_DMA_CHANNEL_5
 137   *         @arg @ref LL_DMA_CHANNEL_6
 138   *         @arg @ref LL_DMA_CHANNEL_7 (*)
 139   *         @arg @ref LL_DMA_CHANNEL_8 (*)
 140   *         @arg @ref LL_DMA_CHANNEL_ALL
 141   *         (*) Not on all G4 devices
 142   * @retval An ErrorStatus enumeration value:
 143   *          - SUCCESS: DMA registers are de-initialized
 144   *          - ERROR: DMA registers are not de-initialized
 145   */
 146 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
 147 {
 148   DMA_Channel_TypeDef *tmp;
 149   ErrorStatus status = SUCCESS;
 150
 151   /* Check the DMA Instance DMAx and Channel parameters*/
 152   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel) || (Channel == LL_DMA_CHANNEL_ALL));
 153
 154   if (Channel == LL_DMA_CHANNEL_ALL)
 155   {
 156     if (DMAx == DMA1)
 157     {
 158       /* Force reset of DMA clock */
 159       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
 160
 161       /* Release reset of DMA clock */
 162       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
 163     }
 164     else if (DMAx == DMA2)
 165     {
 166       /* Force reset of DMA clock */
 167       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
 168
 169       /* Release reset of DMA clock */
 170       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
 171     }
 172     else
 173     {
 174       status = ERROR;
 175     }
 176   }
 177   else
 178   {
 179     tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
 180
 181     /* Disable the selected DMAx_Channely */
 182     CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
 183
 184     /* Reset DMAx_Channely control register */
 185     WRITE_REG(tmp->CCR, 0U);
 186
 187     /* Reset DMAx_Channely remaining bytes register */
 188     WRITE_REG(tmp->CNDTR, 0U);
 189
 190     /* Reset DMAx_Channely peripheral address register */
 191     WRITE_REG(tmp->CPAR, 0U);
 192
 193     /* Reset DMAx_Channely memory address register */
 194     WRITE_REG(tmp->CMAR, 0U);
 195
 196     /* Reset Request register field for DMAx Channel */
 197     LL_DMA_SetPeriphRequest(DMAx, Channel, LL_DMAMUX_REQ_MEM2MEM);
 198
 199     if (Channel == LL_DMA_CHANNEL_1)
 200     {
 201       /* Reset interrupt pending bits for DMAx Channel1 */
 202       LL_DMA_ClearFlag_GI1(DMAx);
 203     }
 204     else if (Channel == LL_DMA_CHANNEL_2)
 205     {
 206       /* Reset interrupt pending bits for DMAx Channel2 */
 207       LL_DMA_ClearFlag_GI2(DMAx);
 208     }
 209     else if (Channel == LL_DMA_CHANNEL_3)
 210     {
 211       /* Reset interrupt pending bits for DMAx Channel3 */
 212       LL_DMA_ClearFlag_GI3(DMAx);
 213     }
 214     else if (Channel == LL_DMA_CHANNEL_4)
 215     {
 216       /* Reset interrupt pending bits for DMAx Channel4 */
 217       LL_DMA_ClearFlag_GI4(DMAx);
 218     }
 219     else if (Channel == LL_DMA_CHANNEL_5)
 220     {
 221       /* Reset interrupt pending bits for DMAx Channel5 */
 222       LL_DMA_ClearFlag_GI5(DMAx);
 223     }
 224
 225     else if (Channel == LL_DMA_CHANNEL_6)
 226     {
 227       /* Reset interrupt pending bits for DMAx Channel6 */
 228       LL_DMA_ClearFlag_GI6(DMAx);
 229     }
 230 #if defined (DMA1_Channel7)
 231     else if (Channel == LL_DMA_CHANNEL_7)
 232     {
 233       /* Reset interrupt pending bits for DMAx Channel7 */
 234       LL_DMA_ClearFlag_GI7(DMAx);
 235     }
 236 #endif /* DMA1_Channel7 */
 237 #if defined (DMA1_Channel8)
 238     else if (Channel == LL_DMA_CHANNEL_8)
 239     {
 240       /* Reset interrupt pending bits for DMAx Channel8 */
 241       LL_DMA_ClearFlag_GI8(DMAx);
 242     }
 243 #endif /* DMA1_Channel8 */
 244     else
 245     {
 246       status = ERROR;
 247     }
 248   }
 249
 250   return (uint32_t)status;
 251 }
 252
 253 /**
 254   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
 255   * @note   To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
 256   *         @arg @ref __LL_DMA_GET_INSTANCE
 257   *         @arg @ref __LL_DMA_GET_CHANNEL
 258   * @param  DMAx DMAx Instance
 259   * @param  Channel This parameter can be one of the following values:
 260   *         @arg @ref LL_DMA_CHANNEL_1
 261   *         @arg @ref LL_DMA_CHANNEL_2
 262   *         @arg @ref LL_DMA_CHANNEL_3
 263   *         @arg @ref LL_DMA_CHANNEL_4
 264   *         @arg @ref LL_DMA_CHANNEL_5
 265   *         @arg @ref LL_DMA_CHANNEL_6
 266   *         @arg @ref LL_DMA_CHANNEL_7 (*)
 267   *         @arg @ref LL_DMA_CHANNEL_8 (*)
 268   *         (*) Not on all G4 devices
 269   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
 270   * @retval An ErrorStatus enumeration value:
 271   *          - SUCCESS: DMA registers are initialized
 272   *          - ERROR: Not applicable
 273   */
 274 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
 275 {
 276   /* Check the DMA Instance DMAx and Channel parameters*/
 277   assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
 278
 279   /* Check the DMA parameters from DMA_InitStruct */
 280   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
 281   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
 282   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
 283   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
 284   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
 285   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
 286   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
 287   assert_param(IS_LL_DMA_PERIPHREQUEST(DMA_InitStruct->PeriphRequest));
 288   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
 289
 290   /*---------------------------- DMAx CCR Configuration ------------------------
 291    * Configure DMAx_Channely: data transfer direction, data transfer mode,
 292    *                          peripheral and memory increment mode,
 293    *                          data size alignment and  priority level with parameters :
 294    * - Direction:      DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
 295    * - Mode:           DMA_CCR_CIRC bit
 296    * - PeriphOrM2MSrcIncMode:  DMA_CCR_PINC bit
 297    * - MemoryOrM2MDstIncMode:  DMA_CCR_MINC bit
 298    * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
 299    * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
 300    * - Priority:               DMA_CCR_PL[1:0] bits
 301    */
 302   LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction              | \
 303                         DMA_InitStruct->Mode                   | \
 304                         DMA_InitStruct->PeriphOrM2MSrcIncMode  | \
 305                         DMA_InitStruct->MemoryOrM2MDstIncMode  | \
 306                         DMA_InitStruct->PeriphOrM2MSrcDataSize | \
 307                         DMA_InitStruct->MemoryOrM2MDstDataSize | \
 308                         DMA_InitStruct->Priority);
 309
 310   /*-------------------------- DMAx CMAR Configuration -------------------------
 311    * Configure the memory or destination base address with parameter :
 312    * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
 313    */
 314   LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
 315
 316   /*-------------------------- DMAx CPAR Configuration -------------------------
 317    * Configure the peripheral or source base address with parameter :
 318    * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
 319    */
 320   LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
 321
 322   /*--------------------------- DMAx CNDTR Configuration -----------------------
 323    * Configure the peripheral base address with parameter :
 324    * - NbData: DMA_CNDTR_NDT[15:0] bits
 325    */
 326   LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
 327
 328   /*--------------------------- DMAMUXx CCR Configuration ----------------------
 329    * Configure the DMA request for DMA Channels on DMAMUX Channel x with parameter :
 330    * - PeriphRequest: DMA_CxCR[7:0] bits
 331    */
 332   LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->PeriphRequest);
 333
 334   return (uint32_t)SUCCESS;
 335 }
 336
 337 /**
 338   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
 339   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
 340   * @retval None
 341   */
 342 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 343 {
 344   /* Set DMA_InitStruct fields to default values */
 345   DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
 346   DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
 347   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
 348   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
 349   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
 350   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
 351   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
 352   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
 353   DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
 354   DMA_InitStruct->PeriphRequest          = LL_DMAMUX_REQ_MEM2MEM;
 355   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
 356 }
 357
 358 /**
 359   * @}
 360   */
 361
 362 /**
 363   * @}
 364   */
 365
 366 /**
 367   * @}
 368   */
 369
 370 #endif /* DMA1 || DMA2 */
 371
 372 /**
 373   * @}
 374   */
 375
 376 #endif /* USE_FULL_LL_DRIVER */
 377
 378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/