lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_rcc.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_rcc.c
   4   * @author  MCD Application Team
   5   * @brief   RCC LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32g4xx_ll_rcc.h"
  23 #ifdef  USE_FULL_ASSERT
  24   #include "stm32_assert.h"
  25 #else
  26   #define assert_param(expr) ((void)0U)
  27 #endif
  28 /** @addtogroup STM32G4xx_LL_Driver
  29   * @{
  30   */
  31
  32 /** @addtogroup RCC_LL
  33   * @{
  34   */
  35
  36 /* Private types -------------------------------------------------------------*/
  37 /* Private variables ---------------------------------------------------------*/
  38 /* Private constants ---------------------------------------------------------*/
  39 /* Private macros ------------------------------------------------------------*/
  40 /** @addtogroup RCC_LL_Private_Macros
  41   * @{
  42   */
  43 #define IS_LL_RCC_USART_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \
  44                                             || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \
  45                                             || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE))
  46 #if defined(RCC_CCIPR_UART5SEL)
  47 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \
  48                                              || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE))
  49 #elif defined(RCC_CCIPR_UART4SEL)
  50 #define IS_LL_RCC_UART_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_UART4_CLKSOURCE)
  51 #endif /* RCC_CCIPR_UART5SEL*/
  52
  53 #define IS_LL_RCC_LPUART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPUART1_CLKSOURCE))
  54
  55 #if defined(RCC_CCIPR2_I2C4SEL)
  56 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
  57                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
  58                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \
  59                                             || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE))
  60
  61 #else
  62 #define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \
  63                                             || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \
  64                                             || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE))
  65 #endif /* RCC_CCIPR2_I2C4SEL */
  66 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
  67
  68 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_SAI1_CLKSOURCE)
  69
  70 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__)    ((__VALUE__) == LL_RCC_I2S_CLKSOURCE)
  71
  72 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
  73
  74 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
  75
  76 #if defined(ADC345_COMMON)
  77 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE) \
  78                                             || ((__VALUE__) == LL_RCC_ADC345_CLKSOURCE))
  79 #else
  80 #define IS_LL_RCC_ADC_CLKSOURCE(__VALUE__)    (((__VALUE__) == LL_RCC_ADC12_CLKSOURCE))
  81 #endif /* ADC345_COMMON */
  82
  83 #if defined(QUADSPI)
  84 #define IS_LL_RCC_QUADSPI_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_QUADSPI_CLKSOURCE))
  85 #endif /* QUADSPI */
  86
  87 #if defined(FDCAN1)
  88 #define IS_LL_RCC_FDCAN_CLKSOURCE(__VALUE__)  (((__VALUE__) == LL_RCC_FDCAN_CLKSOURCE))
  89 #endif /* FDCAN1 */
  90
  91 /**
  92   * @}
  93   */
  94
  95 /* Private function prototypes -----------------------------------------------*/
  96 /** @defgroup RCC_LL_Private_Functions RCC Private functions
  97   * @{
  98   */
  99 uint32_t RCC_GetSystemClockFreq(void);
 100 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
 101 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
 102 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
 103 uint32_t RCC_PLL_GetFreqDomain_SYS(void);
 104 uint32_t RCC_PLL_GetFreqDomain_ADC(void);
 105 uint32_t RCC_PLL_GetFreqDomain_48M(void);
 106 /**
 107   * @}
 108   */
 109
 110
 111 /* Exported functions --------------------------------------------------------*/
 112 /** @addtogroup RCC_LL_Exported_Functions
 113   * @{
 114   */
 115
 116 /** @addtogroup RCC_LL_EF_Init
 117   * @{
 118   */
 119
 120 /**
 121   * @brief  Reset the RCC clock configuration to the default reset state.
 122   * @note   The default reset state of the clock configuration is given below:
 123   *         - HSI  ON and used as system clock source
 124   *         - HSE and PLL OFF
 125   *         - AHB, APB1 and APB2 prescaler set to 1.
 126   *         - CSS, MCO OFF
 127   *         - All interrupts disabled
 128   * @note   This function doesn't modify the configuration of the
 129   *         - Peripheral clocks
 130   *         - LSI, LSE and RTC clocks
 131   * @retval An ErrorStatus enumeration value:
 132   *          - SUCCESS: RCC registers are de-initialized
 133   *          - ERROR: not applicable
 134   */
 135 ErrorStatus LL_RCC_DeInit(void)
 136 {
 137   uint32_t vl_mask;
 138
 139   /* Set HSION bit and wait for HSI READY bit */
 140   LL_RCC_HSI_Enable();
 141   while (LL_RCC_HSI_IsReady() == 0U)
 142   {}
 143
 144   /* Set HSITRIM bits to reset value*/
 145   LL_RCC_HSI_SetCalibTrimming(0x40U);
 146
 147   /* Reset whole CFGR register but keep HSI as system clock source */
 148   LL_RCC_WriteReg(CFGR, LL_RCC_SYS_CLKSOURCE_HSI);
 149   while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {};
 150
 151   /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */
 152   LL_RCC_WriteReg(CR, RCC_CR_HSION);
 153   LL_RCC_WriteReg(CR, RCC_CR_HSION);
 154
 155   /* Wait for PLL READY bit to be reset */
 156   while (LL_RCC_PLL_IsReady() != 0U)
 157   {}
 158
 159   /* Reset PLLCFGR register */
 160   LL_RCC_WriteReg(PLLCFGR, 16U << RCC_PLLCFGR_PLLN_Pos);
 161
 162   /* Disable all interrupts */
 163   LL_RCC_WriteReg(CIER, 0x00000000U);
 164
 165   /* Clear all interrupt flags */
 166   vl_mask = RCC_CICR_LSIRDYC | RCC_CICR_LSERDYC | RCC_CICR_HSIRDYC | RCC_CICR_HSERDYC | RCC_CICR_PLLRDYC | \
 167             RCC_CICR_HSI48RDYC | RCC_CICR_CSSC | RCC_CICR_LSECSSC;
 168
 169   LL_RCC_WriteReg(CICR, vl_mask);
 170
 171   /* Clear reset flags */
 172   LL_RCC_ClearResetFlags();
 173
 174   return SUCCESS;
 175 }
 176
 177 /**
 178   * @}
 179   */
 180
 181 /** @addtogroup RCC_LL_EF_Get_Freq
 182   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
 183   *         and different peripheral clocks available on the device.
 184   * @note   If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
 185   * @note   If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
 186   * @note   If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
 187   *         or HSI_VALUE(**) multiplied/divided by the PLL factors.
 188   * @note   (**) HSI_VALUE is a constant defined in this file (default value
 189   *              16 MHz) but the real value may vary depending on the variations
 190   *              in voltage and temperature.
 191   * @note   (***) HSE_VALUE is a constant defined in this file (default value
 192   *               8 MHz), user has to ensure that HSE_VALUE is same as the real
 193   *               frequency of the crystal used. Otherwise, this function may
 194   *               have wrong result.
 195   * @note   The result of this function could be incorrect when using fractional
 196   *         value for HSE crystal.
 197   * @note   This function can be used by the user application to compute the
 198   *         baud-rate for the communication peripherals or configure other parameters.
 199   * @{
 200   */
 201
 202 /**
 203   * @brief  Return the frequencies of different on chip clocks;  System, AHB, APB1 and APB2 buses clocks
 204   * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
 205   *         must be called to update structure fields. Otherwise, any
 206   *         configuration based on this function will be incorrect.
 207   * @param  RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
 208   * @retval None
 209   */
 210 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
 211 {
 212   /* Get SYSCLK frequency */
 213   RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
 214
 215   /* HCLK clock frequency */
 216   RCC_Clocks->HCLK_Frequency   = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
 217
 218   /* PCLK1 clock frequency */
 219   RCC_Clocks->PCLK1_Frequency  = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
 220
 221   /* PCLK2 clock frequency */
 222   RCC_Clocks->PCLK2_Frequency  = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
 223 }
 224
 225 /**
 226   * @brief  Return USARTx clock frequency
 227   * @param  USARTxSource This parameter can be one of the following values:
 228   *         @arg @ref LL_RCC_USART1_CLKSOURCE
 229   *         @arg @ref LL_RCC_USART2_CLKSOURCE
 230   *         @arg @ref LL_RCC_USART3_CLKSOURCE
 231   *
 232   * @retval USART clock frequency (in Hz)
 233   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
 234   */
 235 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource)
 236 {
 237   uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 238
 239   /* Check parameter */
 240   assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource));
 241
 242   if (USARTxSource == LL_RCC_USART1_CLKSOURCE)
 243   {
 244     /* USART1CLK clock frequency */
 245     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
 246     {
 247       case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */
 248         usart_frequency = RCC_GetSystemClockFreq();
 249         break;
 250
 251       case LL_RCC_USART1_CLKSOURCE_HSI:    /* USART1 Clock is HSI Osc. */
 252         if (LL_RCC_HSI_IsReady() != 0U)
 253         {
 254           usart_frequency = HSI_VALUE;
 255         }
 256         break;
 257
 258       case LL_RCC_USART1_CLKSOURCE_LSE:    /* USART1 Clock is LSE Osc. */
 259         if (LL_RCC_LSE_IsReady() != 0U)
 260         {
 261           usart_frequency = LSE_VALUE;
 262         }
 263         break;
 264
 265       case LL_RCC_USART1_CLKSOURCE_PCLK2:  /* USART1 Clock is PCLK2 */
 266       default:
 267         usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 268         break;
 269     }
 270   }
 271   else if (USARTxSource == LL_RCC_USART2_CLKSOURCE)
 272   {
 273     /* USART2CLK clock frequency */
 274     switch (LL_RCC_GetUSARTClockSource(USARTxSource))
 275     {
 276       case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */
 277         usart_frequency = RCC_GetSystemClockFreq();
 278         break;
 279
 280       case LL_RCC_USART2_CLKSOURCE_HSI:    /* USART2 Clock is HSI Osc. */
 281         if (LL_RCC_HSI_IsReady() != 0U)
 282         {
 283           usart_frequency = HSI_VALUE;
 284         }
 285         break;
 286
 287       case LL_RCC_USART2_CLKSOURCE_LSE:    /* USART2 Clock is LSE Osc. */
 288         if (LL_RCC_LSE_IsReady() != 0U)
 289         {
 290           usart_frequency = LSE_VALUE;
 291         }
 292         break;
 293
 294       case LL_RCC_USART2_CLKSOURCE_PCLK1:  /* USART2 Clock is PCLK1 */
 295       default:
 296         usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 297         break;
 298     }
 299   }
 300   else
 301   {
 302     if (USARTxSource == LL_RCC_USART3_CLKSOURCE)
 303     {
 304       /* USART3CLK clock frequency */
 305       switch (LL_RCC_GetUSARTClockSource(USARTxSource))
 306       {
 307         case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */
 308           usart_frequency = RCC_GetSystemClockFreq();
 309           break;
 310
 311         case LL_RCC_USART3_CLKSOURCE_HSI:    /* USART3 Clock is HSI Osc. */
 312           if (LL_RCC_HSI_IsReady() != 0U)
 313           {
 314             usart_frequency = HSI_VALUE;
 315           }
 316           break;
 317
 318         case LL_RCC_USART3_CLKSOURCE_LSE:    /* USART3 Clock is LSE Osc. */
 319           if (LL_RCC_LSE_IsReady() != 0U)
 320           {
 321             usart_frequency = LSE_VALUE;
 322           }
 323           break;
 324
 325         case LL_RCC_USART3_CLKSOURCE_PCLK1:  /* USART3 Clock is PCLK1 */
 326         default:
 327           usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 328           break;
 329       }
 330     }
 331   }
 332   return usart_frequency;
 333 }
 334
 335 #if defined(RCC_CCIPR_UART4SEL)
 336 /**
 337   * @brief  Return UARTx clock frequency
 338   * @param  UARTxSource This parameter can be one of the following values:
 339   *         @arg @ref LL_RCC_UART4_CLKSOURCE (*)
 340   *         @arg @ref LL_RCC_UART5_CLKSOURCE (*)
 341   *
 342   *         (*) value not defined in all devices.
 343   * @retval UART clock frequency (in Hz)
 344   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
 345   */
 346 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource)
 347 {
 348   uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 349
 350   /* Check parameter */
 351   assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource));
 352
 353   if (UARTxSource == LL_RCC_UART4_CLKSOURCE)
 354   {
 355     /* UART4CLK clock frequency */
 356     switch (LL_RCC_GetUARTClockSource(UARTxSource))
 357     {
 358       case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */
 359         uart_frequency = RCC_GetSystemClockFreq();
 360         break;
 361
 362       case LL_RCC_UART4_CLKSOURCE_HSI:    /* UART4 Clock is HSI Osc. */
 363         if (LL_RCC_HSI_IsReady() != 0U)
 364         {
 365           uart_frequency = HSI_VALUE;
 366         }
 367         break;
 368
 369       case LL_RCC_UART4_CLKSOURCE_LSE:    /* UART4 Clock is LSE Osc. */
 370         if (LL_RCC_LSE_IsReady() != 0U)
 371         {
 372           uart_frequency = LSE_VALUE;
 373         }
 374         break;
 375
 376       case LL_RCC_UART4_CLKSOURCE_PCLK1:  /* UART4 Clock is PCLK1 */
 377       default:
 378         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 379         break;
 380     }
 381   }
 382
 383 #if defined(RCC_CCIPR_UART5SEL)
 384   if (UARTxSource == LL_RCC_UART5_CLKSOURCE)
 385   {
 386     /* UART5CLK clock frequency */
 387     switch (LL_RCC_GetUARTClockSource(UARTxSource))
 388     {
 389       case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */
 390         uart_frequency = RCC_GetSystemClockFreq();
 391         break;
 392
 393       case LL_RCC_UART5_CLKSOURCE_HSI:    /* UART5 Clock is HSI Osc. */
 394         if (LL_RCC_HSI_IsReady() != 0U)
 395         {
 396           uart_frequency = HSI_VALUE;
 397         }
 398         break;
 399
 400       case LL_RCC_UART5_CLKSOURCE_LSE:    /* UART5 Clock is LSE Osc. */
 401         if (LL_RCC_LSE_IsReady() != 0U)
 402         {
 403           uart_frequency = LSE_VALUE;
 404         }
 405         break;
 406
 407       case LL_RCC_UART5_CLKSOURCE_PCLK1:  /* UART5 Clock is PCLK1 */
 408       default:
 409         uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 410         break;
 411     }
 412   }
 413 #endif /* RCC_CCIPR_UART5SEL */
 414
 415   return uart_frequency;
 416 }
 417 #endif /* RCC_CCIPR_UART4SEL */
 418
 419 /**
 420   * @brief  Return I2Cx clock frequency
 421   * @param  I2CxSource This parameter can be one of the following values:
 422   *         @arg @ref LL_RCC_I2C1_CLKSOURCE
 423   *         @arg @ref LL_RCC_I2C2_CLKSOURCE
 424   *         @arg @ref LL_RCC_I2C3_CLKSOURCE
 425   *         @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
 426   *
 427   *         (*) value not defined in all devices.
 428   * @retval I2C clock frequency (in Hz)
 429   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
 430   */
 431 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource)
 432 {
 433   uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 434
 435   /* Check parameter */
 436   assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource));
 437
 438   if (I2CxSource == LL_RCC_I2C1_CLKSOURCE)
 439   {
 440     /* I2C1 CLK clock frequency */
 441     switch (LL_RCC_GetI2CClockSource(I2CxSource))
 442     {
 443       case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */
 444         i2c_frequency = RCC_GetSystemClockFreq();
 445         break;
 446
 447       case LL_RCC_I2C1_CLKSOURCE_HSI:    /* I2C1 Clock is HSI Osc. */
 448         if (LL_RCC_HSI_IsReady() != 0U)
 449         {
 450           i2c_frequency = HSI_VALUE;
 451         }
 452         break;
 453
 454       case LL_RCC_I2C1_CLKSOURCE_PCLK1:  /* I2C1 Clock is PCLK1 */
 455       default:
 456         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 457         break;
 458     }
 459   }
 460   else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE)
 461   {
 462     /* I2C2 CLK clock frequency */
 463     switch (LL_RCC_GetI2CClockSource(I2CxSource))
 464     {
 465       case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */
 466         i2c_frequency = RCC_GetSystemClockFreq();
 467         break;
 468
 469       case LL_RCC_I2C2_CLKSOURCE_HSI:    /* I2C2 Clock is HSI Osc. */
 470         if (LL_RCC_HSI_IsReady() != 0U)
 471         {
 472           i2c_frequency = HSI_VALUE;
 473         }
 474         break;
 475
 476       case LL_RCC_I2C2_CLKSOURCE_PCLK1:  /* I2C2 Clock is PCLK1 */
 477       default:
 478         i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 479         break;
 480     }
 481   }
 482   else
 483   {
 484     if (I2CxSource == LL_RCC_I2C3_CLKSOURCE)
 485     {
 486       /* I2C3 CLK clock frequency */
 487       switch (LL_RCC_GetI2CClockSource(I2CxSource))
 488       {
 489         case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */
 490           i2c_frequency = RCC_GetSystemClockFreq();
 491           break;
 492
 493         case LL_RCC_I2C3_CLKSOURCE_HSI:    /* I2C3 Clock is HSI Osc. */
 494           if (LL_RCC_HSI_IsReady() != 0U)
 495           {
 496             i2c_frequency = HSI_VALUE;
 497           }
 498           break;
 499
 500         case LL_RCC_I2C3_CLKSOURCE_PCLK1:  /* I2C3 Clock is PCLK1 */
 501         default:
 502           i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 503           break;
 504       }
 505     }
 506 #if defined(RCC_CCIPR2_I2C4SEL)
 507     else
 508     {
 509       if (I2CxSource == LL_RCC_I2C4_CLKSOURCE)
 510       {
 511         /* I2C4 CLK clock frequency */
 512         switch (LL_RCC_GetI2CClockSource(I2CxSource))
 513         {
 514           case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */
 515             i2c_frequency = RCC_GetSystemClockFreq();
 516             break;
 517
 518           case LL_RCC_I2C4_CLKSOURCE_HSI:    /* I2C4 Clock is HSI Osc. */
 519             if (LL_RCC_HSI_IsReady() != 0U)
 520             {
 521               i2c_frequency = HSI_VALUE;
 522             }
 523             break;
 524
 525           case LL_RCC_I2C4_CLKSOURCE_PCLK1:  /* I2C4 Clock is PCLK1 */
 526           default:
 527             i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 528             break;
 529         }
 530       }
 531     }
 532 #endif /*RCC_CCIPR2_I2C4SEL*/
 533   }
 534
 535   return i2c_frequency;
 536 }
 537
 538
 539 /**
 540   * @brief  Return LPUARTx clock frequency
 541   * @param  LPUARTxSource This parameter can be one of the following values:
 542   *         @arg @ref LL_RCC_LPUART1_CLKSOURCE
 543   * @retval LPUART clock frequency (in Hz)
 544   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
 545   */
 546 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource)
 547 {
 548   uint32_t lpuart_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 549
 550   /* Check parameter */
 551   assert_param(IS_LL_RCC_LPUART_CLKSOURCE(LPUARTxSource));
 552
 553   /* LPUART1CLK clock frequency */
 554   switch (LL_RCC_GetLPUARTClockSource(LPUARTxSource))
 555   {
 556     case LL_RCC_LPUART1_CLKSOURCE_SYSCLK: /* LPUART1 Clock is System Clock */
 557       lpuart_frequency = RCC_GetSystemClockFreq();
 558       break;
 559
 560     case LL_RCC_LPUART1_CLKSOURCE_HSI:    /* LPUART1 Clock is HSI Osc. */
 561       if (LL_RCC_HSI_IsReady() != 0U)
 562       {
 563         lpuart_frequency = HSI_VALUE;
 564       }
 565       break;
 566
 567     case LL_RCC_LPUART1_CLKSOURCE_LSE:    /* LPUART1 Clock is LSE Osc. */
 568       if (LL_RCC_LSE_IsReady() != 0U)
 569       {
 570         lpuart_frequency = LSE_VALUE;
 571       }
 572       break;
 573
 574     case LL_RCC_LPUART1_CLKSOURCE_PCLK1:  /* LPUART1 Clock is PCLK1 */
 575     default:
 576       lpuart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 577       break;
 578   }
 579
 580   return lpuart_frequency;
 581 }
 582
 583 /**
 584   * @brief  Return LPTIMx clock frequency
 585   * @param  LPTIMxSource This parameter can be one of the following values:
 586   *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
 587   * @retval LPTIM clock frequency (in Hz)
 588   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
 589   */
 590 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
 591 {
 592   uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 593
 594   /* Check parameter */
 595   assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
 596
 597   if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
 598   {
 599     /* LPTIM1CLK clock frequency */
 600     switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
 601     {
 602       case LL_RCC_LPTIM1_CLKSOURCE_LSI:    /* LPTIM1 Clock is LSI Osc. */
 603         if (LL_RCC_LSI_IsReady() != 0U)
 604         {
 605           lptim_frequency = LSI_VALUE;
 606         }
 607         break;
 608
 609       case LL_RCC_LPTIM1_CLKSOURCE_HSI:    /* LPTIM1 Clock is HSI Osc. */
 610         if (LL_RCC_HSI_IsReady() != 0U)
 611         {
 612           lptim_frequency = HSI_VALUE;
 613         }
 614         break;
 615
 616       case LL_RCC_LPTIM1_CLKSOURCE_LSE:    /* LPTIM1 Clock is LSE Osc. */
 617         if (LL_RCC_LSE_IsReady() != 0U)
 618         {
 619           lptim_frequency = LSE_VALUE;
 620         }
 621         break;
 622
 623       case LL_RCC_LPTIM1_CLKSOURCE_PCLK1:  /* LPTIM1 Clock is PCLK1 */
 624       default:
 625         lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 626         break;
 627     }
 628   }
 629
 630   return lptim_frequency;
 631 }
 632
 633 /**
 634   * @brief  Return SAIx clock frequency
 635   * @param  SAIxSource This parameter can be one of the following values:
 636   *         @arg @ref LL_RCC_SAI1_CLKSOURCE
 637   *
 638   * @retval SAI clock frequency (in Hz)
 639   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
 640   */
 641 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
 642 {
 643   uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 644
 645   /* Check parameter */
 646   assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
 647
 648   if (SAIxSource == LL_RCC_SAI1_CLKSOURCE)
 649   {
 650     /* SAI1CLK clock frequency */
 651     switch (LL_RCC_GetSAIClockSource(SAIxSource))
 652     {
 653       case LL_RCC_SAI1_CLKSOURCE_SYSCLK:      /* System clock used as SAI1 clock source */
 654         sai_frequency = RCC_GetSystemClockFreq();
 655         break;
 656
 657       case LL_RCC_SAI1_CLKSOURCE_PLL:        /* PLL clock used as SAI1 clock source */
 658         if (LL_RCC_PLL_IsReady() != 0U)
 659         {
 660           sai_frequency = RCC_PLL_GetFreqDomain_48M();
 661         }
 662         break;
 663
 664       case LL_RCC_SAI1_CLKSOURCE_PIN:          /* SAI1 Clock is External clock */
 665         sai_frequency = EXTERNAL_CLOCK_VALUE;
 666         break;
 667
 668       case LL_RCC_SAI1_CLKSOURCE_HSI:        /* HSI clock used as SAI1 clock source */
 669       default:
 670         if (LL_RCC_HSI_IsReady() != 0U)
 671         {
 672           sai_frequency = HSI_VALUE;
 673         }
 674         break;
 675
 676     }
 677   }
 678
 679   return sai_frequency;
 680 }
 681
 682 /**
 683   * @brief  Return I2Sx clock frequency
 684   * @param  I2SxSource This parameter can be one of the following values:
 685   *         @arg @ref LL_RCC_I2S_CLKSOURCE
 686   * @retval I2S clock frequency (in Hz)
 687   *         @arg @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
 688   */
 689 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
 690 {
 691   uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 692
 693   /* Check parameter */
 694   assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
 695
 696   if (I2SxSource == LL_RCC_I2S_CLKSOURCE)
 697   {
 698     /* I2S CLK clock frequency */
 699     switch (LL_RCC_GetI2SClockSource(I2SxSource))
 700     {
 701       case LL_RCC_I2S_CLKSOURCE_SYSCLK:  /* I2S Clock is System Clock */
 702         i2s_frequency = RCC_GetSystemClockFreq();
 703       break;
 704
 705       case LL_RCC_I2S_CLKSOURCE_PLL:    /* I2S Clock is PLL"Q" */
 706       if (LL_RCC_PLL_IsReady() != 0U)
 707       {
 708         i2s_frequency = RCC_PLL_GetFreqDomain_48M();
 709       }
 710       break;
 711
 712       case LL_RCC_I2S_CLKSOURCE_PIN:    /* I2S Clock is External clock */
 713         i2s_frequency = EXTERNAL_CLOCK_VALUE;
 714         break;
 715
 716       case LL_RCC_I2S_CLKSOURCE_HSI:    /* I2S Clock is HSI */
 717       default:
 718         if (LL_RCC_HSI_IsReady() != 0U)
 719         {
 720           i2s_frequency = HSI_VALUE;
 721         }
 722       break;
 723       }
 724   }
 725
 726   return i2s_frequency;
 727 }
 728
 729 #if defined(FDCAN1)
 730 /**
 731   * @brief  Return FDCAN kernel clock frequency
 732   * @param  FDCANxSource This parameter can be one of the following values:
 733   *         @arg @ref LL_RCC_FDCAN_CLKSOURCE
 734   * @retval FDCAN kernel clock frequency (in Hz)
 735   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
 736   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
 737   */
 738 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource)
 739 {
 740   uint32_t fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 741
 742   /* Check parameter */
 743   assert_param(IS_LL_RCC_FDCAN_CLKSOURCE(FDCANxSource));
 744
 745   /* FDCAN kernel clock frequency */
 746   switch (LL_RCC_GetFDCANClockSource(FDCANxSource))
 747   {
 748     case LL_RCC_FDCAN_CLKSOURCE_HSE:   /* HSE clock used as FDCAN kernel clock */
 749       if (LL_RCC_HSE_IsReady() != 0U)
 750       {
 751         fdcan_frequency = HSE_VALUE;
 752       }
 753       break;
 754
 755     case LL_RCC_FDCAN_CLKSOURCE_PLL:   /* PLL clock used as FDCAN kernel clock */
 756       if (LL_RCC_PLL_IsReady() != 0U)
 757       {
 758         fdcan_frequency = RCC_PLL_GetFreqDomain_48M();
 759       }
 760       break;
 761
 762     case LL_RCC_FDCAN_CLKSOURCE_PCLK1: /* PCLK1 clock used as FDCAN kernel clock */
 763       fdcan_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
 764       break;
 765
 766     default:
 767       fdcan_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
 768       break;
 769   }
 770   return fdcan_frequency;
 771 }
 772 #endif /* FDCAN1 */
 773
 774 /**
 775   * @brief  Return RNGx clock frequency
 776   * @param  RNGxSource This parameter can be one of the following values:
 777   *         @arg @ref LL_RCC_RNG_CLKSOURCE
 778   * @retval RNG clock frequency (in Hz)
 779   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
 780   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
 781   */
 782 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
 783 {
 784   uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 785
 786   /* Check parameter */
 787   assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
 788
 789   /* RNGCLK clock frequency */
 790   switch (LL_RCC_GetRNGClockSource(RNGxSource))
 791   {
 792     case LL_RCC_RNG_CLKSOURCE_PLL:           /* PLL clock used as RNG clock source */
 793       if (LL_RCC_PLL_IsReady() != 0U)
 794       {
 795         rng_frequency = RCC_PLL_GetFreqDomain_48M();
 796       }
 797       break;
 798
 799     case LL_RCC_RNG_CLKSOURCE_HSI48:         /* HSI48 used as RNG clock source */
 800       if (LL_RCC_HSI48_IsReady() != 0U)
 801       {
 802         rng_frequency = HSI48_VALUE;
 803       }
 804       break;
 805
 806     default:
 807       rng_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
 808       break;
 809
 810   }
 811
 812   return rng_frequency;
 813 }
 814
 815 /**
 816   * @brief  Return USBx clock frequency
 817   * @param  USBxSource This parameter can be one of the following values:
 818   *         @arg @ref LL_RCC_USB_CLKSOURCE
 819   * @retval USB clock frequency (in Hz)
 820   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI48) or PLL is not ready
 821   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
 822   */
 823 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
 824 {
 825   uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 826
 827   /* Check parameter */
 828   assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
 829
 830   /* USBCLK clock frequency */
 831   switch (LL_RCC_GetUSBClockSource(USBxSource))
 832   {
 833     case LL_RCC_USB_CLKSOURCE_PLL:           /* PLL clock used as USB clock source */
 834       if (LL_RCC_PLL_IsReady() != 0U)
 835       {
 836         usb_frequency = RCC_PLL_GetFreqDomain_48M();
 837       }
 838       break;
 839
 840     case LL_RCC_USB_CLKSOURCE_HSI48:         /* HSI48 used as USB clock source */
 841       if (LL_RCC_HSI48_IsReady() != 0U)
 842       {
 843         usb_frequency = HSI48_VALUE;
 844       }
 845       break;
 846
 847     default:
 848       usb_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
 849       break;
 850   }
 851
 852   return usb_frequency;
 853 }
 854
 855 /**
 856   * @brief  Return ADCx clock frequency
 857   * @param  ADCxSource This parameter can be one of the following values:
 858   *         @arg @ref LL_RCC_ADC12_CLKSOURCE
 859   *         @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
 860   *
 861   *         (*) value not defined in all devices.
 862   * @retval ADC clock frequency (in Hz)
 863   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready
 864   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected
 865   */
 866 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource)
 867 {
 868   uint32_t adc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 869
 870   /* Check parameter */
 871   assert_param(IS_LL_RCC_ADC_CLKSOURCE(ADCxSource));
 872
 873   if (ADCxSource == LL_RCC_ADC12_CLKSOURCE)
 874   {
 875     /* ADC12CLK clock frequency */
 876     switch (LL_RCC_GetADCClockSource(ADCxSource))
 877     {
 878       case LL_RCC_ADC12_CLKSOURCE_PLL:       /* PLL clock used as ADC12 clock source */
 879         if (LL_RCC_PLL_IsReady() != 0U)
 880         {
 881           adc_frequency = RCC_PLL_GetFreqDomain_ADC();
 882         }
 883         break;
 884
 885       case LL_RCC_ADC12_CLKSOURCE_SYSCLK:    /* System clock used as ADC12 clock source */
 886         adc_frequency = RCC_GetSystemClockFreq();
 887         break;
 888
 889       case LL_RCC_ADC12_CLKSOURCE_NONE:        /* No clock used as ADC12 clock source */
 890       default:
 891         adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
 892         break;
 893     }
 894   }
 895 #if defined(ADC345_COMMON)
 896   else
 897   {
 898     /* ADC345CLK clock frequency */
 899     switch (LL_RCC_GetADCClockSource(ADCxSource))
 900     {
 901       case LL_RCC_ADC345_CLKSOURCE_PLL:       /* PLL clock used as ADC345 clock source */
 902         if (LL_RCC_PLL_IsReady() != 0U)
 903         {
 904           adc_frequency = RCC_PLL_GetFreqDomain_ADC();
 905         }
 906         break;
 907
 908       case LL_RCC_ADC345_CLKSOURCE_SYSCLK:    /* System clock used as ADC345 clock source */
 909         adc_frequency = RCC_GetSystemClockFreq();
 910         break;
 911
 912       case LL_RCC_ADC345_CLKSOURCE_NONE:        /* No clock used as ADC345 clock source */
 913       default:
 914         adc_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
 915         break;
 916     }
 917   }
 918 #endif /* ADC345_COMMON */
 919
 920   return adc_frequency;
 921 }
 922
 923 #if defined(QUADSPI)
 924 /**
 925   * @brief  Return QUADSPI clock frequency
 926   * @param  QUADSPIxSource This parameter can be one of the following values:
 927   *         @arg @ref LL_RCC_QUADSPI_CLKSOURCE
 928   * @retval QUADSPI clock frequency (in Hz)
 929   *         - @ref  LL_RCC_PERIPH_FREQUENCY_NO indicates that no clock is configured
 930   */
 931 uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource)
 932 {
 933   uint32_t quadspi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
 934
 935   /* Check parameter */
 936   assert_param(IS_LL_RCC_QUADSPI_CLKSOURCE(QUADSPIxSource));
 937
 938   /* QUADSPI clock frequency */
 939   switch (LL_RCC_GetQUADSPIClockSource(QUADSPIxSource))
 940   {
 941     case LL_RCC_QUADSPI_CLKSOURCE_SYSCLK:   /* SYSCLK used as QUADSPI source */
 942       quadspi_frequency = RCC_GetSystemClockFreq();
 943       break;
 944
 945     case LL_RCC_QUADSPI_CLKSOURCE_HSI:      /* HSI clock used as QUADSPI source */
 946       if (LL_RCC_HSI_IsReady() != 0U)
 947       {
 948         quadspi_frequency = HSI_VALUE;
 949       }
 950       break;
 951
 952     case LL_RCC_QUADSPI_CLKSOURCE_PLL:      /* PLL clock used as QUADSPI source */
 953       if (LL_RCC_PLL_IsReady() != 0U)
 954       {
 955         quadspi_frequency = RCC_PLL_GetFreqDomain_48M();
 956       }
 957       break;
 958
 959     default:
 960       /* Nothing to do: quadspi frequency already initilalized to LL_RCC_PERIPH_FREQUENCY_NO */
 961       break;
 962   }
 963
 964   return quadspi_frequency;
 965 }
 966 #endif /* QUADSPI */
 967
 968 /**
 969   * @}
 970   */
 971
 972 /**
 973   * @}
 974   */
 975
 976 /** @addtogroup RCC_LL_Private_Functions
 977   * @{
 978   */
 979
 980 /**
 981   * @brief  Return SYSTEM clock frequency
 982   * @retval SYSTEM clock frequency (in Hz)
 983   */
 984 uint32_t RCC_GetSystemClockFreq(void)
 985 {
 986   uint32_t frequency;
 987
 988   /* Get SYSCLK source -------------------------------------------------------*/
 989   switch (LL_RCC_GetSysClkSource())
 990   {
 991     case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:  /* HSI used as system clock  source */
 992       frequency = HSI_VALUE;
 993       break;
 994
 995     case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:  /* HSE used as system clock  source */
 996       frequency = HSE_VALUE;
 997       break;
 998
 999     case LL_RCC_SYS_CLKSOURCE_STATUS_PLL:  /* PLL used as system clock  source */
1000       frequency = RCC_PLL_GetFreqDomain_SYS();
1001       break;
1002
1003     default:
1004       frequency = HSI_VALUE;
1005       break;
1006   }
1007
1008   return frequency;
1009 }
1010
1011 /**
1012   * @brief  Return HCLK clock frequency
1013   * @param  SYSCLK_Frequency SYSCLK clock frequency
1014   * @retval HCLK clock frequency (in Hz)
1015   */
1016 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1017 {
1018   /* HCLK clock frequency */
1019   return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1020 }
1021
1022 /**
1023   * @brief  Return PCLK1 clock frequency
1024   * @param  HCLK_Frequency HCLK clock frequency
1025   * @retval PCLK1 clock frequency (in Hz)
1026   */
1027 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1028 {
1029   /* PCLK1 clock frequency */
1030   return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1031 }
1032
1033 /**
1034   * @brief  Return PCLK2 clock frequency
1035   * @param  HCLK_Frequency HCLK clock frequency
1036   * @retval PCLK2 clock frequency (in Hz)
1037   */
1038 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1039 {
1040   /* PCLK2 clock frequency */
1041   return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1042 }
1043
1044 /**
1045   * @brief  Return PLL clock frequency used for system domain
1046   * @retval PLL clock frequency (in Hz)
1047   */
1048 uint32_t RCC_PLL_GetFreqDomain_SYS(void)
1049 {
1050   uint32_t pllinputfreq, pllsource;
1051
1052   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1053      SYSCLK = PLL_VCO / PLLR
1054   */
1055   pllsource = LL_RCC_PLL_GetMainSource();
1056
1057   switch (pllsource)
1058   {
1059     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
1060       pllinputfreq = HSI_VALUE;
1061       break;
1062
1063     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
1064       pllinputfreq = HSE_VALUE;
1065       break;
1066
1067     default:
1068       pllinputfreq = HSI_VALUE;
1069       break;
1070   }
1071   return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1072                                    LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1073 }
1074
1075 /**
1076   * @brief  Return PLL clock frequency used for ADC domain
1077   * @retval PLL clock frequency (in Hz)
1078   */
1079 uint32_t RCC_PLL_GetFreqDomain_ADC(void)
1080 {
1081   uint32_t pllinputfreq, pllsource;
1082
1083   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1084      ADC Domain clock = PLL_VCO / PLLP
1085   */
1086   pllsource = LL_RCC_PLL_GetMainSource();
1087
1088   switch (pllsource)
1089   {
1090     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
1091       pllinputfreq = HSI_VALUE;
1092       break;
1093
1094     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
1095       pllinputfreq = HSE_VALUE;
1096       break;
1097
1098     default:
1099       pllinputfreq = HSI_VALUE;
1100       break;
1101   }
1102   return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1103                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1104 }
1105
1106 /**
1107   * @brief  Return PLL clock frequency used for 48 MHz domain
1108   * @retval PLL clock frequency (in Hz)
1109   */
1110 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1111 {
1112   uint32_t pllinputfreq, pllsource;
1113
1114   /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1115      48M Domain clock = PLL_VCO / PLLQ
1116   */
1117   pllsource = LL_RCC_PLL_GetMainSource();
1118
1119   switch (pllsource)
1120   {
1121     case LL_RCC_PLLSOURCE_HSI:  /* HSI used as PLL clock source */
1122       pllinputfreq = HSI_VALUE;
1123       break;
1124
1125     case LL_RCC_PLLSOURCE_HSE:  /* HSE used as PLL clock source */
1126       pllinputfreq = HSE_VALUE;
1127       break;
1128
1129     default:
1130       pllinputfreq = HSI_VALUE;
1131       break;
1132   }
1133   return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1134                                         LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1135 }
1136
1137 /**
1138   * @}
1139   */
1140
1141 /**
1142   * @}
1143   */
1144
1145 /**
1146   * @}
1147   */
1148
1149 #endif /* USE_FULL_LL_DRIVER */
1150
1151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/