lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_spi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_spi.c
   4   * @author  MCD Application Team
   5   * @brief   SPI LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32g4xx_ll_spi.h"
  23 #include "stm32g4xx_ll_bus.h"
  24 #include "stm32g4xx_ll_rcc.h"
  25
  26 #ifdef  USE_FULL_ASSERT
  27 #include "stm32_assert.h"
  28 #else
  29 #define assert_param(expr) ((void)0U)
  30 #endif
  31
  32 /** @addtogroup STM32G4xx_LL_Driver
  33   * @{
  34   */
  35
  36 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
  37
  38 /** @addtogroup SPI_LL
  39   * @{
  40   */
  41
  42 /* Private types -------------------------------------------------------------*/
  43 /* Private variables ---------------------------------------------------------*/
  44
  45 /* Private constants ---------------------------------------------------------*/
  46 /** @defgroup SPI_LL_Private_Constants SPI Private Constants
  47   * @{
  48   */
  49 /* SPI registers Masks */
  50 #define SPI_CR1_CLEAR_MASK                 (SPI_CR1_CPHA    | SPI_CR1_CPOL     | SPI_CR1_MSTR   | \
  51                                             SPI_CR1_BR      | SPI_CR1_LSBFIRST | SPI_CR1_SSI    | \
  52                                             SPI_CR1_SSM     | SPI_CR1_RXONLY   | SPI_CR1_CRCL   | \
  53                                             SPI_CR1_CRCNEXT | SPI_CR1_CRCEN    | SPI_CR1_BIDIOE | \
  54                                             SPI_CR1_BIDIMODE)
  55 /**
  56   * @}
  57   */
  58
  59 /* Private macros ------------------------------------------------------------*/
  60 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
  61   * @{
  62   */
  63 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX)       \
  64                                                  || ((__VALUE__) == LL_SPI_SIMPLEX_RX)     \
  65                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
  66                                                  || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
  67
  68 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
  69                                    || ((__VALUE__) == LL_SPI_MODE_SLAVE))
  70
  71 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT)     \
  72                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT)  \
  73                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT)  \
  74                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT)  \
  75                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT)  \
  76                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT)  \
  77                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
  78                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
  79                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
  80                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
  81                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
  82                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
  83                                         || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
  84
  85 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
  86                                        || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
  87
  88 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
  89                                     || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
  90
  91 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT)          \
  92                                   || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
  93                                   || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
  94
  95 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2)      \
  96                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4)   \
  97                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8)   \
  98                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16)  \
  99                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32)  \
 100                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64)  \
 101                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
 102                                        || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
 103
 104 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
 105                                        || ((__VALUE__) == LL_SPI_MSB_FIRST))
 106
 107 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
 108                                              || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
 109
 110 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
 111
 112 /**
 113   * @}
 114   */
 115
 116 /* Private function prototypes -----------------------------------------------*/
 117
 118 /* Exported functions --------------------------------------------------------*/
 119 /** @addtogroup SPI_LL_Exported_Functions
 120   * @{
 121   */
 122
 123 /** @addtogroup SPI_LL_EF_Init
 124   * @{
 125   */
 126
 127 /**
 128   * @brief  De-initialize the SPI registers to their default reset values.
 129   * @param  SPIx SPI Instance
 130   * @retval An ErrorStatus enumeration value:
 131   *          - SUCCESS: SPI registers are de-initialized
 132   *          - ERROR: SPI registers are not de-initialized
 133   */
 134 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
 135 {
 136   ErrorStatus status = ERROR;
 137
 138   /* Check the parameters */
 139   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 140
 141 #if defined(SPI1)
 142   if (SPIx == SPI1)
 143   {
 144     /* Force reset of SPI clock */
 145     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
 146
 147     /* Release reset of SPI clock */
 148     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
 149
 150     status = SUCCESS;
 151   }
 152 #endif /* SPI1 */
 153 #if defined(SPI2)
 154   if (SPIx == SPI2)
 155   {
 156     /* Force reset of SPI clock */
 157     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
 158
 159     /* Release reset of SPI clock */
 160     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
 161
 162     status = SUCCESS;
 163   }
 164 #endif /* SPI2 */
 165 #if defined(SPI3)
 166   if (SPIx == SPI3)
 167   {
 168     /* Force reset of SPI clock */
 169     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
 170
 171     /* Release reset of SPI clock */
 172     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
 173
 174     status = SUCCESS;
 175   }
 176 #endif /* SPI3 */
 177 #if defined(SPI4)
 178   if (SPIx == SPI4)
 179   {
 180     /* Force reset of SPI clock */
 181     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
 182
 183     /* Release reset of SPI clock */
 184     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
 185
 186     status = SUCCESS;
 187   }
 188 #endif /* SPI4 */
 189
 190   return status;
 191 }
 192
 193 /**
 194   * @brief  Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
 195   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 196   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 197   * @param  SPIx SPI Instance
 198   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 199   * @retval An ErrorStatus enumeration value. (Return always SUCCESS)
 200   */
 201 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
 202 {
 203   ErrorStatus status = ERROR;
 204
 205   /* Check the SPI Instance SPIx*/
 206   assert_param(IS_SPI_ALL_INSTANCE(SPIx));
 207
 208   /* Check the SPI parameters from SPI_InitStruct*/
 209   assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
 210   assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
 211   assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
 212   assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
 213   assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
 214   assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
 215   assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
 216   assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
 217   assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
 218
 219   if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
 220   {
 221     /*---------------------------- SPIx CR1 Configuration ------------------------
 222      * Configure SPIx CR1 with parameters:
 223      * - TransferDirection:  SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
 224      * - Master/Slave Mode:  SPI_CR1_MSTR bit
 225      * - ClockPolarity:      SPI_CR1_CPOL bit
 226      * - ClockPhase:         SPI_CR1_CPHA bit
 227      * - NSS management:     SPI_CR1_SSM bit
 228      * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
 229      * - BitOrder:           SPI_CR1_LSBFIRST bit
 230      * - CRCCalculation:     SPI_CR1_CRCEN bit
 231      */
 232     MODIFY_REG(SPIx->CR1,
 233                SPI_CR1_CLEAR_MASK,
 234                SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
 235                SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
 236                SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
 237                SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
 238
 239     /*---------------------------- SPIx CR2 Configuration ------------------------
 240      * Configure SPIx CR2 with parameters:
 241      * - DataWidth:          DS[3:0] bits
 242      * - NSS management:     SSOE bit
 243      */
 244     MODIFY_REG(SPIx->CR2,
 245                SPI_CR2_DS | SPI_CR2_SSOE,
 246                SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
 247
 248     /*---------------------------- SPIx CRCPR Configuration ----------------------
 249      * Configure SPIx CRCPR with parameters:
 250      * - CRCPoly:            CRCPOLY[15:0] bits
 251      */
 252     if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
 253     {
 254       assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
 255       LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
 256     }
 257     status = SUCCESS;
 258   }
 259
 260 #if defined (SPI_I2S_SUPPORT)
 261   /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
 262   CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 263 #endif /* SPI_I2S_SUPPORT */
 264   return status;
 265 }
 266
 267 /**
 268   * @brief  Set each @ref LL_SPI_InitTypeDef field to default value.
 269   * @param  SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
 270   * whose fields will be set to default values.
 271   * @retval None
 272   */
 273 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
 274 {
 275   /* Set SPI_InitStruct fields to default values */
 276   SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
 277   SPI_InitStruct->Mode              = LL_SPI_MODE_SLAVE;
 278   SPI_InitStruct->DataWidth         = LL_SPI_DATAWIDTH_8BIT;
 279   SPI_InitStruct->ClockPolarity     = LL_SPI_POLARITY_LOW;
 280   SPI_InitStruct->ClockPhase        = LL_SPI_PHASE_1EDGE;
 281   SPI_InitStruct->NSS               = LL_SPI_NSS_HARD_INPUT;
 282   SPI_InitStruct->BaudRate          = LL_SPI_BAUDRATEPRESCALER_DIV2;
 283   SPI_InitStruct->BitOrder          = LL_SPI_MSB_FIRST;
 284   SPI_InitStruct->CRCCalculation    = LL_SPI_CRCCALCULATION_DISABLE;
 285   SPI_InitStruct->CRCPoly           = 7U;
 286 }
 287
 288 /**
 289   * @}
 290   */
 291
 292 /**
 293   * @}
 294   */
 295
 296 /**
 297   * @}
 298   */
 299
 300 #if defined(SPI_I2S_SUPPORT)
 301 /** @addtogroup I2S_LL
 302   * @{
 303   */
 304
 305 /* Private types -------------------------------------------------------------*/
 306 /* Private variables ---------------------------------------------------------*/
 307 /* Private constants ---------------------------------------------------------*/
 308 /** @defgroup I2S_LL_Private_Constants I2S Private Constants
 309   * @{
 310   */
 311 /* I2S registers Masks */
 312 #define I2S_I2SCFGR_CLEAR_MASK             (SPI_I2SCFGR_CHLEN   | SPI_I2SCFGR_DATLEN | \
 313                                             SPI_I2SCFGR_CKPOL   | SPI_I2SCFGR_I2SSTD | \
 314                                             SPI_I2SCFGR_I2SCFG  | SPI_I2SCFGR_I2SMOD )
 315
 316 #define I2S_I2SPR_CLEAR_MASK               0x0002U
 317 /**
 318   * @}
 319   */
 320 /* Private macros ------------------------------------------------------------*/
 321 /** @defgroup I2S_LL_Private_Macros I2S Private Macros
 322   * @{
 323   */
 324
 325 #define IS_LL_I2S_DATAFORMAT(__VALUE__)  (((__VALUE__) == LL_I2S_DATAFORMAT_16B)             \
 326                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
 327                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_24B)          \
 328                                           || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
 329
 330 #define IS_LL_I2S_CPOL(__VALUE__)        (((__VALUE__) == LL_I2S_POLARITY_LOW)  \
 331                                           || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
 332
 333 #define IS_LL_I2S_STANDARD(__VALUE__)    (((__VALUE__) == LL_I2S_STANDARD_PHILIPS)      \
 334                                           || ((__VALUE__) == LL_I2S_STANDARD_MSB)       \
 335                                           || ((__VALUE__) == LL_I2S_STANDARD_LSB)       \
 336                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
 337                                           || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
 338
 339 #define IS_LL_I2S_MODE(__VALUE__)        (((__VALUE__) == LL_I2S_MODE_SLAVE_TX)     \
 340                                           || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX)  \
 341                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
 342                                           || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
 343
 344 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
 345                                           || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
 346
 347 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K)       \
 348                                           && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
 349                                          || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
 350
 351 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__)  ((__VALUE__) >= 0x2U)
 352
 353 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
 354                                                || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
 355 /**
 356   * @}
 357   */
 358
 359 /* Private function prototypes -----------------------------------------------*/
 360
 361 /* Exported functions --------------------------------------------------------*/
 362 /** @addtogroup I2S_LL_Exported_Functions
 363   * @{
 364   */
 365
 366 /** @addtogroup I2S_LL_EF_Init
 367   * @{
 368   */
 369
 370 /**
 371   * @brief  De-initialize the SPI/I2S registers to their default reset values.
 372   * @param  SPIx SPI Instance
 373   * @retval An ErrorStatus enumeration value:
 374   *          - SUCCESS: SPI registers are de-initialized
 375   *          - ERROR: SPI registers are not de-initialized
 376   */
 377 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
 378 {
 379   return LL_SPI_DeInit(SPIx);
 380 }
 381
 382 /**
 383   * @brief  Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
 384   * @note   As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
 385   *         SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
 386   * @param  SPIx SPI Instance
 387   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 388   * @retval An ErrorStatus enumeration value:
 389   *          - SUCCESS: SPI registers are Initialized
 390   *          - ERROR: SPI registers are not Initialized
 391   */
 392 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
 393 {
 394   uint32_t i2sdiv = 2U;
 395   uint32_t i2sodd = 0U;
 396   uint32_t packetlength = 1U;
 397   uint32_t tmp;
 398   uint32_t sourceclock;
 399   ErrorStatus status = ERROR;
 400
 401   /* Check the I2S parameters */
 402   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 403   assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
 404   assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
 405   assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
 406   assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
 407   assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
 408   assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
 409
 410   if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
 411   {
 412     /*---------------------------- SPIx I2SCFGR Configuration --------------------
 413      * Configure SPIx I2SCFGR with parameters:
 414      * - Mode:          SPI_I2SCFGR_I2SCFG[1:0] bit
 415      * - Standard:      SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
 416      * - DataFormat:    SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
 417      * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
 418      */
 419
 420     /* Write to SPIx I2SCFGR */
 421     MODIFY_REG(SPIx->I2SCFGR,
 422                I2S_I2SCFGR_CLEAR_MASK,
 423                I2S_InitStruct->Mode | I2S_InitStruct->Standard |
 424                I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
 425                SPI_I2SCFGR_I2SMOD);
 426
 427     /*---------------------------- SPIx I2SPR Configuration ----------------------
 428      * Configure SPIx I2SPR with parameters:
 429      * - MCLKOutput:    SPI_I2SPR_MCKOE bit
 430      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
 431      */
 432
 433     /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
 434      * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
 435      */
 436     if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
 437     {
 438       /* Check the frame length (For the Prescaler computing)
 439        * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
 440        */
 441       if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
 442       {
 443         /* Packet length is 32 bits */
 444         packetlength = 2U;
 445       }
 446
 447       /* If an external I2S clock has to be used, the specific define should be set
 448       in the project configuration or in the stm32g4xx_ll_rcc.h file */
 449       /* Get the I2S source clock value */
 450       sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S_CLKSOURCE);
 451
 452       /* Compute the Real divider depending on the MCLK output state with a floating point */
 453       if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
 454       {
 455         /* MCLK output is enabled */
 456         tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 457       }
 458       else
 459       {
 460         /* MCLK output is disabled */
 461         tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
 462       }
 463
 464       /* Remove the floating point */
 465       tmp = tmp / 10U;
 466
 467       /* Check the parity of the divider */
 468       i2sodd = (tmp & (uint16_t)0x0001U);
 469
 470       /* Compute the i2sdiv prescaler */
 471       i2sdiv = ((tmp - i2sodd) / 2U);
 472
 473       /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
 474       i2sodd = (i2sodd << 8U);
 475     }
 476
 477     /* Test if the divider is 1 or 0 or greater than 0xFF */
 478     if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
 479     {
 480       /* Set the default values */
 481       i2sdiv = 2U;
 482       i2sodd = 0U;
 483     }
 484
 485     /* Write to SPIx I2SPR register the computed value */
 486     WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
 487
 488     status = SUCCESS;
 489   }
 490   return status;
 491 }
 492
 493 /**
 494   * @brief  Set each @ref LL_I2S_InitTypeDef field to default value.
 495   * @param  I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
 496   *         whose fields will be set to default values.
 497   * @retval None
 498   */
 499 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
 500 {
 501   /*--------------- Reset I2S init structure parameters values -----------------*/
 502   I2S_InitStruct->Mode              = LL_I2S_MODE_SLAVE_TX;
 503   I2S_InitStruct->Standard          = LL_I2S_STANDARD_PHILIPS;
 504   I2S_InitStruct->DataFormat        = LL_I2S_DATAFORMAT_16B;
 505   I2S_InitStruct->MCLKOutput        = LL_I2S_MCLK_OUTPUT_DISABLE;
 506   I2S_InitStruct->AudioFreq         = LL_I2S_AUDIOFREQ_DEFAULT;
 507   I2S_InitStruct->ClockPolarity     = LL_I2S_POLARITY_LOW;
 508 }
 509
 510 /**
 511   * @brief  Set linear and parity prescaler.
 512   * @note   To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
 513   *         Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
 514   * @param  SPIx SPI Instance
 515   * @param  PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF.
 516   * @param  PrescalerParity This parameter can be one of the following values:
 517   *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
 518   *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD
 519   * @retval None
 520   */
 521 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
 522 {
 523   /* Check the I2S parameters */
 524   assert_param(IS_I2S_ALL_INSTANCE(SPIx));
 525   assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
 526   assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
 527
 528   /* Write to SPIx I2SPR */
 529   MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
 530 }
 531
 532 /**
 533   * @}
 534   */
 535
 536 /**
 537   * @}
 538   */
 539
 540 /**
 541   * @}
 542   */
 543 #endif /* SPI_I2S_SUPPORT */
 544
 545 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
 546
 547 /**
 548   * @}
 549   */
 550
 551 #endif /* USE_FULL_LL_DRIVER */
 552
 553 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/