lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @brief   TIM LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32g4xx_ll_tim.h"
  23 #include "stm32g4xx_ll_bus.h"
  24
  25 #ifdef  USE_FULL_ASSERT
  26 #include "stm32_assert.h"
  27 #else
  28 #define assert_param(expr) ((void)0U)
  29 #endif /* USE_FULL_ASSERT */
  30
  31 /** @addtogroup STM32G4xx_LL_Driver
  32   * @{
  33   */
  34
  35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
  36
  37 /** @addtogroup TIM_LL
  38   * @{
  39   */
  40
  41 /* Private types -------------------------------------------------------------*/
  42 /* Private variables ---------------------------------------------------------*/
  43 /* Private constants ---------------------------------------------------------*/
  44 /* Private macros ------------------------------------------------------------*/
  45 /** @addtogroup TIM_LL_Private_Macros
  46   * @{
  47   */
  48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  49                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  50                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  51                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  52                                           || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  53
  54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  55                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  56                                             || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  57
  58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  59                                      || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  60                                      || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  61                                      || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  62                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  63                                      || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  64                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  65                                      || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  66                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  67                                      || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  68                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  69                                      || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  70                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  71                                      || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2) \
  72                                      || ((__VALUE__) == LL_TIM_OCMODE_PULSE_ON_COMPARE) \
  73                                      || ((__VALUE__) == LL_TIM_OCMODE_DIRECTION_OUTPUT))
  74
  75 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  76                                       || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  77
  78 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  79                                          || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  80
  81 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  82                                           || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  83
  84 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
  85                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
  86                                           || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
  87
  88 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
  89                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
  90                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
  91                                     || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
  92
  93 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
  94                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
  95                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
  96                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
  97                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
  98                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
  99                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
 100                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
 101                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 102                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 103                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 104                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 105                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 106                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 107                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 108                                         || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 109
 110 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 111                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 112                                           || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 113
 114 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 115                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 116                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12) \
 117                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) \
 118                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) \
 119                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) \
 120                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) \
 121                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI1) \
 122                                           || ((__VALUE__) == LL_TIM_ENCODERMODE_X1_TI2))
 123
 124 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 125                                                   || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 126
 127 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 128                                          || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 129
 130 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 131                                          || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 132
 133 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 134                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 135                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 136                                          || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 137
 138 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 139                                           || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 140
 141 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 142                                              || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 143
 144 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
 145                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
 146                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
 147                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
 148                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
 149                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
 150                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
 151                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
 152                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
 153                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
 154                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
 155                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
 156                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
 157                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
 158                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
 159                                            || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
 160
 161 #define IS_LL_TIM_BREAK_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_AFMODE_INPUT)          \
 162                                            || ((__VALUE__) == LL_TIM_BREAK_AFMODE_BIDIRECTIONAL))
 163
 164 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
 165                                            || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
 166
 167 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
 168                                               || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
 169
 170 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
 171                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
 172                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
 173                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
 174                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
 175                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
 176                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
 177                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
 178                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
 179                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
 180                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
 181                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
 182                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
 183                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
 184                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
 185                                             || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
 186
 187 #define IS_LL_TIM_BREAK2_AFMODE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_AFMODE_INPUT)       \
 188                                             || ((__VALUE__) == LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL))
 189
 190 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 191                                                      || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 192 /**
 193   * @}
 194   */
 195
 196
 197 /* Private function prototypes -----------------------------------------------*/
 198 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 199   * @{
 200   */
 201 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 202 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 203 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 204 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 205 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 206 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 207 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 208 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 209 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 210 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 211 /**
 212   * @}
 213   */
 214
 215 /* Exported functions --------------------------------------------------------*/
 216 /** @addtogroup TIM_LL_Exported_Functions
 217   * @{
 218   */
 219
 220 /** @addtogroup TIM_LL_EF_Init
 221   * @{
 222   */
 223
 224 /**
 225   * @brief  Set TIMx registers to their reset values.
 226   * @param  TIMx Timer instance
 227   * @retval An ErrorStatus enumeration value:
 228   *          - SUCCESS: TIMx registers are de-initialized
 229   *          - ERROR: invalid TIMx instance
 230   */
 231 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 232 {
 233   ErrorStatus result = SUCCESS;
 234
 235   /* Check the parameters */
 236   assert_param(IS_TIM_INSTANCE(TIMx));
 237
 238   if (TIMx == TIM1)
 239   {
 240     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 241     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 242   }
 243   else if (TIMx == TIM2)
 244   {
 245     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 246     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 247   }
 248   else if (TIMx == TIM3)
 249   {
 250     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 251     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 252   }
 253   else if (TIMx == TIM4)
 254   {
 255     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 256     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 257   }
 258 #if defined(TIM5)
 259   else if (TIMx == TIM5)
 260   {
 261     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 262     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 263   }
 264 #endif /* TIM5 */
 265   else if (TIMx == TIM6)
 266   {
 267     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 268     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 269   }
 270   else if (TIMx == TIM7)
 271   {
 272     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 273     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 274   }
 275   else if (TIMx == TIM8)
 276   {
 277     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 278     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 279   }
 280   else if (TIMx == TIM15)
 281   {
 282     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
 283     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
 284   }
 285   else if (TIMx == TIM16)
 286   {
 287     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
 288     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
 289   }
 290   else if (TIMx == TIM17)
 291   {
 292     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
 293     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
 294   }
 295 #if defined(TIM20)
 296   else if (TIMx == TIM20)
 297   {
 298     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM20);
 299     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM20);
 300   }
 301 #endif /* TIM20 */
 302   else
 303   {
 304     result = ERROR;
 305   }
 306
 307   return result;
 308 }
 309
 310 /**
 311   * @brief  Set the fields of the time base unit configuration data structure
 312   *         to their default values.
 313   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 314   * @retval None
 315   */
 316 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 317 {
 318   /* Set the default configuration */
 319   TIM_InitStruct->Prescaler         = (uint16_t)0x0000;
 320   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 321   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 322   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 323   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00;
 324 }
 325
 326 /**
 327   * @brief  Configure the TIMx time base unit.
 328   * @param  TIMx Timer Instance
 329   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 330   * @retval An ErrorStatus enumeration value:
 331   *          - SUCCESS: TIMx registers are de-initialized
 332   *          - ERROR: not applicable
 333   */
 334 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 335 {
 336   uint32_t tmpcr1;
 337
 338   /* Check the parameters */
 339   assert_param(IS_TIM_INSTANCE(TIMx));
 340   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 341   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 342
 343   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 344
 345   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 346   {
 347     /* Select the Counter Mode */
 348     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 349   }
 350
 351   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 352   {
 353     /* Set the clock division */
 354     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 355   }
 356
 357   /* Write to TIMx CR1 */
 358   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 359
 360   /* Set the Autoreload value */
 361   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 362
 363   /* Set the Prescaler value */
 364   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 365
 366   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 367   {
 368     /* Set the Repetition Counter value */
 369     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 370   }
 371
 372   /* Generate an update event to reload the Prescaler
 373      and the repetition counter value (if applicable) immediately */
 374   LL_TIM_GenerateEvent_UPDATE(TIMx);
 375
 376   return SUCCESS;
 377 }
 378
 379 /**
 380   * @brief  Set the fields of the TIMx output channel configuration data
 381   *         structure to their default values.
 382   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 383   * @retval None
 384   */
 385 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 386 {
 387   /* Set the default configuration */
 388   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 389   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 390   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 391   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 392   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 393   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 394   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 395   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 396 }
 397
 398 /**
 399   * @brief  Configure the TIMx output channel.
 400   * @param  TIMx Timer Instance
 401   * @param  Channel This parameter can be one of the following values:
 402   *         @arg @ref LL_TIM_CHANNEL_CH1
 403   *         @arg @ref LL_TIM_CHANNEL_CH2
 404   *         @arg @ref LL_TIM_CHANNEL_CH3
 405   *         @arg @ref LL_TIM_CHANNEL_CH4
 406   *         @arg @ref LL_TIM_CHANNEL_CH5
 407   *         @arg @ref LL_TIM_CHANNEL_CH6
 408   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 409   * @retval An ErrorStatus enumeration value:
 410   *          - SUCCESS: TIMx output channel is initialized
 411   *          - ERROR: TIMx output channel is not initialized
 412   */
 413 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 414 {
 415   ErrorStatus result = ERROR;
 416
 417   switch (Channel)
 418   {
 419     case LL_TIM_CHANNEL_CH1:
 420       result = OC1Config(TIMx, TIM_OC_InitStruct);
 421       break;
 422     case LL_TIM_CHANNEL_CH2:
 423       result = OC2Config(TIMx, TIM_OC_InitStruct);
 424       break;
 425     case LL_TIM_CHANNEL_CH3:
 426       result = OC3Config(TIMx, TIM_OC_InitStruct);
 427       break;
 428     case LL_TIM_CHANNEL_CH4:
 429       result = OC4Config(TIMx, TIM_OC_InitStruct);
 430       break;
 431     case LL_TIM_CHANNEL_CH5:
 432       result = OC5Config(TIMx, TIM_OC_InitStruct);
 433       break;
 434     case LL_TIM_CHANNEL_CH6:
 435       result = OC6Config(TIMx, TIM_OC_InitStruct);
 436       break;
 437     default:
 438       break;
 439   }
 440
 441   return result;
 442 }
 443
 444 /**
 445   * @brief  Set the fields of the TIMx input channel configuration data
 446   *         structure to their default values.
 447   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 448   * @retval None
 449   */
 450 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 451 {
 452   /* Set the default configuration */
 453   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 454   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 455   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 456   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 457 }
 458
 459 /**
 460   * @brief  Configure the TIMx input channel.
 461   * @param  TIMx Timer Instance
 462   * @param  Channel This parameter can be one of the following values:
 463   *         @arg @ref LL_TIM_CHANNEL_CH1
 464   *         @arg @ref LL_TIM_CHANNEL_CH2
 465   *         @arg @ref LL_TIM_CHANNEL_CH3
 466   *         @arg @ref LL_TIM_CHANNEL_CH4
 467   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 468   * @retval An ErrorStatus enumeration value:
 469   *          - SUCCESS: TIMx output channel is initialized
 470   *          - ERROR: TIMx output channel is not initialized
 471   */
 472 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 473 {
 474   ErrorStatus result = ERROR;
 475
 476   switch (Channel)
 477   {
 478     case LL_TIM_CHANNEL_CH1:
 479       result = IC1Config(TIMx, TIM_IC_InitStruct);
 480       break;
 481     case LL_TIM_CHANNEL_CH2:
 482       result = IC2Config(TIMx, TIM_IC_InitStruct);
 483       break;
 484     case LL_TIM_CHANNEL_CH3:
 485       result = IC3Config(TIMx, TIM_IC_InitStruct);
 486       break;
 487     case LL_TIM_CHANNEL_CH4:
 488       result = IC4Config(TIMx, TIM_IC_InitStruct);
 489       break;
 490     default:
 491       break;
 492   }
 493
 494   return result;
 495 }
 496
 497 /**
 498   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 499   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 500   * @retval None
 501   */
 502 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 503 {
 504   /* Set the default configuration */
 505   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 506   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 507   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 508   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 509   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 510   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 511   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 512   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 513   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 514 }
 515
 516 /**
 517   * @brief  Configure the encoder interface of the timer instance.
 518   * @param  TIMx Timer Instance
 519   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 520   * @retval An ErrorStatus enumeration value:
 521   *          - SUCCESS: TIMx registers are de-initialized
 522   *          - ERROR: not applicable
 523   */
 524 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 525 {
 526   uint32_t tmpccmr1;
 527   uint32_t tmpccer;
 528
 529   /* Check the parameters */
 530   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 531   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 532   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 533   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 534   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 535   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 536   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 537   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 538   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 539   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 540
 541   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 542   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 543
 544   /* Get the TIMx CCMR1 register value */
 545   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 546
 547   /* Get the TIMx CCER register value */
 548   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 549
 550   /* Configure TI1 */
 551   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 552   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 553   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 554   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 555
 556   /* Configure TI2 */
 557   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 558   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 559   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 560   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 561
 562   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 563   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 564   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 565   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 566   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 567
 568   /* Set encoder mode */
 569   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 570
 571   /* Write to TIMx CCMR1 */
 572   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 573
 574   /* Write to TIMx CCER */
 575   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 576
 577   return SUCCESS;
 578 }
 579
 580 /**
 581   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 582   *         structure to their default values.
 583   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 584   * @retval None
 585   */
 586 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 587 {
 588   /* Set the default configuration */
 589   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 590   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 591   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 592   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 593 }
 594
 595 /**
 596   * @brief  Configure the Hall sensor interface of the timer instance.
 597   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 598   *       to the TI1 input channel
 599   * @note TIMx slave mode controller is configured in reset mode.
 600           Selected internal trigger is TI1F_ED.
 601   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 602   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 603   *       between 2 changes on the inputs. It gives information about motor speed.
 604   * @note Channel 2 is configured in output PWM 2 mode.
 605   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 606   * @note OC2REF is selected as trigger output on TRGO.
 607   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 608   *       when TIMx operates in Hall sensor interface mode.
 609   * @param  TIMx Timer Instance
 610   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 611   * @retval An ErrorStatus enumeration value:
 612   *          - SUCCESS: TIMx registers are de-initialized
 613   *          - ERROR: not applicable
 614   */
 615 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 616 {
 617   uint32_t tmpcr2;
 618   uint32_t tmpccmr1;
 619   uint32_t tmpccer;
 620   uint32_t tmpsmcr;
 621
 622   /* Check the parameters */
 623   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 624   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 625   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 626   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 627
 628   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 629   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 630
 631   /* Get the TIMx CR2 register value */
 632   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 633
 634   /* Get the TIMx CCMR1 register value */
 635   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 636
 637   /* Get the TIMx CCER register value */
 638   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 639
 640   /* Get the TIMx SMCR register value */
 641   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 642
 643   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 644   tmpcr2 |= TIM_CR2_TI1S;
 645
 646   /* OC2REF signal is used as trigger output (TRGO) */
 647   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 648
 649   /* Configure the slave mode controller */
 650   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 651   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 652   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 653
 654   /* Configure input channel 1 */
 655   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 656   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 657   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 658   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 659
 660   /* Configure input channel 2 */
 661   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 662   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 663
 664   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 665   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 666   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 667   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 668
 669   /* Write to TIMx CR2 */
 670   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 671
 672   /* Write to TIMx SMCR */
 673   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 674
 675   /* Write to TIMx CCMR1 */
 676   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 677
 678   /* Write to TIMx CCER */
 679   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 680
 681   /* Write to TIMx CCR2 */
 682   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 683
 684   return SUCCESS;
 685 }
 686
 687 /**
 688   * @brief  Set the fields of the Break and Dead Time configuration data structure
 689   *         to their default values.
 690   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 691   * @retval None
 692   */
 693 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 694 {
 695   /* Set the default configuration */
 696   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 697   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 698   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 699   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00;
 700   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 701   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 702   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
 703   TIM_BDTRInitStruct->BreakAFMode     = LL_TIM_BREAK_AFMODE_INPUT;
 704   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
 705   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
 706   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
 707   TIM_BDTRInitStruct->Break2AFMode    = LL_TIM_BREAK2_AFMODE_INPUT;
 708   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 709 }
 710
 711 /**
 712   * @brief  Configure the Break and Dead Time feature of the timer instance.
 713   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
 714   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
 715   *  can be necessary to configure all of them during the first write access to
 716   *  the TIMx_BDTR register.
 717   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 718   *       a timer instance provides a break input.
 719   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
 720   *       a timer instance provides a second break input.
 721   * @param  TIMx Timer Instance
 722   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 723   * @retval An ErrorStatus enumeration value:
 724   *          - SUCCESS: Break and Dead Time is initialized
 725   *          - ERROR: not applicable
 726   */
 727 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 728 {
 729   uint32_t tmpbdtr = 0;
 730
 731   /* Check the parameters */
 732   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 733   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 734   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 735   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 736   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 737   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 738   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 739
 740   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 741   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 742
 743   /* Set the BDTR bits */
 744   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 745   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 746   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 747   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 748   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 749   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 750   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 751   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 752   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
 753   {
 754     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
 755     assert_param(IS_LL_TIM_BREAK_AFMODE(TIM_BDTRInitStruct->BreakAFMode));
 756     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
 757     MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, TIM_BDTRInitStruct->BreakAFMode);
 758   }
 759
 760   if (IS_TIM_BKIN2_INSTANCE(TIMx))
 761   {
 762     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
 763     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
 764     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
 765     assert_param(IS_LL_TIM_BREAK2_AFMODE(TIM_BDTRInitStruct->Break2AFMode));
 766
 767     /* Set the BREAK2 input related BDTR bit-fields */
 768     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
 769     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
 770     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
 771     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, TIM_BDTRInitStruct->Break2AFMode);
 772   }
 773
 774   /* Set TIMx_BDTR */
 775   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 776
 777   return SUCCESS;
 778 }
 779 /**
 780   * @}
 781   */
 782
 783 /**
 784   * @}
 785   */
 786
 787 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 788   *  @brief   Private functions
 789   * @{
 790   */
 791 /**
 792   * @brief  Configure the TIMx output channel 1.
 793   * @param  TIMx Timer Instance
 794   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 795   * @retval An ErrorStatus enumeration value:
 796   *          - SUCCESS: TIMx registers are de-initialized
 797   *          - ERROR: not applicable
 798   */
 799 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 800 {
 801   uint32_t tmpccmr1;
 802   uint32_t tmpccer;
 803   uint32_t tmpcr2;
 804
 805   /* Check the parameters */
 806   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 807   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 808   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 809   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 810   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 811   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 812
 813   /* Disable the Channel 1: Reset the CC1E Bit */
 814   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 815
 816   /* Get the TIMx CCER register value */
 817   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 818
 819   /* Get the TIMx CR2 register value */
 820   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 821
 822   /* Get the TIMx CCMR1 register value */
 823   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 824
 825   /* Reset Capture/Compare selection Bits */
 826   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 827
 828   /* Set the Output Compare Mode */
 829   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 830
 831   /* Set the Output Compare Polarity */
 832   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 833
 834   /* Set the Output State */
 835   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 836
 837   if (IS_TIM_BREAK_INSTANCE(TIMx))
 838   {
 839     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 840     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 841
 842     /* Set the complementary output Polarity */
 843     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 844
 845     /* Set the complementary output State */
 846     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 847
 848     /* Set the Output Idle state */
 849     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 850
 851     /* Set the complementary output Idle state */
 852     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 853   }
 854
 855   /* Write to TIMx CR2 */
 856   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 857
 858   /* Write to TIMx CCMR1 */
 859   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 860
 861   /* Set the Capture Compare Register value */
 862   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 863
 864   /* Write to TIMx CCER */
 865   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 866
 867   return SUCCESS;
 868 }
 869
 870 /**
 871   * @brief  Configure the TIMx output channel 2.
 872   * @param  TIMx Timer Instance
 873   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 874   * @retval An ErrorStatus enumeration value:
 875   *          - SUCCESS: TIMx registers are de-initialized
 876   *          - ERROR: not applicable
 877   */
 878 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 879 {
 880   uint32_t tmpccmr1;
 881   uint32_t tmpccer;
 882   uint32_t tmpcr2;
 883
 884   /* Check the parameters */
 885   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 886   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 887   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 888   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 889   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 890   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 891
 892   /* Disable the Channel 2: Reset the CC2E Bit */
 893   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 894
 895   /* Get the TIMx CCER register value */
 896   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 897
 898   /* Get the TIMx CR2 register value */
 899   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 900
 901   /* Get the TIMx CCMR1 register value */
 902   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 903
 904   /* Reset Capture/Compare selection Bits */
 905   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 906
 907   /* Select the Output Compare Mode */
 908   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 909
 910   /* Set the Output Compare Polarity */
 911   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 912
 913   /* Set the Output State */
 914   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 915
 916   if (IS_TIM_BREAK_INSTANCE(TIMx))
 917   {
 918     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 919     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 920
 921     /* Set the complementary output Polarity */
 922     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 923
 924     /* Set the complementary output State */
 925     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 926
 927     /* Set the Output Idle state */
 928     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 929
 930     /* Set the complementary output Idle state */
 931     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 932   }
 933
 934   /* Write to TIMx CR2 */
 935   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 936
 937   /* Write to TIMx CCMR1 */
 938   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 939
 940   /* Set the Capture Compare Register value */
 941   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 942
 943   /* Write to TIMx CCER */
 944   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 945
 946   return SUCCESS;
 947 }
 948
 949 /**
 950   * @brief  Configure the TIMx output channel 3.
 951   * @param  TIMx Timer Instance
 952   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 953   * @retval An ErrorStatus enumeration value:
 954   *          - SUCCESS: TIMx registers are de-initialized
 955   *          - ERROR: not applicable
 956   */
 957 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 958 {
 959   uint32_t tmpccmr2;
 960   uint32_t tmpccer;
 961   uint32_t tmpcr2;
 962
 963   /* Check the parameters */
 964   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 965   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 966   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 967   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 968   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 969   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 970
 971   /* Disable the Channel 3: Reset the CC3E Bit */
 972   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
 973
 974   /* Get the TIMx CCER register value */
 975   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 976
 977   /* Get the TIMx CR2 register value */
 978   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 979
 980   /* Get the TIMx CCMR2 register value */
 981   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
 982
 983   /* Reset Capture/Compare selection Bits */
 984   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
 985
 986   /* Select the Output Compare Mode */
 987   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
 988
 989   /* Set the Output Compare Polarity */
 990   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
 991
 992   /* Set the Output State */
 993   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
 994
 995   if (IS_TIM_BREAK_INSTANCE(TIMx))
 996   {
 997     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 998     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 999
1000     /* Set the complementary output Polarity */
1001     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1002
1003     /* Set the complementary output State */
1004     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1005
1006     /* Set the Output Idle state */
1007     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1008
1009     /* Set the complementary output Idle state */
1010     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1011   }
1012
1013   /* Write to TIMx CR2 */
1014   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1015
1016   /* Write to TIMx CCMR2 */
1017   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1018
1019   /* Set the Capture Compare Register value */
1020   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1021
1022   /* Write to TIMx CCER */
1023   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1024
1025   return SUCCESS;
1026 }
1027
1028 /**
1029   * @brief  Configure the TIMx output channel 4.
1030   * @param  TIMx Timer Instance
1031   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1032   * @retval An ErrorStatus enumeration value:
1033   *          - SUCCESS: TIMx registers are de-initialized
1034   *          - ERROR: not applicable
1035   */
1036 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1037 {
1038   uint32_t tmpccmr2;
1039   uint32_t tmpccer;
1040   uint32_t tmpcr2;
1041
1042   /* Check the parameters */
1043   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1044   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1045   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1046   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1047   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1048   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1049
1050   /* Disable the Channel 4: Reset the CC4E Bit */
1051   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1052
1053   /* Get the TIMx CCER register value */
1054   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1055
1056   /* Get the TIMx CR2 register value */
1057   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1058
1059   /* Get the TIMx CCMR2 register value */
1060   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1061
1062   /* Reset Capture/Compare selection Bits */
1063   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1064
1065   /* Select the Output Compare Mode */
1066   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1067
1068   /* Set the Output Compare Polarity */
1069   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1070
1071   /* Set the Output State */
1072   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1073
1074   if (IS_TIM_BREAK_INSTANCE(TIMx))
1075   {
1076     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1077     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1078
1079     /* Set the complementary output Polarity */
1080     MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U);
1081
1082     /* Set the complementary output State */
1083     MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U);
1084
1085     /* Set the Output Idle state */
1086     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1087
1088     /* Set the complementary output Idle state */
1089     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);
1090   }
1091
1092   /* Write to TIMx CR2 */
1093   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1094
1095   /* Write to TIMx CCMR2 */
1096   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1097
1098   /* Set the Capture Compare Register value */
1099   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1100
1101   /* Write to TIMx CCER */
1102   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1103
1104   return SUCCESS;
1105 }
1106
1107 /**
1108   * @brief  Configure the TIMx output channel 5.
1109   * @param  TIMx Timer Instance
1110   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1111   * @retval An ErrorStatus enumeration value:
1112   *          - SUCCESS: TIMx registers are de-initialized
1113   *          - ERROR: not applicable
1114   */
1115 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1116 {
1117   uint32_t tmpccmr3;
1118   uint32_t tmpccer;
1119
1120   /* Check the parameters */
1121   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1122   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1123   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1124   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1125   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1126   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1127
1128   /* Disable the Channel 5: Reset the CC5E Bit */
1129   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1130
1131   /* Get the TIMx CCER register value */
1132   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1133
1134   /* Get the TIMx CCMR3 register value */
1135   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1136
1137   /* Select the Output Compare Mode */
1138   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1139
1140   /* Set the Output Compare Polarity */
1141   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1142
1143   /* Set the Output State */
1144   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1145
1146   if (IS_TIM_BREAK_INSTANCE(TIMx))
1147   {
1148     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1149     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1150
1151     /* Set the Output Idle state */
1152     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1153
1154   }
1155
1156   /* Write to TIMx CCMR3 */
1157   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1158
1159   /* Set the Capture Compare Register value */
1160   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1161
1162   /* Write to TIMx CCER */
1163   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1164
1165   return SUCCESS;
1166 }
1167
1168 /**
1169   * @brief  Configure the TIMx output channel 6.
1170   * @param  TIMx Timer Instance
1171   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1172   * @retval An ErrorStatus enumeration value:
1173   *          - SUCCESS: TIMx registers are de-initialized
1174   *          - ERROR: not applicable
1175   */
1176 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1177 {
1178   uint32_t tmpccmr3;
1179   uint32_t tmpccer;
1180
1181   /* Check the parameters */
1182   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1183   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1184   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1185   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1186   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1187   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1188
1189   /* Disable the Channel 5: Reset the CC6E Bit */
1190   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1191
1192   /* Get the TIMx CCER register value */
1193   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1194
1195   /* Get the TIMx CCMR3 register value */
1196   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1197
1198   /* Select the Output Compare Mode */
1199   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1200
1201   /* Set the Output Compare Polarity */
1202   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1203
1204   /* Set the Output State */
1205   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1206
1207   if (IS_TIM_BREAK_INSTANCE(TIMx))
1208   {
1209     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1210     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1211
1212     /* Set the Output Idle state */
1213     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1214   }
1215
1216   /* Write to TIMx CCMR3 */
1217   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1218
1219   /* Set the Capture Compare Register value */
1220   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1221
1222   /* Write to TIMx CCER */
1223   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1224
1225   return SUCCESS;
1226 }
1227
1228 /**
1229   * @brief  Configure the TIMx input channel 1.
1230   * @param  TIMx Timer Instance
1231   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1232   * @retval An ErrorStatus enumeration value:
1233   *          - SUCCESS: TIMx registers are de-initialized
1234   *          - ERROR: not applicable
1235   */
1236 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1237 {
1238   /* Check the parameters */
1239   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1240   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1241   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1242   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1243   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1244
1245   /* Disable the Channel 1: Reset the CC1E Bit */
1246   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1247
1248   /* Select the Input and set the filter and the prescaler value */
1249   MODIFY_REG(TIMx->CCMR1,
1250              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1251              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1252
1253   /* Select the Polarity and set the CC1E Bit */
1254   MODIFY_REG(TIMx->CCER,
1255              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1256              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1257
1258   return SUCCESS;
1259 }
1260
1261 /**
1262   * @brief  Configure the TIMx input channel 2.
1263   * @param  TIMx Timer Instance
1264   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1265   * @retval An ErrorStatus enumeration value:
1266   *          - SUCCESS: TIMx registers are de-initialized
1267   *          - ERROR: not applicable
1268   */
1269 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1270 {
1271   /* Check the parameters */
1272   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1273   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1274   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1275   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1276   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1277
1278   /* Disable the Channel 2: Reset the CC2E Bit */
1279   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1280
1281   /* Select the Input and set the filter and the prescaler value */
1282   MODIFY_REG(TIMx->CCMR1,
1283              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1284              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1285
1286   /* Select the Polarity and set the CC2E Bit */
1287   MODIFY_REG(TIMx->CCER,
1288              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1289              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1290
1291   return SUCCESS;
1292 }
1293
1294 /**
1295   * @brief  Configure the TIMx input channel 3.
1296   * @param  TIMx Timer Instance
1297   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1298   * @retval An ErrorStatus enumeration value:
1299   *          - SUCCESS: TIMx registers are de-initialized
1300   *          - ERROR: not applicable
1301   */
1302 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1303 {
1304   /* Check the parameters */
1305   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1306   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1307   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1308   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1309   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1310
1311   /* Disable the Channel 3: Reset the CC3E Bit */
1312   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1313
1314   /* Select the Input and set the filter and the prescaler value */
1315   MODIFY_REG(TIMx->CCMR2,
1316              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1317              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1318
1319   /* Select the Polarity and set the CC3E Bit */
1320   MODIFY_REG(TIMx->CCER,
1321              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1322              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1323
1324   return SUCCESS;
1325 }
1326
1327 /**
1328   * @brief  Configure the TIMx input channel 4.
1329   * @param  TIMx Timer Instance
1330   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1331   * @retval An ErrorStatus enumeration value:
1332   *          - SUCCESS: TIMx registers are de-initialized
1333   *          - ERROR: not applicable
1334   */
1335 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1336 {
1337   /* Check the parameters */
1338   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1339   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1340   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1341   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1342   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1343
1344   /* Disable the Channel 4: Reset the CC4E Bit */
1345   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1346
1347   /* Select the Input and set the filter and the prescaler value */
1348   MODIFY_REG(TIMx->CCMR2,
1349              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1350              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1351
1352   /* Select the Polarity and set the CC2E Bit */
1353   MODIFY_REG(TIMx->CCER,
1354              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1355              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1356
1357   return SUCCESS;
1358 }
1359
1360
1361 /**
1362   * @}
1363   */
1364
1365 /**
1366   * @}
1367   */
1368
1369 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
1370
1371 /**
1372   * @}
1373   */
1374
1375 #endif /* USE_FULL_LL_DRIVER */
1376
1377 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/