lib/main/STM32G4/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_utils.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32g4xx_ll_utils.c
   4   * @author  MCD Application Team
   5   * @brief   UTILS LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19
  20 /* Includes ------------------------------------------------------------------*/
  21 #include "stm32g4xx_ll_utils.h"
  22 #include "stm32g4xx_ll_rcc.h"
  23 #include "stm32g4xx_ll_system.h"
  24 #include "stm32g4xx_ll_pwr.h"
  25 #ifdef  USE_FULL_ASSERT
  26 #include "stm32_assert.h"
  27 #else
  28 #define assert_param(expr) ((void)0U)
  29 #endif /* USE_FULL_ASSERT */
  30
  31 /** @addtogroup STM32G4xx_LL_Driver
  32   * @{
  33   */
  34
  35 /** @addtogroup UTILS_LL
  36   * @{
  37   */
  38
  39 /* Private types -------------------------------------------------------------*/
  40 /* Private variables ---------------------------------------------------------*/
  41 /* Private constants ---------------------------------------------------------*/
  42 /** @addtogroup UTILS_LL_Private_Constants
  43   * @{
  44   */
  45 #define UTILS_MAX_FREQUENCY_SCALE1  170000000U       /*!< Maximum frequency for system clock at power scale1, in Hz */
  46 #define UTILS_MAX_FREQUENCY_SCALE2   26000000U       /*!< Maximum frequency for system clock at power scale2, in Hz */
  47
  48 /* Defines used for PLL range */
  49 #define UTILS_PLLVCO_INPUT_MIN        2660000U       /*!< Frequency min for PLLVCO input, in Hz   */
  50 #define UTILS_PLLVCO_INPUT_MAX        8000000U       /*!< Frequency max for PLLVCO input, in Hz   */
  51 #define UTILS_PLLVCO_OUTPUT_MIN      64000000U       /*!< Frequency min for PLLVCO output, in Hz  */
  52 #define UTILS_PLLVCO_OUTPUT_MAX     344000000U       /*!< Frequency max for PLLVCO output, in Hz  */
  53
  54 /* Defines used for HSE range */
  55 #define UTILS_HSE_FREQUENCY_MIN      4000000U        /*!< Frequency min for HSE frequency, in Hz   */
  56 #define UTILS_HSE_FREQUENCY_MAX     48000000U        /*!< Frequency max for HSE frequency, in Hz   */
  57
  58 /* Defines used for FLASH latency according to HCLK Frequency */
  59 #define UTILS_SCALE1_LATENCY1_FREQ   20000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
  60 #define UTILS_SCALE1_LATENCY2_FREQ   40000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
  61 #define UTILS_SCALE1_LATENCY3_FREQ   60000000U       /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
  62 #define UTILS_SCALE1_LATENCY4_FREQ   80000000U       /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
  63 #define UTILS_SCALE1_LATENCY5_FREQ  100000000U       /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
  64 #define UTILS_SCALE1_LATENCY6_FREQ  120000000U       /*!< HCLK frequency to set FLASH latency 6 in power scale 1 */
  65 #define UTILS_SCALE1_LATENCY7_FREQ  140000000U       /*!< HCLK frequency to set FLASH latency 7 in power scale 1 */
  66 #define UTILS_SCALE1_LATENCY8_FREQ  160000000U       /*!< HCLK frequency to set FLASH latency 8 in power scale 1 */
  67 #define UTILS_SCALE1_LATENCY9_FREQ  170000000U       /*!< HCLK frequency to set FLASH latency 9 in power scale 1 */
  68 #define UTILS_SCALE2_LATENCY1_FREQ    8000000U       /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
  69 #define UTILS_SCALE2_LATENCY2_FREQ   16000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  70 #define UTILS_SCALE2_LATENCY3_FREQ   26000000U       /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
  71 /**
  72   * @}
  73   */
  74
  75 /* Private macros ------------------------------------------------------------*/
  76 /** @addtogroup UTILS_LL_Private_Macros
  77   * @{
  78   */
  79 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1)   \
  80                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2)   \
  81                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4)   \
  82                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8)   \
  83                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16)  \
  84                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64)  \
  85                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
  86                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
  87                                         || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
  88
  89 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
  90                                       || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
  91                                       || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
  92                                       || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
  93                                       || ((__VALUE__) == LL_RCC_APB1_DIV_16))
  94
  95 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
  96                                       || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
  97                                       || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
  98                                       || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
  99                                       || ((__VALUE__) == LL_RCC_APB2_DIV_16))
 100
 101 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_1) \
 102                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_2) \
 103                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
 104                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
 105                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
 106                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
 107                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
 108                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
 109                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
 110                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
 111                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
 112                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
 113                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
 114                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
 115                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
 116                                         || ((__VALUE__) == LL_RCC_PLLM_DIV_16))
 117
 118 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
 119
 120 #define IS_LL_UTILS_PLLR_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLR_DIV_2) \
 121                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_4) \
 122                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_6) \
 123                                         || ((__VALUE__) == LL_RCC_PLLR_DIV_8))
 124
 125 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__)  ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
 126
 127 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
 128
 129 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
 130                                              ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
 131
 132 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
 133                                         || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
 134
 135 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
 136 /**
 137   * @}
 138   */
 139 /* Private function prototypes -----------------------------------------------*/
 140 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
 141   * @{
 142   */
 143 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
 144                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
 145 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
 146 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 147 static ErrorStatus UTILS_PLL_IsBusy(void);
 148 /**
 149   * @}
 150   */
 151
 152 /* Exported functions --------------------------------------------------------*/
 153 /** @addtogroup UTILS_LL_Exported_Functions
 154   * @{
 155   */
 156
 157 /** @addtogroup UTILS_LL_EF_DELAY
 158   * @{
 159   */
 160
 161 /**
 162   * @brief  This function configures the Cortex-M SysTick source to have 1ms time base.
 163   * @note   When a RTOS is used, it is recommended to avoid changing the Systick
 164   *         configuration by calling this function, for a delay use rather osDelay RTOS service.
 165   * @param  HCLKFrequency HCLK frequency in Hz
 166   * @note   HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
 167   * @retval None
 168   */
 169 void LL_Init1msTick(uint32_t HCLKFrequency)
 170 {
 171   /* Use frequency provided in argument */
 172   LL_InitTick(HCLKFrequency, 1000U);
 173 }
 174
 175 /**
 176   * @brief  This function provides accurate delay (in milliseconds) based
 177   *         on SysTick counter flag
 178   * @note   When a RTOS is used, it is recommended to avoid using blocking delay
 179   *         and use rather osDelay service.
 180   * @note   To respect 1ms timebase, user should call @ref LL_Init1msTick function which
 181   *         will configure Systick to 1ms
 182   * @param  Delay specifies the delay time length, in milliseconds.
 183   * @retval None
 184   */
 185 void LL_mDelay(uint32_t Delay)
 186 {
 187   __IO uint32_t  tmp = SysTick->CTRL;  /* Clear the COUNTFLAG first */
 188   uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */
 189   /* Add this code to indicate that local variable is not used */
 190   ((void)tmp);
 191   tmpDelay = Delay;
 192   /* Add a period to guaranty minimum wait */
 193   if(tmpDelay < LL_MAX_DELAY)
 194   {
 195     tmpDelay++;
 196   }
 197
 198   while (tmpDelay != 0U)
 199   {
 200     if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
 201     {
 202       tmpDelay--;
 203     }
 204   }
 205 }
 206
 207 /**
 208   * @}
 209   */
 210
 211 /** @addtogroup UTILS_EF_SYSTEM
 212   *  @brief    System Configuration functions
 213   *
 214   @verbatim
 215  ===============================================================================
 216            ##### System Configuration functions #####
 217  ===============================================================================
 218     [..]
 219          System, AHB and APB buses clocks configuration
 220
 221          (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is
 222              170000000 Hz for STM32G4xx.
 223   @endverbatim
 224   @internal
 225              Depending on the device voltage range, the maximum frequency should be
 226              adapted accordingly:
 227
 228              (++) Table 1. HCLK clock frequency for STM32G4xx devices
 229              (++) +--------------------------------------------------------+
 230              (++) | Latency         |     HCLK clock frequency (MHz)       |
 231              (++) |                 |--------------------------------------|
 232              (++) |                 |  voltage range 1  | voltage range 2  |
 233              (++) |                 |       1.2 V       |     1.0 V        |
 234              (++) |-----------------|-------------------|------------------|
 235              (++) |0WS(1 CPU cycles)|   0 < HCLK <= 20  |  0 < HCLK <= 8   |
 236              (++) |-----------------|-------------------|------------------|
 237              (++) |1WS(2 CPU cycles)|  20 < HCLK <= 40  |  8 < HCLK <= 16  |
 238              (++) |-----------------|-------------------|------------------|
 239              (++) |2WS(3 CPU cycles)|  40 < HCLK <= 60  | 16 < HCLK <= 26  |
 240              (++) |-----------------|-------------------|------------------|
 241              (++) |3WS(4 CPU cycles)|  60 < HCLK <= 80  | 16 < HCLK <= 26  |
 242              (++) |-----------------|-------------------|------------------|
 243              (++) |4WS(5 CPU cycles)|  80 < HCLK <= 100 | 16 < HCLK <= 26  |
 244              (++) |-----------------|-------------------|------------------|
 245              (++) |5WS(6 CPU cycles)| 100 < HCLK <= 120 | 16 < HCLK <= 26  |
 246              (++) |-----------------|-------------------|------------------|
 247              (++) |6WS(7 CPU cycles)| 120 < HCLK <= 140 | 16 < HCLK <= 26  |
 248              (++) |-----------------|-------------------|------------------|
 249              (++) |7WS(8 CPU cycles)| 140 < HCLK <= 160 | 16 < HCLK <= 26  |
 250              (++) |-----------------|-------------------|------------------|
 251              (++) |8WS(9 CPU cycles)| 160 < HCLK <= 170 | 16 < HCLK <= 26  |
 252              (++) +--------------------------------------------------------+
 253
 254
 255   @endinternal
 256   * @{
 257   */
 258
 259 /**
 260   * @brief  This function sets directly SystemCoreClock CMSIS variable.
 261   * @note   Variable can be calculated also through SystemCoreClockUpdate function.
 262   * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
 263   * @retval None
 264   */
 265 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
 266 {
 267   /* HCLK clock frequency */
 268   SystemCoreClock = HCLKFrequency;
 269 }
 270
 271 /**
 272   * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
 273   * @note   The application need to ensure that PLL is disabled.
 274   * @note   Function is based on the following formula:
 275   *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR)
 276   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSI frequency / PLLM)
 277   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
 278   *         - PLLR: ensure that max frequency at 170000000 Hz is reach (PLLVCO_output / PLLR)
 279   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 280   *                             the configuration information for the PLL.
 281   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 282   *                             the configuration information for the BUS prescalers.
 283   * @retval An ErrorStatus enumeration value:
 284   *          - SUCCESS: Max frequency configuration done
 285   *          - ERROR: Max frequency configuration not done
 286   */
 287 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
 288                                          LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 289 {
 290   ErrorStatus status;
 291   uint32_t pllfreq;
 292   uint32_t hpre = 0U;
 293
 294   /* Check if one of the PLL is enabled */
 295   if(UTILS_PLL_IsBusy() == SUCCESS)
 296   {
 297     /* Calculate the new PLL output frequency */
 298     pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
 299
 300     /* Enable HSI if not enabled */
 301     if(LL_RCC_HSI_IsReady() != 1U)
 302     {
 303       LL_RCC_HSI_Enable();
 304       while (LL_RCC_HSI_IsReady() != 1U)
 305       {
 306         /* Wait for HSI ready */
 307       }
 308     }
 309
 310     /* Configure PLL */
 311     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
 312                                 UTILS_PLLInitStruct->PLLR);
 313
 314     /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
 315     if(pllfreq > 80000000U)
 316     {
 317       hpre = UTILS_ClkInitStruct->AHBCLKDivider;
 318       if(hpre == LL_RCC_SYSCLK_DIV_1)
 319       {
 320         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
 321       }
 322     }
 323
 324     /* Enable PLL and switch system clock to PLL */
 325     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
 326
 327     /* Apply definitive AHB prescaler value if necessary */
 328     if((status == SUCCESS) && (hpre != 0U))
 329     {
 330       UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
 331       LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
 332     }
 333   }
 334   else
 335   {
 336     /* Current PLL configuration cannot be modified */
 337     status = ERROR;
 338   }
 339
 340   return status;
 341 }
 342
 343 /**
 344   * @brief  This function configures system clock with HSE as clock source of the PLL
 345   * @note   The application need to ensure that PLL is disabled.
 346   * @note   Function is based on the following formula:
 347   *         - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR)
 348   *         - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz (PLLVCO_input = HSE frequency / PLLM)
 349   *         - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz (PLLVCO_output = PLLVCO_input * PLLN)
 350   *         - PLLR: ensure that max frequency at 170000000 Hz is reached (PLLVCO_output / PLLR)
 351   * @param  HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000
 352   * @param  HSEBypass This parameter can be one of the following values:
 353   *         @arg @ref LL_UTILS_HSEBYPASS_ON
 354   *         @arg @ref LL_UTILS_HSEBYPASS_OFF
 355   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 356   *                             the configuration information for the PLL.
 357   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 358   *                             the configuration information for the BUS prescalers.
 359   * @retval An ErrorStatus enumeration value:
 360   *          - SUCCESS: Max frequency configuration done
 361   *          - ERROR: Max frequency configuration not done
 362   */
 363 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
 364                                          LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 365 {
 366   ErrorStatus status;
 367   uint32_t pllfreq;
 368   uint32_t hpre = 0U;
 369
 370   /* Check the parameters */
 371   assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
 372   assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
 373
 374   /* Check if one of the PLL is enabled */
 375   if(UTILS_PLL_IsBusy() == SUCCESS)
 376   {
 377     /* Calculate the new PLL output frequency */
 378     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
 379
 380     /* Enable HSE if not enabled */
 381     if(LL_RCC_HSE_IsReady() != 1U)
 382     {
 383       /* Check if need to enable HSE bypass feature or not */
 384       if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
 385       {
 386         LL_RCC_HSE_EnableBypass();
 387       }
 388       else
 389       {
 390         LL_RCC_HSE_DisableBypass();
 391       }
 392
 393       /* Enable HSE */
 394       LL_RCC_HSE_Enable();
 395       while (LL_RCC_HSE_IsReady() != 1U)
 396       {
 397         /* Wait for HSE ready */
 398       }
 399     }
 400
 401     /* Configure PLL */
 402     LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
 403                                 UTILS_PLLInitStruct->PLLR);
 404
 405     /* Prevent undershoot at highest frequency by applying intermediate AHB prescaler 2 */
 406     if(pllfreq > 80000000U)
 407     {
 408       hpre = UTILS_ClkInitStruct->AHBCLKDivider;
 409       if(hpre == LL_RCC_SYSCLK_DIV_1)
 410       {
 411         UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_2;
 412       }
 413     }
 414
 415     /* Enable PLL and switch system clock to PLL */
 416     status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
 417
 418     /* Apply definitive AHB prescaler value if necessary */
 419     if((status == SUCCESS) && (hpre != 0U))
 420     {
 421       UTILS_ClkInitStruct->AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
 422       LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
 423     }
 424   }
 425   else
 426   {
 427     /* Current PLL configuration cannot be modified */
 428     status = ERROR;
 429   }
 430
 431   return status;
 432 }
 433
 434 /**
 435   * @}
 436   */
 437
 438 /**
 439   * @}
 440   */
 441
 442 /** @addtogroup UTILS_LL_Private_Functions
 443   * @{
 444   */
 445 /**
 446   * @brief  Update number of Flash wait states in line with new frequency and current
 447             voltage range.
 448   * @param  HCLK_Frequency  HCLK frequency
 449   * @retval An ErrorStatus enumeration value:
 450   *          - SUCCESS: Latency has been modified
 451   *          - ERROR: Latency cannot be modified
 452   */
 453 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
 454 {
 455   ErrorStatus status = SUCCESS;
 456
 457   uint32_t latency = LL_FLASH_LATENCY_0;  /* default value 0WS */
 458
 459   /* Frequency cannot be equal to 0 */
 460   if(HCLK_Frequency == 0U)
 461   {
 462     status = ERROR;
 463   }
 464   else
 465   {
 466     if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
 467     {
 468       if(HCLK_Frequency > UTILS_SCALE1_LATENCY8_FREQ)
 469       {
 470         /* 160 < HCLK <= 170 => 8WS (9 CPU cycles) */
 471         latency = LL_FLASH_LATENCY_8;
 472       }
 473       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
 474       {
 475         /* 140 < HCLK <= 160 => 7WS (8 CPU cycles) */
 476         latency = LL_FLASH_LATENCY_7;
 477       }
 478       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ)
 479       {
 480         /* 120 < HCLK <= 140 => 6WS (7 CPU cycles) */
 481         latency = LL_FLASH_LATENCY_6;
 482       }
 483       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)
 484       {
 485         /* 100 < HCLK <= 120 => 5WS (6 CPU cycles) */
 486         latency = LL_FLASH_LATENCY_5;
 487       }
 488       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)
 489       {
 490         /* 80 < HCLK <= 100 => 4WS (5 CPU cycles) */
 491         latency = LL_FLASH_LATENCY_4;
 492       }
 493       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)
 494       {
 495         /* 60 < HCLK <= 80 => 3WS (4 CPU cycles) */
 496         latency = LL_FLASH_LATENCY_3;
 497       }
 498       else if(HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)
 499       {
 500         /* 40 < HCLK <= 60 => 2WS (3 CPU cycles) */
 501         latency = LL_FLASH_LATENCY_2;
 502       }
 503       else
 504       {
 505         if(HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)
 506         {
 507           /* 20 < HCLK <= 40 => 1WS (2 CPU cycles) */
 508           latency = LL_FLASH_LATENCY_1;
 509         }
 510         /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */
 511       }
 512     }
 513     else /* SCALE2 */
 514     {
 515       if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
 516       {
 517         /* 16 < HCLK <= 26 => 2WS (3 CPU cycles) */
 518         latency = LL_FLASH_LATENCY_2;
 519       }
 520       else
 521       {
 522         if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
 523         {
 524           /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */
 525           latency = LL_FLASH_LATENCY_1;
 526         }
 527         /* else HCLK_Frequency <= 8MHz default LL_FLASH_LATENCY_0 0WS */
 528       }
 529     }
 530
 531     LL_FLASH_SetLatency(latency);
 532
 533     /* Check that the new number of wait states is taken into account to access the Flash
 534        memory by reading the FLASH_ACR register */
 535     if(LL_FLASH_GetLatency() != latency)
 536     {
 537       status = ERROR;
 538     }
 539   }
 540   return status;
 541 }
 542
 543 /**
 544   * @brief  Function to check that PLL can be modified
 545   * @param  PLL_InputFrequency  PLL input frequency (in Hz)
 546   * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
 547   *                             the configuration information for the PLL.
 548   * @retval PLL output frequency (in Hz)
 549   */
 550 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
 551 {
 552   uint32_t pllfreq;
 553
 554   /* Check the parameters */
 555   assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
 556   assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
 557   assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR));
 558
 559   /* Check different PLL parameters according to RM                          */
 560   /*  - PLLM: ensure that the VCO input frequency ranges from 2.66 to 8 MHz.   */
 561   pllfreq = PLL_InputFrequency / (((UTILS_PLLInitStruct->PLLM >> RCC_PLLCFGR_PLLM_Pos) + 1U));
 562   assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
 563
 564   /*  - PLLN: ensure that the VCO output frequency is between 64 and 344 MHz.*/
 565   pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
 566   assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
 567
 568   /*  - PLLR: ensure that max frequency at 170000000 Hz is reached                   */
 569   pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLR >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U);
 570   assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
 571
 572   return pllfreq;
 573 }
 574
 575 /**
 576   * @brief  Function to check that PLL can be modified
 577   * @retval An ErrorStatus enumeration value:
 578   *          - SUCCESS: PLL modification can be done
 579   *          - ERROR: PLL is busy
 580   */
 581 static ErrorStatus UTILS_PLL_IsBusy(void)
 582 {
 583   ErrorStatus status = SUCCESS;
 584
 585   /* Check if PLL is busy*/
 586   if(LL_RCC_PLL_IsReady() != 0U)
 587   {
 588     /* PLL configuration cannot be modified */
 589     status = ERROR;
 590   }
 591
 592   return status;
 593 }
 594
 595 /**
 596   * @brief  Function to enable PLL and switch system clock to PLL
 597   * @param  SYSCLK_Frequency SYSCLK frequency
 598   * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
 599   *                             the configuration information for the BUS prescalers.
 600   * @retval An ErrorStatus enumeration value:
 601   *          - SUCCESS: No problem to switch system to PLL
 602   *          - ERROR: Problem to switch system to PLL
 603   */
 604 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
 605 {
 606   ErrorStatus status = SUCCESS;
 607   uint32_t hclk_frequency;
 608
 609   assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
 610   assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
 611   assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
 612
 613   /* Calculate HCLK frequency */
 614   hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
 615
 616   /* Increasing the number of wait states because of higher CPU frequency */
 617   if(SystemCoreClock < hclk_frequency)
 618   {
 619     /* Set FLASH latency to highest latency */
 620     status = UTILS_SetFlashLatency(hclk_frequency);
 621   }
 622
 623   /* Update system clock configuration */
 624   if(status == SUCCESS)
 625   {
 626     /* Enable PLL */
 627     LL_RCC_PLL_Enable();
 628     LL_RCC_PLL_EnableDomain_SYS();
 629     while (LL_RCC_PLL_IsReady() != 1U)
 630     {
 631       /* Wait for PLL ready */
 632     }
 633
 634     /* Sysclk activation on the main PLL */
 635     LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
 636     LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
 637     while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
 638     {
 639       /* Wait for system clock switch to PLL */
 640     }
 641
 642     /* Set APB1 & APB2 prescaler*/
 643     LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
 644     LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
 645   }
 646
 647   /* Decreasing the number of wait states because of lower CPU frequency */
 648   if(SystemCoreClock > hclk_frequency)
 649   {
 650     /* Set FLASH latency to lowest latency */
 651     status = UTILS_SetFlashLatency(hclk_frequency);
 652   }
 653
 654   /* Update SystemCoreClock variable */
 655   if(status == SUCCESS)
 656   {
 657     LL_SetSystemCoreClock(hclk_frequency);
 658   }
 659
 660   return status;
 661 }
 662
 663 /**
 664   * @}
 665   */
 666
 667 /**
 668   * @}
 669   */
 670
 671 /**
 672   * @}
 673   */
 674
 675 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/