lib/main/STM32H7/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_dma.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32h7xx_ll_dma.c
   4   * @author  MCD Application Team
   5   * @brief   DMA LL module driver.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
  10   * All rights reserved.</center></h2>
  11   *
  12   * This software component is licensed by ST under BSD 3-Clause license,
  13   * the "License"; You may not use this file except in compliance with the
  14   * License. You may obtain a copy of the License at:
  15   *                        opensource.org/licenses/BSD-3-Clause
  16   *
  17   ******************************************************************************
  18   */
  19 #if defined(USE_FULL_LL_DRIVER)
  20
  21 /* Includes ------------------------------------------------------------------*/
  22 #include "stm32h7xx_ll_dma.h"
  23 #include "stm32h7xx_ll_bus.h"
  24
  25 /** @addtogroup STM32H7xx_LL_Driver
  26   * @{
  27   */
  28
  29 #if defined (DMA1) || defined (DMA2)
  30
  31 /** @addtogroup DMA_LL
  32   * @{
  33   */
  34
  35 /* Private types -------------------------------------------------------------*/
  36 /* Private variables ---------------------------------------------------------*/
  37 /* Private constants ---------------------------------------------------------*/
  38 /* Private macros ------------------------------------------------------------*/
  39 /** @addtogroup DMA_LL_Private_Macros
  40   * @{
  41   */
  42 #define IS_LL_DMA_DIRECTION(__VALUE__)          (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
  43                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
  44                                                  ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
  45
  46 #define IS_LL_DMA_MODE(__VALUE__)               (((__VALUE__) == LL_DMA_MODE_NORMAL)    || \
  47                                                  ((__VALUE__) == LL_DMA_MODE_CIRCULAR)  || \
  48                                                  ((__VALUE__) == LL_DMA_MODE_PFCTRL))
  49
  50 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
  51                                                  ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
  52
  53 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__)      (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
  54                                                  ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
  55
  56 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE)      || \
  57                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD)  || \
  58                                                  ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
  59
  60 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__)     (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE)      || \
  61                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
  62                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
  63
  64 #define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
  65
  66 #if defined(TIM24)
  67 #define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_TIM24_TRIG))
  68 #elif defined(ADC3)
  69 #define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_ADC3))
  70 #else
  71 #define IS_LL_DMA_REQUEST(REQUEST)              (((REQUEST)   <= LL_DMAMUX1_REQ_USART10_TX))
  72 #endif /* TIM24 */
  73
  74 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
  75                                                  ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
  76                                                  ((__VALUE__) == LL_DMA_PRIORITY_HIGH)   || \
  77                                                  ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
  78
  79 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM)   ((((INSTANCE) == DMA1) && \
  80                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
  81                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
  82                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
  83                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
  84                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
  85                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
  86                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
  87                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
  88                                                             ((STREAM) == LL_DMA_STREAM_ALL))) || \
  89                                                            (((INSTANCE) == DMA2) && \
  90                                                            (((STREAM) == LL_DMA_STREAM_0)     || \
  91                                                             ((STREAM) == LL_DMA_STREAM_1)     || \
  92                                                             ((STREAM) == LL_DMA_STREAM_2)     || \
  93                                                             ((STREAM) == LL_DMA_STREAM_3)     || \
  94                                                             ((STREAM) == LL_DMA_STREAM_4)     || \
  95                                                             ((STREAM) == LL_DMA_STREAM_5)     || \
  96                                                             ((STREAM) == LL_DMA_STREAM_6)     || \
  97                                                             ((STREAM) == LL_DMA_STREAM_7)     || \
  98                                                             ((STREAM) == LL_DMA_STREAM_ALL))))
  99
 100 #define IS_LL_DMA_FIFO_MODE_STATE(STATE)    (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
 101                                              ((STATE) == LL_DMA_FIFOMODE_ENABLE))
 102
 103 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4)  || \
 104                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2)  || \
 105                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4)  || \
 106                                              ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
 107
 108 #define IS_LL_DMA_MEMORY_BURST(BURST)       (((BURST) == LL_DMA_MBURST_SINGLE) || \
 109                                              ((BURST) == LL_DMA_MBURST_INC4)   || \
 110                                              ((BURST) == LL_DMA_MBURST_INC8)   || \
 111                                              ((BURST) == LL_DMA_MBURST_INC16))
 112
 113 #define IS_LL_DMA_PERIPHERAL_BURST(BURST)  (((BURST) == LL_DMA_PBURST_SINGLE) || \
 114                                             ((BURST) == LL_DMA_PBURST_INC4)   || \
 115                                             ((BURST) == LL_DMA_PBURST_INC8)   || \
 116                                             ((BURST) == LL_DMA_PBURST_INC16))
 117
 118 /**
 119   * @}
 120   */
 121
 122 /* Private function prototypes -----------------------------------------------*/
 123
 124 /* Exported functions --------------------------------------------------------*/
 125 /** @addtogroup DMA_LL_Exported_Functions
 126   * @{
 127   */
 128
 129 /** @addtogroup DMA_LL_EF_Init
 130   * @{
 131   */
 132
 133 /**
 134   * @brief  De-initialize the DMA registers to their default reset values.
 135   * @param  DMAx DMAx Instance
 136   * @param  Stream This parameter can be one of the following values:
 137   *         @arg @ref LL_DMA_STREAM_0
 138   *         @arg @ref LL_DMA_STREAM_1
 139   *         @arg @ref LL_DMA_STREAM_2
 140   *         @arg @ref LL_DMA_STREAM_3
 141   *         @arg @ref LL_DMA_STREAM_4
 142   *         @arg @ref LL_DMA_STREAM_5
 143   *         @arg @ref LL_DMA_STREAM_6
 144   *         @arg @ref LL_DMA_STREAM_7
 145   *         @arg @ref LL_DMA_STREAM_ALL
 146   * @retval An ErrorStatus enumeration value:
 147   *          - SUCCESS: DMA registers are de-initialized
 148   *          - ERROR: DMA registers are not de-initialized
 149   */
 150 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
 151 {
 152   DMA_Stream_TypeDef *tmp;
 153   ErrorStatus status = SUCCESS;
 154
 155   /* Check the DMA Instance DMAx and Stream parameters */
 156   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
 157
 158   if (Stream == LL_DMA_STREAM_ALL)
 159   {
 160     if (DMAx == DMA1)
 161     {
 162       /* Force reset of DMA clock */
 163       LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
 164
 165       /* Release reset of DMA clock */
 166       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
 167     }
 168     else if (DMAx == DMA2)
 169     {
 170       /* Force reset of DMA clock */
 171        LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
 172
 173       /* Release reset of DMA clock */
 174       LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
 175     }
 176     else
 177     {
 178       status = ERROR;
 179     }
 180   }
 181   else
 182   {
 183     /* Disable the selected Stream */
 184     LL_DMA_DisableStream(DMAx, Stream);
 185
 186     /* Get the DMA Stream Instance */
 187     tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
 188
 189     /* Reset DMAx_Streamy configuration register */
 190     LL_DMA_WriteReg(tmp, CR, 0U);
 191
 192     /* Reset DMAx_Streamy remaining bytes register */
 193     LL_DMA_WriteReg(tmp, NDTR, 0U);
 194
 195     /* Reset DMAx_Streamy peripheral address register */
 196     LL_DMA_WriteReg(tmp, PAR, 0U);
 197
 198     /* Reset DMAx_Streamy memory address register */
 199     LL_DMA_WriteReg(tmp, M0AR, 0U);
 200
 201     /* Reset DMAx_Streamy memory address register */
 202     LL_DMA_WriteReg(tmp, M1AR, 0U);
 203
 204     /* Reset DMAx_Streamy FIFO control register */
 205     LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
 206
 207     /* Reset Channel register field for DMAx Stream */
 208     LL_DMA_SetPeriphRequest(DMAx, Stream, LL_DMAMUX1_REQ_MEM2MEM);
 209
 210     if (Stream == LL_DMA_STREAM_0)
 211     {
 212       /* Reset the Stream0 pending flags */
 213       DMAx->LIFCR = 0x0000003FU;
 214     }
 215     else if (Stream == LL_DMA_STREAM_1)
 216     {
 217       /* Reset the Stream1 pending flags */
 218       DMAx->LIFCR = 0x00000F40U;
 219     }
 220     else if (Stream == LL_DMA_STREAM_2)
 221     {
 222       /* Reset the Stream2 pending flags */
 223       DMAx->LIFCR = 0x003F0000U;
 224     }
 225     else if (Stream == LL_DMA_STREAM_3)
 226     {
 227       /* Reset the Stream3 pending flags */
 228       DMAx->LIFCR = 0x0F400000U;
 229     }
 230     else if (Stream == LL_DMA_STREAM_4)
 231     {
 232       /* Reset the Stream4 pending flags */
 233       DMAx->HIFCR = 0x0000003FU;
 234     }
 235     else if (Stream == LL_DMA_STREAM_5)
 236     {
 237       /* Reset the Stream5 pending flags */
 238       DMAx->HIFCR = 0x00000F40U;
 239     }
 240     else if (Stream == LL_DMA_STREAM_6)
 241     {
 242       /* Reset the Stream6 pending flags */
 243       DMAx->HIFCR = 0x003F0000U;
 244     }
 245     else if (Stream == LL_DMA_STREAM_7)
 246     {
 247       /* Reset the Stream7 pending flags */
 248       DMAx->HIFCR = 0x0F400000U;
 249     }
 250     else
 251     {
 252       status = ERROR;
 253     }
 254   }
 255
 256   return (uint32_t)status;
 257 }
 258
 259 /**
 260   * @brief  Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
 261   * @note   To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
 262   *         @arg @ref __LL_DMA_GET_INSTANCE
 263   *         @arg @ref __LL_DMA_GET_STREAM
 264   * @param  DMAx DMAx Instance
 265   * @param  Stream This parameter can be one of the following values:
 266   *         @arg @ref LL_DMA_STREAM_0
 267   *         @arg @ref LL_DMA_STREAM_1
 268   *         @arg @ref LL_DMA_STREAM_2
 269   *         @arg @ref LL_DMA_STREAM_3
 270   *         @arg @ref LL_DMA_STREAM_4
 271   *         @arg @ref LL_DMA_STREAM_5
 272   *         @arg @ref LL_DMA_STREAM_6
 273   *         @arg @ref LL_DMA_STREAM_7
 274   * @param  DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
 275   * @retval An ErrorStatus enumeration value:
 276   *          - SUCCESS: DMA registers are initialized
 277   *          - ERROR: Not applicable
 278   */
 279 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
 280 {
 281   /* Check the DMA Instance DMAx and Stream parameters */
 282   assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
 283
 284   /* Check the DMA parameters from DMA_InitStruct */
 285   assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
 286   assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
 287   assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
 288   assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
 289   assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
 290   assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
 291   assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
 292   assert_param(IS_LL_DMA_REQUEST(DMA_InitStruct->PeriphRequest));
 293   assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
 294   assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
 295
 296   /* Check the memory burst, peripheral burst and FIFO threshold parameters only
 297      when FIFO mode is enabled */
 298   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
 299   {
 300     assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
 301     assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
 302     assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
 303   }
 304
 305   /*---------------------------- DMAx SxCR Configuration ------------------------
 306    * Configure DMAx_Streamy: data transfer direction, data transfer mode,
 307    *                          peripheral and memory increment mode,
 308    *                          data size alignment and  priority level with parameters :
 309    * - Direction:      DMA_SxCR_DIR[1:0] bits
 310    * - Mode:           DMA_SxCR_CIRC bit
 311    * - PeriphOrM2MSrcIncMode:  DMA_SxCR_PINC bit
 312    * - MemoryOrM2MDstIncMode:  DMA_SxCR_MINC bit
 313    * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
 314    * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
 315    * - Priority:               DMA_SxCR_PL[1:0] bits
 316    */
 317   LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
 318                         DMA_InitStruct->Mode                    | \
 319                         DMA_InitStruct->PeriphOrM2MSrcIncMode   | \
 320                         DMA_InitStruct->MemoryOrM2MDstIncMode   | \
 321                         DMA_InitStruct->PeriphOrM2MSrcDataSize  | \
 322                         DMA_InitStruct->MemoryOrM2MDstDataSize  | \
 323                         DMA_InitStruct->Priority
 324                        );
 325
 326   if (DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
 327   {
 328     /*---------------------------- DMAx SxFCR Configuration ------------------------
 329      * Configure DMAx_Streamy:  fifo mode and fifo threshold with parameters :
 330      * - FIFOMode:                DMA_SxFCR_DMDIS bit
 331      * - FIFOThreshold:           DMA_SxFCR_FTH[1:0] bits
 332      */
 333     LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
 334
 335     /*---------------------------- DMAx SxCR Configuration --------------------------
 336      * Configure DMAx_Streamy:  memory burst transfer with parameters :
 337      * - MemBurst:                DMA_SxCR_MBURST[1:0] bits
 338      */
 339     LL_DMA_SetMemoryBurstxfer(DMAx, Stream, DMA_InitStruct->MemBurst);
 340
 341     /*---------------------------- DMAx SxCR Configuration --------------------------
 342      * Configure DMAx_Streamy:  peripheral burst transfer with parameters :
 343      * - PeriphBurst:             DMA_SxCR_PBURST[1:0] bits
 344      */
 345     LL_DMA_SetPeriphBurstxfer(DMAx, Stream, DMA_InitStruct->PeriphBurst);
 346   }
 347
 348   /*-------------------------- DMAx SxM0AR Configuration --------------------------
 349    * Configure the memory or destination base address with parameter :
 350    * - MemoryOrM2MDstAddress:     DMA_SxM0AR_M0A[31:0] bits
 351    */
 352   LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
 353
 354   /*-------------------------- DMAx SxPAR Configuration ---------------------------
 355    * Configure the peripheral or source base address with parameter :
 356    * - PeriphOrM2MSrcAddress:     DMA_SxPAR_PA[31:0] bits
 357    */
 358   LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
 359
 360   /*--------------------------- DMAx SxNDTR Configuration -------------------------
 361    * Configure the peripheral base address with parameter :
 362    * - NbData:                    DMA_SxNDT[15:0] bits
 363    */
 364   LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
 365
 366   /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
 367    * Configure the peripheral base address with parameter :
 368    * - PeriphRequest:             DMA_SxCR_CHSEL[3:0] bits
 369    */
 370   LL_DMA_SetPeriphRequest(DMAx, Stream, DMA_InitStruct->PeriphRequest);
 371
 372   return (uint32_t)SUCCESS;
 373 }
 374
 375 /**
 376   * @brief  Set each @ref LL_DMA_InitTypeDef field to default value.
 377   * @param  DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
 378   * @retval None
 379   */
 380 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 381 {
 382   /* Set DMA_InitStruct fields to default values */
 383   DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
 384   DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
 385   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
 386   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
 387   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
 388   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
 389   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
 390   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
 391   DMA_InitStruct->NbData                 = 0x00000000U;
 392   DMA_InitStruct->PeriphRequest          = LL_DMAMUX1_REQ_MEM2MEM;
 393   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
 394   DMA_InitStruct->FIFOMode               = LL_DMA_FIFOMODE_DISABLE;
 395   DMA_InitStruct->FIFOThreshold          = LL_DMA_FIFOTHRESHOLD_1_4;
 396   DMA_InitStruct->MemBurst               = LL_DMA_MBURST_SINGLE;
 397   DMA_InitStruct->PeriphBurst            = LL_DMA_PBURST_SINGLE;
 398 }
 399
 400 /**
 401   * @}
 402   */
 403
 404 /**
 405   * @}
 406   */
 407
 408 /**
 409   * @}
 410   */
 411
 412 #endif /* DMA1 || DMA2 */
 413
 414 /**
 415   * @}
 416   */
 417
 418 #endif /* USE_FULL_LL_DRIVER */
 419
 420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/