src/platform/AT32/platform_mcu.h

   1 /*
   2  * This file is part of Betaflight.
   3  *
   4  * Betaflight is free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Betaflight is distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #pragma once
  22
  23 #if defined(AT32F435)
  24
  25 #include "at32f435_437.h"
  26 #include "at32f435_437_i2c.h"
  27 #include "i2c_application.h"
  28
  29 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
  30
  31 #define I2C_TypeDef         i2c_type
  32 #define I2C_HandleTypeDef   i2c_handle_type
  33 #define GPIO_TypeDef        gpio_type
  34 #define GPIO_InitTypeDef    gpio_init_type
  35 #define TIM_TypeDef         tmr_type
  36 #define TIM_OCInitTypeDef   tmr_output_config_type
  37 #define DMA_TypeDef         dma_type
  38 #define DMA_InitTypeDef     dma_init_type
  39 #define DMA_Channel_TypeDef dma_channel_type
  40 #define SPI_TypeDef         spi_type
  41 #define ADC_TypeDef         adc_type
  42 #define USART_TypeDef       usart_type
  43 #define TIM_OCInitTypeDef   tmr_output_config_type
  44 #define TIM_ICInitTypeDef   tmr_input_config_type
  45 #define TIM_OCStructInit    tmr_output_default_para_init
  46 #define TIM_Cmd             tmr_counter_enable
  47 #define TIM_CtrlPWMOutputs  tmr_output_enable
  48 #define TIM_TimeBaseInit    tmr_base_init
  49 #define TIM_ARRPreloadConfig tmr_period_buffer_enable
  50 #define SystemCoreClock     system_core_clock
  51 #define EXTI_TypeDef        exint_type
  52 #define EXTI_InitTypeDef    exint_init_type
  53 #define USART_TypeDef       usart_type
  54
  55 // Chip Unique ID on F43X
  56 #define U_ID_0 (*(uint32_t*)0x1ffff7e8)
  57 #define U_ID_1 (*(uint32_t*)0x1ffff7ec)
  58 #define U_ID_2 (*(uint32_t*)0x1ffff7f0)
  59
  60 #define USE_PIN_AF
  61
  62 #ifndef AT32F4
  63 #define AT32F4
  64 #endif
  65
  66 #define SET_BIT(REG, BIT)     ((REG) |= (BIT))
  67 #define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
  68 #define READ_BIT(REG, BIT)    ((REG) & (BIT))
  69 #define CLEAR_REG(REG)        ((REG) = (0x0))
  70 #define WRITE_REG(REG, VAL)   ((REG) = (VAL))
  71 #define READ_REG(REG)         ((REG))
  72 #define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
  73
  74 #endif
  75
  76 #define USE_USB_MSC
  77
  78 #define USE_TIMER_MGMT
  79 #define USE_TIMER_AF
  80 #define USE_DMA_SPEC
  81 #define USE_PERSISTENT_OBJECTS
  82 #define USE_ADC_INTERNAL
  83
  84 #define USE_LATE_TASK_STATISTICS
  85
  86 #define TASK_GYROPID_DESIRED_PERIOD     1000 // 1000us = 1kHz
  87 #define SCHEDULER_DELAY_LIMIT           100
  88
  89 #define DEFAULT_CPU_OVERCLOCK 0
  90 #define FAST_IRQ_HANDLER FAST_CODE
  91
  92 #define DMA_DATA_ZERO_INIT
  93 #define DMA_DATA
  94 #define STATIC_DMA_DATA_AUTO        static
  95
  96 #define DMA_RAM
  97 #define DMA_RW_AXI
  98 #define DMA_RAM_R
  99 #define DMA_RAM_W
 100 #define DMA_RAM_RW
 101
 102 #define USE_LATE_TASK_STATISTICS
 103
 104 #define USE_RPM_FILTER
 105 #define USE_DYN_IDLE
 106 #define USE_DYN_NOTCH_FILTER