src/main/drivers/dma_stm32g4xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <stdbool.h>
  22 #include <stdint.h>
  23 #include <string.h>
  24
  25 #include "platform.h"
  26
  27 #ifdef USE_DMA
  28
  29 #include "drivers/nvic.h"
  30 #include "drivers/dma.h"
  31 #include "drivers/rcc.h"
  32 #include "resource.h"
  33
  34 /*
  35  * DMA descriptors.
  36  */
  37 dmaChannelDescriptor_t dmaDescriptors[DMA_LAST_HANDLER] = {
  38     DEFINE_DMA_CHANNEL(DMA1, 1,  0),
  39     DEFINE_DMA_CHANNEL(DMA1, 2,  4),
  40     DEFINE_DMA_CHANNEL(DMA1, 3,  8),
  41     DEFINE_DMA_CHANNEL(DMA1, 4, 12),
  42     DEFINE_DMA_CHANNEL(DMA1, 5, 16),
  43     DEFINE_DMA_CHANNEL(DMA1, 6, 20),
  44     DEFINE_DMA_CHANNEL(DMA1, 7, 24),
  45     DEFINE_DMA_CHANNEL(DMA1, 8, 28),
  46
  47     DEFINE_DMA_CHANNEL(DMA2, 1,  0),
  48     DEFINE_DMA_CHANNEL(DMA2, 2,  4),
  49     DEFINE_DMA_CHANNEL(DMA2, 3,  8),
  50     DEFINE_DMA_CHANNEL(DMA2, 4, 12),
  51     DEFINE_DMA_CHANNEL(DMA2, 5, 16),
  52     DEFINE_DMA_CHANNEL(DMA2, 6, 20),
  53     DEFINE_DMA_CHANNEL(DMA2, 7, 24),
  54     DEFINE_DMA_CHANNEL(DMA2, 8, 28),
  55 };
  56
  57 /*
  58  * DMA IRQ Handlers
  59  */
  60 DEFINE_DMA_IRQ_HANDLER(1, 1, DMA1_CH1_HANDLER)
  61 DEFINE_DMA_IRQ_HANDLER(1, 2, DMA1_CH2_HANDLER)
  62 DEFINE_DMA_IRQ_HANDLER(1, 3, DMA1_CH3_HANDLER)
  63 DEFINE_DMA_IRQ_HANDLER(1, 4, DMA1_CH4_HANDLER)
  64 DEFINE_DMA_IRQ_HANDLER(1, 5, DMA1_CH5_HANDLER)
  65 DEFINE_DMA_IRQ_HANDLER(1, 6, DMA1_CH6_HANDLER)
  66 DEFINE_DMA_IRQ_HANDLER(1, 7, DMA1_CH7_HANDLER)
  67 DEFINE_DMA_IRQ_HANDLER(1, 8, DMA1_CH8_HANDLER)
  68 DEFINE_DMA_IRQ_HANDLER(2, 1, DMA2_CH1_HANDLER)
  69 DEFINE_DMA_IRQ_HANDLER(2, 2, DMA2_CH2_HANDLER)
  70 DEFINE_DMA_IRQ_HANDLER(2, 3, DMA2_CH3_HANDLER)
  71 DEFINE_DMA_IRQ_HANDLER(2, 4, DMA2_CH4_HANDLER)
  72 DEFINE_DMA_IRQ_HANDLER(2, 5, DMA2_CH5_HANDLER)
  73 DEFINE_DMA_IRQ_HANDLER(2, 6, DMA2_CH6_HANDLER)
  74 DEFINE_DMA_IRQ_HANDLER(2, 7, DMA2_CH7_HANDLER)
  75 DEFINE_DMA_IRQ_HANDLER(2, 8, DMA2_CH8_HANDLER)
  76
  77 static void enableDmaClock(int index)
  78 {
  79     RCC_ClockCmd(dmaDescriptors[index].dma == DMA1 ?  RCC_AHB1(DMA1) : RCC_AHB1(DMA2), ENABLE);
  80     // G4 has an independent enable bit for DMAMUX
  81     RCC_ClockCmd(RCC_AHB1(DMAMUX1), ENABLE);
  82 }
  83
  84 void dmaEnable(dmaIdentifier_e identifier)
  85 {
  86     const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
  87
  88     enableDmaClock(index);
  89 }
  90
  91 void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam)
  92 {
  93     const int index = DMA_IDENTIFIER_TO_INDEX(identifier);
  94
  95     enableDmaClock(index);
  96     dmaDescriptors[index].irqHandlerCallback = callback;
  97     dmaDescriptors[index].userParam = userParam;
  98
  99     HAL_NVIC_SetPriority(dmaDescriptors[index].irqN, NVIC_PRIORITY_BASE(priority), NVIC_PRIORITY_SUB(priority));
 100     HAL_NVIC_EnableIRQ(dmaDescriptors[index].irqN);
 101 }
 102 #endif