src/main/drivers/system_stm32f4xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <stdbool.h>
  22 #include <stdint.h>
  23
  24 #include "platform.h"
  25
  26 #include "drivers/accgyro/accgyro_mpu.h"
  27 #include "drivers/exti.h"
  28 #include "drivers/nvic.h"
  29 #include "drivers/system.h"
  30 #include "drivers/persistent.h"
  31
  32
  33 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
  34 void SetSysClock(void);
  35
  36 void systemReset(void)
  37 {
  38     __disable_irq();
  39     NVIC_SystemReset();
  40 }
  41
  42 void systemResetToBootloader(bootloaderRequestType_e requestType)
  43 {
  44     switch (requestType) {
  45     case BOOTLOADER_REQUEST_ROM:
  46     default:
  47         persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_BOOTLOADER_REQUEST_ROM);
  48
  49         break;
  50     }
  51
  52     __disable_irq();
  53     NVIC_SystemReset();
  54 }
  55
  56 typedef void resetHandler_t(void);
  57
  58 typedef struct isrVector_s {
  59     __I uint32_t    stackEnd;
  60     resetHandler_t *resetHandler;
  61 } isrVector_t;
  62
  63 // Used in the startup files for F4
  64 void checkForBootLoaderRequest(void)
  65 {
  66     uint32_t bootloaderRequest = persistentObjectRead(PERSISTENT_OBJECT_RESET_REASON);
  67
  68     if (bootloaderRequest != RESET_BOOTLOADER_REQUEST_ROM) {
  69         return;
  70     }
  71     persistentObjectWrite(PERSISTENT_OBJECT_RESET_REASON, RESET_NONE);
  72
  73     extern isrVector_t system_isr_vector_table_base;
  74
  75     __set_MSP(system_isr_vector_table_base.stackEnd);
  76     system_isr_vector_table_base.resetHandler();
  77     while (1);
  78 }
  79
  80 void enableGPIOPowerUsageAndNoiseReductions(void)
  81 {
  82
  83     RCC_AHB1PeriphClockCmd(
  84         RCC_AHB1Periph_SRAM1 |
  85         RCC_AHB1Periph_SRAM2 |
  86         RCC_AHB1Periph_BKPSRAM |
  87         RCC_AHB1Periph_DMA1 |
  88         RCC_AHB1Periph_DMA2 |
  89         0, ENABLE
  90     );
  91
  92     RCC_AHB2PeriphClockCmd(0, ENABLE);
  93 #ifdef STM32F40_41xxx
  94     RCC_AHB3PeriphClockCmd(0, ENABLE);
  95 #endif
  96     RCC_APB1PeriphClockCmd(
  97         RCC_APB1Periph_TIM2 |
  98         RCC_APB1Periph_TIM3 |
  99         RCC_APB1Periph_TIM4 |
 100         RCC_APB1Periph_TIM5 |
 101         RCC_APB1Periph_TIM6 |
 102         RCC_APB1Periph_TIM7 |
 103         RCC_APB1Periph_TIM12 |
 104         RCC_APB1Periph_TIM13 |
 105         RCC_APB1Periph_TIM14 |
 106         RCC_APB1Periph_WWDG |
 107         RCC_APB1Periph_SPI2 |
 108         RCC_APB1Periph_SPI3 |
 109         RCC_APB1Periph_USART2 |
 110         RCC_APB1Periph_USART3 |
 111         RCC_APB1Periph_UART4 |
 112         RCC_APB1Periph_UART5 |
 113         RCC_APB1Periph_I2C1 |
 114         RCC_APB1Periph_I2C2 |
 115         RCC_APB1Periph_I2C3 |
 116         RCC_APB1Periph_CAN1 |
 117         RCC_APB1Periph_CAN2 |
 118         RCC_APB1Periph_PWR |
 119         RCC_APB1Periph_DAC |
 120         0, ENABLE);
 121
 122     RCC_APB2PeriphClockCmd(
 123         RCC_APB2Periph_TIM1 |
 124         RCC_APB2Periph_TIM8 |
 125         RCC_APB2Periph_USART1 |
 126         RCC_APB2Periph_USART6 |
 127         RCC_APB2Periph_ADC |
 128         RCC_APB2Periph_ADC1 |
 129         RCC_APB2Periph_ADC2 |
 130         RCC_APB2Periph_ADC3 |
 131         RCC_APB2Periph_SDIO |
 132         RCC_APB2Periph_SPI1 |
 133         RCC_APB2Periph_SYSCFG |
 134         RCC_APB2Periph_TIM9 |
 135         RCC_APB2Periph_TIM10 |
 136         RCC_APB2Periph_TIM11 |
 137         0, ENABLE);
 138 }
 139
 140 bool isMPUSoftReset(void)
 141 {
 142     if (cachedRccCsrValue & RCC_CSR_SFTRSTF)
 143         return true;
 144     else
 145         return false;
 146 }
 147
 148 void systemInit(void)
 149 {
 150     SetSysClock();
 151
 152     // Configure NVIC preempt/priority groups
 153     NVIC_PriorityGroupConfig(NVIC_PRIORITY_GROUPING);
 154
 155     // cache RCC->CSR value to use it in isMPUSoftReset() and others
 156     cachedRccCsrValue = RCC->CSR;
 157
 158     // Although VTOR is already loaded with a possible vector table in RAM,
 159     // removing the call to NVIC_SetVectorTable causes USB not to become active,
 160
 161     extern uint8_t isr_vector_table_base;
 162     NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
 163
 164     RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, DISABLE);
 165
 166     RCC_ClearFlag();
 167
 168     enableGPIOPowerUsageAndNoiseReductions();
 169
 170     // Init cycle counter
 171     cycleCounterInit();
 172
 173     // SysTick
 174     SysTick_Config(SystemCoreClock / 1000);
 175 }