src/main/drivers/timer_stm32g4xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22
  23 #ifdef USE_TIMER
  24
  25 #include "common/utils.h"
  26
  27 #include "drivers/dma.h"
  28 #include "drivers/io.h"
  29 #include "drivers/timer_def.h"
  30
  31 #include "stm32g4xx.h"
  32 #include "rcc.h"
  33 #include "timer.h"
  34
  35
  36 const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
  37     { .TIMx = TIM1,  .rcc = RCC_APB2(TIM1),  .inputIrq = TIM1_CC_IRQn},
  38     { .TIMx = TIM2,  .rcc = RCC_APB11(TIM2), .inputIrq = TIM2_IRQn},
  39     { .TIMx = TIM3,  .rcc = RCC_APB11(TIM3), .inputIrq = TIM3_IRQn},
  40     { .TIMx = TIM4,  .rcc = RCC_APB11(TIM4), .inputIrq = TIM4_IRQn},
  41     { .TIMx = TIM5,  .rcc = RCC_APB11(TIM5), .inputIrq = TIM5_IRQn},
  42     { .TIMx = TIM6,  .rcc = RCC_APB11(TIM6), .inputIrq = TIM6_DAC_IRQn},
  43     { .TIMx = TIM7,  .rcc = RCC_APB11(TIM7), .inputIrq = TIM7_DAC_IRQn},
  44     { .TIMx = TIM8,  .rcc = RCC_APB2(TIM8),  .inputIrq = TIM8_CC_IRQn},
  45     { .TIMx = TIM15, .rcc = RCC_APB2(TIM15), .inputIrq = TIM1_BRK_TIM15_IRQn},
  46     { .TIMx = TIM16, .rcc = RCC_APB2(TIM16), .inputIrq = TIM1_UP_TIM16_IRQn},
  47     { .TIMx = TIM17, .rcc = RCC_APB2(TIM17), .inputIrq = TIM1_TRG_COM_TIM17_IRQn},
  48     { .TIMx = TIM20, .rcc = RCC_APB2(TIM20), .inputIrq = TIM20_CC_IRQn},
  49 };
  50
  51 #if defined(USE_TIMER_MGMT)
  52 const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
  53     // Auto-generated from 'timer_def.h'
  54 // Port A
  55     DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
  56     DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
  57     DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
  58     DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
  59     DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
  60     DEF_TIM(TIM16, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
  61     DEF_TIM(TIM17, CH1, PA7, TIM_USE_ANY, 0, 0, 0),
  62     DEF_TIM(TIM16, CH1, PA12, TIM_USE_ANY, 0, 0, 0),
  63     DEF_TIM(TIM16, CH1N, PA13, TIM_USE_ANY, 0, 0, 0),
  64     DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
  65
  66     DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
  67     DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
  68     DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
  69     DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
  70     DEF_TIM(TIM3, CH2, PA4, TIM_USE_ANY, 0, 0, 0),
  71     DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
  72     DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
  73     DEF_TIM(TIM8, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
  74
  75     DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
  76
  77     DEF_TIM(TIM8, CH2, PA14, TIM_USE_ANY, 0, 0, 0),
  78
  79     DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
  80     DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
  81     DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
  82     DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
  83     DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0, 0),
  84     DEF_TIM(TIM1, CH2N, PA12, TIM_USE_ANY, 0, 0, 0),
  85
  86     DEF_TIM(TIM15, CH1N, PA1, TIM_USE_ANY, 0, 0, 0),
  87     DEF_TIM(TIM15, CH1, PA2, TIM_USE_ANY, 0, 0, 0),
  88     DEF_TIM(TIM15, CH2, PA3, TIM_USE_ANY, 0, 0, 0),
  89
  90     DEF_TIM(TIM2, CH3, PA9, TIM_USE_ANY, 0, 0, 0),
  91     DEF_TIM(TIM2, CH4, PA10, TIM_USE_ANY, 0, 0, 0),
  92     DEF_TIM(TIM4, CH1, PA11, TIM_USE_ANY, 0, 0, 0),
  93     DEF_TIM(TIM4, CH2, PA12, TIM_USE_ANY, 0, 0, 0),
  94     DEF_TIM(TIM4, CH3, PA13, TIM_USE_ANY, 0, 0, 0),
  95
  96     DEF_TIM(TIM1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
  97
  98 // Port B
  99     DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
 100     DEF_TIM(TIM16, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
 101     DEF_TIM(TIM16, CH1N, PB6, TIM_USE_ANY, 0, 0, 0),
 102     DEF_TIM(TIM17, CH1N, PB7, TIM_USE_ANY, 0, 0, 0),
 103     DEF_TIM(TIM16, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
 104     DEF_TIM(TIM17, CH1, PB9, TIM_USE_ANY, 0, 0, 0),
 105     DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
 106     DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
 107     DEF_TIM(TIM15, CH1, PB14, TIM_USE_ANY, 0, 0, 0),
 108     DEF_TIM(TIM15, CH2, PB15, TIM_USE_ANY, 0, 0, 0),
 109
 110     DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
 111     DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
 112     DEF_TIM(TIM5, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
 113     DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
 114     DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
 115     DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
 116     DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0, 0),
 117     DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0, 0),
 118     DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0, 0),
 119     DEF_TIM(TIM15, CH1N, PB15, TIM_USE_ANY, 0, 0, 0),
 120
 121     DEF_TIM(TIM20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
 122     DEF_TIM(TIM8, CH3N, PB5, TIM_USE_ANY, 0, 0, 0),
 123
 124     DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
 125     DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
 126     DEF_TIM(TIM8, CH1N, PB3, TIM_USE_ANY, 0, 0, 0),
 127     DEF_TIM(TIM8, CH2N, PB4, TIM_USE_ANY, 0, 0, 0),
 128     DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
 129
 130     DEF_TIM(TIM8, CH1, PB6, TIM_USE_ANY, 0, 0, 0),
 131
 132     DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
 133     DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
 134     DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
 135     DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
 136
 137     DEF_TIM(TIM17, CH1, PB5, TIM_USE_ANY, 0, 0, 0),
 138     DEF_TIM(TIM3, CH4, PB7, TIM_USE_ANY, 0, 0, 0),
 139     DEF_TIM(TIM8, CH2, PB8, TIM_USE_ANY, 0, 0, 0),
 140     DEF_TIM(TIM8, CH3, PB9, TIM_USE_ANY, 0, 0, 0),
 141
 142     DEF_TIM(TIM1, CH3N, PB9, TIM_USE_ANY, 0, 0, 0),
 143
 144 // Port C
 145     DEF_TIM(TIM5, CH2, PC12, TIM_USE_ANY, 0, 0, 0),
 146
 147     DEF_TIM(TIM1, CH1, PC0, TIM_USE_ANY, 0, 0, 0),
 148     DEF_TIM(TIM1, CH2, PC1, TIM_USE_ANY, 0, 0, 0),
 149     DEF_TIM(TIM1, CH3, PC2, TIM_USE_ANY, 0, 0, 0),
 150     DEF_TIM(TIM1, CH4, PC3, TIM_USE_ANY, 0, 0, 0),
 151     DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
 152     DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
 153     DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
 154     DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
 155
 156     DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
 157     DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
 158     DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
 159     DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
 160     DEF_TIM(TIM8, CH1N, PC10, TIM_USE_ANY, 0, 0, 0),
 161     DEF_TIM(TIM8, CH2N, PC11, TIM_USE_ANY, 0, 0, 0),
 162     DEF_TIM(TIM8, CH3N, PC12, TIM_USE_ANY, 0, 0, 0),
 163     DEF_TIM(TIM1, CH1N, PC13, TIM_USE_ANY, 0, 0, 0),
 164
 165     DEF_TIM(TIM20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
 166     DEF_TIM(TIM1, CH4N, PC5, TIM_USE_ANY, 0, 0, 0),
 167     DEF_TIM(TIM20, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
 168     DEF_TIM(TIM8, CH4N, PC13, TIM_USE_ANY, 0, 0, 0),
 169 };
 170 #endif
 171
 172 uint32_t timerClock(TIM_TypeDef *tim)
 173 {
 174     /*
 175      * RM0440 Rev.1
 176      * 6.2.13 Timer clock
 177      * The timer clock frequencies are automatically defined by hardware. There are two cases:
 178      * 1. If the APB prescaler equals 1, the timer clock frequencies are set to the same frequency as that of the APB domain.
 179      * 2. Otherwise, they are set to twice (×2) the frequency of the APB domain.
 180      */
 181
 182     uint32_t pclk;
 183
 184     if (tim == TIM1 || tim == TIM8 || tim == TIM15 || tim == TIM16 || tim == TIM17 || tim == TIM20) {
 185         // Timers on APB2; PCLK2
 186         pclk = HAL_RCC_GetPCLK2Freq();
 187         if (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)) {
 188             pclk *= 2;
 189         }
 190     } else {
 191         // Timers on APB1; PCLK1
 192         pclk = HAL_RCC_GetPCLK1Freq();
 193         if (READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)) {
 194             pclk *= 2;
 195         }
 196     }
 197
 198     return pclk;
 199 }
 200 #endif