lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/syscfg.h

   1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
   2
   3 /**
   4  * Copyright (c) 2024 Raspberry Pi Ltd.
   5  *
   6  * SPDX-License-Identifier: BSD-3-Clause
   7  */
   8 // =============================================================================
   9 // Register block : SYSCFG
  10 // Version        : 1
  11 // Bus type       : apb
  12 // Description    : Register block for various chip control signals
  13 // =============================================================================
  14 #ifndef _HARDWARE_REGS_SYSCFG_H
  15 #define _HARDWARE_REGS_SYSCFG_H
  16 // =============================================================================
  17 // Register    : SYSCFG_PROC_CONFIG
  18 // Description : Configuration for processors
  19 #define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000)
  20 #define SYSCFG_PROC_CONFIG_BITS   _u(0x00000003)
  21 #define SYSCFG_PROC_CONFIG_RESET  _u(0x00000000)
  22 // -----------------------------------------------------------------------------
  23 // Field       : SYSCFG_PROC_CONFIG_PROC1_HALTED
  24 // Description : Indication that proc1 has halted
  25 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET  _u(0x0)
  26 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS   _u(0x00000002)
  27 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB    _u(1)
  28 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB    _u(1)
  29 #define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
  30 // -----------------------------------------------------------------------------
  31 // Field       : SYSCFG_PROC_CONFIG_PROC0_HALTED
  32 // Description : Indication that proc0 has halted
  33 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET  _u(0x0)
  34 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS   _u(0x00000001)
  35 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB    _u(0)
  36 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB    _u(0)
  37 #define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
  38 // =============================================================================
  39 // Register    : SYSCFG_PROC_IN_SYNC_BYPASS
  40 // Description : For each bit, if 1, bypass the input synchronizer between that
  41 //               GPIO
  42 //               and the GPIO input register in the SIO. The input synchronizers
  43 //               should
  44 //               generally be unbypassed, to avoid injecting metastabilities
  45 //               into processors.
  46 //               If you're feeling brave, you can bypass to save two cycles of
  47 //               input
  48 //               latency. This register applies to GPIO 0...31.
  49 #define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004)
  50 #define SYSCFG_PROC_IN_SYNC_BYPASS_BITS   _u(0xffffffff)
  51 #define SYSCFG_PROC_IN_SYNC_BYPASS_RESET  _u(0x00000000)
  52 // -----------------------------------------------------------------------------
  53 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO
  54 #define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET  _u(0x00000000)
  55 #define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS   _u(0xffffffff)
  56 #define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB    _u(31)
  57 #define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB    _u(0)
  58 #define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW"
  59 // =============================================================================
  60 // Register    : SYSCFG_PROC_IN_SYNC_BYPASS_HI
  61 // Description : For each bit, if 1, bypass the input synchronizer between that
  62 //               GPIO
  63 //               and the GPIO input register in the SIO. The input synchronizers
  64 //               should
  65 //               generally be unbypassed, to avoid injecting metastabilities
  66 //               into processors.
  67 //               If you're feeling brave, you can bypass to save two cycles of
  68 //               input
  69 //               latency. This register applies to GPIO 32...47. USB GPIO 56..57
  70 //               QSPI GPIO 58..63
  71 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008)
  72 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS   _u(0xff00ffff)
  73 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET  _u(0x00000000)
  74 // -----------------------------------------------------------------------------
  75 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD
  76 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET  _u(0x0)
  77 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS   _u(0xf0000000)
  78 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB    _u(31)
  79 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB    _u(28)
  80 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW"
  81 // -----------------------------------------------------------------------------
  82 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN
  83 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET  _u(0x0)
  84 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS   _u(0x08000000)
  85 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB    _u(27)
  86 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB    _u(27)
  87 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW"
  88 // -----------------------------------------------------------------------------
  89 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK
  90 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET  _u(0x0)
  91 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS   _u(0x04000000)
  92 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB    _u(26)
  93 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB    _u(26)
  94 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW"
  95 // -----------------------------------------------------------------------------
  96 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM
  97 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET  _u(0x0)
  98 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS   _u(0x02000000)
  99 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB    _u(25)
 100 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB    _u(25)
 101 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW"
 102 // -----------------------------------------------------------------------------
 103 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP
 104 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET  _u(0x0)
 105 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS   _u(0x01000000)
 106 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB    _u(24)
 107 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB    _u(24)
 108 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW"
 109 // -----------------------------------------------------------------------------
 110 // Field       : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO
 111 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET  _u(0x0000)
 112 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS   _u(0x0000ffff)
 113 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB    _u(15)
 114 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB    _u(0)
 115 #define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW"
 116 // =============================================================================
 117 // Register    : SYSCFG_DBGFORCE
 118 // Description : Directly control the chip SWD debug port
 119 #define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c)
 120 #define SYSCFG_DBGFORCE_BITS   _u(0x0000000f)
 121 #define SYSCFG_DBGFORCE_RESET  _u(0x00000006)
 122 // -----------------------------------------------------------------------------
 123 // Field       : SYSCFG_DBGFORCE_ATTACH
 124 // Description : Attach chip debug port to syscfg controls, and disconnect it
 125 //               from external SWD pads.
 126 #define SYSCFG_DBGFORCE_ATTACH_RESET  _u(0x0)
 127 #define SYSCFG_DBGFORCE_ATTACH_BITS   _u(0x00000008)
 128 #define SYSCFG_DBGFORCE_ATTACH_MSB    _u(3)
 129 #define SYSCFG_DBGFORCE_ATTACH_LSB    _u(3)
 130 #define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW"
 131 // -----------------------------------------------------------------------------
 132 // Field       : SYSCFG_DBGFORCE_SWCLK
 133 // Description : Directly drive SWCLK, if ATTACH is set
 134 #define SYSCFG_DBGFORCE_SWCLK_RESET  _u(0x1)
 135 #define SYSCFG_DBGFORCE_SWCLK_BITS   _u(0x00000004)
 136 #define SYSCFG_DBGFORCE_SWCLK_MSB    _u(2)
 137 #define SYSCFG_DBGFORCE_SWCLK_LSB    _u(2)
 138 #define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW"
 139 // -----------------------------------------------------------------------------
 140 // Field       : SYSCFG_DBGFORCE_SWDI
 141 // Description : Directly drive SWDIO input, if ATTACH is set
 142 #define SYSCFG_DBGFORCE_SWDI_RESET  _u(0x1)
 143 #define SYSCFG_DBGFORCE_SWDI_BITS   _u(0x00000002)
 144 #define SYSCFG_DBGFORCE_SWDI_MSB    _u(1)
 145 #define SYSCFG_DBGFORCE_SWDI_LSB    _u(1)
 146 #define SYSCFG_DBGFORCE_SWDI_ACCESS "RW"
 147 // -----------------------------------------------------------------------------
 148 // Field       : SYSCFG_DBGFORCE_SWDO
 149 // Description : Observe the value of SWDIO output.
 150 #define SYSCFG_DBGFORCE_SWDO_RESET  "-"
 151 #define SYSCFG_DBGFORCE_SWDO_BITS   _u(0x00000001)
 152 #define SYSCFG_DBGFORCE_SWDO_MSB    _u(0)
 153 #define SYSCFG_DBGFORCE_SWDO_LSB    _u(0)
 154 #define SYSCFG_DBGFORCE_SWDO_ACCESS "RO"
 155 // =============================================================================
 156 // Register    : SYSCFG_MEMPOWERDOWN
 157 // Description : Control PD pins to memories.
 158 //               Set high to put memories to a low power state. In this state
 159 //               the memories will retain contents but not be accessible
 160 //               Use with caution
 161 #define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010)
 162 #define SYSCFG_MEMPOWERDOWN_BITS   _u(0x00001fff)
 163 #define SYSCFG_MEMPOWERDOWN_RESET  _u(0x00000000)
 164 // -----------------------------------------------------------------------------
 165 // Field       : SYSCFG_MEMPOWERDOWN_BOOTRAM
 166 #define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET  _u(0x0)
 167 #define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS   _u(0x00001000)
 168 #define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB    _u(12)
 169 #define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB    _u(12)
 170 #define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW"
 171 // -----------------------------------------------------------------------------
 172 // Field       : SYSCFG_MEMPOWERDOWN_ROM
 173 #define SYSCFG_MEMPOWERDOWN_ROM_RESET  _u(0x0)
 174 #define SYSCFG_MEMPOWERDOWN_ROM_BITS   _u(0x00000800)
 175 #define SYSCFG_MEMPOWERDOWN_ROM_MSB    _u(11)
 176 #define SYSCFG_MEMPOWERDOWN_ROM_LSB    _u(11)
 177 #define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
 178 // -----------------------------------------------------------------------------
 179 // Field       : SYSCFG_MEMPOWERDOWN_USB
 180 #define SYSCFG_MEMPOWERDOWN_USB_RESET  _u(0x0)
 181 #define SYSCFG_MEMPOWERDOWN_USB_BITS   _u(0x00000400)
 182 #define SYSCFG_MEMPOWERDOWN_USB_MSB    _u(10)
 183 #define SYSCFG_MEMPOWERDOWN_USB_LSB    _u(10)
 184 #define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
 185 // -----------------------------------------------------------------------------
 186 // Field       : SYSCFG_MEMPOWERDOWN_SRAM9
 187 #define SYSCFG_MEMPOWERDOWN_SRAM9_RESET  _u(0x0)
 188 #define SYSCFG_MEMPOWERDOWN_SRAM9_BITS   _u(0x00000200)
 189 #define SYSCFG_MEMPOWERDOWN_SRAM9_MSB    _u(9)
 190 #define SYSCFG_MEMPOWERDOWN_SRAM9_LSB    _u(9)
 191 #define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW"
 192 // -----------------------------------------------------------------------------
 193 // Field       : SYSCFG_MEMPOWERDOWN_SRAM8
 194 #define SYSCFG_MEMPOWERDOWN_SRAM8_RESET  _u(0x0)
 195 #define SYSCFG_MEMPOWERDOWN_SRAM8_BITS   _u(0x00000100)
 196 #define SYSCFG_MEMPOWERDOWN_SRAM8_MSB    _u(8)
 197 #define SYSCFG_MEMPOWERDOWN_SRAM8_LSB    _u(8)
 198 #define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW"
 199 // -----------------------------------------------------------------------------
 200 // Field       : SYSCFG_MEMPOWERDOWN_SRAM7
 201 #define SYSCFG_MEMPOWERDOWN_SRAM7_RESET  _u(0x0)
 202 #define SYSCFG_MEMPOWERDOWN_SRAM7_BITS   _u(0x00000080)
 203 #define SYSCFG_MEMPOWERDOWN_SRAM7_MSB    _u(7)
 204 #define SYSCFG_MEMPOWERDOWN_SRAM7_LSB    _u(7)
 205 #define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW"
 206 // -----------------------------------------------------------------------------
 207 // Field       : SYSCFG_MEMPOWERDOWN_SRAM6
 208 #define SYSCFG_MEMPOWERDOWN_SRAM6_RESET  _u(0x0)
 209 #define SYSCFG_MEMPOWERDOWN_SRAM6_BITS   _u(0x00000040)
 210 #define SYSCFG_MEMPOWERDOWN_SRAM6_MSB    _u(6)
 211 #define SYSCFG_MEMPOWERDOWN_SRAM6_LSB    _u(6)
 212 #define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW"
 213 // -----------------------------------------------------------------------------
 214 // Field       : SYSCFG_MEMPOWERDOWN_SRAM5
 215 #define SYSCFG_MEMPOWERDOWN_SRAM5_RESET  _u(0x0)
 216 #define SYSCFG_MEMPOWERDOWN_SRAM5_BITS   _u(0x00000020)
 217 #define SYSCFG_MEMPOWERDOWN_SRAM5_MSB    _u(5)
 218 #define SYSCFG_MEMPOWERDOWN_SRAM5_LSB    _u(5)
 219 #define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
 220 // -----------------------------------------------------------------------------
 221 // Field       : SYSCFG_MEMPOWERDOWN_SRAM4
 222 #define SYSCFG_MEMPOWERDOWN_SRAM4_RESET  _u(0x0)
 223 #define SYSCFG_MEMPOWERDOWN_SRAM4_BITS   _u(0x00000010)
 224 #define SYSCFG_MEMPOWERDOWN_SRAM4_MSB    _u(4)
 225 #define SYSCFG_MEMPOWERDOWN_SRAM4_LSB    _u(4)
 226 #define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
 227 // -----------------------------------------------------------------------------
 228 // Field       : SYSCFG_MEMPOWERDOWN_SRAM3
 229 #define SYSCFG_MEMPOWERDOWN_SRAM3_RESET  _u(0x0)
 230 #define SYSCFG_MEMPOWERDOWN_SRAM3_BITS   _u(0x00000008)
 231 #define SYSCFG_MEMPOWERDOWN_SRAM3_MSB    _u(3)
 232 #define SYSCFG_MEMPOWERDOWN_SRAM3_LSB    _u(3)
 233 #define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
 234 // -----------------------------------------------------------------------------
 235 // Field       : SYSCFG_MEMPOWERDOWN_SRAM2
 236 #define SYSCFG_MEMPOWERDOWN_SRAM2_RESET  _u(0x0)
 237 #define SYSCFG_MEMPOWERDOWN_SRAM2_BITS   _u(0x00000004)
 238 #define SYSCFG_MEMPOWERDOWN_SRAM2_MSB    _u(2)
 239 #define SYSCFG_MEMPOWERDOWN_SRAM2_LSB    _u(2)
 240 #define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
 241 // -----------------------------------------------------------------------------
 242 // Field       : SYSCFG_MEMPOWERDOWN_SRAM1
 243 #define SYSCFG_MEMPOWERDOWN_SRAM1_RESET  _u(0x0)
 244 #define SYSCFG_MEMPOWERDOWN_SRAM1_BITS   _u(0x00000002)
 245 #define SYSCFG_MEMPOWERDOWN_SRAM1_MSB    _u(1)
 246 #define SYSCFG_MEMPOWERDOWN_SRAM1_LSB    _u(1)
 247 #define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
 248 // -----------------------------------------------------------------------------
 249 // Field       : SYSCFG_MEMPOWERDOWN_SRAM0
 250 #define SYSCFG_MEMPOWERDOWN_SRAM0_RESET  _u(0x0)
 251 #define SYSCFG_MEMPOWERDOWN_SRAM0_BITS   _u(0x00000001)
 252 #define SYSCFG_MEMPOWERDOWN_SRAM0_MSB    _u(0)
 253 #define SYSCFG_MEMPOWERDOWN_SRAM0_LSB    _u(0)
 254 #define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
 255 // =============================================================================
 256 // Register    : SYSCFG_AUXCTRL
 257 // Description : Auxiliary system control register
 258 //               * Bits 7:2: Reserved
 259 //
 260 //               * Bit 1: When clear, the LPOSC output is XORed into the TRNG
 261 //               ROSC output as an additional, uncorrelated entropy source. When
 262 //               set, this behaviour is disabled.
 263 //
 264 //               * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting
 265 //               its WDRESET input. This must be set before initiating a
 266 //               watchdog reset of the RSM from a stage that includes CLOCKS, if
 267 //               POWMAN is running from clk_ref at the point that the watchdog
 268 //               reset takes place. Otherwise, the short pulse generated on
 269 //               clk_ref by the reset of the CLOCKS block may affect POWMAN
 270 //               register state.
 271 #define SYSCFG_AUXCTRL_OFFSET _u(0x00000014)
 272 #define SYSCFG_AUXCTRL_BITS   _u(0x000000ff)
 273 #define SYSCFG_AUXCTRL_RESET  _u(0x00000000)
 274 #define SYSCFG_AUXCTRL_MSB    _u(7)
 275 #define SYSCFG_AUXCTRL_LSB    _u(0)
 276 #define SYSCFG_AUXCTRL_ACCESS "RW"
 277 // =============================================================================
 278 #endif // _HARDWARE_REGS_SYSCFG_H
 279