lib/main/pico-sdk/rp2350/hardware_regs/include/hardware/regs/trng.h

   1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
   2
   3 /**
   4  * Copyright (c) 2024 Raspberry Pi Ltd.
   5  *
   6  * SPDX-License-Identifier: BSD-3-Clause
   7  */
   8 // =============================================================================
   9 // Register block : TRNG
  10 // Version        : 1
  11 // Bus type       : apb
  12 // Description    : ARM TrustZone RNG register block
  13 // =============================================================================
  14 #ifndef _HARDWARE_REGS_TRNG_H
  15 #define _HARDWARE_REGS_TRNG_H
  16 // =============================================================================
  17 // Register    : TRNG_RNG_IMR
  18 // Description : Interrupt masking.
  19 #define TRNG_RNG_IMR_OFFSET _u(0x00000100)
  20 #define TRNG_RNG_IMR_BITS   _u(0xffffffff)
  21 #define TRNG_RNG_IMR_RESET  _u(0x0000000f)
  22 // -----------------------------------------------------------------------------
  23 // Field       : TRNG_RNG_IMR_RESERVED
  24 // Description : RESERVED
  25 #define TRNG_RNG_IMR_RESERVED_RESET  _u(0x0000000)
  26 #define TRNG_RNG_IMR_RESERVED_BITS   _u(0xfffffff0)
  27 #define TRNG_RNG_IMR_RESERVED_MSB    _u(31)
  28 #define TRNG_RNG_IMR_RESERVED_LSB    _u(4)
  29 #define TRNG_RNG_IMR_RESERVED_ACCESS "RO"
  30 // -----------------------------------------------------------------------------
  31 // Field       : TRNG_RNG_IMR_VN_ERR_INT_MASK
  32 // Description : 1'b1-mask interrupt, no interrupt will be generated. See
  33 //               RNG_ISR for an explanation on this interrupt.
  34 #define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET  _u(0x1)
  35 #define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS   _u(0x00000008)
  36 #define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB    _u(3)
  37 #define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB    _u(3)
  38 #define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW"
  39 // -----------------------------------------------------------------------------
  40 // Field       : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK
  41 // Description : 1'b1-mask interrupt, no interrupt will be generated. See
  42 //               RNG_ISR for an explanation on this interrupt.
  43 #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET  _u(0x1)
  44 #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS   _u(0x00000004)
  45 #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB    _u(2)
  46 #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB    _u(2)
  47 #define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW"
  48 // -----------------------------------------------------------------------------
  49 // Field       : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK
  50 // Description : 1'b1-mask interrupt, no interrupt will be generated. See
  51 //               RNG_ISR for an explanation on this interrupt.
  52 #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET  _u(0x1)
  53 #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS   _u(0x00000002)
  54 #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB    _u(1)
  55 #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB    _u(1)
  56 #define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW"
  57 // -----------------------------------------------------------------------------
  58 // Field       : TRNG_RNG_IMR_EHR_VALID_INT_MASK
  59 // Description : 1'b1-mask interrupt, no interrupt will be generated. See
  60 //               RNG_ISR for an explanation on this interrupt.
  61 #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET  _u(0x1)
  62 #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS   _u(0x00000001)
  63 #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB    _u(0)
  64 #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB    _u(0)
  65 #define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW"
  66 // =============================================================================
  67 // Register    : TRNG_RNG_ISR
  68 // Description : RNG status register. If corresponding RNG_IMR bit is unmasked,
  69 //               an interrupt will be generated.
  70 #define TRNG_RNG_ISR_OFFSET _u(0x00000104)
  71 #define TRNG_RNG_ISR_BITS   _u(0xffffffff)
  72 #define TRNG_RNG_ISR_RESET  _u(0x00000000)
  73 // -----------------------------------------------------------------------------
  74 // Field       : TRNG_RNG_ISR_RESERVED
  75 // Description : RESERVED
  76 #define TRNG_RNG_ISR_RESERVED_RESET  _u(0x0000000)
  77 #define TRNG_RNG_ISR_RESERVED_BITS   _u(0xfffffff0)
  78 #define TRNG_RNG_ISR_RESERVED_MSB    _u(31)
  79 #define TRNG_RNG_ISR_RESERVED_LSB    _u(4)
  80 #define TRNG_RNG_ISR_RESERVED_ACCESS "RO"
  81 // -----------------------------------------------------------------------------
  82 // Field       : TRNG_RNG_ISR_VN_ERR
  83 // Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if
  84 //               32 consecutive collected bits are identical, ZERO or ONE.
  85 #define TRNG_RNG_ISR_VN_ERR_RESET  _u(0x0)
  86 #define TRNG_RNG_ISR_VN_ERR_BITS   _u(0x00000008)
  87 #define TRNG_RNG_ISR_VN_ERR_MSB    _u(3)
  88 #define TRNG_RNG_ISR_VN_ERR_LSB    _u(3)
  89 #define TRNG_RNG_ISR_VN_ERR_ACCESS "RO"
  90 // -----------------------------------------------------------------------------
  91 // Field       : TRNG_RNG_ISR_CRNGT_ERR
  92 // Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs
  93 //               when two consecutive blocks of 16 collected bits are equal.
  94 #define TRNG_RNG_ISR_CRNGT_ERR_RESET  _u(0x0)
  95 #define TRNG_RNG_ISR_CRNGT_ERR_BITS   _u(0x00000004)
  96 #define TRNG_RNG_ISR_CRNGT_ERR_MSB    _u(2)
  97 #define TRNG_RNG_ISR_CRNGT_ERR_LSB    _u(2)
  98 #define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO"
  99 // -----------------------------------------------------------------------------
 100 // Field       : TRNG_RNG_ISR_AUTOCORR_ERR
 101 // Description : 1'b1 indicates Autocorrelation test failed four times in a row.
 102 //               When set, RNG cease from functioning until next reset.
 103 #define TRNG_RNG_ISR_AUTOCORR_ERR_RESET  _u(0x0)
 104 #define TRNG_RNG_ISR_AUTOCORR_ERR_BITS   _u(0x00000002)
 105 #define TRNG_RNG_ISR_AUTOCORR_ERR_MSB    _u(1)
 106 #define TRNG_RNG_ISR_AUTOCORR_ERR_LSB    _u(1)
 107 #define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO"
 108 // -----------------------------------------------------------------------------
 109 // Field       : TRNG_RNG_ISR_EHR_VALID
 110 // Description : 1'b1 indicates that 192 bits have been collected in the RNG,
 111 //               and are ready to be read.
 112 #define TRNG_RNG_ISR_EHR_VALID_RESET  _u(0x0)
 113 #define TRNG_RNG_ISR_EHR_VALID_BITS   _u(0x00000001)
 114 #define TRNG_RNG_ISR_EHR_VALID_MSB    _u(0)
 115 #define TRNG_RNG_ISR_EHR_VALID_LSB    _u(0)
 116 #define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO"
 117 // =============================================================================
 118 // Register    : TRNG_RNG_ICR
 119 // Description : Interrupt/status bit clear Register.
 120 #define TRNG_RNG_ICR_OFFSET _u(0x00000108)
 121 #define TRNG_RNG_ICR_BITS   _u(0xffffffff)
 122 #define TRNG_RNG_ICR_RESET  _u(0x00000000)
 123 // -----------------------------------------------------------------------------
 124 // Field       : TRNG_RNG_ICR_RESERVED
 125 // Description : RESERVED
 126 #define TRNG_RNG_ICR_RESERVED_RESET  _u(0x0000000)
 127 #define TRNG_RNG_ICR_RESERVED_BITS   _u(0xfffffff0)
 128 #define TRNG_RNG_ICR_RESERVED_MSB    _u(31)
 129 #define TRNG_RNG_ICR_RESERVED_LSB    _u(4)
 130 #define TRNG_RNG_ICR_RESERVED_ACCESS "RO"
 131 // -----------------------------------------------------------------------------
 132 // Field       : TRNG_RNG_ICR_VN_ERR
 133 // Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
 134 #define TRNG_RNG_ICR_VN_ERR_RESET  _u(0x0)
 135 #define TRNG_RNG_ICR_VN_ERR_BITS   _u(0x00000008)
 136 #define TRNG_RNG_ICR_VN_ERR_MSB    _u(3)
 137 #define TRNG_RNG_ICR_VN_ERR_LSB    _u(3)
 138 #define TRNG_RNG_ICR_VN_ERR_ACCESS "RW"
 139 // -----------------------------------------------------------------------------
 140 // Field       : TRNG_RNG_ICR_CRNGT_ERR
 141 // Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
 142 #define TRNG_RNG_ICR_CRNGT_ERR_RESET  _u(0x0)
 143 #define TRNG_RNG_ICR_CRNGT_ERR_BITS   _u(0x00000004)
 144 #define TRNG_RNG_ICR_CRNGT_ERR_MSB    _u(2)
 145 #define TRNG_RNG_ICR_CRNGT_ERR_LSB    _u(2)
 146 #define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW"
 147 // -----------------------------------------------------------------------------
 148 // Field       : TRNG_RNG_ICR_AUTOCORR_ERR
 149 // Description : Cannot be cleared by SW! Only RNG reset clears this bit.
 150 #define TRNG_RNG_ICR_AUTOCORR_ERR_RESET  _u(0x0)
 151 #define TRNG_RNG_ICR_AUTOCORR_ERR_BITS   _u(0x00000002)
 152 #define TRNG_RNG_ICR_AUTOCORR_ERR_MSB    _u(1)
 153 #define TRNG_RNG_ICR_AUTOCORR_ERR_LSB    _u(1)
 154 #define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW"
 155 // -----------------------------------------------------------------------------
 156 // Field       : TRNG_RNG_ICR_EHR_VALID
 157 // Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
 158 #define TRNG_RNG_ICR_EHR_VALID_RESET  _u(0x0)
 159 #define TRNG_RNG_ICR_EHR_VALID_BITS   _u(0x00000001)
 160 #define TRNG_RNG_ICR_EHR_VALID_MSB    _u(0)
 161 #define TRNG_RNG_ICR_EHR_VALID_LSB    _u(0)
 162 #define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW"
 163 // =============================================================================
 164 // Register    : TRNG_TRNG_CONFIG
 165 // Description : Selecting the inverter-chain length.
 166 #define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c)
 167 #define TRNG_TRNG_CONFIG_BITS   _u(0xffffffff)
 168 #define TRNG_TRNG_CONFIG_RESET  _u(0x00000000)
 169 // -----------------------------------------------------------------------------
 170 // Field       : TRNG_TRNG_CONFIG_RESERVED
 171 // Description : RESERVED
 172 #define TRNG_TRNG_CONFIG_RESERVED_RESET  _u(0x00000000)
 173 #define TRNG_TRNG_CONFIG_RESERVED_BITS   _u(0xfffffffc)
 174 #define TRNG_TRNG_CONFIG_RESERVED_MSB    _u(31)
 175 #define TRNG_TRNG_CONFIG_RESERVED_LSB    _u(2)
 176 #define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO"
 177 // -----------------------------------------------------------------------------
 178 // Field       : TRNG_TRNG_CONFIG_RND_SRC_SEL
 179 // Description : Selects the number of inverters (out of four possible
 180 //               selections) in the ring oscillator (the entropy source).
 181 #define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET  _u(0x0)
 182 #define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS   _u(0x00000003)
 183 #define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB    _u(1)
 184 #define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB    _u(0)
 185 #define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW"
 186 // =============================================================================
 187 // Register    : TRNG_TRNG_VALID
 188 // Description : 192 bit collection indication.
 189 #define TRNG_TRNG_VALID_OFFSET _u(0x00000110)
 190 #define TRNG_TRNG_VALID_BITS   _u(0xffffffff)
 191 #define TRNG_TRNG_VALID_RESET  _u(0x00000000)
 192 // -----------------------------------------------------------------------------
 193 // Field       : TRNG_TRNG_VALID_RESERVED
 194 // Description : RESERVED
 195 #define TRNG_TRNG_VALID_RESERVED_RESET  _u(0x00000000)
 196 #define TRNG_TRNG_VALID_RESERVED_BITS   _u(0xfffffffe)
 197 #define TRNG_TRNG_VALID_RESERVED_MSB    _u(31)
 198 #define TRNG_TRNG_VALID_RESERVED_LSB    _u(1)
 199 #define TRNG_TRNG_VALID_RESERVED_ACCESS "RO"
 200 // -----------------------------------------------------------------------------
 201 // Field       : TRNG_TRNG_VALID_EHR_VALID
 202 // Description : 1'b1 indicates that collection of bits in the RNG is completed,
 203 //               and data can be read from EHR_DATA register.
 204 #define TRNG_TRNG_VALID_EHR_VALID_RESET  _u(0x0)
 205 #define TRNG_TRNG_VALID_EHR_VALID_BITS   _u(0x00000001)
 206 #define TRNG_TRNG_VALID_EHR_VALID_MSB    _u(0)
 207 #define TRNG_TRNG_VALID_EHR_VALID_LSB    _u(0)
 208 #define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO"
 209 // =============================================================================
 210 // Register    : TRNG_EHR_DATA0
 211 // Description : RNG collected bits.
 212 //               Bits [31:0] of Entropy Holding Register (EHR) - RNG output
 213 //               register
 214 #define TRNG_EHR_DATA0_OFFSET _u(0x00000114)
 215 #define TRNG_EHR_DATA0_BITS   _u(0xffffffff)
 216 #define TRNG_EHR_DATA0_RESET  _u(0x00000000)
 217 #define TRNG_EHR_DATA0_MSB    _u(31)
 218 #define TRNG_EHR_DATA0_LSB    _u(0)
 219 #define TRNG_EHR_DATA0_ACCESS "RO"
 220 // =============================================================================
 221 // Register    : TRNG_EHR_DATA1
 222 // Description : RNG collected bits.
 223 //               Bits [63:32] of Entropy Holding Register (EHR) - RNG output
 224 //               register
 225 #define TRNG_EHR_DATA1_OFFSET _u(0x00000118)
 226 #define TRNG_EHR_DATA1_BITS   _u(0xffffffff)
 227 #define TRNG_EHR_DATA1_RESET  _u(0x00000000)
 228 #define TRNG_EHR_DATA1_MSB    _u(31)
 229 #define TRNG_EHR_DATA1_LSB    _u(0)
 230 #define TRNG_EHR_DATA1_ACCESS "RO"
 231 // =============================================================================
 232 // Register    : TRNG_EHR_DATA2
 233 // Description : RNG collected bits.
 234 //               Bits [95:64] of Entropy Holding Register (EHR) - RNG output
 235 //               register
 236 #define TRNG_EHR_DATA2_OFFSET _u(0x0000011c)
 237 #define TRNG_EHR_DATA2_BITS   _u(0xffffffff)
 238 #define TRNG_EHR_DATA2_RESET  _u(0x00000000)
 239 #define TRNG_EHR_DATA2_MSB    _u(31)
 240 #define TRNG_EHR_DATA2_LSB    _u(0)
 241 #define TRNG_EHR_DATA2_ACCESS "RO"
 242 // =============================================================================
 243 // Register    : TRNG_EHR_DATA3
 244 // Description : RNG collected bits.
 245 //               Bits [127:96] of Entropy Holding Register (EHR) - RNG output
 246 //               register
 247 #define TRNG_EHR_DATA3_OFFSET _u(0x00000120)
 248 #define TRNG_EHR_DATA3_BITS   _u(0xffffffff)
 249 #define TRNG_EHR_DATA3_RESET  _u(0x00000000)
 250 #define TRNG_EHR_DATA3_MSB    _u(31)
 251 #define TRNG_EHR_DATA3_LSB    _u(0)
 252 #define TRNG_EHR_DATA3_ACCESS "RO"
 253 // =============================================================================
 254 // Register    : TRNG_EHR_DATA4
 255 // Description : RNG collected bits.
 256 //               Bits [159:128] of Entropy Holding Register (EHR) - RNG output
 257 //               register
 258 #define TRNG_EHR_DATA4_OFFSET _u(0x00000124)
 259 #define TRNG_EHR_DATA4_BITS   _u(0xffffffff)
 260 #define TRNG_EHR_DATA4_RESET  _u(0x00000000)
 261 #define TRNG_EHR_DATA4_MSB    _u(31)
 262 #define TRNG_EHR_DATA4_LSB    _u(0)
 263 #define TRNG_EHR_DATA4_ACCESS "RO"
 264 // =============================================================================
 265 // Register    : TRNG_EHR_DATA5
 266 // Description : RNG collected bits.
 267 //               Bits [191:160] of Entropy Holding Register (EHR) - RNG output
 268 //               register
 269 #define TRNG_EHR_DATA5_OFFSET _u(0x00000128)
 270 #define TRNG_EHR_DATA5_BITS   _u(0xffffffff)
 271 #define TRNG_EHR_DATA5_RESET  _u(0x00000000)
 272 #define TRNG_EHR_DATA5_MSB    _u(31)
 273 #define TRNG_EHR_DATA5_LSB    _u(0)
 274 #define TRNG_EHR_DATA5_ACCESS "RO"
 275 // =============================================================================
 276 // Register    : TRNG_RND_SOURCE_ENABLE
 277 // Description : Enable signal for the random source.
 278 #define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c)
 279 #define TRNG_RND_SOURCE_ENABLE_BITS   _u(0xffffffff)
 280 #define TRNG_RND_SOURCE_ENABLE_RESET  _u(0x00000000)
 281 // -----------------------------------------------------------------------------
 282 // Field       : TRNG_RND_SOURCE_ENABLE_RESERVED
 283 // Description : RESERVED
 284 #define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET  _u(0x00000000)
 285 #define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS   _u(0xfffffffe)
 286 #define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB    _u(31)
 287 #define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB    _u(1)
 288 #define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO"
 289 // -----------------------------------------------------------------------------
 290 // Field       : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN
 291 // Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is
 292 //               disabled
 293 #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET  _u(0x0)
 294 #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS   _u(0x00000001)
 295 #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB    _u(0)
 296 #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB    _u(0)
 297 #define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW"
 298 // =============================================================================
 299 // Register    : TRNG_SAMPLE_CNT1
 300 // Description : Counts clocks between sampling of random bit.
 301 #define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130)
 302 #define TRNG_SAMPLE_CNT1_BITS   _u(0xffffffff)
 303 #define TRNG_SAMPLE_CNT1_RESET  _u(0x0000ffff)
 304 // -----------------------------------------------------------------------------
 305 // Field       : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1
 306 // Description : Sets the number of rng_clk cycles between two consecutive ring
 307 //               oscillator samples. Note! If the Von-Neuman is bypassed, the
 308 //               minimum value for sample counter must not be less then decimal
 309 //               seventeen
 310 #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET  _u(0x0000ffff)
 311 #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS   _u(0xffffffff)
 312 #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB    _u(31)
 313 #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB    _u(0)
 314 #define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW"
 315 // =============================================================================
 316 // Register    : TRNG_AUTOCORR_STATISTIC
 317 // Description : Statistic about Autocorrelation test activations.
 318 #define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134)
 319 #define TRNG_AUTOCORR_STATISTIC_BITS   _u(0xffffffff)
 320 #define TRNG_AUTOCORR_STATISTIC_RESET  _u(0x00000000)
 321 // -----------------------------------------------------------------------------
 322 // Field       : TRNG_AUTOCORR_STATISTIC_RESERVED
 323 // Description : RESERVED
 324 #define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET  _u(0x000)
 325 #define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS   _u(0xffc00000)
 326 #define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB    _u(31)
 327 #define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB    _u(22)
 328 #define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO"
 329 // -----------------------------------------------------------------------------
 330 // Field       : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS
 331 // Description : Count each time an autocorrelation test fails. Any write to the
 332 //               register reset the counter. Stop collecting statistic if one of
 333 //               the counters reached the limit.
 334 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET  _u(0x00)
 335 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS   _u(0x003fc000)
 336 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB    _u(21)
 337 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB    _u(14)
 338 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW"
 339 // -----------------------------------------------------------------------------
 340 // Field       : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS
 341 // Description : Count each time an autocorrelation test starts. Any write to
 342 //               the register reset the counter. Stop collecting statistic if
 343 //               one of the counters reached the limit.
 344 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET  _u(0x0000)
 345 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS   _u(0x00003fff)
 346 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB    _u(13)
 347 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB    _u(0)
 348 #define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW"
 349 // =============================================================================
 350 // Register    : TRNG_TRNG_DEBUG_CONTROL
 351 // Description : Debug register.
 352 #define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138)
 353 #define TRNG_TRNG_DEBUG_CONTROL_BITS   _u(0x0000000f)
 354 #define TRNG_TRNG_DEBUG_CONTROL_RESET  _u(0x00000000)
 355 // -----------------------------------------------------------------------------
 356 // Field       : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS
 357 // Description : When set, the autocorrelation test in the TRNG module is
 358 //               bypassed.
 359 #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET  _u(0x0)
 360 #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS   _u(0x00000008)
 361 #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB    _u(3)
 362 #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB    _u(3)
 363 #define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW"
 364 // -----------------------------------------------------------------------------
 365 // Field       : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS
 366 // Description : When set, the CRNGT test in the RNG is bypassed.
 367 #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET  _u(0x0)
 368 #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS   _u(0x00000004)
 369 #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB    _u(2)
 370 #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB    _u(2)
 371 #define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW"
 372 // -----------------------------------------------------------------------------
 373 // Field       : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS
 374 // Description : When set, the Von-Neuman balancer is bypassed (including the 32
 375 //               consecutive bits test).
 376 #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET  _u(0x0)
 377 #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS   _u(0x00000002)
 378 #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB    _u(1)
 379 #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB    _u(1)
 380 #define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW"
 381 // -----------------------------------------------------------------------------
 382 // Field       : TRNG_TRNG_DEBUG_CONTROL_RESERVED
 383 // Description : N/A
 384 #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET  _u(0x0)
 385 #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS   _u(0x00000001)
 386 #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB    _u(0)
 387 #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB    _u(0)
 388 #define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO"
 389 // =============================================================================
 390 // Register    : TRNG_TRNG_SW_RESET
 391 // Description : Generate internal SW reset within the RNG block.
 392 #define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140)
 393 #define TRNG_TRNG_SW_RESET_BITS   _u(0xffffffff)
 394 #define TRNG_TRNG_SW_RESET_RESET  _u(0x00000000)
 395 // -----------------------------------------------------------------------------
 396 // Field       : TRNG_TRNG_SW_RESET_RESERVED
 397 // Description : RESERVED
 398 #define TRNG_TRNG_SW_RESET_RESERVED_RESET  _u(0x00000000)
 399 #define TRNG_TRNG_SW_RESET_RESERVED_BITS   _u(0xfffffffe)
 400 #define TRNG_TRNG_SW_RESET_RESERVED_MSB    _u(31)
 401 #define TRNG_TRNG_SW_RESET_RESERVED_LSB    _u(1)
 402 #define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO"
 403 // -----------------------------------------------------------------------------
 404 // Field       : TRNG_TRNG_SW_RESET_TRNG_SW_RESET
 405 // Description : Writing 1'b1 to this register causes an internal RNG reset.
 406 #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET  _u(0x0)
 407 #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS   _u(0x00000001)
 408 #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB    _u(0)
 409 #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB    _u(0)
 410 #define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW"
 411 // =============================================================================
 412 // Register    : TRNG_RNG_DEBUG_EN_INPUT
 413 // Description : Enable the RNG debug mode
 414 #define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4)
 415 #define TRNG_RNG_DEBUG_EN_INPUT_BITS   _u(0xffffffff)
 416 #define TRNG_RNG_DEBUG_EN_INPUT_RESET  _u(0x00000000)
 417 // -----------------------------------------------------------------------------
 418 // Field       : TRNG_RNG_DEBUG_EN_INPUT_RESERVED
 419 // Description : RESERVED
 420 #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET  _u(0x00000000)
 421 #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS   _u(0xfffffffe)
 422 #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB    _u(31)
 423 #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB    _u(1)
 424 #define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO"
 425 // -----------------------------------------------------------------------------
 426 // Field       : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN
 427 // Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled
 428 #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET  _u(0x0)
 429 #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS   _u(0x00000001)
 430 #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB    _u(0)
 431 #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB    _u(0)
 432 #define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW"
 433 // =============================================================================
 434 // Register    : TRNG_TRNG_BUSY
 435 // Description : RNG Busy indication.
 436 #define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8)
 437 #define TRNG_TRNG_BUSY_BITS   _u(0xffffffff)
 438 #define TRNG_TRNG_BUSY_RESET  _u(0x00000000)
 439 // -----------------------------------------------------------------------------
 440 // Field       : TRNG_TRNG_BUSY_RESERVED
 441 // Description : RESERVED
 442 #define TRNG_TRNG_BUSY_RESERVED_RESET  _u(0x00000000)
 443 #define TRNG_TRNG_BUSY_RESERVED_BITS   _u(0xfffffffe)
 444 #define TRNG_TRNG_BUSY_RESERVED_MSB    _u(31)
 445 #define TRNG_TRNG_BUSY_RESERVED_LSB    _u(1)
 446 #define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO"
 447 // -----------------------------------------------------------------------------
 448 // Field       : TRNG_TRNG_BUSY_TRNG_BUSY
 449 // Description : Reflects rng_busy status.
 450 #define TRNG_TRNG_BUSY_TRNG_BUSY_RESET  _u(0x0)
 451 #define TRNG_TRNG_BUSY_TRNG_BUSY_BITS   _u(0x00000001)
 452 #define TRNG_TRNG_BUSY_TRNG_BUSY_MSB    _u(0)
 453 #define TRNG_TRNG_BUSY_TRNG_BUSY_LSB    _u(0)
 454 #define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO"
 455 // =============================================================================
 456 // Register    : TRNG_RST_BITS_COUNTER
 457 // Description : Reset the counter of collected bits in the RNG.
 458 #define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc)
 459 #define TRNG_RST_BITS_COUNTER_BITS   _u(0xffffffff)
 460 #define TRNG_RST_BITS_COUNTER_RESET  _u(0x00000000)
 461 // -----------------------------------------------------------------------------
 462 // Field       : TRNG_RST_BITS_COUNTER_RESERVED
 463 // Description : RESERVED
 464 #define TRNG_RST_BITS_COUNTER_RESERVED_RESET  _u(0x00000000)
 465 #define TRNG_RST_BITS_COUNTER_RESERVED_BITS   _u(0xfffffffe)
 466 #define TRNG_RST_BITS_COUNTER_RESERVED_MSB    _u(31)
 467 #define TRNG_RST_BITS_COUNTER_RESERVED_LSB    _u(1)
 468 #define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO"
 469 // -----------------------------------------------------------------------------
 470 // Field       : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER
 471 // Description : Writing any value to this address will reset the bits counter
 472 //               and RNG valid registers. RND_SORCE_ENABLE register must be
 473 //               unset in order for the reset to take place.
 474 #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET  _u(0x0)
 475 #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS   _u(0x00000001)
 476 #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB    _u(0)
 477 #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB    _u(0)
 478 #define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW"
 479 // =============================================================================
 480 // Register    : TRNG_RNG_VERSION
 481 // Description : Displays the version settings of the TRNG.
 482 #define TRNG_RNG_VERSION_OFFSET _u(0x000001c0)
 483 #define TRNG_RNG_VERSION_BITS   _u(0xffffffff)
 484 #define TRNG_RNG_VERSION_RESET  _u(0x00000000)
 485 // -----------------------------------------------------------------------------
 486 // Field       : TRNG_RNG_VERSION_RESERVED
 487 // Description : RESERVED
 488 #define TRNG_RNG_VERSION_RESERVED_RESET  _u(0x000000)
 489 #define TRNG_RNG_VERSION_RESERVED_BITS   _u(0xffffff00)
 490 #define TRNG_RNG_VERSION_RESERVED_MSB    _u(31)
 491 #define TRNG_RNG_VERSION_RESERVED_LSB    _u(8)
 492 #define TRNG_RNG_VERSION_RESERVED_ACCESS "RO"
 493 // -----------------------------------------------------------------------------
 494 // Field       : TRNG_RNG_VERSION_RNG_USE_5_SBOXES
 495 // Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES
 496 #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET  _u(0x0)
 497 #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS   _u(0x00000080)
 498 #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB    _u(7)
 499 #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB    _u(7)
 500 #define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO"
 501 // -----------------------------------------------------------------------------
 502 // Field       : TRNG_RNG_VERSION_RESEEDING_EXISTS
 503 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 504 #define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET  _u(0x0)
 505 #define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS   _u(0x00000040)
 506 #define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB    _u(6)
 507 #define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB    _u(6)
 508 #define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO"
 509 // -----------------------------------------------------------------------------
 510 // Field       : TRNG_RNG_VERSION_KAT_EXISTS
 511 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 512 #define TRNG_RNG_VERSION_KAT_EXISTS_RESET  _u(0x0)
 513 #define TRNG_RNG_VERSION_KAT_EXISTS_BITS   _u(0x00000020)
 514 #define TRNG_RNG_VERSION_KAT_EXISTS_MSB    _u(5)
 515 #define TRNG_RNG_VERSION_KAT_EXISTS_LSB    _u(5)
 516 #define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO"
 517 // -----------------------------------------------------------------------------
 518 // Field       : TRNG_RNG_VERSION_PRNG_EXISTS
 519 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 520 #define TRNG_RNG_VERSION_PRNG_EXISTS_RESET  _u(0x0)
 521 #define TRNG_RNG_VERSION_PRNG_EXISTS_BITS   _u(0x00000010)
 522 #define TRNG_RNG_VERSION_PRNG_EXISTS_MSB    _u(4)
 523 #define TRNG_RNG_VERSION_PRNG_EXISTS_LSB    _u(4)
 524 #define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO"
 525 // -----------------------------------------------------------------------------
 526 // Field       : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN
 527 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 528 #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET  _u(0x0)
 529 #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS   _u(0x00000008)
 530 #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB    _u(3)
 531 #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB    _u(3)
 532 #define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO"
 533 // -----------------------------------------------------------------------------
 534 // Field       : TRNG_RNG_VERSION_AUTOCORR_EXISTS
 535 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 536 #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET  _u(0x0)
 537 #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS   _u(0x00000004)
 538 #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB    _u(2)
 539 #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB    _u(2)
 540 #define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO"
 541 // -----------------------------------------------------------------------------
 542 // Field       : TRNG_RNG_VERSION_CRNGT_EXISTS
 543 // Description : * 1'b1 - Exists. *1'b0 - Does not exist
 544 #define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET  _u(0x0)
 545 #define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS   _u(0x00000002)
 546 #define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB    _u(1)
 547 #define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB    _u(1)
 548 #define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO"
 549 // -----------------------------------------------------------------------------
 550 // Field       : TRNG_RNG_VERSION_EHR_WIDTH_192
 551 // Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR
 552 #define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET  _u(0x0)
 553 #define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS   _u(0x00000001)
 554 #define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB    _u(0)
 555 #define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB    _u(0)
 556 #define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO"
 557 // =============================================================================
 558 // Register    : TRNG_RNG_BIST_CNTR_0
 559 // Description : Collected BIST results.
 560 #define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0)
 561 #define TRNG_RNG_BIST_CNTR_0_BITS   _u(0xffffffff)
 562 #define TRNG_RNG_BIST_CNTR_0_RESET  _u(0x00000000)
 563 // -----------------------------------------------------------------------------
 564 // Field       : TRNG_RNG_BIST_CNTR_0_RESERVED
 565 // Description : RESERVED
 566 #define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET  _u(0x000)
 567 #define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS   _u(0xffc00000)
 568 #define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB    _u(31)
 569 #define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB    _u(22)
 570 #define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO"
 571 // -----------------------------------------------------------------------------
 572 // Field       : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL
 573 // Description : Reflects the results of RNG BIST counter.
 574 #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET  _u(0x000000)
 575 #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS   _u(0x003fffff)
 576 #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB    _u(21)
 577 #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB    _u(0)
 578 #define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO"
 579 // =============================================================================
 580 // Register    : TRNG_RNG_BIST_CNTR_1
 581 // Description : Collected BIST results.
 582 #define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4)
 583 #define TRNG_RNG_BIST_CNTR_1_BITS   _u(0xffffffff)
 584 #define TRNG_RNG_BIST_CNTR_1_RESET  _u(0x00000000)
 585 // -----------------------------------------------------------------------------
 586 // Field       : TRNG_RNG_BIST_CNTR_1_RESERVED
 587 // Description : RESERVED
 588 #define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET  _u(0x000)
 589 #define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS   _u(0xffc00000)
 590 #define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB    _u(31)
 591 #define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB    _u(22)
 592 #define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO"
 593 // -----------------------------------------------------------------------------
 594 // Field       : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL
 595 // Description : Reflects the results of RNG BIST counter.
 596 #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET  _u(0x000000)
 597 #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS   _u(0x003fffff)
 598 #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB    _u(21)
 599 #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB    _u(0)
 600 #define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO"
 601 // =============================================================================
 602 // Register    : TRNG_RNG_BIST_CNTR_2
 603 // Description : Collected BIST results.
 604 #define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8)
 605 #define TRNG_RNG_BIST_CNTR_2_BITS   _u(0xffffffff)
 606 #define TRNG_RNG_BIST_CNTR_2_RESET  _u(0x00000000)
 607 // -----------------------------------------------------------------------------
 608 // Field       : TRNG_RNG_BIST_CNTR_2_RESERVED
 609 // Description : RESERVED
 610 #define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET  _u(0x000)
 611 #define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS   _u(0xffc00000)
 612 #define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB    _u(31)
 613 #define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB    _u(22)
 614 #define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO"
 615 // -----------------------------------------------------------------------------
 616 // Field       : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL
 617 // Description : Reflects the results of RNG BIST counter.
 618 #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET  _u(0x000000)
 619 #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS   _u(0x003fffff)
 620 #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB    _u(21)
 621 #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB    _u(0)
 622 #define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO"
 623 // =============================================================================
 624 #endif // _HARDWARE_REGS_TRNG_H
 625