lib/main/STM32F4/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f4xx_hal_adc.h
   4   * @author  MCD Application Team
   5   * @version V1.7.1
   6   * @date    14-April-2017
   7   * @brief   Header file containing functions prototypes of ADC HAL library.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F4xx_ADC_H
  40 #define __STM32F4xx_ADC_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f4xx_hal_def.h"
  48
  49 /** @addtogroup STM32F4xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup ADC
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup ADC_Exported_Types ADC Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  Structure definition of ADC and regular group initialization
  64   * @note   Parameters of this structure are shared within 2 scopes:
  65   *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
  66   *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
  67   * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
  68   *         ADC state can be either:
  69   *          - For all parameters: ADC disabled
  70   *          - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
  71   *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
  72   *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
  73   *         without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
  74   */
  75 typedef struct
  76 {
  77   uint32_t ClockPrescaler;        /*!< Select ADC clock prescaler. The clock is common for
  78                                        all the ADCs.
  79                                        This parameter can be a value of @ref ADC_ClockPrescaler */
  80   uint32_t Resolution;            /*!< Configures the ADC resolution.
  81                                        This parameter can be a value of @ref ADC_Resolution */
  82   uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
  83                                        or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
  84                                        This parameter can be a value of @ref ADC_Data_align */
  85   uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
  86                                        This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
  87                                        If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
  88                                                     Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
  89                                        If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
  90                                                     Scan direction is upward: from rank1 to rank 'n'.
  91                                        This parameter can be set to ENABLE or DISABLE */
  92   uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
  93                                        This parameter can be a value of @ref ADC_EOCSelection.
  94                                        Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
  95                                              Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
  96                                              or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
  97                                        Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
  98                                              If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
  99   uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
 100                                        after the selected trigger occurred (software start or external trigger).
 101                                        This parameter can be set to ENABLE or DISABLE. */
 102   uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
 103                                        To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
 104                                        This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
 105   uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
 106                                        Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
 107                                        Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
 108                                        This parameter can be set to ENABLE or DISABLE. */
 109   uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
 110                                        If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
 111                                        This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
 112   uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
 113                                        If set to ADC_SOFTWARE_START, external triggers are disabled.
 114                                        If set to external trigger source, triggering is on event rising edge by default.
 115                                        This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
 116   uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
 117                                        If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
 118                                        This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
 119   uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
 120                                        or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
 121                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
 122                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
 123                                        This parameter can be set to ENABLE or DISABLE. */
 124 }ADC_InitTypeDef;
 125
 126
 127
 128 /**
 129   * @brief  Structure definition of ADC channel for regular group
 130   * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
 131   *         ADC can be either disabled or enabled without conversion on going on regular group.
 132   */
 133 typedef struct
 134 {
 135   uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
 136                                         This parameter can be a value of @ref ADC_channels */
 137   uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer.
 138                                         This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
 139   uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
 140                                         Unit: ADC clock cycles
 141                                         Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
 142                                         This parameter can be a value of @ref ADC_sampling_times
 143                                         Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
 144                                                  If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
 145                                         Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
 146                                               sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
 147                                               Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
 148   uint32_t Offset;                 /*!< Reserved for future use, can be set to 0 */
 149 }ADC_ChannelConfTypeDef;
 150
 151 /**
 152   * @brief ADC Configuration multi-mode structure definition
 153   */
 154 typedef struct
 155 {
 156   uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode.
 157                                    This parameter can be a value of @ref ADC_analog_watchdog_selection */
 158   uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
 159                                    This parameter must be a 12-bit value. */
 160   uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
 161                                    This parameter must be a 12-bit value. */
 162   uint32_t Channel;           /*!< Configures ADC channel for the analog watchdog.
 163                                    This parameter has an effect only if watchdog mode is configured on single channel
 164                                    This parameter can be a value of @ref ADC_channels */
 165   uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured
 166                                    is interrupt mode or in polling mode.
 167                                    This parameter can be set to ENABLE or DISABLE */
 168   uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
 169 }ADC_AnalogWDGConfTypeDef;
 170
 171 /**
 172   * @brief  HAL ADC state machine: ADC states definition (bitfields)
 173   */
 174 /* States of ADC global scope */
 175 #define HAL_ADC_STATE_RESET             0x00000000U    /*!< ADC not yet initialized or disabled */
 176 #define HAL_ADC_STATE_READY             0x00000001U    /*!< ADC peripheral ready for use */
 177 #define HAL_ADC_STATE_BUSY_INTERNAL     0x00000002U    /*!< ADC is busy to internal process (initialization, calibration) */
 178 #define HAL_ADC_STATE_TIMEOUT           0x00000004U    /*!< TimeOut occurrence */
 179
 180 /* States of ADC errors */
 181 #define HAL_ADC_STATE_ERROR_INTERNAL    0x00000010U    /*!< Internal error occurrence */
 182 #define HAL_ADC_STATE_ERROR_CONFIG      0x00000020U    /*!< Configuration error occurrence */
 183 #define HAL_ADC_STATE_ERROR_DMA         0x00000040U    /*!< DMA error occurrence */
 184
 185 /* States of ADC group regular */
 186 #define HAL_ADC_STATE_REG_BUSY          0x00000100U    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
 187                                                             external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
 188 #define HAL_ADC_STATE_REG_EOC           0x00000200U    /*!< Conversion data available on group regular */
 189 #define HAL_ADC_STATE_REG_OVR           0x00000400U    /*!< Overrun occurrence */
 190
 191 /* States of ADC group injected */
 192 #define HAL_ADC_STATE_INJ_BUSY          0x00001000U    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
 193                                                             external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
 194 #define HAL_ADC_STATE_INJ_EOC           0x00002000U    /*!< Conversion data available on group injected */
 195
 196 /* States of ADC analog watchdogs */
 197 #define HAL_ADC_STATE_AWD1              0x00010000U    /*!< Out-of-window occurrence of analog watchdog 1 */
 198 #define HAL_ADC_STATE_AWD2              0x00020000U    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */
 199 #define HAL_ADC_STATE_AWD3              0x00040000U    /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */
 200
 201 /* States of ADC multi-mode */
 202 #define HAL_ADC_STATE_MULTIMODE_SLAVE   0x00100000U    /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
 203
 204
 205 /**
 206   * @brief  ADC handle Structure definition
 207   */
 208 typedef struct
 209 {
 210   ADC_TypeDef                   *Instance;                   /*!< Register base address */
 211
 212   ADC_InitTypeDef               Init;                        /*!< ADC required parameters */
 213
 214   __IO uint32_t                 NbrOfCurrentConversionRank;  /*!< ADC number of current conversion rank */
 215
 216   DMA_HandleTypeDef             *DMA_Handle;                 /*!< Pointer DMA Handler */
 217
 218   HAL_LockTypeDef               Lock;                        /*!< ADC locking object */
 219
 220   __IO uint32_t                 State;                       /*!< ADC communication state */
 221
 222   __IO uint32_t                 ErrorCode;                   /*!< ADC Error code */
 223 }ADC_HandleTypeDef;
 224 /**
 225   * @}
 226   */
 227
 228 /* Exported constants --------------------------------------------------------*/
 229 /** @defgroup ADC_Exported_Constants ADC Exported Constants
 230   * @{
 231   */
 232
 233 /** @defgroup ADC_Error_Code ADC Error Code
 234   * @{
 235   */
 236 #define HAL_ADC_ERROR_NONE        0x00U   /*!< No error                                              */
 237 #define HAL_ADC_ERROR_INTERNAL    0x01U   /*!< ADC IP internal error: if problem of clocking,
 238                                                enable/disable, erroneous state                       */
 239 #define HAL_ADC_ERROR_OVR         0x02U   /*!< Overrun error                                         */
 240 #define HAL_ADC_ERROR_DMA         0x04U   /*!< DMA transfer error                                    */
 241 /**
 242   * @}
 243   */
 244
 245
 246 /** @defgroup ADC_ClockPrescaler  ADC Clock Prescaler
 247   * @{
 248   */
 249 #define ADC_CLOCK_SYNC_PCLK_DIV2    0x00000000U
 250 #define ADC_CLOCK_SYNC_PCLK_DIV4    ((uint32_t)ADC_CCR_ADCPRE_0)
 251 #define ADC_CLOCK_SYNC_PCLK_DIV6    ((uint32_t)ADC_CCR_ADCPRE_1)
 252 #define ADC_CLOCK_SYNC_PCLK_DIV8    ((uint32_t)ADC_CCR_ADCPRE)
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
 258   * @{
 259   */
 260 #define ADC_TWOSAMPLINGDELAY_5CYCLES    0x00000000U
 261 #define ADC_TWOSAMPLINGDELAY_6CYCLES    ((uint32_t)ADC_CCR_DELAY_0)
 262 #define ADC_TWOSAMPLINGDELAY_7CYCLES    ((uint32_t)ADC_CCR_DELAY_1)
 263 #define ADC_TWOSAMPLINGDELAY_8CYCLES    ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 264 #define ADC_TWOSAMPLINGDELAY_9CYCLES    ((uint32_t)ADC_CCR_DELAY_2)
 265 #define ADC_TWOSAMPLINGDELAY_10CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
 266 #define ADC_TWOSAMPLINGDELAY_11CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
 267 #define ADC_TWOSAMPLINGDELAY_12CYCLES   ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 268 #define ADC_TWOSAMPLINGDELAY_13CYCLES   ((uint32_t)ADC_CCR_DELAY_3)
 269 #define ADC_TWOSAMPLINGDELAY_14CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
 270 #define ADC_TWOSAMPLINGDELAY_15CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
 271 #define ADC_TWOSAMPLINGDELAY_16CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
 272 #define ADC_TWOSAMPLINGDELAY_17CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
 273 #define ADC_TWOSAMPLINGDELAY_18CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
 274 #define ADC_TWOSAMPLINGDELAY_19CYCLES   ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
 275 #define ADC_TWOSAMPLINGDELAY_20CYCLES   ((uint32_t)ADC_CCR_DELAY)
 276 /**
 277   * @}
 278   */
 279
 280 /** @defgroup ADC_Resolution ADC Resolution
 281   * @{
 282   */
 283 #define ADC_RESOLUTION_12B  0x00000000U
 284 #define ADC_RESOLUTION_10B  ((uint32_t)ADC_CR1_RES_0)
 285 #define ADC_RESOLUTION_8B   ((uint32_t)ADC_CR1_RES_1)
 286 #define ADC_RESOLUTION_6B   ((uint32_t)ADC_CR1_RES)
 287 /**
 288   * @}
 289   */
 290
 291 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
 292   * @{
 293   */
 294 #define ADC_EXTERNALTRIGCONVEDGE_NONE           0x00000000U
 295 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
 296 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
 297 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
 298 /**
 299   * @}
 300   */
 301
 302 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
 303   * @{
 304   */
 305 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for        */
 306 /*       compatibility with other STM32 devices.                              */
 307 #define ADC_EXTERNALTRIGCONV_T1_CC1    0x00000000U
 308 #define ADC_EXTERNALTRIGCONV_T1_CC2    ((uint32_t)ADC_CR2_EXTSEL_0)
 309 #define ADC_EXTERNALTRIGCONV_T1_CC3    ((uint32_t)ADC_CR2_EXTSEL_1)
 310 #define ADC_EXTERNALTRIGCONV_T2_CC2    ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 311 #define ADC_EXTERNALTRIGCONV_T2_CC3    ((uint32_t)ADC_CR2_EXTSEL_2)
 312 #define ADC_EXTERNALTRIGCONV_T2_CC4    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 313 #define ADC_EXTERNALTRIGCONV_T2_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 314 #define ADC_EXTERNALTRIGCONV_T3_CC1    ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 315 #define ADC_EXTERNALTRIGCONV_T3_TRGO   ((uint32_t)ADC_CR2_EXTSEL_3)
 316 #define ADC_EXTERNALTRIGCONV_T4_CC4    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
 317 #define ADC_EXTERNALTRIGCONV_T5_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
 318 #define ADC_EXTERNALTRIGCONV_T5_CC2    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 319 #define ADC_EXTERNALTRIGCONV_T5_CC3    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
 320 #define ADC_EXTERNALTRIGCONV_T8_CC1    ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 321 #define ADC_EXTERNALTRIGCONV_T8_TRGO   ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 322 #define ADC_EXTERNALTRIGCONV_Ext_IT11  ((uint32_t)ADC_CR2_EXTSEL)
 323 #define ADC_SOFTWARE_START             ((uint32_t)ADC_CR2_EXTSEL + 1U)
 324 /**
 325   * @}
 326   */
 327
 328 /** @defgroup ADC_Data_align ADC Data Align
 329   * @{
 330   */
 331 #define ADC_DATAALIGN_RIGHT      0x00000000U
 332 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
 333 /**
 334   * @}
 335   */
 336
 337 /** @defgroup ADC_channels  ADC Common Channels
 338   * @{
 339   */
 340 #define ADC_CHANNEL_0           0x00000000U
 341 #define ADC_CHANNEL_1           ((uint32_t)ADC_CR1_AWDCH_0)
 342 #define ADC_CHANNEL_2           ((uint32_t)ADC_CR1_AWDCH_1)
 343 #define ADC_CHANNEL_3           ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 344 #define ADC_CHANNEL_4           ((uint32_t)ADC_CR1_AWDCH_2)
 345 #define ADC_CHANNEL_5           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
 346 #define ADC_CHANNEL_6           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
 347 #define ADC_CHANNEL_7           ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 348 #define ADC_CHANNEL_8           ((uint32_t)ADC_CR1_AWDCH_3)
 349 #define ADC_CHANNEL_9           ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
 350 #define ADC_CHANNEL_10          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
 351 #define ADC_CHANNEL_11          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 352 #define ADC_CHANNEL_12          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
 353 #define ADC_CHANNEL_13          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
 354 #define ADC_CHANNEL_14          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
 355 #define ADC_CHANNEL_15          ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
 356 #define ADC_CHANNEL_16          ((uint32_t)ADC_CR1_AWDCH_4)
 357 #define ADC_CHANNEL_17          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
 358 #define ADC_CHANNEL_18          ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
 359
 360 #define ADC_CHANNEL_VREFINT     ((uint32_t)ADC_CHANNEL_17)
 361 #define ADC_CHANNEL_VBAT        ((uint32_t)ADC_CHANNEL_18)
 362 /**
 363   * @}
 364   */
 365
 366 /** @defgroup ADC_sampling_times  ADC Sampling Times
 367   * @{
 368   */
 369 #define ADC_SAMPLETIME_3CYCLES    0x00000000U
 370 #define ADC_SAMPLETIME_15CYCLES   ((uint32_t)ADC_SMPR1_SMP10_0)
 371 #define ADC_SAMPLETIME_28CYCLES   ((uint32_t)ADC_SMPR1_SMP10_1)
 372 #define ADC_SAMPLETIME_56CYCLES   ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
 373 #define ADC_SAMPLETIME_84CYCLES   ((uint32_t)ADC_SMPR1_SMP10_2)
 374 #define ADC_SAMPLETIME_112CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
 375 #define ADC_SAMPLETIME_144CYCLES  ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
 376 #define ADC_SAMPLETIME_480CYCLES  ((uint32_t)ADC_SMPR1_SMP10)
 377 /**
 378   * @}
 379   */
 380
 381   /** @defgroup ADC_EOCSelection ADC EOC Selection
 382   * @{
 383   */
 384 #define ADC_EOC_SEQ_CONV              0x00000000U
 385 #define ADC_EOC_SINGLE_CONV           0x00000001U
 386 #define ADC_EOC_SINGLE_SEQ_CONV       0x00000002U  /*!< reserved for future use */
 387 /**
 388   * @}
 389   */
 390
 391 /** @defgroup ADC_Event_type ADC Event Type
 392   * @{
 393   */
 394 #define ADC_AWD_EVENT             ((uint32_t)ADC_FLAG_AWD)
 395 #define ADC_OVR_EVENT             ((uint32_t)ADC_FLAG_OVR)
 396 /**
 397   * @}
 398   */
 399
 400 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
 401   * @{
 402   */
 403 #define ADC_ANALOGWATCHDOG_SINGLE_REG         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
 404 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC       ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
 405 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC    ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
 406 #define ADC_ANALOGWATCHDOG_ALL_REG            ((uint32_t)ADC_CR1_AWDEN)
 407 #define ADC_ANALOGWATCHDOG_ALL_INJEC          ((uint32_t)ADC_CR1_JAWDEN)
 408 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC       ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
 409 #define ADC_ANALOGWATCHDOG_NONE               0x00000000U
 410 /**
 411   * @}
 412   */
 413
 414 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
 415   * @{
 416   */
 417 #define ADC_IT_EOC      ((uint32_t)ADC_CR1_EOCIE)
 418 #define ADC_IT_AWD      ((uint32_t)ADC_CR1_AWDIE)
 419 #define ADC_IT_JEOC     ((uint32_t)ADC_CR1_JEOCIE)
 420 #define ADC_IT_OVR      ((uint32_t)ADC_CR1_OVRIE)
 421 /**
 422   * @}
 423   */
 424
 425 /** @defgroup ADC_flags_definition ADC Flags Definition
 426   * @{
 427   */
 428 #define ADC_FLAG_AWD    ((uint32_t)ADC_SR_AWD)
 429 #define ADC_FLAG_EOC    ((uint32_t)ADC_SR_EOC)
 430 #define ADC_FLAG_JEOC   ((uint32_t)ADC_SR_JEOC)
 431 #define ADC_FLAG_JSTRT  ((uint32_t)ADC_SR_JSTRT)
 432 #define ADC_FLAG_STRT   ((uint32_t)ADC_SR_STRT)
 433 #define ADC_FLAG_OVR    ((uint32_t)ADC_SR_OVR)
 434 /**
 435   * @}
 436   */
 437
 438 /** @defgroup ADC_channels_type ADC Channels Type
 439   * @{
 440   */
 441 #define ADC_ALL_CHANNELS      0x00000001U
 442 #define ADC_REGULAR_CHANNELS  0x00000002U /*!< reserved for future use */
 443 #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */
 444 /**
 445   * @}
 446   */
 447
 448 /**
 449   * @}
 450   */
 451
 452 /* Exported macro ------------------------------------------------------------*/
 453 /** @defgroup ADC_Exported_Macros ADC Exported Macros
 454   * @{
 455   */
 456
 457 /** @brief Reset ADC handle state
 458   * @param  __HANDLE__: ADC handle
 459   * @retval None
 460   */
 461 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
 462
 463 /**
 464   * @brief  Enable the ADC peripheral.
 465   * @param  __HANDLE__: ADC handle
 466   * @retval None
 467   */
 468 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |=  ADC_CR2_ADON)
 469
 470 /**
 471   * @brief  Disable the ADC peripheral.
 472   * @param  __HANDLE__: ADC handle
 473   * @retval None
 474   */
 475 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &=  ~ADC_CR2_ADON)
 476
 477 /**
 478   * @brief  Enable the ADC end of conversion interrupt.
 479   * @param  __HANDLE__: specifies the ADC Handle.
 480   * @param  __INTERRUPT__: ADC Interrupt.
 481   * @retval None
 482   */
 483 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
 484
 485 /**
 486   * @brief  Disable the ADC end of conversion interrupt.
 487   * @param  __HANDLE__: specifies the ADC Handle.
 488   * @param  __INTERRUPT__: ADC interrupt.
 489   * @retval None
 490   */
 491 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
 492
 493 /** @brief  Check if the specified ADC interrupt source is enabled or disabled.
 494   * @param  __HANDLE__: specifies the ADC Handle.
 495   * @param  __INTERRUPT__: specifies the ADC interrupt source to check.
 496   * @retval The new state of __IT__ (TRUE or FALSE).
 497   */
 498 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 499
 500 /**
 501   * @brief  Clear the ADC's pending flags.
 502   * @param  __HANDLE__: specifies the ADC Handle.
 503   * @param  __FLAG__: ADC flag.
 504   * @retval None
 505   */
 506 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
 507
 508 /**
 509   * @brief  Get the selected ADC's flag status.
 510   * @param  __HANDLE__: specifies the ADC Handle.
 511   * @param  __FLAG__: ADC flag.
 512   * @retval None
 513   */
 514 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 515
 516 /**
 517   * @}
 518   */
 519
 520 /* Include ADC HAL Extension module */
 521 #include "stm32f4xx_hal_adc_ex.h"
 522
 523 /* Exported functions --------------------------------------------------------*/
 524 /** @addtogroup ADC_Exported_Functions
 525   * @{
 526   */
 527
 528 /** @addtogroup ADC_Exported_Functions_Group1
 529   * @{
 530   */
 531 /* Initialization/de-initialization functions ***********************************/
 532 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
 533 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
 534 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
 535 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
 536 /**
 537   * @}
 538   */
 539
 540 /** @addtogroup ADC_Exported_Functions_Group2
 541   * @{
 542   */
 543 /* I/O operation functions ******************************************************/
 544 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
 545 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
 546 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
 547
 548 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
 549
 550 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
 551 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
 552
 553 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
 554
 555 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
 556 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
 557
 558 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
 559
 560 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
 561 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
 562 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
 563 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
 564 /**
 565   * @}
 566   */
 567
 568 /** @addtogroup ADC_Exported_Functions_Group3
 569   * @{
 570   */
 571 /* Peripheral Control functions *************************************************/
 572 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
 573 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
 574 /**
 575   * @}
 576   */
 577
 578 /** @addtogroup ADC_Exported_Functions_Group4
 579   * @{
 580   */
 581 /* Peripheral State functions ***************************************************/
 582 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
 583 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 584 /**
 585   * @}
 586   */
 587
 588 /**
 589   * @}
 590   */
 591 /* Private types -------------------------------------------------------------*/
 592 /* Private variables ---------------------------------------------------------*/
 593 /* Private constants ---------------------------------------------------------*/
 594 /** @defgroup ADC_Private_Constants ADC Private Constants
 595   * @{
 596   */
 597 /* Delay for ADC stabilization time.                                        */
 598 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
 599 /* Unit: us                                                                 */
 600 #define ADC_STAB_DELAY_US               3U
 601 /* Delay for temperature sensor stabilization time.                         */
 602 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
 603 /* Unit: us                                                                 */
 604 #define ADC_TEMPSENSOR_DELAY_US         10U
 605 /**
 606   * @}
 607   */
 608
 609 /* Private macro ------------------------------------------------------------*/
 610
 611 /** @defgroup ADC_Private_Macros ADC Private Macros
 612   * @{
 613   */
 614 /* Macro reserved for internal HAL driver usage, not intended to be used in
 615    code of final user */
 616
 617 /**
 618   * @brief Verification of ADC state: enabled or disabled
 619   * @param __HANDLE__: ADC handle
 620   * @retval SET (ADC enabled) or RESET (ADC disabled)
 621   */
 622 #define ADC_IS_ENABLE(__HANDLE__)                                              \
 623   ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )            \
 624   ) ? SET : RESET)
 625
 626 /**
 627   * @brief Test if conversion trigger of regular group is software start
 628   *        or external trigger.
 629   * @param __HANDLE__: ADC handle
 630   * @retval SET (software start) or RESET (external trigger)
 631   */
 632 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
 633   (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
 634
 635 /**
 636   * @brief Test if conversion trigger of injected group is software start
 637   *        or external trigger.
 638   * @param __HANDLE__: ADC handle
 639   * @retval SET (software start) or RESET (external trigger)
 640   */
 641 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
 642   (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
 643
 644 /**
 645   * @brief Simultaneously clears and sets specific bits of the handle State
 646   * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
 647   *        the first parameter is the ADC handle State, the second parameter is the
 648   *        bit field to clear, the third and last parameter is the bit field to set.
 649   * @retval None
 650   */
 651 #define ADC_STATE_CLR_SET MODIFY_REG
 652
 653 /**
 654   * @brief Clear ADC error code (set it to error code: "no error")
 655   * @param __HANDLE__: ADC handle
 656   * @retval None
 657   */
 658 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
 659   ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
 660
 661
 662 #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK)     (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
 663                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
 664                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
 665                                               ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8))
 666 #define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
 667                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
 668                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
 669                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
 670                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
 671                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
 672                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
 673                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
 674                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
 675                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
 676                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
 677                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
 678                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
 679                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
 680                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
 681                                       ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES))
 682 #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
 683                                        ((RESOLUTION) == ADC_RESOLUTION_10B) || \
 684                                        ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
 685                                        ((RESOLUTION) == ADC_RESOLUTION_6B))
 686 #define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)    || \
 687                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)  || \
 688                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
 689                                     ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
 690 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1)  || \
 691                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2)  || \
 692                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3)  || \
 693                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)  || \
 694                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)  || \
 695                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4)  || \
 696                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
 697                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)  || \
 698                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \
 699                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)  || \
 700                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1)  || \
 701                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2)  || \
 702                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3)  || \
 703                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1)  || \
 704                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
 705                                   ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \
 706                                   ((REGTRIG) == ADC_SOFTWARE_START))
 707 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
 708                                   ((ALIGN) == ADC_DATAALIGN_LEFT))
 709 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES)   || \
 710                                   ((TIME) == ADC_SAMPLETIME_15CYCLES)  || \
 711                                   ((TIME) == ADC_SAMPLETIME_28CYCLES)  || \
 712                                   ((TIME) == ADC_SAMPLETIME_56CYCLES)  || \
 713                                   ((TIME) == ADC_SAMPLETIME_84CYCLES)  || \
 714                                   ((TIME) == ADC_SAMPLETIME_112CYCLES) || \
 715                                   ((TIME) == ADC_SAMPLETIME_144CYCLES) || \
 716                                   ((TIME) == ADC_SAMPLETIME_480CYCLES))
 717 #define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV)   || \
 718                                            ((EOCSelection) == ADC_EOC_SEQ_CONV)  || \
 719                                            ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV))
 720 #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \
 721                                   ((EVENT) == ADC_OVR_EVENT))
 722 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)        || \
 723                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)      || \
 724                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)   || \
 725                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)           || \
 726                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)         || \
 727                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      || \
 728                                           ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE))
 729 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
 730                                             ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
 731                                             ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
 732 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU)
 733
 734 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U))
 735 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U)))
 736 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U))
 737 #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE)                                     \
 738    ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \
 739     (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \
 740     (((RESOLUTION) == ADC_RESOLUTION_8B)  && ((ADC_VALUE) <= 0x00FFU)) || \
 741     (((RESOLUTION) == ADC_RESOLUTION_6B)  && ((ADC_VALUE) <= 0x003FU)))
 742
 743 /**
 744   * @brief  Set ADC Regular channel sequence length.
 745   * @param  _NbrOfConversion_: Regular channel sequence length.
 746   * @retval None
 747   */
 748 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U)
 749
 750 /**
 751   * @brief  Set the ADC's sample time for channel numbers between 10 and 18.
 752   * @param  _SAMPLETIME_: Sample time parameter.
 753   * @param  _CHANNELNB_: Channel number.
 754   * @retval None
 755   */
 756 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U)))
 757
 758 /**
 759   * @brief  Set the ADC's sample time for channel numbers between 0 and 9.
 760   * @param  _SAMPLETIME_: Sample time parameter.
 761   * @param  _CHANNELNB_: Channel number.
 762   * @retval None
 763   */
 764 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
 765
 766 /**
 767   * @brief  Set the selected regular channel rank for rank between 1 and 6.
 768   * @param  _CHANNELNB_: Channel number.
 769   * @param  _RANKNB_: Rank number.
 770   * @retval None
 771   */
 772 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U)))
 773
 774 /**
 775   * @brief  Set the selected regular channel rank for rank between 7 and 12.
 776   * @param  _CHANNELNB_: Channel number.
 777   * @param  _RANKNB_: Rank number.
 778   * @retval None
 779   */
 780 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U)))
 781
 782 /**
 783   * @brief  Set the selected regular channel rank for rank between 13 and 16.
 784   * @param  _CHANNELNB_: Channel number.
 785   * @param  _RANKNB_: Rank number.
 786   * @retval None
 787   */
 788 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U)))
 789
 790 /**
 791   * @brief  Enable ADC continuous conversion mode.
 792   * @param  _CONTINUOUS_MODE_: Continuous mode.
 793   * @retval None
 794   */
 795 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U)
 796
 797 /**
 798   * @brief  Configures the number of discontinuous conversions for the regular group channels.
 799   * @param  _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
 800   * @retval None
 801   */
 802 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM))
 803
 804 /**
 805   * @brief  Enable ADC scan mode.
 806   * @param  _SCANCONV_MODE_: Scan conversion mode.
 807   * @retval None
 808   */
 809 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U)
 810
 811 /**
 812   * @brief  Enable the ADC end of conversion selection.
 813   * @param  _EOCSelection_MODE_: End of conversion selection mode.
 814   * @retval None
 815   */
 816 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U)
 817
 818 /**
 819   * @brief  Enable the ADC DMA continuous request.
 820   * @param  _DMAContReq_MODE_: DMA continuous request mode.
 821   * @retval None
 822   */
 823 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U)
 824
 825 /**
 826   * @brief Return resolution bits in CR1 register.
 827   * @param __HANDLE__: ADC handle
 828   * @retval None
 829   */
 830 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
 831
 832 /**
 833   * @}
 834   */
 835
 836 /* Private functions ---------------------------------------------------------*/
 837 /** @defgroup ADC_Private_Functions ADC Private Functions
 838   * @{
 839   */
 840
 841 /**
 842   * @}
 843   */
 844
 845 /**
 846   * @}
 847   */
 848
 849 /**
 850   * @}
 851   */
 852
 853 #ifdef __cplusplus
 854 }
 855 #endif
 856
 857 #endif /*__STM32F4xx_ADC_H */
 858
 859
 860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/